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https://github.com/cc65/cc65.git
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More optimization
git-svn-id: svn://svn.cc65.org/cc65/trunk@838 b7a2c559-68d2-44c3-8de9-860c34a00d81
This commit is contained in:
cuz
parent
59a94124a1
commit
24403e151e
@ -131,6 +131,7 @@ static const FuncInfo FuncInfoTable[] = {
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{ "shreax3", REG_AX, REG_AX },
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{ "shreax4", REG_AX, REG_AX },
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{ "staspidx", REG_A | REG_Y, REG_Y },
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{ "stax0sp", REG_AX, REG_Y },
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{ "tosicmp", REG_AX, REG_AXY },
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{ "tosdiva0", REG_AX, REG_AXY },
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{ "tosdivax", REG_AX, REG_AXY },
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@ -1032,7 +1032,7 @@ static unsigned OptCmp6 (CodeSeg* S)
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CodeEntry* E = CS_GetEntry (S, I);
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/* Check for the sequence */
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if ((E->OPC == OP65_LDX || E->OPC == OP65_TAX) &&
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if ((E->OPC == OP65_LDX) &&
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CS_GetEntries (S, L, I+1, 2) &&
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L[0]->OPC == OP65_TXA &&
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!CE_HasLabel (L[0]) &&
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@ -1072,12 +1072,18 @@ static unsigned OptTest1 (CodeSeg* S)
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* ora xxx
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* beq/bne ...
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*
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* if X is zero, the sequence may be changed
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* if X is zero, the sequence may be changed to
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*
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* cmp #$00
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* beq/bne ...
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*
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* which may be optimized further by another step.
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*
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* If A is zero, the sequence may be changed to
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*
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* txa
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* beq/bne ...
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*
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*/
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{
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unsigned Changes = 0;
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@ -1097,7 +1103,6 @@ static unsigned OptTest1 (CodeSeg* S)
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/* Check if it's the sequence we're searching for */
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if (L[0]->OPC == OP65_STX &&
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L[0]->RI->In.RegX == 0 &&
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CS_GetEntries (S, L+1, I+1, 2) &&
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!CE_HasLabel (L[1]) &&
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L[1]->OPC == OP65_ORA &&
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@ -1105,16 +1110,34 @@ static unsigned OptTest1 (CodeSeg* S)
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!CE_HasLabel (L[2]) &&
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(L[2]->Info & OF_ZBRA) != 0) {
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/* Insert the compare */
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CodeEntry* N = NewCodeEntry (OP65_CMP, AM65_IMM, "$00", 0, L[0]->LI);
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CS_InsertEntry (S, N, I+2);
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/* Check if X is zero */
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if (L[0]->RI->In.RegX == 0) {
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/* Remove the two other insns */
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CS_DelEntry (S, I+1);
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CS_DelEntry (S, I);
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/* Insert the compare */
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CodeEntry* N = NewCodeEntry (OP65_CMP, AM65_IMM, "$00", 0, L[0]->LI);
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CS_InsertEntry (S, N, I+2);
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/* We had changes */
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++Changes;
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/* Remove the two other insns */
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CS_DelEntry (S, I+1);
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CS_DelEntry (S, I);
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/* We had changes */
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++Changes;
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/* Check if A is zero */
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} else if (L[1]->RI->In.RegA == 0) {
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/* Insert the txa */
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CodeEntry* N = NewCodeEntry (OP65_TXA, AM65_IMP, 0, 0, L[1]->LI);
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CS_InsertEntry (S, N, I+2);
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/* Remove the two other insns */
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CS_DelEntry (S, I+1);
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CS_DelEntry (S, I);
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/* We had changes */
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++Changes;
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}
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}
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/* Next entry */
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@ -1131,10 +1154,6 @@ static unsigned OptTest1 (CodeSeg* S)
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/*****************************************************************************/
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/* nega optimizations */
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/*****************************************************************************/
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@ -1967,8 +1986,9 @@ static OptFunc OptFuncs [] = {
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OptEntry (OptUnusedLoads, optMain),
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OptEntry (OptDuplicateLoads, optMain),
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OptEntry (OptStoreLoad, optMain),
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OptEntry (OptTransfers, optMain),
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/* Optimize branch distance */
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OptEntry (OptBranchDist, optMain),
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OptEntry (OptBranchDist, optPost),
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};
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@ -44,18 +44,6 @@
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/*****************************************************************************/
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/* Macros */
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/*****************************************************************************/
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/* Macro to increment and decrement register contents if they're valid */
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#define INC(reg,val) if ((reg) >= 0) (reg) = ((reg) + val) & 0xFF
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#define DEC(reg,val) if ((reg) >= 0) (reg) = ((reg) - val) & 0xFF
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/*****************************************************************************/
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/* Replace jumps to RTS by RTS */
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/*****************************************************************************/
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@ -611,20 +599,26 @@ unsigned OptUnusedLoads (CodeSeg* S)
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CodeEntry* E = CS_GetEntry (S, I);
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/* Check if it's a register load or transfer insn */
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if ((E->Info & (OF_LOAD | OF_XFR)) != 0 &&
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(N = CS_GetNextEntry (S, I)) != 0 &&
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if ((E->Info & (OF_LOAD | OF_XFR | OF_REG_INCDEC)) != 0 &&
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(N = CS_GetNextEntry (S, I)) != 0 &&
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(N->Info & OF_FBRA) == 0) {
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/* Check which sort of load or transfer it is */
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unsigned R;
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switch (E->OPC) {
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case OP65_DEA:
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case OP65_INA:
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case OP65_LDA:
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case OP65_TXA:
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case OP65_TYA:
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case OP65_LDA: R = REG_A; break;
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case OP65_TAX:
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case OP65_LDX: R = REG_X; break;
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case OP65_TAY:
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case OP65_LDY: R = REG_Y; break;
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case OP65_TYA: R = REG_A; break;
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case OP65_DEX:
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case OP65_INX:
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case OP65_LDX:
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case OP65_TAX: R = REG_X; break;
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case OP65_DEY:
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case OP65_INY:
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case OP65_LDY:
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case OP65_TAY: R = REG_Y; break;
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default: goto NextEntry; /* OOPS */
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}
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@ -858,6 +852,76 @@ unsigned OptStoreLoad (CodeSeg* S)
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unsigned OptTransfers (CodeSeg* S)
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/* Remove transfers from one register to another and back */
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{
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unsigned Changes = 0;
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/* Walk over the entries */
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unsigned I = 0;
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while (I < CS_GetEntryCount (S)) {
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CodeEntry* N;
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CodeEntry* X;
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CodeEntry* P;
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/* Get next entry */
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CodeEntry* E = CS_GetEntry (S, I);
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/* Check if it is a store instruction followed by a load from the
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* same address which is itself not followed by a conditional branch.
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*/
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if ((E->Info & OF_XFR) != 0 &&
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(N = CS_GetNextEntry (S, I)) != 0 &&
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!CE_HasLabel (N) &&
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(N->Info & OF_XFR) != 0) {
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/* Check if it's a transfer and back */
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if ((E->OPC == OP65_TAX && N->OPC == OP65_TXA && !RegXUsed (S, I+2)) ||
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(E->OPC == OP65_TAY && N->OPC == OP65_TYA && !RegYUsed (S, I+2)) ||
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(E->OPC == OP65_TXA && N->OPC == OP65_TAX && !RegAUsed (S, I+2)) ||
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(E->OPC == OP65_TYA && N->OPC == OP65_TAY && !RegAUsed (S, I+1))) {
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/* If the next insn is a conditional branch, check if the insn
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* preceeding the first xfr will set the flags right, otherwise we
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* may not remove the sequence.
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*/
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if ((X = CS_GetNextEntry (S, I+1)) == 0) {
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goto NextEntry;
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}
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if ((X->Info & OF_FBRA) != 0) {
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if (I == 0) {
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/* No preceeding entry */
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goto NextEntry;
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}
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P = CS_GetEntry (S, I-1);
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if ((P->Info & OF_SETF) == 0) {
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/* Does not set the flags */
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goto NextEntry;
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}
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}
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/* Remove both transfers */
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CS_DelEntry (S, I+1);
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CS_DelEntry (S, I);
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/* Remember, we had changes */
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++Changes;
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}
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}
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NextEntry:
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/* Next entry */
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++I;
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}
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/* Return the number of changes made */
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return Changes;
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}
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/*****************************************************************************/
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/* Optimize branch types */
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/*****************************************************************************/
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@ -95,6 +95,9 @@ unsigned OptDuplicateLoads (CodeSeg* S);
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unsigned OptStoreLoad (CodeSeg* S);
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/* Remove a store followed by a load from the same location. */
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unsigned OptTransfers (CodeSeg* S);
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/* Remove transfers from one register to another and back */
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unsigned OptBranchDist (CodeSeg* S);
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/* Change branches for the distance needed. */
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@ -57,141 +57,27 @@
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/* Opcode description table */
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const OPCDesc OPCTable[OPCODE_COUNT] = {
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/* Opcodes for the virtual stack machine */
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{ OPC_CALL, /* opcode */
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"call", /* mnemonic */
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1, /* size */
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REG_NONE, /* use */
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REG_NONE, /* chg */
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OF_CPU_VM | OF_CALL /* flags */
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},
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{ OPC_ENTER, /* opcode */
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"enter", /* mnemonic */
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1, /* size */
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REG_Y, /* use */
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REG_AXY, /* chg */
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OF_CPU_VM /* flags */
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},
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{ OPC_JMP, /* opcode */
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"jump", /* mnemonic */
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1, /* size */
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REG_NONE, /* use */
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REG_NONE, /* chg */
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OF_CPU_VM | OF_UBRA /* flags */
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},
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{ OPC_LDA, /* opcode */
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"lda", /* mnemonic */
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1, /* size */
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REG_NONE, /* use */
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REG_A, /* chg */
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OF_CPU_VM | OF_LOAD /* flags */
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},
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{ OPC_LDAX, /* opcode */
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"ldax", /* mnemonic */
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1, /* size */
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REG_NONE, /* use */
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REG_AX, /* chg */
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OF_CPU_VM | OF_LOAD /* flags */
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},
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{ OPC_LDEAX, /* opcode */
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"ldeax", /* mnemonic */
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1, /* size */
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REG_NONE, /* use */
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REG_EAX, /* chg */
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OF_CPU_VM | OF_LOAD /* flags */
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},
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{ OPC_LEA, /* opcode */
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"lea", /* mnemonic */
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1, /* size */
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REG_NONE, /* use */
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REG_AX, /* chg */
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OF_CPU_VM /* flags */
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},
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{ OPC_LEAVE, /* opcode */
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"leave", /* mnemonic */
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1, /* size */
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REG_NONE, /* use */
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REG_NONE, /* chg */
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OF_CPU_VM /* flags */
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},
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{ OPC_PHA, /* opcode */
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"pha", /* mnemonic */
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1, /* size */
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REG_A, /* use */
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REG_NONE, /* chg */
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OF_CPU_VM /* flags */
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},
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{ OPC_PHAX, /* opcode */
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"phax", /* mnemonic */
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1, /* size */
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REG_AX, /* use */
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REG_NONE, /* chg */
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OF_CPU_VM /* flags */
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},
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{ OPC_PHEAX, /* opcode */
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"pheax", /* mnemonic */
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1, /* size */
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REG_EAX, /* use */
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REG_NONE, /* chg */
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OF_CPU_VM /* flags */
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},
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{ OPC_RET, /* opcode */
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"ret", /* mnemonic */
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1, /* size */
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REG_NONE, /* use */
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REG_NONE, /* chg */
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OF_CPU_VM | OF_RET /* flags */
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},
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{ OPC_SPACE, /* opcode */
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"space", /* mnemonic */
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1, /* size */
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REG_NONE, /* use */
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REG_NONE, /* chg */
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OF_CPU_VM /* flags */
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},
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{ OPC_STA, /* opcode */
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"sta", /* mnemonic */
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1, /* size */
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REG_A, /* use */
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REG_NONE, /* chg */
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OF_CPU_VM /* flags */
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},
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{ OPC_STAX, /* opcode */
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"stax", /* mnemonic */
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1, /* size */
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REG_AX, /* use */
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REG_NONE, /* chg */
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OF_CPU_VM /* flags */
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},
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{ OPC_STEAX, /* opcode */
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"steax", /* mnemonic */
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1, /* size */
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REG_EAX, /* use */
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REG_NONE, /* chg */
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OF_CPU_VM /* flags */
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},
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/* 65XX opcodes */
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{ OP65_ADC, /* opcode */
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"adc", /* mnemonic */
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0, /* size */
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REG_A, /* use */
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REG_A, /* chg */
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OF_NONE /* flags */
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OF_SETF /* flags */
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},
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{ OP65_AND, /* opcode */
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"and", /* mnemonic */
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0, /* size */
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REG_A, /* use */
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REG_A, /* chg */
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OF_NONE /* flags */
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OF_SETF /* flags */
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},
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{ OP65_ASL, /* opcode */
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"asl", /* mnemonic */
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0, /* size */
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REG_A, /* use */
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REG_A, /* chg */
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OF_NONE /* flags */
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OF_SETF /* flags */
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},
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{ OP65_BCC, /* opcode */
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"bcc", /* mnemonic */
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@ -219,7 +105,7 @@ const OPCDesc OPCTable[OPCODE_COUNT] = {
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0, /* size */
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REG_A, /* use */
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REG_NONE, /* chg */
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OF_NONE /* flags */
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OF_SETF /* flags */
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},
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{ OP65_BMI, /* opcode */
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"bmi", /* mnemonic */
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@ -303,84 +189,84 @@ const OPCDesc OPCTable[OPCODE_COUNT] = {
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0, /* size */
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REG_A, /* use */
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REG_NONE, /* chg */
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OF_NONE /* flags */
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OF_SETF /* flags */
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},
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{ OP65_CPX, /* opcode */
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"cpx", /* mnemonic */
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0, /* size */
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REG_X, /* use */
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REG_NONE, /* chg */
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OF_NONE /* flags */
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OF_SETF /* flags */
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},
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{ OP65_CPY, /* opcode */
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"cpy", /* mnemonic */
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0, /* size */
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REG_Y, /* use */
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REG_NONE, /* chg */
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OF_NONE /* flags */
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OF_SETF /* flags */
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},
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{ OP65_DEA, /* opcode */
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"dea", /* mnemonic */
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1, /* size */
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REG_A, /* use */
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REG_A, /* chg */
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OF_NONE /* flags */
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OF_REG_INCDEC | OF_SETF /* flags */
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},
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{ OP65_DEC, /* opcode */
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"dec", /* mnemonic */
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0, /* size */
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REG_NONE, /* use */
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REG_NONE, /* chg */
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OF_NONE /* flags */
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OF_SETF /* flags */
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},
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{ OP65_DEX, /* opcode */
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"dex", /* mnemonic */
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1, /* size */
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REG_X, /* use */
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REG_X, /* chg */
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OF_NONE /* flags */
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OF_REG_INCDEC | OF_SETF /* flags */
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},
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{ OP65_DEY, /* opcode */
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"dey", /* mnemonic */
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1, /* size */
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REG_Y, /* use */
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REG_Y, /* chg */
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OF_NONE /* flags */
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OF_REG_INCDEC | OF_SETF /* flags */
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},
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{ OP65_EOR, /* opcode */
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"eor", /* mnemonic */
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0, /* size */
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REG_A, /* use */
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REG_A, /* chg */
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OF_NONE /* flags */
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OF_SETF /* flags */
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},
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{ OP65_INA, /* opcode */
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"ina", /* mnemonic */
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1, /* size */
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REG_A, /* use */
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REG_A, /* chg */
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OF_NONE /* flags */
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OF_REG_INCDEC | OF_SETF /* flags */
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},
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{ OP65_INC, /* opcode */
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"inc", /* mnemonic */
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0, /* size */
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REG_NONE, /* use */
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REG_NONE, /* chg */
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OF_NONE /* flags */
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OF_SETF /* flags */
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},
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{ OP65_INX, /* opcode */
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"inx", /* mnemonic */
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1, /* size */
|
||||
REG_X, /* use */
|
||||
REG_X, /* chg */
|
||||
OF_NONE /* flags */
|
||||
OF_REG_INCDEC | OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_INY, /* opcode */
|
||||
"iny", /* mnemonic */
|
||||
1, /* size */
|
||||
REG_Y, /* use */
|
||||
REG_Y, /* chg */
|
||||
OF_NONE /* flags */
|
||||
OF_REG_INCDEC | OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_JCC, /* opcode */
|
||||
"jcc", /* mnemonic */
|
||||
@ -457,28 +343,28 @@ const OPCDesc OPCTable[OPCODE_COUNT] = {
|
||||
0, /* size */
|
||||
REG_NONE, /* use */
|
||||
REG_A, /* chg */
|
||||
OF_LOAD /* flags */
|
||||
OF_LOAD | OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_LDX, /* opcode */
|
||||
"ldx", /* mnemonic */
|
||||
0, /* size */
|
||||
REG_NONE, /* use */
|
||||
REG_X, /* chg */
|
||||
OF_LOAD /* flags */
|
||||
OF_LOAD | OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_LDY, /* opcode */
|
||||
"ldy", /* mnemonic */
|
||||
0, /* size */
|
||||
REG_NONE, /* use */
|
||||
REG_Y, /* chg */
|
||||
OF_LOAD /* flags */
|
||||
OF_LOAD | OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_LSR, /* opcode */
|
||||
"lsr", /* mnemonic */
|
||||
0, /* size */
|
||||
REG_A, /* use */
|
||||
REG_A, /* chg */
|
||||
OF_NONE /* flags */
|
||||
OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_NOP, /* opcode */
|
||||
"nop", /* mnemonic */
|
||||
@ -492,7 +378,7 @@ const OPCDesc OPCTable[OPCODE_COUNT] = {
|
||||
0, /* size */
|
||||
REG_A, /* use */
|
||||
REG_A, /* chg */
|
||||
OF_NONE /* flags */
|
||||
OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_PHA, /* opcode */
|
||||
"pha", /* mnemonic */
|
||||
@ -527,7 +413,7 @@ const OPCDesc OPCTable[OPCODE_COUNT] = {
|
||||
1, /* size */
|
||||
REG_NONE, /* use */
|
||||
REG_A, /* chg */
|
||||
OF_NONE /* flags */
|
||||
OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_PLP, /* opcode */
|
||||
"plp", /* mnemonic */
|
||||
@ -541,49 +427,49 @@ const OPCDesc OPCTable[OPCODE_COUNT] = {
|
||||
1, /* size */
|
||||
REG_NONE, /* use */
|
||||
REG_X, /* chg */
|
||||
OF_NONE /* flags */
|
||||
OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_PLY, /* opcode */
|
||||
"ply", /* mnemonic */
|
||||
1, /* size */
|
||||
REG_NONE, /* use */
|
||||
REG_Y, /* chg */
|
||||
OF_NONE /* flags */
|
||||
OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_ROL, /* opcode */
|
||||
"rol", /* mnemonic */
|
||||
0, /* size */
|
||||
REG_A, /* use */
|
||||
REG_A, /* chg */
|
||||
OF_NONE /* flags */
|
||||
OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_ROR, /* opcode */
|
||||
"ror", /* mnemonic */
|
||||
0, /* size */
|
||||
REG_A, /* use */
|
||||
REG_A, /* chg */
|
||||
OF_NONE /* flags */
|
||||
OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_RTI, /* opcode */
|
||||
"rti", /* mnemonic */
|
||||
1, /* size */
|
||||
REG_NONE, /* use */
|
||||
REG_NONE, /* chg */
|
||||
OF_RET /* flags */
|
||||
OF_RET /* flags */
|
||||
},
|
||||
{ OP65_RTS, /* opcode */
|
||||
"rts", /* mnemonic */
|
||||
1, /* size */
|
||||
REG_NONE, /* use */
|
||||
REG_NONE, /* chg */
|
||||
OF_RET /* flags */
|
||||
OF_RET /* flags */
|
||||
},
|
||||
{ OP65_SBC, /* opcode */
|
||||
"sbc", /* mnemonic */
|
||||
0, /* size */
|
||||
REG_A, /* use */
|
||||
REG_A, /* chg */
|
||||
OF_NONE /* flags */
|
||||
OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_SEC, /* opcode */
|
||||
"sec", /* mnemonic */
|
||||
@ -632,42 +518,42 @@ const OPCDesc OPCTable[OPCODE_COUNT] = {
|
||||
1, /* size */
|
||||
REG_A, /* use */
|
||||
REG_X, /* chg */
|
||||
OF_XFR /* flags */
|
||||
OF_XFR | OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_TAY, /* opcode */
|
||||
"tay", /* mnemonic */
|
||||
1, /* size */
|
||||
REG_A, /* use */
|
||||
REG_Y, /* chg */
|
||||
OF_XFR /* flags */
|
||||
OF_XFR | OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_TRB, /* opcode */
|
||||
"trb", /* mnemonic */
|
||||
0, /* size */
|
||||
REG_A, /* use */
|
||||
REG_NONE, /* chg */
|
||||
OF_NONE /* flags */
|
||||
OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_TSB, /* opcode */
|
||||
"tsb", /* mnemonic */
|
||||
0, /* size */
|
||||
REG_A, /* use */
|
||||
REG_NONE, /* chg */
|
||||
OF_NONE /* flags */
|
||||
OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_TSX, /* opcode */
|
||||
"tsx", /* mnemonic */
|
||||
1, /* size */
|
||||
REG_NONE, /* use */
|
||||
REG_X, /* chg */
|
||||
OF_XFR /* flags */
|
||||
OF_XFR | OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_TXA, /* opcode */
|
||||
"txa", /* mnemonic */
|
||||
1, /* size */
|
||||
REG_X, /* use */
|
||||
REG_A, /* chg */
|
||||
OF_XFR /* flags */
|
||||
OF_XFR | OF_SETF /* flags */
|
||||
},
|
||||
{ OP65_TXS, /* opcode */
|
||||
"txs", /* mnemonic */
|
||||
@ -681,7 +567,7 @@ const OPCDesc OPCTable[OPCODE_COUNT] = {
|
||||
1, /* size */
|
||||
REG_Y, /* use */
|
||||
REG_A, /* chg */
|
||||
OF_XFR /* flags */
|
||||
OF_XFR | OF_SETF /* flags */
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
@ -52,24 +52,6 @@
|
||||
/* Definitions for the possible opcodes */
|
||||
typedef enum {
|
||||
|
||||
/* Opcodes for the virtual stack machine */
|
||||
OPC_CALL,
|
||||
OPC_ENTER,
|
||||
OPC_JMP,
|
||||
OPC_LDA,
|
||||
OPC_LDAX,
|
||||
OPC_LDEAX,
|
||||
OPC_LEA,
|
||||
OPC_LEAVE,
|
||||
OPC_PHA,
|
||||
OPC_PHAX,
|
||||
OPC_PHEAX,
|
||||
OPC_RET,
|
||||
OPC_SPACE,
|
||||
OPC_STA,
|
||||
OPC_STAX,
|
||||
OPC_STEAX,
|
||||
|
||||
/* 65XX opcodes */
|
||||
OP65_ADC,
|
||||
OP65_AND,
|
||||
@ -193,19 +175,18 @@ typedef enum {
|
||||
|
||||
/* Opcode info */
|
||||
#define OF_NONE 0x0000U /* No additional information */
|
||||
#define OF_CPU_6502 0x0000U /* 6502 opcode */
|
||||
#define OF_CPU_VM 0x0001U /* Virtual machine opcode */
|
||||
#define OF_MASK_CPU 0x0001U /* Mask for the cpu field */
|
||||
#define OF_UBRA 0x0010U /* Unconditional branch */
|
||||
#define OF_CBRA 0x0020U /* Conditional branch */
|
||||
#define OF_ZBRA 0x0040U /* Branch on zero flag condition */
|
||||
#define OF_FBRA 0x0080U /* Branch on cond set by a load */
|
||||
#define OF_LBRA 0x0100U /* Jump/branch is long */
|
||||
#define OF_RET 0x0200U /* Return from function */
|
||||
#define OF_LOAD 0x0400U /* Register load */
|
||||
#define OF_STORE 0x0800U /* Register store */
|
||||
#define OF_XFR 0x1000U /* Transfer instruction */
|
||||
#define OF_CALL 0x2000U /* A subroutine call */
|
||||
#define OF_UBRA 0x0001U /* Unconditional branch */
|
||||
#define OF_CBRA 0x0002U /* Conditional branch */
|
||||
#define OF_ZBRA 0x0004U /* Branch on zero flag condition */
|
||||
#define OF_FBRA 0x0008U /* Branch on cond set by a load */
|
||||
#define OF_LBRA 0x0010U /* Jump/branch is long */
|
||||
#define OF_RET 0x0020U /* Return from function */
|
||||
#define OF_LOAD 0x0040U /* Register load */
|
||||
#define OF_STORE 0x0080U /* Register store */
|
||||
#define OF_XFR 0x0100U /* Transfer instruction */
|
||||
#define OF_CALL 0x0200U /* A subroutine call */
|
||||
#define OF_REG_INCDEC 0x0400U /* A register increment or decrement */
|
||||
#define OF_SETF 0x0800U /* Insn will set all load flags (not carry) */
|
||||
|
||||
/* Combined infos */
|
||||
#define OF_BRA (OF_UBRA | OF_CBRA) /* Operation is a jump/branch */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user