diff --git a/doc/ca65.sgml b/doc/ca65.sgml index b4ef3e188..29e04a29e 100644 --- a/doc/ca65.sgml +++ b/doc/ca65.sgml @@ -120,7 +120,7 @@ Long options: --list-bytes n Maximum number of bytes per listing line --memory-model model Set the memory model --pagelength n Set the page length for the listing - --relax-checks Relax some checks (see docs) + --relax-checks Disables some error checks (see <ref id="option--relax-checks" name="below">) --smart Enable smart mode --target sys Set the target system --verbose Increase verbosity @@ -265,14 +265,17 @@ Here is a description of all the command line options: <label id="option--relax-checks"> <tag><tt>--relax-checks</tt></tag> - Relax some checks done by the assembler. This will allow code that is an + Disables some error checks done by the assembler. This will allow code that is an error in most cases and flagged as such by the assembler, but can be valid in special situations. - Examples are: + Disabled checks are: <itemize> -<item>Short branches between two different segments. -<item>Byte sized address loads where the address is not a zeropage address. +<item>Address vs. fragment size: a byte sized load from an non-zeropage + address is truncated instead of producing an error. +<item>Indirect jump on page boundary: <tt>jmp (label)</tt> on a label that + resides on a page boundary (<tt>$xxFF</tt>) fetches the second byte from the + wrong address on 6502 CPUs, now allowed instead of producing an error. </itemize> diff --git a/src/ca65/instr.c b/src/ca65/instr.c index 0afa281b4..da6bd6e44 100644 --- a/src/ca65/instr.c +++ b/src/ca65/instr.c @@ -1618,7 +1618,7 @@ static void PutJMP (const InsDesc* Ins) if (EvalEA (Ins, &A)) { /* Check for indirect addressing */ - if ((A.AddrModeBit & AM65_ABS_IND) && (CPU < CPU_65SC02)) { + if ((A.AddrModeBit & AM65_ABS_IND) && (CPU < CPU_65SC02) && (RelaxChecks == 0)) { /* Compare the low byte of the expression to 0xFF to check for ** a page cross. Be sure to use a copy of the expression otherwise