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Changed the PC-Engine's configuration file, so that the command line can build 8K, 16K, and 32K carts.
Adjusted the PCE's document, the start-up code, and the PCE library test makefile. That makefile shows how to post-process the linker's output file.
This commit is contained in:
Greg King
parent
83890e56eb
commit
3a0506ccb3
43
cfg/pce.cfg
43
cfg/pce.cfg
@ -1,34 +1,29 @@
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# linker config to produce simple NEC PC-Engine cartridge (.pce)
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# linker config. to produce a NEC PC-Engine 8K, 16K, or 32K image (.bin)
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SYMBOLS {
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__CARTSIZE__: type = weak, value = $2000; # $2000, $4000, or $8000
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__STACKSIZE__: type = weak, value = $0300; # 3 pages stack
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}
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MEMORY {
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# FIXME: is this correct? the first 3? bytes cant be used?
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ZP: file = "", start = $0003, size = $00FD, type = rw, define = yes;
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# reset-bank and hardware vectors
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ROM0: file = %O, start = $E000, size = $1FF6, fill = yes, define = yes;
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ROMV: file = %O, start = $FFF6, size = $000A, fill = yes;
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# first RAM page (also contains stack and zeropage)
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RAM: file = "", start = $2200, size = $1e00, define = yes;
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ZP: file = "", start = $0000, size = $0100, define = yes;
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# RAM bank
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MAIN: file = "", start = $2200, size = $1E00 - __STACKSIZE__, define = yes;
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# ROM banks, before swapping, and after mapping
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ROM: file = %O, start = $10000 - __CARTSIZE__, size = __CARTSIZE__, fill = yes, fillval = $FF;
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}
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SEGMENTS {
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ZEROPAGE: load = ZP, type = zp, define = yes;
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EXTZP: load = ZP, type = zp, define = yes, optional = yes;
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APPZP: load = ZP, type = zp, define = yes, optional = yes;
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STARTUP: load = ROM0, type = ro, define = yes;
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ONCE: load = ROM0, type = ro, optional = yes;
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CODE: load = ROM0, type = ro, define = yes;
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RODATA: load = ROM0, type = ro, define = yes;
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DATA: load = ROM0, run = RAM, type = rw, define = yes;
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BSS: load = RAM, type = bss, define = yes;
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VECTORS: load = ROMV, type = rw, define = yes;
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ZEROPAGE: load = ZP, type = zp;
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EXTZP: load = ZP, type = zp, optional = yes;
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APPZP: load = ZP, type = zp, optional = yes;
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DATA: load = ROM, run = MAIN, type = rw, define = yes;
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INIT: load = MAIN, type = bss, optional = yes;
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BSS: load = MAIN, type = bss, define = yes;
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RODATA: load = ROM, type = ro;
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CODE: load = ROM, type = ro;
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LOWCODE: load = ROM, type = ro, optional = yes;
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ONCE: load = ROM, type = ro, optional = yes;
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STARTUP: load = ROM, type = ro, start = $FFF6 - $0066;
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VECTORS: load = ROM, type = ro, start = $FFF6;
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}
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FEATURES {
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CONDES: type = constructor,
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label = __CONSTRUCTOR_TABLE__,
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61
doc/pce.sgml
61
doc/pce.sgml
@ -3,9 +3,9 @@
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<article>
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<title>PC-Engine (TurboGrafx) System specific information for cc65
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<author>
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<url url="mailto:groepaz@gmx.net" name="Groepaz/Hitmen">
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<date>2016-09-29
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<author><url url="mailto:groepaz@gmx.net" name="Groepaz/Hitmen">,<newline>
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<url url="mailto:greg.king5@verizon.net" name="Greg King">
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<date>2018-02-12
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<abstract>
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An overview over the PCE runtime system as it is implemented for the
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@ -30,11 +30,36 @@ more than one platform. Please see the function reference for more
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information.
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<sect>Binary format<p>
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The standard binary output format generated by the linker for the PCE target
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is a cartridge image with no header. It is of course possible to change this
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behaviour by using a modified startup file and linker config.
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The binary output file generated by the linker, for the PCE target, is an
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image, with no header, that has 8K bytes in the wrong place. That file must be
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post-processed; the 8K at the end must be moved to the front of the image.
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On POSIX systems, the <tt/dd/ command and the shell give a convenient way to do
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it. Here is an example of their use:
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<tscreen><verb>
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dd if=conio.bin bs=8K skip=3 > conio.pce
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dd if=conio.bin bs=8K count=3 >> conio.pce
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</verb></tscreen>
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The first command grabs the last 8K of a 32K file, and writes it as the first
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part of a new file. The second command reads all but the last part of the old
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file, and appends it to the new file.
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<tscreen><verb>
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+--------+--------+--------+--------+
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| Bank 1 | Bank 2 | Bank 3 | Bank 0 | <-- "conio.bin"
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+--------+--------+--------+--------+
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+--------+--------+--------+--------+
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| Bank 0 | Bank 1 | Bank 2 | Bank 3 | <-- "conio.pce"
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+--------+--------+--------+--------+
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</verb></tscreen>
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<em/Note/: That <tt/.pce/ file shows the format of the ROM cartridge that is
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plugged into a PC-Engine. But, that <tt/.bin/ file shows what programs
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actually see when they execute the code in that cartridge.
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<sect>Memory layout<p>
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@ -52,19 +77,23 @@ Special locations:
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<tag/Stack/
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The C runtime stack is located in system RAM at $3FFF and growing downwards.
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<tag/BSS and Data/
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The BSS (uninitialized variables) and Data (initialized variables) sections are
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placed one after the other into system RAM at $2000.
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<tag/Data and BSS/
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The Data (initialized variables) and BSS (uninitialized variables) sections are
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placed one after the other into system RAM at $2200.
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<tag/Heap/
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The C heap is located after the end of the Data section and grows towards the C
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The C heap is located after the end of the BSS section; and, grows towards the C
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runtime stack.
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<tag/Code/
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The startup code is located at $E000 in the System/Hardware bank. Further
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code can be placed in other ROM banks, this must be done manually however.
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In an 8K ROM cartridge, code and read-only data are located between
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$E000 and $FFF5 in the System bank.
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In a 16K cartridge, code and read-only data are located between $C000
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and $FFF5.
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In a 32K cartridge, code and read-only data are located between $8000
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and $FFF5.
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</descrip><p>
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@ -171,7 +200,8 @@ following functions (and a few others):
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<sect>Other hints<p>
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<itemize>
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<item>a good emulator to use for PC-Engine is "mednafen" (<url url="http://mednafen.fobby.net/">)
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<item><url url="https://mednafen.github.io/" name= "Mednafen"> is a good
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emulator to use for the PC-Engine.
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</itemize>
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some useful resources on PCE coding:
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@ -210,6 +240,3 @@ freely, subject to the following restrictions:
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</enum>
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</article>
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@ -4,33 +4,26 @@
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; by Groepaz/Hitmen <groepaz@gmx.net>
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; based on code by Ullrich von Bassewitz <uz@cc65.org>
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;
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; This must be the *first* file on the linker command line
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; 2018-02-11, Greg King
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;
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.export _exit
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.export __STARTUP__ : absolute = 1 ; Mark as startup
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.import initlib, donelib
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.import push0, _main, zerobss
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.import initheap
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.import push0, _main
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.import IRQStub
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; Linker generated
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.import __RAM_START__, __RAM_SIZE__
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.import __ROM0_START__, __ROM0_SIZE__
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.import __ROM_START__, __ROM_SIZE__
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.import __STARTUP_LOAD__,__STARTUP_RUN__, __STARTUP_SIZE__
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.import __CODE_LOAD__,__CODE_RUN__, __CODE_SIZE__
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.import __RODATA_LOAD__,__RODATA_RUN__, __RODATA_SIZE__
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.import __DATA_LOAD__,__DATA_RUN__, __DATA_SIZE__
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.import __BSS_SIZE__
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; Linker-generated
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.import __CARTSIZE__
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.import __DATA_LOAD__, __DATA_RUN__, __DATA_SIZE__
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.import __BSS_RUN__, __BSS_SIZE__
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.import __MAIN_START__, __MAIN_SIZE__, __STACKSIZE__
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.include "pce.inc"
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.include "extzp.inc"
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.importzp sp
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.importzp ptr1,ptr2
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.importzp tmp1,tmp2,tmp3
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; ------------------------------------------------------------------------
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; Place the startup code in a special segment.
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@ -53,29 +46,27 @@ start:
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ldx #$FF ; Stack top ($21FF)
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txs
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; At startup all MPRs are set to 0, so init them
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lda #$ff
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tam #%00000001 ; 0000-1FFF = Hardware page
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; At power-on, most MPRs have random values; so, initiate them.
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lda #$FF
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tam #%00000001 ; $0000-$1FFF = Hardware bank
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lda #$F8
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tam #%00000010 ; 2000-3FFF = Work RAM
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; FIXME: setup a larger block of memory to use with C-code
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tam #%00000010 ; $2000-$3FFF = Work RAM
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;lda #$F7
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;tam #%00000100 ; 4000-5FFF = Save RAM
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;lda #1
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;tam #%00001000 ; 6000-7FFF Page 2
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;lda #2
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;tam #%00010000 ; 8000-9FFF Page 3
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;lda #3
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;tam #%00100000 ; A000-BFFF Page 4
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;tam #%00000100 ; $4000-$47FF = 2K Battery-backed RAM
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;lda #4
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;tam #%01000000 ; C000-DFFF Page 5
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;lda #0
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;tam #%10000000 ; e000-fFFF hucard/syscard bank 0
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;tam #%00001000 ; $6000-$7FFF
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; Clear work RAM (2000-3FFF)
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stz <$00
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tii $2000, $2001, $1FFF
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lda #$01
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ldx #>$8000
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cpx #>__CARTSIZE__
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bcc @L1 ;(blt)
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tam #%00010000 ; $8000-$9FFF = ROM bank 1 (32K block of ROM)
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inc a
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tam #%00100000 ; $A000-$BFFF = ROM bank 2
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inc a
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@L1: tam #%01000000 ; $C000-$DFFF = ROM bank 3 (32K) or 1 (16K)
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;lda #$00 ; (The reset default)
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;tam #%10000000 ; $E000-$FFFF hucard/syscard bank 0
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; Initialize hardware
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stz TIMER_CTRL ; Timer off
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@ -91,15 +82,16 @@ start:
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lda #$05
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sta IRQ_MASK ; IRQ1=on
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; Clear the BSS data
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jsr zerobss
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; Copy the .data segment to RAM
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tii __DATA_LOAD__, __DATA_RUN__, __DATA_SIZE__
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; Clear the .bss segment
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stz __BSS_RUN__
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tii __BSS_RUN__, __BSS_RUN__ + 1, __BSS_SIZE__ - 1
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; Set up the stack
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lda #<(__RAM_START__+__RAM_SIZE__)
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ldx #>(__RAM_START__+__RAM_SIZE__)
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lda #<(__MAIN_START__ + __MAIN_SIZE__ + __STACKSIZE__)
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ldx #>(__MAIN_START__ + __MAIN_SIZE__ + __STACKSIZE__)
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sta sp
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stx sp + 1
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@ -1,12 +1,29 @@
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.PHONY: all clean test
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# Size of cartridge to generate.
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# Possible values:
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# 8K = 0x2000
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# 16K = 0x4000
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# 32K = 0x8000
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CARTSIZE := 0x2000
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ifeq (${CARTSIZE},0x8000)
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COUNT := 3
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else
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COUNT := 1
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endif
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all: conio.pce
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conio.pce: conio.c
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../../../bin/cl65 -t pce conio.c --mapfile conio.map -o conio.pce
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%.pce: %.bin
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dd if=$< bs=8K skip=${COUNT} > $@
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dd if=$< bs=8K count=${COUNT} >> $@
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%.bin: %.c ../../../lib/pce.lib
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../../../bin/cl65 -t pce $< -Wl -D__CARTSIZE__=${CARTSIZE} -m $*.map -o $@
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clean:
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$(RM) conio.o conio.pce conio.map
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$(RM) conio.o conio.???
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test: conio.pce
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mednafen -force_module pce conio.pce
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mednafen -force_module pce $<
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@ -45,7 +45,7 @@ void main(void)
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p[8],p[9],p[10],p[11],p[12],p[13],p[14],p[15]
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);
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}
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memcpy(p, main, 0); /* test that a zero length doesn't copy 64K */
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memcpy(p, main, i = 0); /* test that a zero length doesn't copy 64K */
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gotoxy(0,ysize - 1);
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for (i = 0; i < xsize; ++i) {
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