mirror of https://github.com/cc65/cc65.git
Move Atari-specific PIA reg vals to atari.h
PIA is also used in the Commodore PET, and for different purposes (see http://www.6502.org/users/andre/petindex/progmod.html#pia1), so extracted Atari-specific register #defines and placed them in atari.h.
This commit is contained in:
Bill Kendrick
Christian Groessler
parent
7445550831
commit
417ef278a3
116
include/_pia.h
116
include/_pia.h
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@ -11,7 +11,6 @@
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/* */
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/* */
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/* (C) 2000 Freddy Offenga <taf_offenga@yahoo.com> */
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/* 2019-01-17: Bill Kendrick <nbs@sonic.net>: Defines for registers */
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/* */
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/* */
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/* This software is provided 'as-is', without any expressed or implied */
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@ -47,120 +46,7 @@ struct __pia {
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unsigned char pbctl; /* port B control */
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};
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/*****************************************************************************/
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/* PORTA and PORTB register bits */
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/*****************************************************************************/
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/* See also: "JOY_xxx_MASK" in "atari.h" */
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/* Paddle 0-3 triggers (per PORTA bits) */
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#define PORTA_PTRIG3 0x80
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#define PORTA_PTRIG2 0x40
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#define PORTA_PTRIG1 0x08
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#define PORTA_PTRIG0 0x04
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/* On the Atari 400/800, PORTB is the same as PORTA, but for controller ports 3 & 4. */
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/* Paddle 4-7 triggers (per PORTB bits); only 400/800 had four controller ports */
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#define PORTB_PTRIG7 0x80
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#define PORTB_PTRIG6 0x40
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#define PORTB_PTRIG5 0x08
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#define PORTB_PTRIG4 0x04
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/* On the XL series of computers, PORTB has been changed to a memory and
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** LED control (1200XL model only) register (read/write):
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*/
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/* If set, the built-in OS is enabled, and occupies the address range $C000-$FFFF
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** (except that the area $D000-$D7FF will only access the hardware registers.)
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** If clear, RAM is enabled in this area (again, save for the hole.)
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*/
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#define PORTB_OSROM 0x01
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/* If set, RAM is enabled for the address range $A000-$BFFF.
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** If clear, the built-in BASIC ROM is enabled at this address.
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** And if there is a cartridge installed in the computer, it makes no difference.
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*/
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#define PORTB_BASICROM 0x02
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/* If set, the corresponding LED is turned off. If clear, the LED will be on.
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** (1200XL only)
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*/
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#define PORTB_LED1 0x04
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#define PORTB_LED2 0x08
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/* On the XE series of computers, PORTB is a bank-selected memory control register (read/write): */
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/* These bits determine which memory bank is visible to the CPU and/or ANTIC chip
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** when their Bank Switch bit is set. There are four possible banks of 16KB each.
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*/
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#define PORTB_BANKSELECT1 0x00
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#define PORTB_BANKSELECT2 0x04
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#define PORTB_BANKSELECT3 0x08
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#define PORTB_BANKSELECT4 0x0C
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/* If set, the CPU and/or ANTIC chip will access bank-switched memory mapped to the
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** address range $4000-$7FFF.
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** If clear, the CPU and/or ANTIC will see normal memory in this region.
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*/
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#define PORTB_BANKSWITCH_CPU 0x10
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#define PORTB_BANKSWITCH_ANTIC 0x20
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/* If set, RAM is enabled for the address range $5000-$57FF.
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** If clear, the self-test ROM (physically located at $D000-$D7FF, under the hardware registers)
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** is remapped to this memory area.
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*/
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#define PORTB_SELFTEST 0x80
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/*****************************************************************************/
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/* PACTL and PBCTL register bits */
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/*****************************************************************************/
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/* (W) Peripheral PA1/PB1 interrupt (IRQ) ("peripheral proceed line available") enable.
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** One equals enable. Set by the OS but available to the user; reset on powerup.
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** (PxCTL_IRQ_STATUS (R) bit will get set upon interrupt occurance)
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*/
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#define PxCTL_IRQ_ENABLE 0x01 /* bit 0 */
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/* Note: Bit 1 is always set to */
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/* (W) Controls PORTA/PORTB addressing
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** 1 = PORTA/PORTB register; read/write to controller port
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** 0 = direction control register; write to direction controls
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** (allows setting data flow; write 0s & 1s to PORTA/PORTB bits
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** to set which port's pins are read (input), or write (output),
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** respectively)
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*/
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#define PxCTL_ADDRESSING 0x04 /* bit 2 */
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/* (W) Peripheral motor control line; Turn the cassette on or off
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** (PACTL-specific register bit)
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** 0 = on
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** 1 = off
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*/
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#define PACTL_MOTOR_CONTROL 0x08 /* bit 3 */
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/* Peripheral command identification (serial bus command line)
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** (PBCTL-specific register bit)
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*/
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#define PBCTL_PERIPH_CMD_IDENT 0x08 /* bit 3 */
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/* Note: Bits 4 & 5 are always set to 1 */
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/* Note: Bit 6 is always set to 0 */
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/* (R) Peripheral interrupt (IRQ) status bit.
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** Set by Peripherals (PORTA / PORTB). Reset by reading from PORTA / PORTB.
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** PACTL's is interrupt status of PROCEED
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** PBCTL's is interrupt status of SIO
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*/
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#define PxCTL_IRQ_STATUS 0x80
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/* (Some specific register values for Atari defined in atari.h) */
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/* End of _pia.h */
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#endif
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114
include/atari.h
114
include/atari.h
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@ -375,6 +375,120 @@ extern void atrx15p2_tgi[];
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#define ANTIC (*(struct __antic*)0xD400)
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/*****************************************************************************/
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/* PIA PORTA and PORTB register bits */
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/*****************************************************************************/
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/* See also: "JOY_xxx_MASK" in "atari.h" */
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/* Paddle 0-3 triggers (per PORTA bits) */
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#define PORTA_PTRIG3 0x80
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#define PORTA_PTRIG2 0x40
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#define PORTA_PTRIG1 0x08
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#define PORTA_PTRIG0 0x04
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/* On the Atari 400/800, PORTB is the same as PORTA, but for controller ports 3 & 4. */
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/* Paddle 4-7 triggers (per PORTB bits); only 400/800 had four controller ports */
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#define PORTB_PTRIG7 0x80
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#define PORTB_PTRIG6 0x40
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#define PORTB_PTRIG5 0x08
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#define PORTB_PTRIG4 0x04
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/* On the XL series of computers, PORTB has been changed to a memory and
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** LED control (1200XL model only) register (read/write):
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*/
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/* If set, the built-in OS is enabled, and occupies the address range $C000-$FFFF
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** (except that the area $D000-$D7FF will only access the hardware registers.)
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** If clear, RAM is enabled in this area (again, save for the hole.)
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*/
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#define PORTB_OSROM 0x01
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/* If set, RAM is enabled for the address range $A000-$BFFF.
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** If clear, the built-in BASIC ROM is enabled at this address.
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** And if there is a cartridge installed in the computer, it makes no difference.
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*/
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#define PORTB_BASICROM 0x02
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/* If set, the corresponding LED is turned off. If clear, the LED will be on.
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** (1200XL only)
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*/
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#define PORTB_LED1 0x04
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#define PORTB_LED2 0x08
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/* On the XE series of computers, PORTB is a bank-selected memory control register (read/write): */
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/* These bits determine which memory bank is visible to the CPU and/or ANTIC chip
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** when their Bank Switch bit is set. There are four possible banks of 16KB each.
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*/
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#define PORTB_BANKSELECT1 0x00
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#define PORTB_BANKSELECT2 0x04
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#define PORTB_BANKSELECT3 0x08
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#define PORTB_BANKSELECT4 0x0C
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/* If set, the CPU and/or ANTIC chip will access bank-switched memory mapped to the
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** address range $4000-$7FFF.
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** If clear, the CPU and/or ANTIC will see normal memory in this region.
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*/
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#define PORTB_BANKSWITCH_CPU 0x10
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#define PORTB_BANKSWITCH_ANTIC 0x20
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/* If set, RAM is enabled for the address range $5000-$57FF.
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** If clear, the self-test ROM (physically located at $D000-$D7FF, under the hardware registers)
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** is remapped to this memory area.
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*/
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#define PORTB_SELFTEST 0x80
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/*****************************************************************************/
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/* PACTL and PBCTL register bits */
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/*****************************************************************************/
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/* (W) Peripheral PA1/PB1 interrupt (IRQ) ("peripheral proceed line available") enable.
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** One equals enable. Set by the OS but available to the user; reset on powerup.
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** (PxCTL_IRQ_STATUS (R) bit will get set upon interrupt occurance)
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*/
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#define PxCTL_IRQ_ENABLE 0x01 /* bit 0 */
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/* Note: Bit 1 is always set to */
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/* (W) Controls PORTA/PORTB addressing
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** 1 = PORTA/PORTB register; read/write to controller port
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** 0 = direction control register; write to direction controls
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** (allows setting data flow; write 0s & 1s to PORTA/PORTB bits
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** to set which port's pins are read (input), or write (output),
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** respectively)
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*/
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#define PxCTL_ADDRESSING 0x04 /* bit 2 */
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/* (W) Peripheral motor control line; Turn the cassette on or off
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** (PACTL-specific register bit)
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** 0 = on
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** 1 = off
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*/
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#define PACTL_MOTOR_CONTROL 0x08 /* bit 3 */
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/* Peripheral command identification (serial bus command line)
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** (PBCTL-specific register bit)
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*/
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#define PBCTL_PERIPH_CMD_IDENT 0x08 /* bit 3 */
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/* Note: Bits 4 & 5 are always set to 1 */
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/* Note: Bit 6 is always set to 0 */
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/* (R) Peripheral interrupt (IRQ) status bit.
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** Set by Peripherals (PORTA / PORTB). Reset by reading from PORTA / PORTB.
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** PACTL's is interrupt status of PROCEED
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** PBCTL's is interrupt status of SIO
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*/
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#define PxCTL_IRQ_STATUS 0x80
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/*****************************************************************************/
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/* Shadow registers for hardware registers */
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/*****************************************************************************/
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