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Fixed clock-cycle timing of branch (Bxx) instructions.

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Branch instructions, when taken, take three or four cycles,
depending on whether a page is crossed by the branch.

The proper check to determine whether the extra cycle must be added
is the target address of the branch vs the address immediately
following the branch.

In the former version of the BRANCH instruction handler, the target
address was incorrectly checked vs the address of the branch instruction
itself.

The corrected behavior was verified against a real 6502 (Atari) and
the 65x02 testsuite.
This commit is contained in:
Sidney Cadot 2024-11-30 19:56:31 +01:00
parent 05a653d3f9
commit 709d71ef70
1 changed files with 2 additions and 1 deletions
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3
src/sim65/6502.c
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@ -707,8 +707,9 @@ static unsigned HaveIRQRequest;
unsigned char OldPCH; \
++Cycles; \
Offs = (signed char) MemReadByte (Regs.PC+1); \
Regs.PC +=2; \
OldPCH = PCH; \
Regs.PC = (Regs.PC + 2 + (int) Offs) & 0xFFFF; \
Regs.PC = (Regs.PC + (int) Offs) & 0xFFFF; \
if (PCH != OldPCH) { \
++Cycles; \
} \