From 709d71ef704b51a5729318a9b839293a00b78590 Mon Sep 17 00:00:00 2001 From: Sidney Cadot Date: Sat, 30 Nov 2024 19:56:31 +0100 Subject: [PATCH] Fixed clock-cycle timing of branch (Bxx) instructions. Branch instructions, when taken, take three or four cycles, depending on whether a page is crossed by the branch. The proper check to determine whether the extra cycle must be added is the target address of the branch vs the address immediately following the branch. In the former version of the BRANCH instruction handler, the target address was incorrectly checked vs the address of the branch instruction itself. The corrected behavior was verified against a real 6502 (Atari) and the 65x02 testsuite. --- src/sim65/6502.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/sim65/6502.c b/src/sim65/6502.c index 448e81669..41ffc8329 100644 --- a/src/sim65/6502.c +++ b/src/sim65/6502.c @@ -707,8 +707,9 @@ static unsigned HaveIRQRequest; unsigned char OldPCH; \ ++Cycles; \ Offs = (signed char) MemReadByte (Regs.PC+1); \ + Regs.PC +=2; \ OldPCH = PCH; \ - Regs.PC = (Regs.PC + 2 + (int) Offs) & 0xFFFF; \ + Regs.PC = (Regs.PC + (int) Offs) & 0xFFFF; \ if (PCH != OldPCH) { \ ++Cycles; \ } \