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https://github.com/cc65/cc65.git
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Fix register r/w timing
This commit is contained in:
Colin Leroy-Mira
Oliver Schmidt
parent
b300b7ac8b
commit
9e87e558d2
@ -239,33 +239,34 @@ SER_FLAG_CH_B = %00000111
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.code
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; Read a register
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; Input: X as channel
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; Output result in A
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.macro rra In,Reg
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lda Reg
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sta In,x
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lda In,x
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.endmacro
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; Read register value to A.
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; Input: X as channel
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; Y as register
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; Output: A
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readSSCReg:
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cpx #0
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bne ReadAreg
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sty SCCBREG
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lda SCCBREG
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rts
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ReadAreg:
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sty SCCAREG
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lda SCCAREG
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rts
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; Write value of A to a register.
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; Input: X as channel
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.macro wra Out,Reg
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pha
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lda Reg
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sta Out,x
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pla
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sta Out,x
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.endmacro
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; Write value passed as parameter to a register.
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; Input: X as channel
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.macro wrr Out,Reg,Val
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lda Reg
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sta Out,x
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lda Val
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sta Out,x
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.endmacro
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; Y as register
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writeSCCReg:
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cpx #0
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bne WriteAreg
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sty SCCBREG
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sta SCCBREG
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rts
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WriteAreg:
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sty SCCAREG
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sta SCCAREG
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rts
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;----------------------------------------------------------------------------
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; SER_INSTALL: Is called after the driver is loaded into memory. If possible,
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@ -291,8 +292,13 @@ SER_CLOSE:
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; Deactivate interrupts
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sei
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wrr SCCBREG, #WR_MASTER_IRQ_RST, #MASTER_IRQ_SHUTDOWN
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wrr SCCBREG, #WR_TX_RX_MODE_CTRL, #TX_RX_MODE_OFF
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ldy #WR_MASTER_IRQ_RST
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lda #MASTER_IRQ_SHUTDOWN
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jsr writeSCCReg
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ldy #WR_TX_RX_MODE_CTRL
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lda #TX_RX_MODE_OFF
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jsr writeSCCReg
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; Reset SerFlag to what it was
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lda SerFlagOrig
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@ -303,14 +309,13 @@ SER_CLOSE:
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; Clear external interrupts (twice)
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ldy #WR_INIT_CTRL
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lda #INIT_CTRL_CLEAR_EIRQ
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sty SCCBREG
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sta SCCBREG
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sty SCCBREG
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sta SCCBREG
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jsr writeSCCReg
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jsr writeSCCReg
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; Reset MIE for firmware use
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wrr SCCBREG, #WR_MASTER_IRQ_RST, #MASTER_IRQ_MIE_RST
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ldy #WR_MASTER_IRQ_RST
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lda #MASTER_IRQ_MIE_RST
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jsr writeSCCReg
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ldx #$00
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stx Slot ; Mark port as closed
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@ -346,6 +351,8 @@ SetupErrOut:
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rts
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HardwareFound:
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sei ; Disable interrupts
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; Check if the handshake setting is valid
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ldy #SER_PARAMS::HANDSHAKE ; Handshake
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lda (ptr1),y
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@ -370,7 +377,12 @@ SetupBufs:
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ldx Channel
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rra SCCBREG,#$00 ; Hit rr0 once to sync up
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ldy #RR_INIT_STATUS ; Hit rr0 once to sync up
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jsr readSSCReg
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ldy #WR_MISC_CTRL ; Turn everything off
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lda #$00
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jsr writeSCCReg
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ldy #SER_PARAMS::STOPBITS
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lda (ptr1),y ; Stop bits
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@ -388,19 +400,24 @@ SetupBufs:
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ora #TX_RX_CLOCK_MUL
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wra SCCBREG,#WR_TX_RX_CTRL
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ldy #WR_TX_RX_CTRL ; Setup stop & parity bits
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jsr writeSCCReg
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cpx #$00
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bne ClockA
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ClockB:
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wrr SCCBREG,#WR_CLOCK_CTRL,#CLOCK_CTRL_CH_B
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ldy #WR_CLOCK_CTRL
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lda #CLOCK_CTRL_CH_B
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jsr writeSCCReg
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lda #INTR_PENDING_RX_EXT_B ; Store which IRQ bits we'll check
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sta CurChanIrqFlags
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bra SetBaud
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ClockA:
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wrr SCCBREG,#WR_CLOCK_CTRL,#CLOCK_CTRL_CH_A
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ldy #WR_CLOCK_CTRL
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lda #CLOCK_CTRL_CH_A
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jsr writeSCCReg
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lda #INTR_PENDING_RX_EXT_A ; Store which IRQ bits we'll check
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sta CurChanIrqFlags
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@ -416,50 +433,58 @@ SetBaud:
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lda BaudLowTable,y ; Get low byte
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bmi InvParam ; Branch if rate not supported
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wra SCCBREG,#WR_BAUDL_CTRL
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phy
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ldy #WR_BAUDL_CTRL
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jsr writeSCCReg
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ply
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lda BaudHighTable,y ; Get high byte
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wra SCCBREG,#WR_BAUDH_CTRL
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ldy #WR_BAUDH_CTRL
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jsr writeSCCReg
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lda #$00
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wra SCCBREG,#WR_MISC_CTRL
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ldy #WR_MISC_CTRL ; Time to turn this thing on
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lda #MISC_CTRL_RATE_GEN_ON
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jsr writeSCCReg
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ora #MISC_CTRL_RATE_GEN_ON ; Time to turn this thing on
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wra SCCBREG,#WR_MISC_CTRL
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; Final write to RX_CTRL
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ldy #SER_PARAMS::DATABITS
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lda (ptr1),y ; Data bits
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tay
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lda RxBitTable,y ; Data bits for RX
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ora #RX_CTRL_ON ; Plus turn on
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wra SCCBREG,#WR_RX_CTRL
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ora #RX_CTRL_ON ; and turn RX on
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phy
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ldy #WR_RX_CTRL
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jsr writeSCCReg
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ply
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lda TxBitTable,y ; Data bits for TX
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ora #TX_CTRL_ON ; Plus turn on
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ora #TX_CTRL_ON ; and turn TX on
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and #TX_DTR_ON
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sta RtsOff ; Save value for flow control
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ora #TX_RTS_ON
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wra SCCBREG,#WR_TX_CTRL
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wrr SCCBREG,#WR_IRQ_CTRL,#IRQ_CLEANUP_EIRQ
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ldy #WR_TX_CTRL
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jsr writeSCCReg
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lda #WR_INIT_CTRL ; Clear ext status (write twice)
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sta SCCBREG,x
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ldy #WR_IRQ_CTRL
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lda #IRQ_CLEANUP_EIRQ
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jsr writeSCCReg
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ldy #WR_INIT_CTRL ; Clear ext status (write twice)
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lda #INIT_CTRL_CLEAR_EIRQ
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sta SCCBREG,x
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jsr writeSCCReg
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jsr writeSCCReg
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lda #WR_INIT_CTRL
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sta SCCBREG,x
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lda #INIT_CTRL_CLEAR_EIRQ
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sta SCCBREG,x
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ldy #WR_TX_RX_MODE_CTRL ; Activate RX IRQ
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lda #TX_RX_MODE_RXIRQ
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jsr writeSCCReg
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; Activate RX IRQ
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wrr SCCBREG,#WR_TX_RX_MODE_CTRL,#TX_RX_MODE_RXIRQ
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wrr SCCBREG,#WR_MASTER_IRQ_RST,#MASTER_IRQ_SET
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lda SCCBREG ; Activate master IRQ
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ldy #WR_MASTER_IRQ_RST
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lda #MASTER_IRQ_SET
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jsr writeSCCReg
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lda SER_FLAG ; Get SerFlag's current value
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sta SerFlagOrig ; and save it
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@ -502,7 +527,9 @@ SER_GET:
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lda RtsOff
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ora #TX_RTS_ON
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wra SCCBREG,#WR_TX_CTRL
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ldy #WR_TX_CTRL
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jsr writeSCCReg
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: ldy RecvHead ; Get byte from buffer
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lda RecvBuf,y
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@ -597,8 +624,10 @@ SER_IOCTL:
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; was handled, otherwise with carry clear.
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SER_IRQ:
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ldx #$00 ; IRQ status is always in A reg
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rra SCCAREG,#RR_INTR_PENDING_STATUS
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ldx #$01 ; IRQ status is always in A reg
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ldy #RR_INTR_PENDING_STATUS
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jsr readSSCReg
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and CurChanIrqFlags ; Is this ours?
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beq Done
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@ -620,7 +649,8 @@ SER_IRQ:
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CheckSpecial:
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; Always check IRQ special flags from Channel B (Ref page 5-24)
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; X is still 0 there.
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rra SCCBREG,#RR_IRQ_STATUS
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ldy #RR_IRQ_STATUS
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jsr readSSCReg
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and #IRQ_MASQ
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cmp #IRQ_SPECIAL
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@ -628,19 +658,28 @@ CheckSpecial:
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; Clear exint
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ldx Channel
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wrr SCCBREG,#WR_INIT_CTRL,#INIT_CTRL_CLEAR_EIRQ
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ldy #WR_INIT_CTRL
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lda #INIT_CTRL_CLEAR_EIRQ
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jsr writeSCCReg
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sec
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rts
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Flow: ldx Channel ; Assert flow control if buffer space too low
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ldy #WR_TX_CTRL
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lda RtsOff
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wra SCCBREG,#WR_TX_CTRL
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jsr writeSCCReg
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sta Stopped
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sec ; Interrupt handled
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Done: rts
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Special:
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rra SCCBREG,#RR_SPEC_COND_STATUS
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Special:ldx Channel
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ldy #RR_SPEC_COND_STATUS
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jsr readSSCReg
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tax
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and #SPEC_COND_FRAMING_ERR
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bne BadChar
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@ -648,7 +687,10 @@ Special:
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and #SPEC_COND_OVERRUN_ERR
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beq BadChar
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wrr SCCBREG,#WR_INIT_CTRL,#INIT_CTRL_CLEAR_ERR
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ldy #WR_INIT_CTRL
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lda #INIT_CTRL_CLEAR_ERR
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jsr writeSCCReg
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sec
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rts
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@ -669,14 +711,19 @@ Again: lda SendFreeCnt ; Anything to send?
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lda Stopped ; Check for flow stopped
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bne Quit ; Bail out if it is
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Wait:
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lda SCCBREG,x ; Check that we're ready to send
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tay
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and #INIT_STATUS_READY
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bne Send
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beq NotReady
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tya
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and #INIT_STATUS_RTS ; Ready to send
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bne Send
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NotReady:
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bit tmp1 ; Keep trying if must try hard
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bmi Again
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bmi Wait
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Quit: rts
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Send: ldy SendHead ; Send byte
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