mirror of
https://github.com/cc65/cc65.git
synced 2025-01-01 03:30:20 +00:00
Cleanup coding style a bit
This commit is contained in:
Colin Leroy-Mira
Oliver Schmidt
parent
4ff917816e
commit
df4902157a
@ -38,8 +38,8 @@
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.endif
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; Driver signature
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.byte $73, $65, $72 ; "ser"
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.byte SER_API_VERSION ; Serial API version number
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.byte $73, $65, $72 ; "ser"
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.byte SER_API_VERSION ; Serial API version number
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; Library reference
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.addr $0000
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@ -59,16 +59,16 @@
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; I/O definitions
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.if (.cpu .bitand CPU_ISET_65C02)
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ACIA = $C088
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ACIA := $C088
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.else
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Offset = $8F ; Move 6502 false read out of I/O to page $BF
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ACIA = $C088-Offset
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ACIA := $C088-Offset
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.endif
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ACIA_DATA = ACIA+0 ; Data register
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ACIA_STATUS = ACIA+1 ; Status register
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ACIA_CMD = ACIA+2 ; Command register
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ACIA_CTRL = ACIA+3 ; Control register
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ACIA_DATA := ACIA+0 ; Data register
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ACIA_STATUS := ACIA+1 ; Status register
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ACIA_CMD := ACIA+2 ; Command register
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ACIA_CTRL := ACIA+3 ; Control register
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;----------------------------------------------------------------------------
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; Global variables
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@ -77,16 +77,17 @@ ACIA_CTRL = ACIA+3 ; Control register
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RecvHead: .res 1 ; Head of receive buffer
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RecvTail: .res 1 ; Tail of receive buffer
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RecvFreeCnt: .res 1 ; Number of bytes in receive buffer
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RecvFreeCnt: .res 1 ; Number of free bytes in receive buffer
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SendHead: .res 1 ; Head of send buffer
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SendTail: .res 1 ; Tail of send buffer
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SendFreeCnt: .res 1 ; Number of bytes in send buffer
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SendFreeCnt: .res 1 ; Number of free bytes in send buffer
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Stopped: .res 1 ; Flow-stopped flag
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RtsOff: .res 1 ;
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RtsOff: .res 1 ; Cached value of command register with
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; flow stopped
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RecvBuf: .res 256 ; Receive buffers: 256 bytes
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SendBuf: .res 256 ; Send buffers: 256 bytes
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RecvBuf: .res 256 ; Receive buffer: 256 bytes
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SendBuf: .res 256 ; Send buffer: 256 bytes
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Index: .res 1 ; I/O register index
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@ -96,8 +97,9 @@ Slot: .byte $02 ; Default to SSC in slot 2
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.rodata
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; Tables used to translate RS232 params into register values
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BaudTable: ; bit7 = 1 means setting is invalid
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BaudTable: ; Table used to translate RS232 baudrate param
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; into control register value
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; bit7 = 1 means setting is invalid
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.byte $FF ; SER_BAUD_45_5
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.byte $01 ; SER_BAUD_50
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.byte $02 ; SER_BAUD_75
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@ -118,49 +120,55 @@ BaudTable: ; bit7 = 1 means setting is invalid
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.byte $FF ; SER_BAUD_57600
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.byte $FF ; SER_BAUD_115200
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.byte $FF ; SER_BAUD_230400
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BitTable:
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BitTable: ; Table used to translate RS232 databits param
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; into control register value
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.byte $60 ; SER_BITS_5
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.byte $40 ; SER_BITS_6
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.byte $20 ; SER_BITS_7
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.byte $00 ; SER_BITS_8
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StopTable:
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StopTable: ; Table used to translate RS232 stopbits param
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; into control register value
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.byte $00 ; SER_STOP_1
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.byte $80 ; SER_STOP_2
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ParityTable:
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ParityTable: ; Table used to translate RS232 parity param
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; into command register value
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.byte $00 ; SER_PAR_NONE
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.byte $20 ; SER_PAR_ODD
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.byte $60 ; SER_PAR_EVEN
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.byte $A0 ; SER_PAR_MARK
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.byte $E0 ; SER_PAR_SPACE
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; Check five bytes at known positions on the
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; slot's firmware to make sure this is an SSC
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; (or Apple //c comm port) firmware that drives
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; an ACIA 6551 chip.
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;
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; The SSC firmware and the Apple //c(+) comm
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; port firmware all begin with a BIT instruction.
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; The IIgs, on the other hand, has a
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; Zilog Z8530 chip and its firmware starts with
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; a SEP instruction. We don't want to load this
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; driver on the IIgs' serial port. We'll
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; differentiate the firmware on this byte.
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;
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; The next four bytes we check are the Pascal
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; Firmware Protocol Bytes that identify a
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; serial card. Those are the same bytes for
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; SSC firmwares, Apple //c firmwares and IIgs
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; Zilog Z8530 firmwares - which is the reason
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; we have to check for the firmware's first
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; instruction too.
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IdOfsTable:
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IdOfsTable: ; Table of bytes positions, used to check five
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; specific bytes on the slot's firmware to make
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; sure this is an SSC (or Apple //c comm port)
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; firmware that drives an ACIA 6551 chip.
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;
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; The SSC firmware and the Apple //c(+) comm
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; port firmware all begin with a BIT instruction.
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; The IIgs, on the other hand, has a
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; Zilog Z8530 chip and its firmware starts with
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; a SEP instruction. We don't want to load this
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; driver on the IIgs' serial port. We'll
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; differentiate the firmware on this byte.
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;
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; The next four bytes we check are the Pascal
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; Firmware Protocol Bytes that identify a
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; serial card. Those are the same bytes for
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; SSC firmwares, Apple //c firmwares and IIgs
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; Zilog Z8530 firmwares - which is the reason
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; we have to check for the firmware's first
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; instruction too.
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.byte $00 ; First instruction
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.byte $05 ; Pascal 1.0 ID byte
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.byte $07 ; Pascal 1.0 ID byte
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.byte $0B ; Pascal 1.1 generic signature byte
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.byte $0C ; Device signature byte
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IdValTable:
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IdValTable: ; Table of expected values for the five checked
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; bytes
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.byte $2C ; BIT
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.byte $38 ; ID Byte 0 (from Pascal 1.0), fixed
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.byte $18 ; ID Byte 1 (from Pascal 1.0), fixed
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@ -193,12 +201,10 @@ SER_CLOSE:
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ldx Index ; Check for open port
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beq :+
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; Deactivate DTR and disable 6551 interrupts
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lda #%00001010
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lda #%00001010 ; Deactivate DTR and disable 6551 interrupts
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sta ACIA_CMD,x
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; Done, return an error code
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: lda #SER_ERR_OK
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: lda #SER_ERR_OK ; Done, return an error code
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.assert SER_ERR_OK = 0, error
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tax
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stx Index ; Mark port as closed
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@ -215,98 +221,96 @@ SER_OPEN:
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ora Slot
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sta ptr2+1
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; Check Pascal 1.1 Firmware Protocol ID bytes
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: ldy IdOfsTable,x
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: ldy IdOfsTable,x ; Check Pascal 1.1 Firmware Protocol ID bytes
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lda IdValTable,x
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cmp (ptr2),y
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bne NoDevice
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bne NoDev
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inx
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cpx #IdTableLen
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bcc :-
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; Convert slot to I/O register index
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lda Slot
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lda Slot ; Convert slot to I/O register index
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asl
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asl
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asl
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asl
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.if .not (.cpu .bitand CPU_ISET_65C02)
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adc #Offset ; Assume carry to be clear
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adc #Offset ; Assume carry to be clear
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.endif
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tax
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; Check if the handshake setting is valid
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ldy #SER_PARAMS::HANDSHAKE ; Handshake
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ldy #SER_PARAMS::HANDSHAKE
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lda (ptr1),y
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cmp #SER_HS_HW ; This is all we support
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bne InvParam
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cmp #SER_HS_HW ; This is all we support
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bne InvParm
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; Initialize buffers
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ldy #$00
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ldy #$00 ; Initialize buffers
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sty Stopped
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sty RecvHead
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sty RecvTail
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sty SendHead
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sty SendTail
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dey ; Y = 255
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dey ; Y = 255
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sty RecvFreeCnt
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sty SendFreeCnt
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; Set the value for the control register, which contains stop bits,
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; word length and the baud rate.
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ldy #SER_PARAMS::BAUDRATE
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lda (ptr1),y ; Baudrate index
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lda (ptr1),y ; Baudrate index
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tay
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lda BaudTable,y ; Get 6551 value
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bmi InvBaud ; Branch if rate not supported
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lda BaudTable,y ; Get 6551 value
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bmi InvBaud ; Branch if rate not supported
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sta tmp1
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ldy #SER_PARAMS::DATABITS ; Databits
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lda (ptr1),y
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ldy #SER_PARAMS::DATABITS
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lda (ptr1),y ; Databits index
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tay
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lda BitTable,y
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lda BitTable,y ; Get 6551 value
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ora tmp1
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sta tmp1
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ldy #SER_PARAMS::STOPBITS ; Stopbits
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lda (ptr1),y
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ldy #SER_PARAMS::STOPBITS
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lda (ptr1),y ; Stopbits index
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tay
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lda StopTable,y
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lda StopTable,y ; Get 6551 value
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ora tmp1
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ora #%00010000 ; Receiver clock source = baudrate
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ora #%00010000 ; Set receiver clock source = baudrate
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sta ACIA_CTRL,x
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; Set the value for the command register. We remember the base value
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; in RtsOff, since we will have to manipulate ACIA_CMD often.
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ldy #SER_PARAMS::PARITY ; Parity
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lda (ptr1),y
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ldy #SER_PARAMS::PARITY
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lda (ptr1),y ; Parity index
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tay
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lda ParityTable,y
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ora #%00000001 ; DTR active
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sta RtsOff
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ora #%00001000 ; Enable receive interrupts
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lda ParityTable,y ; Get 6551 value
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ora #%00000001 ; Set DTR active
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sta RtsOff ; Store value to easily handle flow control later
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ora #%00001000 ; Enable receive interrupts (RTS low)
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sta ACIA_CMD,x
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; Done
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stx Index ; Mark port as open
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stx Index ; Mark port as open
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lda #SER_ERR_OK
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.assert SER_ERR_OK = 0, error
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tax
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rts
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; Device (hardware) not found
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NoDevice:lda #SER_ERR_NO_DEVICE
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ldx #0 ; return value is char
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NoDev: lda #SER_ERR_NO_DEVICE
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ldx #$00 ; return value is char
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rts
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; Invalid parameter
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InvParam:lda #SER_ERR_INIT_FAILED
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ldx #0 ; return value is char
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InvParm:lda #SER_ERR_INIT_FAILED
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ldx #$00 ; return value is char
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rts
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; Baud rate not available
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InvBaud:lda #SER_ERR_BAUD_UNAVAIL
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ldx #0 ; return value is char
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ldx #$00 ; return value is char
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rts
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;----------------------------------------------------------------------------
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@ -317,21 +321,19 @@ InvBaud:lda #SER_ERR_BAUD_UNAVAIL
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SER_GET:
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ldx Index
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; Check for buffer empty
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lda RecvFreeCnt ; (25)
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lda RecvFreeCnt ; Check for buffer empty
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cmp #$FF
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bne :+
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lda #SER_ERR_NO_DATA
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ldx #0 ; return value is char
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ldx #$00 ; return value is char
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rts
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; Check for flow stopped & enough free: release flow control
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: ldy Stopped ; (34)
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: ldy Stopped ; Check for flow stopped
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beq :+
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cmp #63
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cmp #63 ; Enough free?
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bcc :+
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.if (.cpu .bitand CPU_ISET_65C02)
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stz Stopped
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stz Stopped ; Release flow control
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.else
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lda #$00
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sta Stopped
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@ -340,14 +342,13 @@ SER_GET:
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ora #%00001000
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sta ACIA_CMD,x
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; Get byte from buffer
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: ldy RecvHead ; (41)
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: ldy RecvHead ; Get byte from buffer
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lda RecvBuf,y
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inc RecvHead
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inc RecvFreeCnt
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ldx #$00 ; (59)
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ldx #$00
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.if (.cpu .bitand CPU_ISET_65C02)
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sta (ptr1)
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sta (ptr1) ; Store it for caller
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.else
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sta (ptr1,x)
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.endif
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@ -361,29 +362,26 @@ SER_GET:
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SER_PUT:
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ldx Index
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; Try to send
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ldy SendFreeCnt
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cpy #$FF ; Nothing to flush
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ldy SendFreeCnt ; Anything to send first?
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cpy #$FF ; No
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beq :+
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pha
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lda #$00 ; TryHard = false
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jsr TryToSend
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jsr TryToSend ; Try to flush send buffer
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pla
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; Reload SendFreeCnt after TryToSend
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ldy SendFreeCnt
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ldy SendFreeCnt ; Reload SendFreeCnt after TryToSend
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bne :+
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lda #SER_ERR_OVERFLOW
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ldx #0 ; return value is char
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ldx #$00 ; return value is char
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rts
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; Put byte into send buffer & send
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: ldy SendTail
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: ldy SendTail ; Put byte into send buffer
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sta SendBuf,y
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inc SendTail
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dec SendFreeCnt
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lda #$FF ; TryHard = true
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jsr TryToSend
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jsr TryToSend ; Flush send buffer
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lda #SER_ERR_OK
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.assert SER_ERR_OK = 0, error
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tax
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@ -405,26 +403,25 @@ SER_STATUS:
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;----------------------------------------------------------------------------
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; SER_IOCTL: Driver defined entry point. The wrapper will pass a pointer to ioctl
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; specific data in ptr1, and the ioctl code in A.
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; The ioctl data is the slot number to open.
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; Must return an SER_ERR_xx code in a/x.
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SER_IOCTL:
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; Check data msb and code to be 0
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ora ptr1+1
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ora ptr1+1 ; Check data msb and code to be 0
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bne :+
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; Check data lsb to be [1..7]
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ldx ptr1
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ldx ptr1 ; Check data lsb to be [1..7]
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beq :+
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cpx #7+1
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bcs :+
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stx Slot
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stx Slot ; Store slot
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.assert SER_ERR_OK = 0, error
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tax
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rts
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: lda #SER_ERR_INV_IOCTL
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ldx #0 ; return value is char
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ldx #$00 ; return value is char
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rts
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;----------------------------------------------------------------------------
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@ -450,8 +447,7 @@ SER_IRQ:
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bcc Flow ; Assert flow control if buffer space low
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rts ; Interrupt handled (carry already set)
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; Assert flow control if buffer space too low
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Flow: ldx Index
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Flow: ldx Index ; Assert flow control if buffer space too low
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lda RtsOff
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sta ACIA_CMD,x
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sta Stopped
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@ -464,26 +460,23 @@ Done: rts
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TryToSend:
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sta tmp1 ; Remember tryHard flag
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NextByte:
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lda SendFreeCnt
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cmp #$FF
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beq Quit ; Bail out
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lda SendFreeCnt ; Is there anything to send? This can happen if
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cmp #$FF ; we got interrupted by RX while sending, and
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beq Quit ; flow control was asserted.
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; Check for flow stopped
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Again: lda Stopped
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bne Quit ; Bail out
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Again: lda Stopped ; Is flow stopped?
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bne Quit ; Yes, Bail out
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; Check that ACIA is ready to send
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lda ACIA_STATUS,x
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lda ACIA_STATUS,x ; Check that ACIA is ready to send
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and #$10
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bne Send
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bne Send ; It is!
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bit tmp1 ; Keep trying if must try hard
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bmi Again
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Quit: rts
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; Send byte and try again
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Send: ldy SendHead
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Send: ldy SendHead ; Get first byte to send
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lda SendBuf,y
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sta ACIA_DATA,x
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sta ACIA_DATA,x ; Send it
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inc SendHead
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inc SendFreeCnt
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jmp NextByte
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jmp NextByte ; And try next one
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