mirror of
https://github.com/cc65/cc65.git
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Mikey enumeration values for cc65 include files and new bit definitions for ca65
This commit is contained in:
Alex Thissen
Alex Thissen
parent
394d3b1964
commit
eb6003aaf7
347
asminc/lynx.inc
347
asminc/lynx.inc
@ -83,7 +83,7 @@ MATHJ = $FC6F
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SPRCTL0 = $FC80
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SPRCTL0 = $FC80
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; Sprite bits-per-pixel definitions
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; Sprite bits-per-pixel definitions
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BPP_MASK = %11000000 ; Mask for settings bits per pixel
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BPP_MASK = %11000000 ; Mask for settings bits per pixel
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BPP_1 = %00000000
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BPP_1 = %00000000
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BPP_2 = %01000000
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BPP_2 = %01000000
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BPP_3 = %10000000
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BPP_3 = %10000000
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@ -94,23 +94,23 @@ VFLIP = %00010000
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; Sprite types - redefined to reflect the reality caused by the shadow error
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; Sprite types - redefined to reflect the reality caused by the shadow error
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TYPE_SHADOW = %00000111
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TYPE_SHADOW = %00000111
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TYPE_XOR = %00000110
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TYPE_XOR = %00000110
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TYPE_NONCOLL = %00000101 ; Non-colliding
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TYPE_NONCOLL = %00000101 ; Non-colliding
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TYPE_NORMAL = %00000100
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TYPE_NORMAL = %00000100
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TYPE_BOUNDARY = %00000011
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TYPE_BOUNDARY = %00000011
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TYPE_BSHADOW = %00000010 ; Background shadow
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TYPE_BSHADOW = %00000010 ; Background shadow
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TYPE_BACKNONCOLL = %00000001 ; Background non-colliding
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TYPE_BACKNONCOLL = %00000001 ; Background non-colliding
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TYPE_BACKGROUND = %00000000
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TYPE_BACKGROUND = %00000000
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SPRCTL1 = $FC81
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SPRCTL1 = $FC81
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LITERAL = %10000000
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LITERAL = %10000000
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PACKED = %00000000
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PACKED = %00000000
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ALGO3 = %01000000 ; Broken, do not set this bit!
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ALGO3 = %01000000 ; Broken, do not set this bit!
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; Sprite reload mask definitions
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; Sprite reload mask definitions
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RELOAD_MASK = %00110000
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RELOAD_MASK = %00110000
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RENONE = %00000000 ; Reload nothing
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RENONE = %00000000 ; Reload nothing
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REHV = %00010000 ; Reload hsize, vsize
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REHV = %00010000 ; Reload hsize, vsize
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REHVS = %00100000 ; Reload hsize, vsize, stretch
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REHVS = %00100000 ; Reload hsize, vsize, stretch
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REHVST = %00110000 ; Reload hsize, vsize, stretch, tilt
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REHVST = %00110000 ; Reload hsize, vsize, stretch, tilt
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; More sprite control 1 bit definitions
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; More sprite control 1 bit definitions
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REUSEPAL = %00001000
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REUSEPAL = %00001000
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SKIP = %00000100
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SKIP = %00000100
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@ -138,8 +138,9 @@ HOWIE = $FCC4
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; *** Mikey Addresses
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; *** Mikey Addresses
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; ***
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; ***
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; Mikey Timers
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; Mikey timers
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; Logical timer names
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TIMER0 = $FD00
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TIMER0 = $FD00
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TIMER1 = $FD04
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TIMER1 = $FD04
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TIMER2 = $FD08
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TIMER2 = $FD08
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@ -148,20 +149,20 @@ TIMER4 = $FD10
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TIMER5 = $FD14
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TIMER5 = $FD14
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TIMER6 = $FD18
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TIMER6 = $FD18
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TIMER7 = $FD1C
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TIMER7 = $FD1C
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HTIMER = $FD00 ; horizontal line timer (timer 0)
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HTIMER = TIMER0 ; horizontal line timer (timer 0)
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VTIMER = $FD08 ; vertical blank timer (timer 2)
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VTIMER = TIMER2 ; vertical blank timer (timer 2)
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STIMER = $FD1C ; sound timer (timer 7)
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STIMER = TIMER7 ; sound timer (timer 7)
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HTIMBKUP = $FD00 ; horizontal line timer (timer 0)
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HTIMBKUP = $FD00 ; horizontal line timer (timer 0)
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HTIMCTLA = $FD01
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HTIMCTLA = $FD01
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HTIMCNT = $FD02
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HTIMCNT = $FD02
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HTIMCTLB = $FD03
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HTIMCTLB = $FD03
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VTIMBKUP = $FD08 ; vertical blank timer (timer 2)
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VTIMBKUP = $FD08 ; vertical blank timer (timer 2)
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VTIMCTLA = $FD09
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VTIMCTLA = $FD09
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VTIMCNT = $FD0A
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VTIMCNT = $FD0A
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VTIMCTLB = $FD0B
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VTIMCTLB = $FD0B
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BAUDBKUP = $FD10 ; serial timer (timer 4)
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BAUDBKUP = $FD10 ; serial timer (timer 4)
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STIMBKUP = $FD1C ; sound timer (timer 7)
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STIMBKUP = $FD1C ; sound timer (timer 7)
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STIMCTLA = $FD1D
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STIMCTLA = $FD1D
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STIMCNT = $FD1E
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STIMCNT = $FD1E
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STIMCTLB = $FD1F
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STIMCTLB = $FD1F
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@ -199,129 +200,227 @@ TIM7CTLA = $FD1D
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TIM7CNT = $FD1E
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TIM7CNT = $FD1E
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TIM7CTLB = $FD1F
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TIM7CTLB = $FD1F
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; Timer offsets
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TIM_BACKUP = 0
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TIM_CONTROLA = 1
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TIM_COUNT = 2
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TIM_CONTROLB = 3
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; TIM_CONTROLA control bits
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ENABLE_INT = %10000000
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RESET_DONE = %01000000
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ENABLE_RELOAD = %00010000
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ENABLE_COUNT = %00001000
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AUD_CLOCK_MASK = %00000111
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; Clock settings
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AUD_LINKING = %00000111
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AUD_64 = %00000110
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AUD_32 = %00000101
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AUD_16 = %00000100
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AUD_8 = %00000011
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AUD_4 = %00000010
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AUD_2 = %00000001
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AUD_1 = %00000000
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; TIM_CONTROLB control bits
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TIMER_DONE = %00001000
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LAST_CLOCK = %00000100
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BORROW_IN = %00000010
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BORROW_OUT = %00000001
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; Mikey Audio
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; Mikey Audio
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AUDIO0 = $FD20 ; audio channel 0
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AUDIO0 = $FD20 ; audio channel 0
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AUDIO1 = $FD28 ; audio channel 1
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AUDIO1 = $FD28 ; audio channel 1
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AUDIO2 = $FD30 ; audio channel 2
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AUDIO2 = $FD30 ; audio channel 2
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AUDIO3 = $FD38 ; audio channel 3
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AUDIO3 = $FD38 ; audio channel 3
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AUD0VOL = $FD20
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AUD0VOL = $FD20
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AUD0FEED = $FD21
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AUD0FEED = $FD21
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AUD0OUT = $FD22
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AUD0OUT = $FD22
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AUD0SHIFT = $FD23
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AUD0SHIFT = $FD23
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AUD0BKUP = $FD24
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AUD0BKUP = $FD24
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AUD0CTLA = $FD25
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AUD0CTLA = $FD25
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AUD0CNT = $FD26
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AUD0CNT = $FD26
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AUD0CTLB = $FD27
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AUD0CTLB = $FD27
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AUD1VOL = $FD28
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AUD1VOL = $FD28
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AUD1FEED = $FD29
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AUD1FEED = $FD29
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AUD1OUT = $FD2A
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AUD1OUT = $FD2A
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AUD1SHIFT = $FD2B
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AUD1SHIFT = $FD2B
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AUD1BKUP = $FD2C
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AUD1BKUP = $FD2C
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AUD1CTLA = $FD2D
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AUD1CTLA = $FD2D
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AUD1CNT = $FD2E
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AUD1CNT = $FD2E
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AUD1CTLB = $FD2F
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AUD1CTLB = $FD2F
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AUD2VOL = $FD30
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AUD2VOL = $FD30
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AUD2FEED = $FD31
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AUD2FEED = $FD31
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AUD2OUT = $FD32
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AUD2OUT = $FD32
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AUD2SHIFT = $FD33
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AUD2SHIFT = $FD33
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AUD2BKUP = $FD34
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AUD2BKUP = $FD34
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AUD2CTLA = $FD35
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AUD2CTLA = $FD35
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AUD2CNT = $FD36
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AUD2CNT = $FD36
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AUD2CTLB = $FD37
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AUD2CTLB = $FD37
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AUD3VOL = $FD38
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AUD3VOL = $FD38
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AUD3FEED = $FD39
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AUD3FEED = $FD39
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AUD3OUT = $FD3A
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AUD3OUT = $FD3A
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AUD3SHIFT = $FD3B
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AUD3SHIFT = $FD3B
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AUD3BKUP = $FD3C
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AUD3BKUP = $FD3C
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AUD3CTLA = $FD3D
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AUD3CTLA = $FD3D
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AUD3CNT = $FD3E
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AUD3CNT = $FD3E
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AUD3CTLB = $FD3F
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AUD3CTLB = $FD3F
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; AUD_CONTROL bits are almost identical to TIM_CONTROLA bits.
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; See TIM_CONTROLA above for the other definitions
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FEEDBACK_7 = %10000000
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ENABLE_INTEGRATE = %00100000
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; Stereo control registers follow
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; Stereo capability does not exist in all Lynxes
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; Left and right may be reversed, and if so will be corrected in a later
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; release
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ATTENREG0 = $FD40 ; Stereo attenuation registers
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ATTENREG1 = $FD41
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ATTENREG2 = $FD42
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ATTENREG3 = $FD43
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LEFT_ATTENMASK = %11110000
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RIGHT_ATTENMASK = %00001111
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; Bit definitions for MPAN and MSTEREO registers
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LEFT3_SELECT = %10000000
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LEFT2_SELECT = %01000000
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LEFT1_SELECT = %00100000
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LEFT0_SELECT = %00010000
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RIGHT3_SELECT = %00001000
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RIGHT2_SELECT = %00000100
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RIGHT1_SELECT = %00000010
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RIGHT0_SELECT = %00000001
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MPAN = $FD44
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MSTEREO = $FD50
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MSTEREO = $FD50
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; Mikey Misc
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; Mikey interrupts
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; Interrupt bits in INTRST and INTSET
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TIMER0_INTERRUPT = $01
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TIMER1_INTERRUPT = $02
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TIMER2_INTERRUPT = $04
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TIMER3_INTERRUPT = $08
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TIMER4_INTERRUPT = $10
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TIMER5_INTERRUPT = $20
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TIMER6_INTERRUPT = $40
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TIMER7_INTERRUPT = $80
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HBL_INTERRUPT = TIMER0_INTERRUPT
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VBL_INTERRUPT = TIMER2_INTERRUPT
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SERIAL_INTERRUPT = TIMER4_INTERRUPT
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SND_INTERRUPT = TIMER7_INTERRUPT
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INTRST = $FD80
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INTRST = $FD80
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INTSET = $FD81
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INTSET = $FD81
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MAGRDY0 = $FD84
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; Interrupt bits in INTRST and INTSET
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MAGRDY1 = $FD85
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TIMER0_INTERRUPT = %00000001
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AUDIN = $FD86
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TIMER1_INTERRUPT = %00000010
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SYSCTL1 = $FD87
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TIMER2_INTERRUPT = %00000100
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MIKEYHREV = $FD88
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TIMER3_INTERRUPT = %00001000
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MIKEYSREV = $FD89
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TIMER4_INTERRUPT = %00010000
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TIMER5_INTERRUPT = %00100000
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TIMER6_INTERRUPT = %01000000
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TIMER7_INTERRUPT = %10000000
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IODIR = $FD8A
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HBL_INTERRUPT = TIMER0_INTERRUPT
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IODAT = $FD8B
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VBL_INTERRUPT = TIMER2_INTERRUPT
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SERIAL_INTERRUPT = TIMER4_INTERRUPT
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SND_INTERRUPT = TIMER7_INTERRUPT
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MAGRDY0 = $FD84
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MAGRDY1 = $FD85
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AUDIN = $FD86
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SYSCTL1 = $FD87
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; SYSCTL1 bit definitions
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POWERON = %00000010
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CART_ADDR_STROBE = %00000001
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MIKEYHREV = $FD88
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MIKEYSREV = $FD89
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IODIR = $FD8A
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IODAT = $FD8B
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; IODIR and IODAT bit definitions
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; IODIR and IODAT bit definitions
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AUDIN_BIT = $10 ; Note that there is also the address AUDIN
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AUDIN_BIT = %00010000 ; Note that there is also the address AUDIN
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READ_ENABLE = $10 ; Same bit for AUDIN_BIT
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READ_ENABLE = %00010000 ; Same bit for AUDIN_BIT
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RESTLESS = $08
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RESTLESS = %00001000
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NOEXP = $04 ; If set, redeye is not connected
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NOEXP = %00000100 ; If set, redeye is not connected
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CART_ADDR_DATA = $02
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CART_ADDR_DATA = %00000010
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CART_POWER_OFF = $02 ; Same bit for CART_ADDR_DATA
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CART_POWER_OFF = %00000010 ; Same bit for CART_ADDR_DATA
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EXTERNAL_POWER = $01
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EXTERNAL_POWER = %00000001
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SERCTL = $FD8C
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SERCTL = $FD8C
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; SERCTL bit definitions for write operations
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; SERCTL bit definitions for write operations
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TXINTEN = $80
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TXINTEN = %10000000
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RXINTEN = $40
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RXINTEN = %01000000
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PAREN = $10
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PAREN = %00010000
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RESETERR = $08
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RESETERR = %00001000
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TXOPEN = $04
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TXOPEN = %00000100
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TXBRK = $02
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TXBRK = %00000010
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PAREVEN = $01
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PAREVEN = %00000001
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; SERCTL bit definitions for read operations
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; SERCTL bit definitions for read operations
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TXRDY = $80
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TXRDY = %10000000
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RXRDY = $40
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RXRDY = %01000000
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TXEMPTY = $20
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TXEMPTY = %00100000
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PARERR = $10
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PARERR = %00010000
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OVERRUN = $08
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OVERRUN = %00001000
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FRAMERR = $04
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FRAMERR = %00000100
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RXBRK = $02
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RXBRK = %00000010
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PARBIT = $01
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PARBIT = %00000001
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SERDAT = $FD8D
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SERDAT = $FD8D
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SDONEACK = $FD90
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SDONEACK = $FD90
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CPUSLEEP = $FD91
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CPUSLEEP = $FD91
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DISPCTL = $FD92
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DISPCTL = $FD92
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PBKUP = $FD93
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; DISPCTL bit definitions
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DISPADRL = $FD94
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DISP_COLOR = %10000000 ; must be set to 1
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DISPADRH = $FD95
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DISP_FOURBIT = %01000000 ; must be set to 1
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MTEST0 = $FD9C
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DISP_FLIP = %00100000
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MTEST1 = $FD9D
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DMA_ENABLE = %00010000 ; must be set to 1
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MTEST2 = $FD9E
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PALETTE = $FDA0 ; hardware rgb palette
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GCOLMAP = $FDA0 ; hardware rgb palette (green)
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RBCOLMAP = $FDB0 ; hardware rgb palette (red-blue)
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PBKUP = $FD93
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DISPADRL = $FD94
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DISPADRH = $FD95
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; ***
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MTEST0 = $FD9C
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; *** Misc Hardware + 6502 vectors
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; MTEST0 bit definitions
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; ***
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AT_CNT16 = %10000000
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AT_TEST = %01000000
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XCLKEN = %00100000
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UART_TURBO = %00010000
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ROM_SEL = %00001000
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ROM_TEST = %00000100
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M_TEST = %00000010
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CPU_TEST = %00000001
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MAPCTL = $FFF9
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MTEST1 = $FD9D
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VECTORS = $FFFB
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; MTEST1 bit definitions
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INTVECTL = $FFFE
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P_CNT16 = %01000000
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INTVECTH = $FFFF
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REF_CNT16 = %00100000
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RSTVECTL = $FFFC
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VID_TRIG = %00010000
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RSTVECTH = $FFFD
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REF_TRIG = %00001000
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NMIVECTL = $FFFA
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VID_DMA_DIS = %00000100
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NMIVECTH = $FFFB
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REF_FAST = %00000010
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REF_DIS = %00000001
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MTEST2 = $FD9E
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; MTEST2 bit definitions
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V_STROBE = %00010000
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V_ZERO = %00001000
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H_120 = %00000100
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H_ZERO = %00000010
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V_BLANKEF = %00000001
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PALETTE = $FDA0 ; hardware rgb palette
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GCOLMAP = $FDA0 ; hardware rgb palette (green)
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RBCOLMAP = $FDB0 ; hardware rgb palette (red-blue)
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; Memory mapping control and 6502 vectors
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MAPCTL = $FFF9
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; MAPCTL bit definitions
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TURBO_DISABLE = %10000000
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VECTOR_SPACE = %00001000 ; 1 maps RAM into specified space
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ROM_SPACE = %00000100
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MIKEY_SPACE = %00000010
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SUZY_SPACE = %00000001
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VECTORS = $FFFB
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INTVECTL = $FFFE
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INTVECTH = $FFFF
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RSTVECTL = $FFFC
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RSTVECTH = $FFFD
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NMIVECTL = $FFFA
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NMIVECTH = $FFFB
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255
include/_mikey.h
255
include/_mikey.h
@ -27,7 +27,7 @@
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#ifndef __MIKEY_H
|
#ifndef __MIKEY_H
|
||||||
#define __MIKEY_H
|
#define __MIKEY_H
|
||||||
|
|
||||||
/* timer structure */
|
/* Timer structure */
|
||||||
typedef struct _mikey_timer {
|
typedef struct _mikey_timer {
|
||||||
unsigned char reload;
|
unsigned char reload;
|
||||||
unsigned char control;
|
unsigned char control;
|
||||||
@ -39,7 +39,7 @@ typedef struct _mikey_all_timers {
|
|||||||
struct _mikey_timer timer[8];
|
struct _mikey_timer timer[8];
|
||||||
} _mikey_all_timers;
|
} _mikey_all_timers;
|
||||||
|
|
||||||
/* audio channel structure */
|
/* Audio channel structure */
|
||||||
typedef struct _mikey_audio {
|
typedef struct _mikey_audio {
|
||||||
unsigned char volume;
|
unsigned char volume;
|
||||||
unsigned char feedback;
|
unsigned char feedback;
|
||||||
@ -53,54 +53,213 @@ typedef struct _mikey_audio {
|
|||||||
|
|
||||||
/* Define a structure with the mikey register offsets */
|
/* Define a structure with the mikey register offsets */
|
||||||
struct __mikey {
|
struct __mikey {
|
||||||
struct _mikey_timer timer0; // 0xFD00
|
struct _mikey_timer timer0; // 0xFD00
|
||||||
struct _mikey_timer timer1; // 0xFD04
|
struct _mikey_timer timer1; // 0xFD04
|
||||||
struct _mikey_timer timer2; // 0xFD08
|
struct _mikey_timer timer2; // 0xFD08
|
||||||
struct _mikey_timer timer3; // 0xFD0C
|
struct _mikey_timer timer3; // 0xFD0C
|
||||||
struct _mikey_timer timer4; // 0xFD10
|
struct _mikey_timer timer4; // 0xFD10
|
||||||
struct _mikey_timer timer5; // 0xFD14
|
struct _mikey_timer timer5; // 0xFD14
|
||||||
struct _mikey_timer timer6; // 0xFD18
|
struct _mikey_timer timer6; // 0xFD18
|
||||||
struct _mikey_timer timer7; // 0xFD1C
|
struct _mikey_timer timer7; // 0xFD1C
|
||||||
struct _mikey_audio channel_a; // 0xFD20
|
struct _mikey_audio channel_a; // 0xFD20
|
||||||
struct _mikey_audio channel_b; // 0xFD28
|
struct _mikey_audio channel_b; // 0xFD28
|
||||||
struct _mikey_audio channel_c; // 0xFD30
|
struct _mikey_audio channel_c; // 0xFD30
|
||||||
struct _mikey_audio channel_d; // 0xFD38
|
struct _mikey_audio channel_d; // 0xFD38
|
||||||
unsigned char attena; // 0xFD40 ?? not yet allocated?
|
unsigned char attena; // 0xFD40 ?? not yet allocated?
|
||||||
unsigned char attenb; // 0xFD41 |
|
unsigned char attenb; // 0xFD41 |
|
||||||
unsigned char attenc; // 0xFD42 |
|
unsigned char attenc; // 0xFD42 |
|
||||||
unsigned char attend; // 0xFD43 |
|
unsigned char attend; // 0xFD43 |
|
||||||
unsigned char panning; // 0xFD44 |
|
unsigned char panning; // 0xFD44 |
|
||||||
unsigned char unused0[11]; // 0xFD45 - 0xFD4F not used
|
unsigned char unused0[11]; // 0xFD45 - 0xFD4F not used
|
||||||
unsigned char mstereo; // 0xFD50 stereo control bits
|
unsigned char mstereo; // 0xFD50 stereo control bits
|
||||||
unsigned char unused1[47]; // 0xFD51 - 0xFD7F not used
|
unsigned char unused1[47]; // 0xFD51 - 0xFD7F not used
|
||||||
unsigned char intrst; // 0xFD80 interrupt poll 0
|
unsigned char intrst; // 0xFD80 interrupt poll 0
|
||||||
unsigned char intset; // 0xFD81 interrupt poll 1
|
unsigned char intset; // 0xFD81 interrupt poll 1
|
||||||
unsigned char unused2[2]; // 0xFD82 - 0xFD83 not used
|
unsigned char unused2[2]; // 0xFD82 - 0xFD83 not used
|
||||||
unsigned char magrdy0; // 0xFD84 mag tape channel0 ready bit
|
unsigned char magrdy0; // 0xFD84 mag tape channel0 ready bit
|
||||||
unsigned char magrdy1; // 0xFD85 mag tape channel1 ready bit
|
unsigned char magrdy1; // 0xFD85 mag tape channel1 ready bit
|
||||||
unsigned char audin; // 0xFD86 audio in
|
unsigned char audin; // 0xFD86 audio in
|
||||||
unsigned char sysctl1; // 0xFD87 control bits
|
unsigned char sysctl1; // 0xFD87 control bits
|
||||||
unsigned char mikeyrev; // 0xFD88 mikey hardware rev
|
unsigned char mikeyrev; // 0xFD88 mikey hardware rev
|
||||||
unsigned char mikeysrev; // 0xFD89 mikey software rev
|
unsigned char mikeysrev; // 0xFD89 mikey software rev
|
||||||
unsigned char iodir; // 0xFD8A parallel i/o data dir
|
unsigned char iodir; // 0xFD8A parallel i/o data dir
|
||||||
unsigned char iodat; // 0xFD8B parallel data
|
unsigned char iodat; // 0xFD8B parallel data
|
||||||
unsigned char serctl; // 0xFD8C serial control register
|
unsigned char serctl; // 0xFD8C serial control register
|
||||||
unsigned char serdat; // 0xFD8D serial data
|
unsigned char serdat; // 0xFD8D serial data
|
||||||
unsigned char unused3[2]; // 0xFD8E - 0xFD8F not used
|
unsigned char unused3[2]; // 0xFD8E - 0xFD8F not used
|
||||||
unsigned char sdoneack; // 0xFD90 suzy done acknowledge
|
unsigned char sdoneack; // 0xFD90 suzy done acknowledge
|
||||||
unsigned char cpusleep; // 0xFD91 cpu bus request disable
|
unsigned char cpusleep; // 0xFD91 cpu bus request disable
|
||||||
unsigned char dispctl; // 0xFD92 video bus request enable, viddma
|
unsigned char dispctl; // 0xFD92 video bus request enable, viddma
|
||||||
unsigned char pkbkup; // 0xFD93 magic 'P' count
|
unsigned char pkbkup; // 0xFD93 magic 'P' count
|
||||||
unsigned char *scrbase; // 0xFD94 start address of video display
|
unsigned char *scrbase; // 0xFD94 start address of video display
|
||||||
unsigned char unused4[6]; // 0xFD96 - 0xFD9B not used
|
unsigned char unused4[6]; // 0xFD96 - 0xFD9B not used
|
||||||
unsigned char mtest0; // 0xFD9C
|
unsigned char mtest0; // 0xFD9C
|
||||||
unsigned char mtest1; // 0xFD9D
|
unsigned char mtest1; // 0xFD9D
|
||||||
unsigned char mtest2; // 0xFD9E
|
unsigned char mtest2; // 0xFD9E
|
||||||
unsigned char unused5; // 0xFD9F not used
|
unsigned char unused5; // 0xFD9F not used
|
||||||
unsigned char palette[32]; // 0xFDA0 - 0xFDBF palette 32 bytes
|
unsigned char palette[32]; // 0xFDA0 - 0xFDBF palette 32 bytes
|
||||||
// 0xFDC0 - 0xFDFF not used
|
unsigned char unused6[64]; // 0xFDC0 - 0xFDFF not used
|
||||||
|
unsigned char bootrom[504]; // 0xFE00 - 0xFFD8 boot rom
|
||||||
|
unsigned char reserved; // 0xFFD8 reserved for future hardware
|
||||||
|
unsigned char mapctl; // 0xFFF9 map control register
|
||||||
|
struct {
|
||||||
|
unsigned char *nmi; // 0xFFFA NMI vector
|
||||||
|
unsigned char *reset; // 0xFFFB reset vector
|
||||||
|
unsigned char *irq; // 0xFFFC IRQ vector
|
||||||
|
} vectors;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
// TIM_CONTROLA control bit definitions
|
||||||
|
enum {
|
||||||
|
ENABLE_INT = 0x80,
|
||||||
|
RESET_DONE = 0x40,
|
||||||
|
ENABLE_RELOAD = 0x10,
|
||||||
|
ENABLE_COUNT = 0x08
|
||||||
|
};
|
||||||
|
|
||||||
|
// AUD_CONTROL control bit definitions
|
||||||
|
enum {
|
||||||
|
FEEDBACK_7 = 0x80,
|
||||||
|
ENABLE_INTEGRATE = 0x20
|
||||||
|
};
|
||||||
|
|
||||||
|
// Audio and timer clock settings for source period
|
||||||
|
enum {
|
||||||
|
AUD_LINKING = 0x07,
|
||||||
|
AUD_64 = 0x06,
|
||||||
|
AUD_32 = 0x05,
|
||||||
|
AUD_16 = 0x04,
|
||||||
|
AUD_8 = 0x03,
|
||||||
|
AUD_4 = 0x02,
|
||||||
|
AUD_2 = 0x01,
|
||||||
|
AUD_1 = 0x00
|
||||||
|
};
|
||||||
|
|
||||||
|
// TIM_CONTROLB control bit definitions
|
||||||
|
enum {
|
||||||
|
TIMER_DONE = 0x08,
|
||||||
|
LAST_CLOCK = 0x04,
|
||||||
|
BORROW_IN = 0x02,
|
||||||
|
BORROW_OUT = 0x01
|
||||||
|
};
|
||||||
|
|
||||||
|
// MPAN and MSTEREO registers bit definitions
|
||||||
|
enum {
|
||||||
|
LEFT3_SELECT = 0x80,
|
||||||
|
LEFT2_SELECT = 0x40,
|
||||||
|
LEFT1_SELECT = 0x20,
|
||||||
|
LEFT0_SELECT = 0x10,
|
||||||
|
RIGHT3_SELECT = 0x08,
|
||||||
|
RIGHT2_SELECT = 0x04,
|
||||||
|
RIGHT1_SELECT = 0x02,
|
||||||
|
RIGHT0_SELECT = 0x01,
|
||||||
|
LEFT_ATTENMASK = 0xF0,
|
||||||
|
RIGHT_ATTENMASK = 0x0F
|
||||||
|
};
|
||||||
|
|
||||||
|
// Interrupt Reset and Set bit definitions
|
||||||
|
enum {
|
||||||
|
TIMER7_INT = 0x80,
|
||||||
|
TIMER6_INT = 0x40,
|
||||||
|
TIMER5_INT = 0x20,
|
||||||
|
TIMER4_INT = 0x10,
|
||||||
|
TIMER3_INT = 0x08,
|
||||||
|
TIMER2_INT = 0x04,
|
||||||
|
TIMER1_INT = 0x02,
|
||||||
|
TIMER0_INT = 0x01,
|
||||||
|
SERIAL_INT = TIMER4_INT,
|
||||||
|
VERTICAL_INT = TIMER2_INT,
|
||||||
|
HORIZONTAL_INT = TIMER0_INT
|
||||||
|
};
|
||||||
|
|
||||||
|
// SYSCTL1 bit definitions
|
||||||
|
enum {
|
||||||
|
POWERON = 0x02,
|
||||||
|
CART_ADDR_STROBE = 0x01
|
||||||
|
};
|
||||||
|
|
||||||
|
// IODIR and IODAT bit definitions
|
||||||
|
enum {
|
||||||
|
AUDIN_BIT = 0x10, // different from AUDIN address
|
||||||
|
READ_ENABLE = 0x10, // same bit for AUDIN_BIT
|
||||||
|
RESTLESS = 0x08,
|
||||||
|
NOEXP = 0x04, // if set, redeye is not connected
|
||||||
|
CART_ADDR_DATA = 0x02, //
|
||||||
|
CART_POWER_OFF = 0x02, // same bit for CART_ADDR_DATA
|
||||||
|
EXTERNAL_POWER = 0x01
|
||||||
|
};
|
||||||
|
|
||||||
|
// SERCTL bit definitions for write operations
|
||||||
|
enum {
|
||||||
|
TXINTEN = 0x80,
|
||||||
|
RXINTEN = 0x40,
|
||||||
|
PAREN = 0x10,
|
||||||
|
RESETERR = 0x08,
|
||||||
|
TXOPEN = 0x04,
|
||||||
|
TXBRK = 0x02,
|
||||||
|
PAREVEN = 0x01
|
||||||
|
};
|
||||||
|
|
||||||
|
// SERCTL bit definitions for read operations
|
||||||
|
enum {
|
||||||
|
TXRDY = 0x80,
|
||||||
|
RXRDY = 0x40,
|
||||||
|
TXEMPTY = 0x20,
|
||||||
|
PARERR = 0x10,
|
||||||
|
OVERRUN = 0x08,
|
||||||
|
FRAMERR = 0x04,
|
||||||
|
RXBRK = 0x02,
|
||||||
|
PARBIT = 0x01
|
||||||
|
};
|
||||||
|
|
||||||
|
// DISPCTL bit definitions
|
||||||
|
enum {
|
||||||
|
DISP_COLOR = 0x08, // must be set to 1
|
||||||
|
DISP_FOURBIT = 0x04, // must be set to 1
|
||||||
|
DISP_FLIP = 0x02, //
|
||||||
|
DMA_ENABLE = 0x01 // must be set to 1
|
||||||
|
};
|
||||||
|
|
||||||
|
// MTEST0 bit definitions
|
||||||
|
enum {
|
||||||
|
AT_CNT16 = 0x80,
|
||||||
|
AT_TEST = 0x40,
|
||||||
|
XCLKEN = 0x20,
|
||||||
|
UART_TURBO = 0x10,
|
||||||
|
ROM_SEL = 0x08,
|
||||||
|
ROM_TEST = 0x04,
|
||||||
|
M_TEST = 0x02,
|
||||||
|
CPU_TEST = 0x01
|
||||||
|
};
|
||||||
|
|
||||||
|
// MTEST1 bit definitions
|
||||||
|
enum {
|
||||||
|
P_CNT16 = 0x40,
|
||||||
|
REF_CNT16 = 0x20,
|
||||||
|
VID_TRIG = 0x10,
|
||||||
|
REF_TRIG = 0x08,
|
||||||
|
VID_DMA_DIS = 0x04,
|
||||||
|
REF_FAST = 0x02,
|
||||||
|
REF_DIS = 0x01
|
||||||
|
};
|
||||||
|
|
||||||
|
// MTEST2 bit definitions
|
||||||
|
enum {
|
||||||
|
V_STROBE = 0x10,
|
||||||
|
V_ZERO = 0x08,
|
||||||
|
H_120 = 0x04,
|
||||||
|
H_ZERO = 0x02,
|
||||||
|
V_BLANKEF = 0x01
|
||||||
|
};
|
||||||
|
|
||||||
|
// MAPCTL bit definitions
|
||||||
|
enum {
|
||||||
|
TURBO_DISABLE = 0x80,
|
||||||
|
VECTOR_SPACE = 0x08,
|
||||||
|
ROM_SPACE = 0x04,
|
||||||
|
MIKEY_SPACE = 0x02,
|
||||||
|
SUZY_SPACE = 0x01
|
||||||
|
};
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user