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Fixed ADC/SBC for the 65C02.
The current (before-this-patch) version of sim65.c does not correctly implement the ADC and SBC instructions in 65C02 mode. This PR fixes that. The 6502 and 65C02 behave identically in binary mode; in decimal behavior however they diverge, both in the handling of inputs that are not BCD values, and in the handling of processor flags. This fix restructures the original "ADC" and "SBC" macros in versions that are specific for the 6502 and the 65C02, and updates the opcode tables to ensure that they point to the correct implementations. Considering the ADC instruction for a moment, the original "ADC" macro was changed to two macros ADC_6502 and ADC_65C02. These check the D (decimal mode) bit, and defer their implementation to any of three macros ADC_BINARY_MODE, ADC_DECIMAL_MODE_6502, and ADC_DECIMAL_MODE_65C02. This is a bit verbose but it makes it very clear what's going on. (For the SBC changes, the analogous changes were made.) The correctness of the changes made is ensured as follows: First, an in-depth study was made how ADC and SBC work, both in the original 6502 and the later 65C02 processor. The actual behavior of both processors was captured on hardware (an Atari 800 XL with a 6502 and a Neo6502 equipped with a WDC 65C02 processor), and was analyzed. The results were cross-referenced with internet sources, leading to a C implementation that reproduces the exact result of the hardware processors. See: https://github.com/sidneycadot/6502-test/blob/main/functional_test/adc_sbc/c_and_python_implementations/6502_adc_sbc.c Next, these C implementations of ADC and SBC were fitted into sim65's macro- based implementation scheme, replacing the existing 6502-only implementation. Finally, the new sim65 implementation was tested against the 65x02 testsuite, showing that (1) the 6502 implementation was still correct; and (2) that the 65C02 implementation is now also correct. As an added bonus, this new implementation of ADC/SBC no longer relies on a dirty implementation detail in sim65: the previous implementation relied on the fact that currently, the A register in the simulator is implemented as an "unsigned", with more bits than the actual A register (8 bits). In the future we want to change the register width to 8 bits, and this updated ADC/SBC is a necessary precursor to that change.
This commit is contained in:
Sidney Cadot
parent
162bc6b305
commit
eda8774e08
465
src/sim65/6502.c
465
src/sim65/6502.c
@ -37,10 +37,11 @@
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/* Known bugs and limitations of the 65C02 simulation:
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* support currently only on the level of 65SC02:
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BBRx, BBSx, RMBx, SMBx, WAI, and STP are unsupported
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* BCD flag handling equals 6502 (unchecked if bug is simulated or wrong for
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6502)
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include "memory.h"
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#include "error.h"
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#include "6502.h"
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@ -555,15 +556,15 @@ static unsigned HaveIRQRequest;
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/* #imm */
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#define ALU_OP_IMM(op) \
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unsigned char immediate; \
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MEM_AD_OP_IMM(immediate); \
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Cycles = 2; \
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MEM_AD_OP_IMM(immediate); \
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Cycles = 2; \
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op (immediate)
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/* zp / zp,x / zp,y / abs / abs,x / abs,y / (zp,x) / (zp),y / (zp) */
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#define ALU_OP(mode, op) \
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unsigned address, operand; \
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Cycles = ALU_CY_##mode; \
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MEM_AD_OP (mode, address, operand); \
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Cycles = ALU_CY_##mode; \
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MEM_AD_OP (mode, address, operand); \
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op (operand)
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/* Store opcode helpers */
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@ -662,40 +663,88 @@ static unsigned HaveIRQRequest;
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TEST_SF (Regs.AC)
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/* ADC */
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#define ADC(v) \
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/* ADC, binary mode (6502 and 65C02) */
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/* TODO: once the Regs fields are properly sized, get rid of the
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* "& 0xff" in the Regs.AC asignment.
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*/
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#define ADC_BINARY_MODE(v) \
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do { \
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unsigned old = Regs.AC; \
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unsigned rhs = (v & 0xFF); \
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if (GET_DF ()) { \
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unsigned lo; \
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int res; \
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lo = (old & 0x0F) + (rhs & 0x0F) + GET_CF (); \
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if (lo >= 0x0A) { \
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lo = ((lo + 0x06) & 0x0F) + 0x10; \
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} \
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Regs.AC = (old & 0xF0) + (rhs & 0xF0) + lo; \
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res = (signed char)(old & 0xF0) + \
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(signed char)(rhs & 0xF0) + \
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(signed char)lo; \
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TEST_ZF (old + rhs + GET_CF ()); \
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TEST_SF (Regs.AC); \
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if (Regs.AC >= 0xA0) { \
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Regs.AC += 0x60; \
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} \
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TEST_CF (Regs.AC); \
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SET_OF ((res < -128) || (res > 127)); \
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if (CPU == CPU_65C02) { \
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++Cycles; \
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} \
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const uint8_t op = v; \
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const uint8_t OldAC = Regs.AC; \
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bool carry = GET_CF(); \
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Regs.AC = (OldAC + op + carry) & 0xff; \
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const bool NV = Regs.AC >= 0x80; \
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carry = OldAC + op + carry >= 0x100; \
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SET_SF(NV); \
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SET_OF(((OldAC >= 0x80) ^ NV) & ((op >= 0x80) ^ NV)); \
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SET_ZF(Regs.AC == 0); \
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SET_CF(carry); \
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} while (0)
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/* ADC, decimal mode (6502 behavior) */
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#define ADC_DECIMAL_MODE_6502(v) \
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do { \
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const uint8_t op = v; \
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const uint8_t OldAC = Regs.AC; \
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bool carry = GET_CF(); \
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const uint8_t binary_result = OldAC + op + carry; \
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uint8_t low_nibble = (OldAC & 15) + (op & 15) + carry; \
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if ((carry = low_nibble > 9)) \
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low_nibble = (low_nibble - 10) & 15; \
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uint8_t high_nibble = (OldAC >> 4) + (op >> 4) + carry; \
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const bool NV = (high_nibble & 8) != 0; \
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if ((carry = high_nibble > 9)) \
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high_nibble = (high_nibble - 10) & 15; \
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Regs.AC = (high_nibble << 4) | low_nibble; \
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SET_SF(NV); \
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SET_OF(((OldAC >= 0x80) ^ NV) & ((op >= 0x80) ^ NV)); \
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SET_ZF(binary_result == 0); \
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SET_CF(carry); \
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} while (0)
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/* ADC, decimal mode (65C02 behavior) */
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#define ADC_DECIMAL_MODE_65C02(v) \
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do { \
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const uint8_t op = v; \
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const uint8_t OldAC = Regs.AC; \
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const bool OldCF = GET_CF(); \
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bool carry = OldCF; \
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uint8_t low_nibble = (OldAC & 15) + (op & 15) + carry; \
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if ((carry = low_nibble > 9)) \
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low_nibble = (low_nibble - 10) & 15; \
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uint8_t high_nibble = (OldAC >> 4) + (op >> 4) + carry; \
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const bool PrematureSF = (high_nibble & 8) != 0; \
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if ((carry = high_nibble > 9)) \
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high_nibble = (high_nibble - 10) & 15; \
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Regs.AC = (high_nibble << 4) | low_nibble; \
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const bool NewZF = Regs.AC == 0; \
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const bool NewSF = Regs.AC >= 0x80; \
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const bool NewOF = ((OldAC >= 0x80) ^ PrematureSF) & \
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((op >= 0x80) ^ PrematureSF); \
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SET_SF(NewSF); \
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SET_OF(NewOF); \
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SET_ZF(NewZF); \
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SET_CF(carry); \
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++Cycles; \
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} while (0)
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/* ADC, 6502 version */
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#define ADC_6502(v) \
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do { \
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if (GET_DF()) { \
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ADC_DECIMAL_MODE_6502(v); \
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} else { \
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Regs.AC += rhs + GET_CF (); \
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TEST_ZF (Regs.AC); \
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TEST_SF (Regs.AC); \
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TEST_CF (Regs.AC); \
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SET_OF (!((old ^ rhs) & 0x80) && \
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((old ^ Regs.AC) & 0x80)); \
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Regs.AC &= 0xFF; \
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ADC_BINARY_MODE(v); \
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} \
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} while (0)
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/* ADC, 65C02 version */
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#define ADC_65C02(v) \
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do { \
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if (GET_DF()) { \
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ADC_DECIMAL_MODE_65C02(v); \
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} else { \
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ADC_BINARY_MODE(v); \
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} \
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} while (0)
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@ -737,23 +786,29 @@ static unsigned HaveIRQRequest;
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/* ROL */
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#define ROL(Val) \
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Val <<= 1; \
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if (GET_CF ()) { \
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Val |= 0x01; \
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} \
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TEST_ZF (Val); \
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TEST_SF (Val); \
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TEST_CF (Val)
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do { \
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unsigned ShiftOut = (Val & 0x80); \
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Val <<= 1; \
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if (GET_CF ()) { \
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Val |= 0x01; \
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} \
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TEST_ZF (Val); \
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TEST_SF (Val); \
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SET_CF (ShiftOut); \
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} while (0)
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/* ROR */
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#define ROR(Val) \
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if (GET_CF ()) { \
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Val |= 0x100; \
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} \
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SET_CF (Val & 0x01); \
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Val >>= 1; \
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TEST_ZF (Val); \
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TEST_SF (Val)
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do { \
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unsigned ShiftOut = (Val & 0x01); \
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Val >>= 1; \
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if (GET_CF ()) { \
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Val |= 0x80; \
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} \
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TEST_ZF (Val); \
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TEST_SF (Val); \
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SET_CF (ShiftOut); \
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} while(0)
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/* ASL */
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#define ASL(Val) \
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@ -816,7 +871,7 @@ static unsigned HaveIRQRequest;
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} \
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SET_CF (Val & 0x01); \
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Val >>= 1; \
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ADC (Val)
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ADC_6502 (Val)
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/* BIT */
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#define BIT(Val) \
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@ -873,7 +928,7 @@ static unsigned HaveIRQRequest;
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/* ISC */
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#define ISC(Val) \
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Val = (Val + 1) & 0xFF; \
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SBC(Val)
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SBC_6502(Val)
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/* ASR */
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#define ASR(Val) \
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@ -971,33 +1026,88 @@ static unsigned HaveIRQRequest;
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TEST_SF (Val); \
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TEST_ZF (Val)
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/* SBC */
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#define SBC(v) \
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/* SBC, binary mode (6502 and 65C02) */
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/* TODO: once the Regs fields are properly sized, get rid of the
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* "& 0xff" in the Regs.AC asignment.
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*/
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#define SBC_BINARY_MODE(v) \
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do { \
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unsigned r_a = Regs.AC; \
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unsigned src = (v) & 0xFF; \
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unsigned ccc = (Regs.SR & CF) ^ CF; \
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unsigned tmp = r_a - src - ccc; \
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\
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SET_CF(tmp < 0x100); \
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TEST_SF(tmp); \
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TEST_ZF(tmp); \
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SET_OF((r_a ^ tmp) & (r_a ^ src) & 0x80); \
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\
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if (GET_DF ()) { \
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unsigned low = (r_a & 0x0f) - (src & 0x0f) - ccc; \
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tmp = (r_a & 0xf0) - (src & 0xf0); \
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if (low & 0x10) { \
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low -= 6; \
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tmp -= 0x10; \
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} \
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tmp = (low & 0xf) | tmp; \
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if (tmp & 0x100) { \
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tmp -= 0x60; \
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} \
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const uint8_t op = v; \
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const uint8_t OldAC = Regs.AC; \
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const bool borrow = !GET_CF(); \
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Regs.AC = (OldAC - op - borrow) & 0xff; \
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const bool NV = Regs.AC >= 0x80; \
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SET_SF(NV); \
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SET_OF(((OldAC >= 0x80) ^ NV) & ((op < 0x80) ^ NV)); \
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SET_ZF(Regs.AC == 0); \
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SET_CF(OldAC >= op + borrow); \
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} while (0)
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/* SBC, decimal mode (6502 behavior) */
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#define SBC_DECIMAL_MODE_6502(v) \
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do { \
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const uint8_t op = v; \
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const uint8_t OldAC = Regs.AC; \
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bool borrow = !GET_CF(); \
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const uint8_t binary_result = OldAC - op - borrow; \
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const bool NV = binary_result >= 0x80; \
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uint8_t low_nibble = (OldAC & 15) - (op & 15) - borrow; \
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if ((borrow = low_nibble >= 0x80)) \
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low_nibble = (low_nibble + 10) & 15; \
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uint8_t high_nibble = (OldAC >> 4) - (op >> 4) - borrow;\
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if ((borrow = high_nibble >= 0x80)) \
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high_nibble = (high_nibble + 10) & 15; \
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Regs.AC = (high_nibble << 4) | low_nibble; \
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SET_SF(NV); \
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SET_OF(((OldAC >= 0x80) ^ NV) & ((op < 0x80) ^ NV)); \
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SET_ZF(binary_result == 0); \
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SET_CF(!borrow); \
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} while (0)
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/* SBC, decimal mode (65C02 behavior) */
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#define SBC_DECIMAL_MODE_65C02(v) \
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do { \
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const uint8_t op = v; \
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const uint8_t OldAC = Regs.AC; \
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bool borrow = !GET_CF(); \
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uint8_t low_nibble = (OldAC & 15) - (op & 15) - borrow; \
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if ((borrow = low_nibble >= 0x80)) \
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low_nibble += 10; \
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const bool low_nibble_still_negative = \
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(low_nibble >= 0x80); \
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low_nibble &= 15; \
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uint8_t high_nibble = (OldAC >> 4) - (op >> 4) - borrow;\
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const bool PN = (high_nibble & 8) != 0; \
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if ((borrow = high_nibble >= 0x80)) \
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high_nibble += 10; \
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high_nibble -= low_nibble_still_negative; \
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high_nibble &= 15; \
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Regs.AC = (high_nibble << 4) | low_nibble; \
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SET_SF(Regs.AC >= 0x80); \
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SET_OF(((OldAC >= 0x80) ^ PN) & ((op < 0x80) ^ PN)); \
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SET_ZF(Regs.AC == 0x00); \
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SET_CF(!borrow); \
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++Cycles; \
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} while (0)
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/* SBC, 6502 version */
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#define SBC_6502(v) \
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do { \
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if (GET_DF()) { \
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SBC_DECIMAL_MODE_6502(v); \
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} else { \
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SBC_BINARY_MODE(v); \
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} \
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} while (0)
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/* SBC, 65C02 version */
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#define SBC_65C02(v) \
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do { \
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if (GET_DF()) { \
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SBC_DECIMAL_MODE_65C02(v); \
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} else { \
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SBC_BINARY_MODE(v); \
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} \
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Regs.AC = tmp & 0xFF; \
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} while (0)
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@ -1881,11 +1991,17 @@ static void OPC_6502_60 (void)
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static void OPC_6502_61 (void)
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/* Opcode $61: ADC (zp,x) */
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{
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ALU_OP (ZPXIND, ADC);
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ALU_OP (ZPXIND, ADC_6502);
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}
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static void OPC_65C02_61 (void)
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/* Opcode $61: ADC (zp,x) */
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{
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ALU_OP (ZPXIND, ADC_65C02);
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}
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static void OPC_6502_63 (void)
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/* Opcode $63: RRA (zp,x) */
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{
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@ -1905,7 +2021,15 @@ static void OPC_65SC02_64 (void)
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static void OPC_6502_65 (void)
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/* Opcode $65: ADC zp */
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{
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ALU_OP (ZP, ADC);
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ALU_OP (ZP, ADC_6502);
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}
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static void OPC_65C02_65 (void)
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/* Opcode $65: ADC zp */
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{
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ALU_OP (ZP, ADC_65C02);
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}
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@ -1941,11 +2065,17 @@ static void OPC_6502_68 (void)
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static void OPC_6502_69 (void)
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/* Opcode $69: ADC #imm */
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{
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ALU_OP_IMM (ADC);
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ALU_OP_IMM (ADC_6502);
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}
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static void OPC_65C02_69 (void)
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/* Opcode $69: ADC #imm */
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{
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ALU_OP_IMM (ADC_65C02);
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}
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static void OPC_6502_6A (void)
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/* Opcode $6A: ROR a */
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{
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@ -2004,7 +2134,15 @@ static void OPC_65C02_6C (void)
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static void OPC_6502_6D (void)
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/* Opcode $6D: ADC abs */
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{
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ALU_OP (ABS, ADC);
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ALU_OP (ABS, ADC_6502);
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}
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static void OPC_65C02_6D (void)
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/* Opcode $6D: ADC abs */
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{
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ALU_OP (ABS, ADC_65C02);
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}
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@ -2036,15 +2174,23 @@ static void OPC_6502_70 (void)
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static void OPC_6502_71 (void)
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/* Opcode $71: ADC (zp),y */
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{
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ALU_OP (ZPINDY, ADC);
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ALU_OP (ZPINDY, ADC_6502);
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}
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|
||||
static void OPC_65SC02_72 (void)
|
||||
static void OPC_65C02_71 (void)
|
||||
/* Opcode $71: ADC (zp),y */
|
||||
{
|
||||
ALU_OP (ZPINDY, ADC_65C02);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void OPC_65C02_72 (void)
|
||||
/* Opcode $72: ADC (zp) */
|
||||
{
|
||||
ALU_OP (ZPIND, ADC);
|
||||
ALU_OP (ZPIND, ADC_65C02);
|
||||
}
|
||||
|
||||
|
||||
@ -2068,11 +2214,17 @@ static void OPC_65SC02_74 (void)
|
||||
static void OPC_6502_75 (void)
|
||||
/* Opcode $75: ADC zp,x */
|
||||
{
|
||||
ALU_OP (ZPX, ADC);
|
||||
ALU_OP (ZPX, ADC_6502);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void OPC_65C02_75 (void)
|
||||
/* Opcode $75: ADC zp,x */
|
||||
{
|
||||
ALU_OP (ZPX, ADC_65C02);
|
||||
}
|
||||
|
||||
static void OPC_6502_76 (void)
|
||||
/* Opcode $76: ROR zp,x */
|
||||
{
|
||||
@ -2102,7 +2254,15 @@ static void OPC_6502_78 (void)
|
||||
static void OPC_6502_79 (void)
|
||||
/* Opcode $79: ADC abs,y */
|
||||
{
|
||||
ALU_OP (ABSY, ADC);
|
||||
ALU_OP (ABSY, ADC_6502);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void OPC_65C02_79 (void)
|
||||
/* Opcode $79: ADC abs,y */
|
||||
{
|
||||
ALU_OP (ABSY, ADC_65C02);
|
||||
}
|
||||
|
||||
|
||||
@ -2144,7 +2304,15 @@ static void OPC_65SC02_7C (void)
|
||||
static void OPC_6502_7D (void)
|
||||
/* Opcode $7D: ADC abs,x */
|
||||
{
|
||||
ALU_OP (ABSX, ADC);
|
||||
ALU_OP (ABSX, ADC_6502);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void OPC_65C02_7D (void)
|
||||
/* Opcode $7D: ADC abs,x */
|
||||
{
|
||||
ALU_OP (ABSX, ADC_65C02);
|
||||
}
|
||||
|
||||
|
||||
@ -2986,11 +3154,17 @@ static void OPC_6502_E0 (void)
|
||||
static void OPC_6502_E1 (void)
|
||||
/* Opcode $E1: SBC (zp,x) */
|
||||
{
|
||||
ALU_OP (ZPXIND, SBC);
|
||||
ALU_OP (ZPXIND, SBC_6502);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void OPC_65C02_E1 (void)
|
||||
/* Opcode $E1: SBC (zp,x) */
|
||||
{
|
||||
ALU_OP (ZPXIND, SBC_65C02);
|
||||
}
|
||||
|
||||
static void OPC_6502_E3 (void)
|
||||
/* Opcode $E3: ISC (zp,x) */
|
||||
{
|
||||
@ -3010,7 +3184,15 @@ static void OPC_6502_E4 (void)
|
||||
static void OPC_6502_E5 (void)
|
||||
/* Opcode $E5: SBC zp */
|
||||
{
|
||||
ALU_OP (ZP, SBC);
|
||||
ALU_OP (ZP, SBC_6502);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void OPC_65C02_E5 (void)
|
||||
/* Opcode $E5: SBC zp */
|
||||
{
|
||||
ALU_OP (ZP, SBC_65C02);
|
||||
}
|
||||
|
||||
|
||||
@ -3041,17 +3223,23 @@ static void OPC_6502_E8 (void)
|
||||
|
||||
|
||||
|
||||
/* Aliases of opcode $EA */
|
||||
/* Aliases of opcode $E9 */
|
||||
#define OPC_6502_EB OPC_6502_E9
|
||||
|
||||
static void OPC_6502_E9 (void)
|
||||
/* Opcode $E9: SBC #imm */
|
||||
{
|
||||
ALU_OP_IMM (SBC);
|
||||
ALU_OP_IMM (SBC_6502);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void OPC_65C02_E9 (void)
|
||||
/* Opcode $E9: SBC #imm */
|
||||
{
|
||||
ALU_OP_IMM (SBC_65C02);
|
||||
}
|
||||
|
||||
/* Aliases of opcode $EA */
|
||||
#define OPC_6502_1A OPC_6502_EA
|
||||
#define OPC_6502_3A OPC_6502_EA
|
||||
@ -3117,7 +3305,15 @@ static void OPC_6502_EC (void)
|
||||
static void OPC_6502_ED (void)
|
||||
/* Opcode $ED: SBC abs */
|
||||
{
|
||||
ALU_OP (ABS, SBC);
|
||||
ALU_OP (ABS, SBC_6502);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void OPC_65C02_ED (void)
|
||||
/* Opcode $ED: SBC abs */
|
||||
{
|
||||
ALU_OP (ABS, SBC_65C02);
|
||||
}
|
||||
|
||||
|
||||
@ -3148,15 +3344,24 @@ static void OPC_6502_F0 (void)
|
||||
static void OPC_6502_F1 (void)
|
||||
/* Opcode $F1: SBC (zp),y */
|
||||
{
|
||||
ALU_OP (ZPINDY, SBC);
|
||||
ALU_OP (ZPINDY, SBC_6502);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void OPC_65SC02_F2 (void)
|
||||
|
||||
static void OPC_65C02_F1 (void)
|
||||
/* Opcode $F1: SBC (zp),y */
|
||||
{
|
||||
ALU_OP (ZPINDY, SBC_65C02);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void OPC_65C02_F2 (void)
|
||||
/* Opcode $F2: SBC (zp) */
|
||||
{
|
||||
ALU_OP (ZPIND, SBC);
|
||||
ALU_OP (ZPIND, SBC_65C02);
|
||||
}
|
||||
|
||||
|
||||
@ -3172,7 +3377,15 @@ static void OPC_6502_F3 (void)
|
||||
static void OPC_6502_F5 (void)
|
||||
/* Opcode $F5: SBC zp,x */
|
||||
{
|
||||
ALU_OP (ZPX, SBC);
|
||||
ALU_OP (ZPX, SBC_6502);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void OPC_65C02_F5 (void)
|
||||
/* Opcode $F5: SBC zp,x */
|
||||
{
|
||||
ALU_OP (ZPX, SBC_65C02);
|
||||
}
|
||||
|
||||
|
||||
@ -3206,7 +3419,15 @@ static void OPC_6502_F8 (void)
|
||||
static void OPC_6502_F9 (void)
|
||||
/* Opcode $F9: SBC abs,y */
|
||||
{
|
||||
ALU_OP (ABSY, SBC);
|
||||
ALU_OP (ABSY, SBC_6502);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void OPC_65C02_F9 (void)
|
||||
/* Opcode $F9: SBC abs,y */
|
||||
{
|
||||
ALU_OP (ABSY, SBC_65C02);
|
||||
}
|
||||
|
||||
|
||||
@ -3234,7 +3455,15 @@ static void OPC_6502_FB (void)
|
||||
static void OPC_6502_FD (void)
|
||||
/* Opcode $FD: SBC abs,x */
|
||||
{
|
||||
ALU_OP (ABSX, SBC);
|
||||
ALU_OP (ABSX, SBC_6502);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void OPC_65C02_FD (void)
|
||||
/* Opcode $FD: SBC abs,x */
|
||||
{
|
||||
ALU_OP (ABSX, SBC_65C02);
|
||||
}
|
||||
|
||||
|
||||
@ -3884,35 +4113,35 @@ static const OPFunc OP65C02Table[256] = {
|
||||
OPC_65C02_5E,
|
||||
OPC_Illegal, // $5F: BBR5 currently unsupported
|
||||
OPC_6502_60,
|
||||
OPC_6502_61,
|
||||
OPC_65C02_61,
|
||||
OPC_65C02_NOP22, // $62
|
||||
OPC_65C02_NOP11, // $63
|
||||
OPC_65SC02_64,
|
||||
OPC_6502_65,
|
||||
OPC_65C02_65,
|
||||
OPC_6502_66,
|
||||
OPC_Illegal, // $67: RMB6 currently unsupported
|
||||
OPC_6502_68,
|
||||
OPC_6502_69,
|
||||
OPC_65C02_69,
|
||||
OPC_6502_6A,
|
||||
OPC_65C02_NOP11, // $6B
|
||||
OPC_65C02_6C,
|
||||
OPC_6502_6D,
|
||||
OPC_65C02_6D,
|
||||
OPC_6502_6E,
|
||||
OPC_Illegal, // $6F: BBR6 currently unsupported
|
||||
OPC_6502_70,
|
||||
OPC_6502_71,
|
||||
OPC_65SC02_72,
|
||||
OPC_65C02_71,
|
||||
OPC_65C02_72,
|
||||
OPC_65C02_NOP11, // $73
|
||||
OPC_65SC02_74,
|
||||
OPC_6502_75,
|
||||
OPC_65C02_75,
|
||||
OPC_6502_76,
|
||||
OPC_Illegal, // $77: RMB7 currently unsupported
|
||||
OPC_6502_78,
|
||||
OPC_6502_79,
|
||||
OPC_65C02_79,
|
||||
OPC_65SC02_7A,
|
||||
OPC_65C02_NOP11, // $7B
|
||||
OPC_65SC02_7C,
|
||||
OPC_6502_7D,
|
||||
OPC_65C02_7D,
|
||||
OPC_65C02_7E,
|
||||
OPC_Illegal, // $7F: BBR7 currently unsupported
|
||||
OPC_65SC02_80,
|
||||
@ -4012,35 +4241,35 @@ static const OPFunc OP65C02Table[256] = {
|
||||
OPC_6502_DE,
|
||||
OPC_Illegal, // $DF: BBS5 currently unsupported
|
||||
OPC_6502_E0,
|
||||
OPC_6502_E1,
|
||||
OPC_65C02_E1,
|
||||
OPC_65C02_NOP22, // $E2
|
||||
OPC_65C02_NOP11, // $E3
|
||||
OPC_6502_E4,
|
||||
OPC_6502_E5,
|
||||
OPC_65C02_E5,
|
||||
OPC_6502_E6,
|
||||
OPC_Illegal, // $E7: SMB6 currently unsupported
|
||||
OPC_6502_E8,
|
||||
OPC_6502_E9,
|
||||
OPC_65C02_E9,
|
||||
OPC_6502_EA,
|
||||
OPC_65C02_NOP11, // $EB
|
||||
OPC_6502_EC,
|
||||
OPC_6502_ED,
|
||||
OPC_65C02_ED,
|
||||
OPC_6502_EE,
|
||||
OPC_Illegal, // $EF: BBS6 currently unsupported
|
||||
OPC_6502_F0,
|
||||
OPC_6502_F1,
|
||||
OPC_65SC02_F2,
|
||||
OPC_65C02_F1,
|
||||
OPC_65C02_F2,
|
||||
OPC_65C02_NOP11, // $F3
|
||||
OPC_65C02_NOP24, // $F4
|
||||
OPC_6502_F5,
|
||||
OPC_65C02_F5,
|
||||
OPC_6502_F6,
|
||||
OPC_Illegal, // $F7: SMB7 currently unsupported
|
||||
OPC_6502_F8,
|
||||
OPC_6502_F9,
|
||||
OPC_65C02_F9,
|
||||
OPC_65SC02_FA,
|
||||
OPC_65C02_NOP11, // $FB
|
||||
OPC_65C02_NOP34, // $FC
|
||||
OPC_6502_FD,
|
||||
OPC_65C02_FD,
|
||||
OPC_6502_FE,
|
||||
OPC_Illegal, // $FF: BBS7 currently unsupported
|
||||
};
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user