Oliver Schmidt
4185caf855
Normalized code.
2014-03-04 01:11:19 +01:00
Oliver Schmidt
85885001b1
Removed (pretty inconsistently used) tab chars from source code base.
2013-05-09 13:57:12 +02:00
uz
3b9032a7c4
Added disassembler support for the NMOS 6502 with illegal opcodes.
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git-svn-id: svn://svn.cc65.org/cc65/trunk@4966 b7a2c559-68d2-44c3-8de9-860c34a00d81
2011-02-06 16:04:46 +00:00
uz
338844cb2e
Patch by Gary Wong: The smbx and rmbx instructions are two byte insns (not one
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byte).
git-svn-id: svn://svn.cc65.org/cc65/trunk@4895 b7a2c559-68d2-44c3-8de9-860c34a00d81
2010-12-30 19:35:10 +00:00
cuz
fdf047b4d7
PEI is no valid opcode for the 6502/sc02/c02
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git-svn-id: svn://svn.cc65.org/cc65/trunk@2602 b7a2c559-68d2-44c3-8de9-860c34a00d81
2003-11-03 15:35:36 +00:00
cuz
cba152f777
An "absolute mode override modifier" is now added for instructions where
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the assembler will otherwise choose the cheaper zeropage addressing mode
because of the size of the operand.
git-svn-id: svn://svn.cc65.org/cc65/trunk@2590 b7a2c559-68d2-44c3-8de9-860c34a00d81
2003-10-31 16:28:56 +00:00
cuz
7496da8f93
Fixed a bug in the opcode tables
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git-svn-id: svn://svn.cc65.org/cc65/trunk@2588 b7a2c559-68d2-44c3-8de9-860c34a00d81
2003-10-30 20:35:07 +00:00
cuz
11328d8ea6
Added additional 65(S)C02 opcodes
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git-svn-id: svn://svn.cc65.org/cc65/trunk@2254 b7a2c559-68d2-44c3-8de9-860c34a00d81
2003-08-08 19:23:55 +00:00
cuz
897f3e9530
Base code for handling different CPUs, more improvements
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git-svn-id: svn://svn.cc65.org/cc65/trunk@2253 b7a2c559-68d2-44c3-8de9-860c34a00d81
2003-08-08 11:12:04 +00:00
