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109 lines
4.4 KiB
PHP
109 lines
4.4 KiB
PHP
;
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; Vic20 generic definitions. Stolen mostly from c64.inc - Steve Schmidtke
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;
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; ---------------------------------------------------------------------------
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; Zero page, Commodore stuff
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VARTAB := $2D ; Pointer to start of BASIC variables
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MEMSIZE := $37 ; Pointer to highest BASIC RAM location (+1)
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TXTPTR := $7A ; Pointer into BASIC source code
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TIME := $A0 ; 60HZ clock
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FNAM_LEN := $B7 ; Length of filename
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SECADR := $B9 ; Secondary address
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DEVNUM := $BA ; Device number
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FNAM := $BB ; Pointer to filename
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KEY_COUNT := $C6 ; Number of keys in input buffer
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RVS := $C7 ; Reverse flag
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CURS_FLAG := $CC ; 1 = cursor off
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CURS_BLINK := $CD ; Blink counter
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CURS_CHAR := $CE ; Character under the cursor
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CURS_STATE := $CF ; Cursor blink state
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SCREEN_PTR := $D1 ; Pointer to current char in text screen
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CURS_X := $D3 ; Cursor column
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CURS_Y := $D6 ; Cursor row
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CRAM_PTR := $F3 ; Pointer to current char in color RAM
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BASIC_BUF := $200 ; Location of command-line
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BASIC_BUF_LEN = 89 ; Maximum length of command-line
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CHARCOLOR := $286
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CURS_COLOR := $287 ; Color under the cursor
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KBDREPEAT := $28a
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KBDREPEATRATE := $28b
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KBDREPEATDELAY := $28c
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; ---------------------------------------------------------------------------
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; Screen size
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XSIZE = 22
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YSIZE = 23
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; ---------------------------------------------------------------------------
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; Kernal routines
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; Direct entries
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CLRSCR := $E55F
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KBDREAD := $E5CF
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; ---------------------------------------------------------------------------
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; Vector and other locations
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IRQVec := $0314
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BRKVec := $0316
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NMIVec := $0318
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; ---------------------------------------------------------------------------
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; I/O: 6560 VIC
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VIC := $9000
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VIC_LINES := $9003 ; Screen lines, bit 7 is bit 0 from VIC_HLINE
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VIC_HLINE := $9004 ; Rasterline, bits 1-8
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VIC_COLOR := $900F ; Border and background color
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; ---------------------------------------------------------------------------
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; I/O: 6522 VIA1
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VIA1 := $9110 ; VIA1 base address
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VIA1_JOY := VIA1+$0 ; *** Deprecated ***
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VIA1_PB := VIA1+$0 ; Port register B
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VIA1_PA1 := VIA1+$1 ; Port register A
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VIA1_DDRB := VIA1+$2 ; Data direction register B
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VIA1_DDRA := VIA1+$3 ; Data direction register A
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VIA1_T1CL := VIA1+$4 ; Timer 1, low byte
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VIA1_T1CH := VIA1+$5 ; Timer 1, high byte
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VIA1_T1LL := VIA1+$6 ; Timer 1 latch, low byte
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VIA1_T1LH := VIA1+$7 ; Timer 1 latch, high byte
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VIA1_T2CL := VIA1+$8 ; Timer 2, low byte
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VIA1_T2CH := VIA1+$9 ; Timer 2, high byte
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VIA1_SR := VIA1+$A ; Shift register
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VIA1_CR := VIA1+$B ; Auxiliary control register
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VIA1_PCR := VIA1+$C ; Peripheral control register
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VIA1_IFR := VIA1+$D ; Interrupt flag register
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VIA1_IER := VIA1+$E ; Interrupt enable register
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VIA1_PA2 := VIA1+$F ; Port register A w/o handshake
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; ---------------------------------------------------------------------------
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; I/O: 6522 VIA2
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VIA2 := $9120 ; VIA2 base address
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VIA2_JOY := VIA2+$0 ; *** Deprecated ***
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VIA2_PB := VIA2+$0 ; Port register B
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VIA2_PA1 := VIA2+$1 ; Port register A
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VIA2_DDRB := VIA2+$2 ; Data direction register B
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VIA2_DDRA := VIA2+$3 ; Data direction register A
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VIA2_T1CL := VIA2+$4 ; Timer 1, low byte
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VIA2_T1CH := VIA2+$5 ; Timer 1, high byte
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VIA2_T1LL := VIA2+$6 ; Timer 1 latch, low byte
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VIA2_T1LH := VIA2+$7 ; Timer 1 latch, high byte
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VIA2_T2CL := VIA2+$8 ; Timer 2, low byte
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VIA2_T2CH := VIA2+$9 ; Timer 2, high byte
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VIA2_SR := VIA2+$A ; Shift register
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VIA2_CR := VIA2+$B ; Auxiliary control register
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VIA2_PCR := VIA2+$C ; Peripheral control register
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VIA2_IFR := VIA2+$D ; Interrupt flag register
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VIA2_IER := VIA2+$E ; Interrupt enable register
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VIA2_PA2 := VIA2+$F ; Port register A w/o handshake
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