mirror of
https://github.com/cc65/cc65.git
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d8c31cf1d3
The name RAM doesn't make much sense in general for a memeory area because i.e. the zero page is for sure RAM but is not part of the memory area named RAM. For disk based targets it makes sense to put the disk file more into focus and here MAIN means the main part of the file - in contrast to some header. Only for ROM based targets the name RAM is kept as it makes sense to focus on the difference between RAM and ROM.
203 lines
5.4 KiB
ArmAsm
203 lines
5.4 KiB
ArmAsm
;
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; Startup code for cc65 (Plus/4 version)
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;
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.export _exit
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.export brk_jmp
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.export __STARTUP__ : absolute = 1 ; Mark as startup
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.import callirq_y, initlib, donelib
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.import callmain, zerobss
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.import __INTERRUPTOR_COUNT__
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.import __MAIN_START__, __MAIN_SIZE__ ; Linker generated
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.import __STACKSIZE__ ; Linker generated
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.importzp ST
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.include "zeropage.inc"
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.include "plus4.inc"
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; ------------------------------------------------------------------------
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; Constants
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IRQInd = $500 ; JMP $0000 - used as indirect IRQ vector
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; ------------------------------------------------------------------------
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; Startup code
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.segment "STARTUP"
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Start:
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; Save the zero-page locations that we need.
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sei ; No interrupts since we're banking out the ROM
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sta ENABLE_RAM
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ldx #zpspace-1
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L1: lda sp,x
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sta zpsave,x
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dex
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bpl L1
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sta ENABLE_ROM
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cli
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; Switch to the second charset.
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lda #14
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jsr $FFD2 ; BSOUT
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; Save some system stuff; and, set up the stack. The stack starts at the top
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; of the usable RAM.
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tsx
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stx spsave ; Save system stk ptr
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lda #<(__MAIN_START__ + __MAIN_SIZE__ + __STACKSIZE__)
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ldx #>(__MAIN_START__ + __MAIN_SIZE__ + __STACKSIZE__)
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sta sp
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stx sp+1
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; Set up the IRQ vector in the banked RAM; and, switch off the ROM.
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ldx #<IRQ
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ldy #>IRQ
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sei ; No ints, handler not yet in place
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sta ENABLE_RAM
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stx $FFFE ; Install interrupt handler
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sty $FFFF
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cli ; Allow interrupts
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; Clear the BSS data.
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jsr zerobss
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; Initialize irqcount, which means that, from now on, custom linked-in IRQ
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; handlers will be called (via condes).
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lda #.lobyte(__INTERRUPTOR_COUNT__*2)
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sta irqcount
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; Call the module constructors.
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jsr initlib
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; Push the command-line arguments; and, call main().
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jsr callmain
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; Back from main() [this is also the exit() entry]. Run the module destructors.
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_exit: pha ; Save the return code
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jsr donelib ; Run module destructors
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; Disable the chained IRQ handlers.
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lda #0
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sta irqcount ; Disable custom IRQ handlers
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; Copy back the zero-page stuff.
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ldx #zpspace-1
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L2: lda zpsave,x
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sta sp,x
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dex
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bpl L2
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; Place the program return code into BASIC's status variable.
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pla
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sta ST
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; Restore the stack pointer.
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ldx spsave
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txs
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; Enable the ROM; and, return to BASIC.
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sta ENABLE_ROM
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rts
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; ------------------------------------------------------------------------
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; IRQ handler. The handler in the ROM enables the Kernal, and jumps to
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; $CE00, where the ROM code checks for a BRK or IRQ, and branches via the
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; indirect vectors at $314/$316.
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; To make our stub as fast as possible, we skip the whole part of the ROM
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; handler, and jump to the indirect vectors directly. We do also call our
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; own interrupt handlers if we have any; so, they need not use $314.
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.segment "LOWCODE"
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IRQ: cld ; Just to be sure
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pha
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txa
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pha
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tya
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pha
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tsx ; Get the stack pointer
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lda $0104,x ; Get the saved status register
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and #$10 ; Test for BRK bit
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bne dobreak
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; It's an IRQ; and, RAM is enabled. If we have handlers, call them. We will use
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; a flag here instead of loading __INTERRUPTOR_COUNT__ directly, since the
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; condes function is not reentrant. The irqcount flag will be set/reset from
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; the main code, to avoid races.
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ldy irqcount
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beq @L1
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jsr callirq_y ; Call the IRQ functions
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; Since the ROM handler will end with an RTI, we have to fake an IRQ return
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; on the stack, so that we get control of the CPU after the ROM handler,
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; and can switch back to RAM.
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@L1: lda #>irq_ret ; Push new return address
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pha
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lda #<irq_ret
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pha
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php ; Push faked IRQ frame on stack
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pha ; Push faked A register
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pha ; Push faked X register
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pha ; Push faked Y register
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sta ENABLE_ROM ; Switch to ROM
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jmp (IRQVec) ; Jump indirect to Kernal IRQ handler
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irq_ret:
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sta ENABLE_RAM ; Switch back to RAM
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pla
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tay
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pla
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tax
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pla
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rti
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dobreak:
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lda brk_jmp+2 ; Check high byte of address
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beq nohandler
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jmp brk_jmp ; Jump to the handler
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; No break handler installed, jump to ROM.
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nohandler:
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sta ENABLE_ROM
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jmp (BRKVec) ; Jump indirect to the break vector
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; ------------------------------------------------------------------------
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; Data
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.data
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; BRK handling
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brk_jmp: jmp $0000
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spsave: .res 1
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irqcount: .byte 0
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.segment "INIT"
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zpsave: .res zpspace
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