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Add new BIM instruction (BIt imMediate mode)
This is not a real instruction in the 65c02 processor; I invented it for the sole purpose of handling the specialized logic that is performed by BIT in IMM mode. To be fair--I can imagine this really _was_ implemented as a "separate" instruction on the chip! But I don't know that for sure.
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@ -73,6 +73,7 @@ enum instruction {
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BCS, // Branch on Carry Set
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BEQ, // Branch on EQual to zero
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BIT, // BIT test
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BIM, // BIt test (imMediate mode) (* not a real instruction in the processor; just used by us)
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BMI, // Branch on MInus
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BNE, // Branch on Not Equal to zero
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BPL, // Branch on PLus
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@ -182,6 +182,7 @@ DECL_INST(bcc);
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DECL_INST(bcs);
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DECL_INST(beq);
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DECL_INST(bit);
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DECL_INST(bim);
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DECL_INST(bmi);
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DECL_INST(bne);
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DECL_INST(bpl);
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@ -74,6 +74,22 @@ DEFINE_INST(bit)
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}
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}
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/*
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* The BIM instruction (which is made up--it's not a real instruction)
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* is here to handle the specific use-case of a BIT instruction in
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* immediate (IMM) mode. We do this in a separate instruction to avoid
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* the need to add logic to the BIT instruction such that it has to know
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* or care about its opcode or its address mode.
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*/
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DEFINE_INST(bim)
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{
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// This is the same behavior as BIT
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cpu->P &= ~MOS_ZERO;
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if (!(cpu->A & oper)) {
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cpu->P |= MOS_ZERO;
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}
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}
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/*
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* Compute the bitwise-exclusive-or between the accumulator and operand,
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* and store the result in A.
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@ -35,7 +35,7 @@ static int instructions[] = {
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BVC, EOR, EOR, BAD, BAD, EOR, LSR, BAD, CLI, EOR, BAD, BAD, BAD, EOR, LSR, BAD, // 5x
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RTS, ADC, BAD, BAD, BAD, ADC, ROR, BAD, PLA, ADC, ROR, BAD, JMP, ADC, ROR, BAD, // 6x
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BVS, ADC, ADC, BAD, BAD, ADC, ROR, BAD, SEI, ADC, BAD, BAD, BAD, ADC, ROR, BAD, // 7x
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BAD, STA, BAD, BAD, STY, STA, STX, BAD, DEY, BIT, TXA, BAD, STY, STA, STX, BAD, // 8x
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BAD, STA, BAD, BAD, STY, STA, STX, BAD, DEY, BIM, TXA, BAD, STY, STA, STX, BAD, // 8x
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BCC, STA, STA, BAD, STY, STA, STX, BAD, TYA, STA, TXS, BAD, BAD, STA, BAD, BAD, // 9x
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LDY, LDA, LDX, BAD, LDY, LDA, LDX, BAD, TAY, LDA, TAX, BAD, LDY, LDA, LDX, BAD, // Ax
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BCS, LDA, LDA, BAD, LDY, LDA, LDX, BAD, CLV, LDA, TSX, BAD, LDY, LDA, LDX, BAD, // Bx
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@ -65,6 +65,7 @@ static mos6502_instruction_handler instruction_handlers[] = {
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INST_HANDLER(bcs),
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INST_HANDLER(beq),
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INST_HANDLER(bit),
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INST_HANDLER(bim),
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INST_HANDLER(bmi),
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INST_HANDLER(bne),
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INST_HANDLER(bpl),
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@ -49,6 +49,7 @@ static char *instruction_strings[] = {
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"BCS",
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"BEQ",
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"BIT",
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"BIM",
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"BMI",
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"BNE",
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"BPL",
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@ -56,6 +56,23 @@ Test(mos6502_bits, bit)
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cr_assert_eq(cpu->P & MOS_ZERO, MOS_ZERO);
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}
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Test(mos6502_bits, bim)
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{
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// This version of BIT should not modify the NV flags
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cpu->P |= MOS_NEGATIVE;
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cpu->P |= MOS_OVERFLOW;
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cpu->A = 63;
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mos6502_handle_bim(cpu, 123);
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cr_assert_eq(cpu->P & MOS_ZERO, 0);
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cr_assert_eq(cpu->P & MOS_NEGATIVE, MOS_NEGATIVE);
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cr_assert_eq(cpu->P & MOS_OVERFLOW, MOS_OVERFLOW);
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cpu->A = 4;
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mos6502_handle_bim(cpu, 123);
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cr_assert_eq(cpu->P & MOS_ZERO, MOS_ZERO);
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}
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Test(mos6502_bits, eor)
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{
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cpu->A = 5;
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