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Add STZ instruction (to store zero)
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@ -122,6 +122,7 @@ enum instruction {
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STA, // STore Accumulator
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STX, // STore X
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STY, // STore Y
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STZ, // STore Zero
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TAX, // Transfer Accumulator to X
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TAY, // Transfer Accumulator to Y
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TSX, // Transfer Stack register to X
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@ -231,6 +231,7 @@ DECL_INST(sei);
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DECL_INST(sta);
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DECL_INST(stx);
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DECL_INST(sty);
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DECL_INST(stz);
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DECL_INST(tax);
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DECL_INST(tay);
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DECL_INST(tsx);
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@ -25,10 +25,10 @@ static int addr_modes[] = {
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REL, IDY, ZPG, NOA, ZPX, ZPX, ZPX, NOA, IMP, ABY, ACC, NOA, ABX, ABX, ABX, NOA, // 3x
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IMP, IDX, NOA, NOA, NOA, ZPG, ZPG, NOA, IMP, IMM, ACC, NOA, ABS, ABS, ABS, NOA, // 4x
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REL, IDY, ZPG, NOA, NOA, ZPX, ZPX, NOA, IMP, ABY, IMP, NOA, NOA, ABX, ABX, NOA, // 5x
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IMP, IDX, NOA, NOA, NOA, ZPG, ZPG, NOA, IMP, IMM, ACC, NOA, IND, ABS, ABS, NOA, // 6x
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REL, IDY, ZPG, NOA, NOA, ZPX, ZPX, NOA, IMP, ABY, IMP, NOA, ABX, ABX, ABX, NOA, // 7x
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IMP, IDX, NOA, NOA, ZPG, ZPG, ZPG, NOA, IMP, IMM, ACC, NOA, IND, ABS, ABS, NOA, // 6x
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REL, IDY, ZPG, NOA, ZPX, ZPX, ZPX, NOA, IMP, ABY, IMP, NOA, ABX, ABX, ABX, NOA, // 7x
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REL, IDX, NOA, NOA, ZPG, ZPG, ZPG, NOA, IMP, IMM, IMP, NOA, ABS, ABS, ABS, NOA, // 8x
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REL, IDY, ZPG, NOA, ZPX, ZPX, ZPY, NOA, IMP, ABY, IMP, NOA, NOA, ABX, NOA, NOA, // 9x
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REL, IDY, ZPG, NOA, ZPX, ZPX, ZPY, NOA, IMP, ABY, IMP, NOA, ABS, ABX, ABX, NOA, // 9x
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IMM, IDX, IMM, NOA, ZPG, ZPG, ZPG, NOA, IMP, IMM, IMP, NOA, ABS, ABS, ABS, NOA, // Ax
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REL, IDY, ZPG, NOA, ZPX, ZPX, ZPY, NOA, IMP, ABY, IMP, NOA, ABX, ABX, ABY, NOA, // Bx
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IMM, IDX, NOA, NOA, ZPG, ZPG, ZPG, NOA, IMP, IMM, IMP, NOA, ABS, ABS, ABS, NOA, // Cx
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@ -33,10 +33,10 @@ static int instructions[] = {
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BMI, AND, AND, BAD, BIT, AND, ROL, BAD, SEC, AND, DEC, BAD, BIT, AND, ROL, BAD, // 3x
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RTI, EOR, BAD, BAD, BAD, EOR, LSR, BAD, PHA, EOR, LSR, BAD, JMP, EOR, LSR, BAD, // 4x
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BVC, EOR, EOR, BAD, BAD, EOR, LSR, BAD, CLI, EOR, PHY, BAD, BAD, EOR, LSR, BAD, // 5x
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RTS, ADC, BAD, BAD, BAD, ADC, ROR, BAD, PLA, ADC, ROR, BAD, JMP, ADC, ROR, BAD, // 6x
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BVS, ADC, ADC, BAD, BAD, ADC, ROR, BAD, SEI, ADC, PLY, BAD, JMP, ADC, ROR, BAD, // 7x
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RTS, ADC, BAD, BAD, STZ, ADC, ROR, BAD, PLA, ADC, ROR, BAD, JMP, ADC, ROR, BAD, // 6x
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BVS, ADC, ADC, BAD, STZ, ADC, ROR, BAD, SEI, ADC, PLY, BAD, JMP, ADC, ROR, BAD, // 7x
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BRA, STA, BAD, BAD, STY, STA, STX, BAD, DEY, BIM, TXA, BAD, STY, STA, STX, BAD, // 8x
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BCC, STA, STA, BAD, STY, STA, STX, BAD, TYA, STA, TXS, BAD, BAD, STA, BAD, BAD, // 9x
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BCC, STA, STA, BAD, STY, STA, STX, BAD, TYA, STA, TXS, BAD, STZ, STA, STZ, BAD, // 9x
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LDY, LDA, LDX, BAD, LDY, LDA, LDX, BAD, TAY, LDA, TAX, BAD, LDY, LDA, LDX, BAD, // Ax
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BCS, LDA, LDA, BAD, LDY, LDA, LDX, BAD, CLV, LDA, TSX, BAD, LDY, LDA, LDX, BAD, // Bx
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CPY, CMP, BAD, BAD, CPY, CMP, DEC, BAD, INY, CMP, DEX, BAD, CPY, CMP, DEC, BAD, // Cx
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@ -114,6 +114,7 @@ static mos6502_instruction_handler instruction_handlers[] = {
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INST_HANDLER(sta),
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INST_HANDLER(stx),
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INST_HANDLER(sty),
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INST_HANDLER(stz),
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INST_HANDLER(tax),
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INST_HANDLER(tay),
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INST_HANDLER(tsx),
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@ -135,10 +136,10 @@ static int cycles[] = {
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2, 5, 5, 0, 4, 4, 6, 0, 2, 4, 2, 0, 4, 4, 7, 0, // 3x
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6, 6, 0, 0, 0, 3, 5, 0, 3, 2, 2, 0, 3, 4, 6, 0, // 4x
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2, 5, 5, 0, 0, 4, 6, 0, 2, 4, 3, 0, 0, 4, 7, 0, // 5x
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6, 6, 0, 0, 0, 3, 5, 0, 4, 2, 2, 0, 5, 4, 6, 0, // 6x
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2, 5, 5, 0, 0, 4, 6, 0, 2, 4, 4, 0, 6, 4, 7, 0, // 7x
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6, 6, 0, 0, 3, 3, 5, 0, 4, 2, 2, 0, 5, 4, 6, 0, // 6x
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2, 5, 5, 0, 4, 4, 6, 0, 2, 4, 4, 0, 6, 4, 7, 0, // 7x
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3, 6, 0, 0, 3, 3, 3, 0, 2, 2, 2, 0, 4, 4, 4, 0, // 8x
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2, 6, 5, 0, 4, 4, 4, 0, 2, 5, 2, 0, 0, 5, 0, 0, // 9x
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2, 6, 5, 0, 4, 4, 4, 0, 2, 5, 2, 0, 4, 5, 5, 0, // 9x
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2, 6, 2, 0, 3, 3, 3, 0, 2, 2, 2, 0, 4, 4, 4, 0, // Ax
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2, 5, 5, 0, 4, 4, 4, 0, 2, 4, 2, 0, 4, 4, 4, 0, // Bx
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2, 6, 0, 0, 3, 3, 5, 0, 2, 2, 2, 0, 4, 4, 3, 0, // Cx
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@ -98,6 +98,7 @@ static char *instruction_strings[] = {
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"STA",
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"STX",
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"STY",
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"STZ",
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"TAX",
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"TAY",
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"TSX",
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@ -129,6 +129,14 @@ DEFINE_INST(sty)
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mos6502_set(cpu, cpu->eff_addr, cpu->Y);
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}
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/*
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* Store a zero byte into the effective address
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*/
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DEFINE_INST(stz)
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{
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mos6502_set(cpu, cpu->eff_addr, 0);
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}
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/*
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* The TAX instruction taxes no one but your patience for my puns. What
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* it does do is transfer the contents of the A register to X.
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@ -110,6 +110,20 @@ Test(mos6502_loadstor, sty)
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cr_assert_eq(mos6502_get(cpu, cpu->eff_addr), cpu->Y);
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}
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Test(mos6502_loadstor, stz)
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{
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// To begin with, we want a non-zero value in eff_addr
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cpu->eff_addr = 111;
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mos6502_set(cpu, cpu->eff_addr, 222);
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// Furthermore, we pass in a non-zero operand to stz, which
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// _shouldn't_ care what the operand is. It should only assign a
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// zero to eff_addr.
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mos6502_handle_stz(cpu, 11);
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cr_assert_eq(mos6502_get(cpu, cpu->eff_addr), 0);
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}
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Test(mos6502_loadstor, tax)
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{
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cpu->A = 111;
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