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Add the ability to INC or DEC the accumulator

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This is an oversight from the 6502 processor that was rectified in the
65c02 model.
This commit is contained in:
Peter Evans 2018-02-21 21:20:05 -06:00
parent 7b65dc1657
commit 8623945bbf
4 changed files with 22 additions and 15 deletions
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4
src/mos6502.addr.c
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@ -20,9 +20,9 @@
static int addr_modes[] = {
// 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
IMP, IDX, NOA, NOA, NOA, ZPG, ZPG, NOA, IMP, IMM, ACC, NOA, NOA, ABS, ABS, NOA, // 0x
REL, IDY, ZPG, NOA, NOA, ZPX, ZPX, NOA, IMP, ABY, NOA, NOA, NOA, ABX, ABX, NOA, // 1x
REL, IDY, ZPG, NOA, NOA, ZPX, ZPX, NOA, IMP, ABY, ACC, NOA, NOA, ABX, ABX, NOA, // 1x
ABS, IDX, NOA, NOA, ZPG, ZPG, ZPG, NOA, IMP, IMM, ACC, NOA, ABS, ABS, ABS, NOA, // 2x
REL, IDY, ZPG, NOA, ZPX, ZPX, ZPX, NOA, IMP, ABY, NOA, NOA, ABX, ABX, ABX, NOA, // 3x
REL, IDY, ZPG, NOA, ZPX, ZPX, ZPX, NOA, IMP, ABY, ACC, NOA, ABX, ABX, ABX, NOA, // 3x
IMP, IDX, NOA, NOA, NOA, ZPG, ZPG, NOA, IMP, IMM, ACC, NOA, ABS, ABS, ABS, NOA, // 4x
REL, IDY, ZPG, NOA, NOA, ZPX, ZPX, NOA, IMP, ABY, NOA, NOA, NOA, ABX, ABX, NOA, // 5x
IMP, IDX, NOA, NOA, NOA, ZPG, ZPG, NOA, IMP, IMM, ACC, NOA, IND, ABS, ABS, NOA, // 6x

16
src/mos6502.arith.c
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@ -72,16 +72,19 @@ DEFINE_INST(cpy)
/*
* Here we will decrement the value at the effective address in memory
* by 1. The DEC instruction is _unable_ to decrement the accumulator,
* which was a tiny oversight in the original build of the 6502.
* (Whoopsie!)
* by 1.
*/
DEFINE_INST(dec)
{
if (cpu->eff_addr) {
mos6502_modify_status(cpu, MOS_NZ, oper, oper - 1);
mos6502_set(cpu, cpu->eff_addr, oper - 1);
return;
}
// If we get here, then this is ACC mode, and we should work off
// that.
cpu->A--;
}
/*
@ -103,16 +106,17 @@ DEFINE_INST(dey)
}
/*
* The INC instruction is basically the same as the DEC one. It, also,
* can only work with an address in memory, and it increments the value
* by 1.
* The INC instruction is basically the same as the DEC one.
*/
DEFINE_INST(inc)
{
if (cpu->eff_addr) {
mos6502_modify_status(cpu, MOS_NZ, oper, oper + 1);
mos6502_set(cpu, cpu->eff_addr, oper + 1);
return;
}
cpu->A++;
}
/*

8
src/mos6502.c
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@ -28,9 +28,9 @@
static int instructions[] = {
// 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
BRK, ORA, BAD, BAD, BAD, ORA, ASL, BAD, PHP, ORA, ASL, BAD, BAD, ORA, ASL, BAD, // 0x
BPL, ORA, ORA, BAD, BAD, ORA, ASL, BAD, CLC, ORA, BAD, BAD, BAD, ORA, ASL, BAD, // 1x
BPL, ORA, ORA, BAD, BAD, ORA, ASL, BAD, CLC, ORA, INC, BAD, BAD, ORA, ASL, BAD, // 1x
JSR, AND, BAD, BAD, BIT, AND, ROL, BAD, PLP, AND, ROL, BAD, BIT, AND, ROL, BAD, // 2x
BMI, AND, AND, BAD, BIT, AND, ROL, BAD, SEC, AND, BAD, BAD, BIT, AND, ROL, BAD, // 3x
BMI, AND, AND, BAD, BIT, AND, ROL, BAD, SEC, AND, DEC, BAD, BIT, AND, ROL, BAD, // 3x
RTI, EOR, BAD, BAD, BAD, EOR, LSR, BAD, PHA, EOR, LSR, BAD, JMP, EOR, LSR, BAD, // 4x
BVC, EOR, EOR, BAD, BAD, EOR, LSR, BAD, CLI, EOR, BAD, BAD, BAD, EOR, LSR, BAD, // 5x
RTS, ADC, BAD, BAD, BAD, ADC, ROR, BAD, PLA, ADC, ROR, BAD, JMP, ADC, ROR, BAD, // 6x
@ -125,9 +125,9 @@ static mos6502_instruction_handler instruction_handlers[] = {
static int cycles[] = {
// 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
7, 6, 0, 0, 0, 3, 5, 0, 3, 2, 2, 0, 0, 4, 6, 0, // 0x
2, 5, 5, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0, // 1x
2, 5, 5, 0, 0, 4, 6, 0, 2, 4, 2, 0, 0, 4, 7, 0, // 1x
6, 6, 0, 0, 3, 3, 5, 0, 4, 2, 2, 0, 4, 4, 6, 0, // 2x
2, 5, 5, 0, 4, 4, 6, 0, 2, 4, 0, 0, 4, 4, 7, 0, // 3x
2, 5, 5, 0, 4, 4, 6, 0, 2, 4, 2, 0, 4, 4, 7, 0, // 3x
6, 6, 0, 0, 0, 3, 5, 0, 3, 2, 2, 0, 3, 4, 6, 0, // 4x
2, 5, 5, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0, // 5x
6, 6, 0, 0, 0, 3, 5, 0, 4, 2, 2, 0, 5, 4, 6, 0, // 6x

9
tests/mos6502.arith.c
View File

@ -58,11 +58,9 @@ Test(mos6502_arith, cpy)
Test(mos6502_arith, dec)
{
// Note that DEC does NOT decrement the accumulator if the last
// address is not set. It does _nothing_.
cpu->A = 5;
mos6502_handle_dec(cpu, 0);
cr_assert_neq(cpu->A, 4);
cr_assert_eq(cpu->A, 4);
cpu->eff_addr = 123;
mos6502_set(cpu, 123, 44);
@ -93,6 +91,11 @@ Test(mos6502_arith, inc)
cpu->eff_addr = 123;
mos6502_handle_inc(cpu, 55);
cr_assert_eq(mos6502_get(cpu, 123), 56);
cpu->A = 8;
cpu->eff_addr = 0;
mos6502_handle_inc(cpu, 0);
cr_assert_eq(cpu->A, 9);
}
Test(mos6502_arith, inx)