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Implement the TRB (Test and Reset Bits) instruction
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@ -125,6 +125,7 @@ enum instruction {
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STZ, // STore Zero
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TAX, // Transfer Accumulator to X
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TAY, // Transfer Accumulator to Y
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TRB, // Test and Reset Bits
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TSX, // Transfer Stack register to X
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TXA, // Transfer X to Accumulator
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TXS, // Transfer X to Stack register
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@ -234,6 +234,7 @@ DECL_INST(sty);
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DECL_INST(stz);
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DECL_INST(tax);
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DECL_INST(tay);
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DECL_INST(trb);
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DECL_INST(tsx);
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DECL_INST(txa);
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DECL_INST(txs);
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@ -20,7 +20,7 @@
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static int addr_modes[] = {
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// 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
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IMP, IDX, NOA, NOA, NOA, ZPG, ZPG, NOA, IMP, IMM, ACC, NOA, NOA, ABS, ABS, NOA, // 0x
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REL, IDY, ZPG, NOA, NOA, ZPX, ZPX, NOA, IMP, ABY, ACC, NOA, NOA, ABX, ABX, NOA, // 1x
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REL, IDY, ZPG, NOA, ZPG, ZPX, ZPX, NOA, IMP, ABY, ACC, NOA, ABS, ABX, ABX, NOA, // 1x
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ABS, IDX, NOA, NOA, ZPG, ZPG, ZPG, NOA, IMP, IMM, ACC, NOA, ABS, ABS, ABS, NOA, // 2x
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REL, IDY, ZPG, NOA, ZPX, ZPX, ZPX, NOA, IMP, ABY, ACC, NOA, ABX, ABX, ABX, NOA, // 3x
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IMP, IDX, NOA, NOA, NOA, ZPG, ZPG, NOA, IMP, IMM, ACC, NOA, ABS, ABS, ABS, NOA, // 4x
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@ -28,7 +28,7 @@
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static int instructions[] = {
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// 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
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BRK, ORA, BAD, BAD, BAD, ORA, ASL, BAD, PHP, ORA, ASL, BAD, BAD, ORA, ASL, BAD, // 0x
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BPL, ORA, ORA, BAD, BAD, ORA, ASL, BAD, CLC, ORA, INC, BAD, BAD, ORA, ASL, BAD, // 1x
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BPL, ORA, ORA, BAD, TRB, ORA, ASL, BAD, CLC, ORA, INC, BAD, TRB, ORA, ASL, BAD, // 1x
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JSR, AND, BAD, BAD, BIT, AND, ROL, BAD, PLP, AND, ROL, BAD, BIT, AND, ROL, BAD, // 2x
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BMI, AND, AND, BAD, BIT, AND, ROL, BAD, SEC, AND, DEC, BAD, BIT, AND, ROL, BAD, // 3x
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RTI, EOR, BAD, BAD, BAD, EOR, LSR, BAD, PHA, EOR, LSR, BAD, JMP, EOR, LSR, BAD, // 4x
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@ -117,6 +117,7 @@ static mos6502_instruction_handler instruction_handlers[] = {
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INST_HANDLER(stz),
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INST_HANDLER(tax),
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INST_HANDLER(tay),
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INST_HANDLER(trb),
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INST_HANDLER(tsx),
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INST_HANDLER(txa),
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INST_HANDLER(txs),
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@ -131,7 +132,7 @@ static mos6502_instruction_handler instruction_handlers[] = {
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static int cycles[] = {
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// 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
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7, 6, 0, 0, 0, 3, 5, 0, 3, 2, 2, 0, 0, 4, 6, 0, // 0x
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2, 5, 5, 0, 0, 4, 6, 0, 2, 4, 2, 0, 0, 4, 7, 0, // 1x
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2, 5, 5, 0, 5, 4, 6, 0, 2, 4, 2, 0, 6, 4, 7, 0, // 1x
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6, 6, 0, 0, 3, 3, 5, 0, 4, 2, 2, 0, 4, 4, 6, 0, // 2x
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2, 5, 5, 0, 4, 4, 6, 0, 2, 4, 2, 0, 4, 4, 7, 0, // 3x
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6, 6, 0, 0, 0, 3, 5, 0, 3, 2, 2, 0, 3, 4, 6, 0, // 4x
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@ -101,6 +101,7 @@ static char *instruction_strings[] = {
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"STZ",
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"TAX",
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"TAY",
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"TRB",
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"TSX",
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"TXA",
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"TXS",
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@ -156,6 +156,37 @@ DEFINE_INST(tay)
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cpu->Y = cpu->A;
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}
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/*
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* This is a really funky instruction. And not in the good, dancy kinda
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* way.
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*
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* First, it does a BIT-style test to see if A & oper are zero; if so,
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* it sets the Z flag.
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*
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* Second, it clears all bits in eff_addr where A's corresponding bits
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* are set to 1. It ignores all bits in eff_addr where A's bits are
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* zero.
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*
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* E.g.:
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*
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* A: 01011001 (accumulator)
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* M: 11111111 (value in memory)
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* R: 10100110 (result)
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*
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* And, as following that, the Z flag should be zero because A&M is a
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* non-zero result.
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*/
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DEFINE_INST(trb)
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{
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cpu->P &= ~MOS_ZERO;
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if (!(cpu->A & oper)) {
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cpu->P |= MOS_ZERO;
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}
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mos6502_set(cpu, cpu->eff_addr,
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(cpu->A ^ 0xff) & oper);
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}
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/*
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* Transfer the stack pointer (S register) to X.
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*/
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@ -140,6 +140,23 @@ Test(mos6502_loadstor, tay)
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cr_assert_eq(cpu->Y, 111);
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}
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Test(mos6502_loadstor, trb)
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{
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cpu->A = 6;
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mos6502_handle_trb(cpu, 3);
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cr_assert_eq(cpu->P & MOS_ZERO, 0);
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cpu->A = 9;
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mos6502_handle_trb(cpu, 2);
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cr_assert_eq(cpu->P & MOS_ZERO, MOS_ZERO);
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cpu->eff_addr = 111;
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mos6502_set(cpu, cpu->eff_addr, 123);
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mos6502_handle_trb(cpu, 123);
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cr_assert_eq(mos6502_get(cpu, cpu->eff_addr),
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(cpu->A ^ 0xff) & 123);
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}
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Test(mos6502_loadstor, tsx)
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{
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cpu->S = 111;
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