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Add missing tests for read/write bank switches
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@ -130,6 +130,48 @@ Test(apple2_mem, write_bank)
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cr_assert_eq(vm_segment_get(mach->main, 0x10073), right);
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}
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Test(apple2_mem, read_bank_switch)
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{
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vm_segment_get(mach->main, 0xC080);
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cr_assert_eq(mach->bank_switch, MEMORY_RAM2);
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vm_segment_get(mach->main, 0xC081);
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cr_assert_eq(mach->bank_switch, MEMORY_ROM | MEMORY_WRITE | MEMORY_RAM2);
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vm_segment_get(mach->main, 0xC082);
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cr_assert_eq(mach->bank_switch, MEMORY_ROM | MEMORY_RAM2);
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vm_segment_get(mach->main, 0xC083);
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cr_assert_eq(mach->bank_switch, MEMORY_WRITE | MEMORY_RAM2);
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vm_segment_get(mach->main, 0xC088);
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cr_assert_eq(mach->bank_switch, 0);
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vm_segment_get(mach->main, 0xC089);
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cr_assert_eq(mach->bank_switch, MEMORY_ROM | MEMORY_WRITE);
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vm_segment_get(mach->main, 0xC08A);
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cr_assert_eq(mach->bank_switch, MEMORY_ROM);
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vm_segment_get(mach->main, 0xC08B);
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cr_assert_eq(mach->bank_switch, MEMORY_WRITE);
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mach->bank_switch = MEMORY_RAM2;
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cr_assert_eq(vm_segment_get(mach->main, 0xC011), 0x80);
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mach->bank_switch = 0;
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cr_assert_eq(vm_segment_get(mach->main, 0xC011), 0x00);
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mach->bank_switch = 0;
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cr_assert_eq(vm_segment_get(mach->main, 0xC012), 0x80);
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mach->bank_switch = MEMORY_ROM;
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cr_assert_eq(vm_segment_get(mach->main, 0xC012), 0x00);
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mach->bank_switch = MEMORY_AUX;
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cr_assert_eq(vm_segment_get(mach->main, 0xC016), 0x80);
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mach->bank_switch = 0;
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cr_assert_eq(vm_segment_get(mach->main, 0xC016), 0x00);
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}
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Test(apple2_mem, write_bank_switch)
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{
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vm_segment_set(mach->main, 0xC008, 1);
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cr_assert_eq(mach->bank_switch & MEMORY_AUX, MEMORY_AUX);
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vm_segment_set(mach->main, 0xC009, 1);
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cr_assert_eq(mach->bank_switch & MEMORY_AUX, 0);
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}
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Test(apple2_mem, init_peripheral_rom)
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{
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// FIXME: this isn't working, _and_ it's pretty tightly coupled into
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