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Add new Branch Always instruction

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This commit is contained in:
Peter Evans 2018-02-21 21:57:21 -06:00
parent 58a1e31f58
commit f9a277e7bc
7 changed files with 25 additions and 3 deletions
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1
include/mos6502.enums.h
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@ -77,6 +77,7 @@ enum instruction {
BMI, // Branch on MInus
BNE, // Branch on Not Equal to zero
BPL, // Branch on PLus
BRA, // BRanch Always
BRK, // BReaK (interrupt)
BVC, // Branch on oVerflow Clear
BVS, // Branch on oVerflow Set

1
include/mos6502.h
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@ -186,6 +186,7 @@ DECL_INST(bim);
DECL_INST(bmi);
DECL_INST(bne);
DECL_INST(bpl);
DECL_INST(bra);
DECL_INST(brk);
DECL_INST(bvc);
DECL_INST(bvs);

2
src/mos6502.addr.c
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@ -27,7 +27,7 @@ static int addr_modes[] = {
REL, IDY, ZPG, NOA, NOA, ZPX, ZPX, NOA, IMP, ABY, NOA, NOA, NOA, ABX, ABX, NOA, // 5x
IMP, IDX, NOA, NOA, NOA, ZPG, ZPG, NOA, IMP, IMM, ACC, NOA, IND, ABS, ABS, NOA, // 6x
REL, IDY, ZPG, NOA, NOA, ZPX, ZPX, NOA, IMP, ABY, NOA, NOA, ABX, ABX, ABX, NOA, // 7x
NOA, IDX, NOA, NOA, ZPG, ZPG, ZPG, NOA, IMP, IMM, IMP, NOA, ABS, ABS, ABS, NOA, // 8x
REL, IDX, NOA, NOA, ZPG, ZPG, ZPG, NOA, IMP, IMM, IMP, NOA, ABS, ABS, ABS, NOA, // 8x
REL, IDY, ZPG, NOA, ZPX, ZPX, ZPY, NOA, IMP, ABY, IMP, NOA, NOA, ABX, NOA, NOA, // 9x
IMM, IDX, IMM, NOA, ZPG, ZPG, ZPG, NOA, IMP, IMM, IMP, NOA, ABS, ABS, ABS, NOA, // Ax
REL, IDY, ZPG, NOA, ZPX, ZPX, ZPY, NOA, IMP, ABY, IMP, NOA, ABX, ABX, ABY, NOA, // Bx

10
src/mos6502.branch.c
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@ -67,6 +67,16 @@ DEFINE_INST(bpl)
JUMP_IF(~cpu->P & MOS_NEGATIVE);
}
/*
* This instruction will branch in all cases. It's not a true
* conditional; it's analagous to a relative address mode JMP.
*/
DEFINE_INST(bra)
{
// Always jump!
JUMP_IF(1);
}
/*
* Branch if the overflow bit is clear.
*/

5
src/mos6502.c
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@ -35,7 +35,7 @@ static int instructions[] = {
BVC, EOR, EOR, BAD, BAD, EOR, LSR, BAD, CLI, EOR, BAD, BAD, BAD, EOR, LSR, BAD, // 5x
RTS, ADC, BAD, BAD, BAD, ADC, ROR, BAD, PLA, ADC, ROR, BAD, JMP, ADC, ROR, BAD, // 6x
BVS, ADC, ADC, BAD, BAD, ADC, ROR, BAD, SEI, ADC, BAD, BAD, JMP, ADC, ROR, BAD, // 7x
BAD, STA, BAD, BAD, STY, STA, STX, BAD, DEY, BIM, TXA, BAD, STY, STA, STX, BAD, // 8x
BRA, STA, BAD, BAD, STY, STA, STX, BAD, DEY, BIM, TXA, BAD, STY, STA, STX, BAD, // 8x
BCC, STA, STA, BAD, STY, STA, STX, BAD, TYA, STA, TXS, BAD, BAD, STA, BAD, BAD, // 9x
LDY, LDA, LDX, BAD, LDY, LDA, LDX, BAD, TAY, LDA, TAX, BAD, LDY, LDA, LDX, BAD, // Ax
BCS, LDA, LDA, BAD, LDY, LDA, LDX, BAD, CLV, LDA, TSX, BAD, LDY, LDA, LDX, BAD, // Bx
@ -69,6 +69,7 @@ static mos6502_instruction_handler instruction_handlers[] = {
INST_HANDLER(bmi),
INST_HANDLER(bne),
INST_HANDLER(bpl),
INST_HANDLER(bra),
INST_HANDLER(brk),
INST_HANDLER(bvc),
INST_HANDLER(bvs),
@ -132,7 +133,7 @@ static int cycles[] = {
2, 5, 5, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0, // 5x
6, 6, 0, 0, 0, 3, 5, 0, 4, 2, 2, 0, 5, 4, 6, 0, // 6x
2, 5, 5, 0, 0, 4, 6, 0, 2, 4, 0, 0, 6, 4, 7, 0, // 7x
0, 6, 0, 0, 3, 3, 3, 0, 2, 2, 2, 0, 4, 4, 4, 0, // 8x
3, 6, 0, 0, 3, 3, 3, 0, 2, 2, 2, 0, 4, 4, 4, 0, // 8x
2, 6, 5, 0, 4, 4, 4, 0, 2, 5, 2, 0, 0, 5, 0, 0, // 9x
2, 6, 2, 0, 3, 3, 3, 0, 2, 2, 2, 0, 4, 4, 4, 0, // Ax
2, 5, 5, 0, 4, 4, 4, 0, 2, 4, 2, 0, 4, 4, 4, 0, // Bx

1
src/mos6502.dis.c
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@ -53,6 +53,7 @@ static char *instruction_strings[] = {
"BMI",
"BNE",
"BPL",
"BRA",
"BRK",
"BVC",
"BVS",

8
tests/mos6502.branch.c
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@ -78,6 +78,14 @@ Test(mos6502_branch, bpl)
cr_assert_eq(cpu->PC, 125);
}
Test(mos6502_branch, bra)
{
cr_assert_eq(cpu->PC, 0);
cpu->eff_addr = 123;
mos6502_handle_bra(cpu, 0);
cr_assert_eq(cpu->PC, 123);
}
Test(mos6502_branch, bvc)
{
cpu->eff_addr = 123;