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Commit Graph

551 Commits

Author SHA1 Message Date
Peter Evans
bee2a0e86a Add missing docblocks for NP2 and NP3 2018-02-22 14:10:19 -06:00
Peter Evans
978ad1faaf Formerly "BAD" instructions are now forms of NOPs
But weird forms. In most cases they basically are NOPs, except with
different opcodes. In other cases, we call them NP2 and NP3s, and do so
because they consume 2 or 3 bytes respectively (vs. just 1 with NOP).

We had to teach some arcane magic to the emulator for this to work. We
may want to refactor to decouple the number of bytes consumed from the
address mode.
2018-02-22 14:07:05 -06:00
Peter Evans
691387894a ASL, LSR, ROL, ROR in ABX now consume only 6 cycles
(Down from 7 cycles.)
2018-02-22 13:45:36 -06:00
Peter Evans
e35ff91fa7 Clear the decimal bit in BRK; also improve test logic for BRK 2018-02-22 13:44:13 -06:00
Peter Evans
90892c32e4 Add TSB (Test and Set Bits) instruction
This commit also moves the TRB code from loadstor to bits, which is
where it should have been all along.
2018-02-22 13:39:48 -06:00
Peter Evans
a4c3d1c4ef Implement the TRB (Test and Reset Bits) instruction 2018-02-22 00:39:33 -06:00
Peter Evans
807362e871 Add STZ instruction (to store zero) 2018-02-22 00:02:57 -06:00
Peter Evans
7363547608 Add PHX/Y and PLX/Y to the opcode, addr mode, cycle tables 2018-02-21 23:35:36 -06:00
Peter Evans
8e1ab0e950 Add support for PHX, PHY, PLX, PLY
These instructions allow you to push and pull (pop) the X and Y
registers via the stack.
2018-02-21 23:32:57 -06:00
Peter Evans
f9a277e7bc Add new Branch Always instruction 2018-02-21 21:57:21 -06:00
Peter Evans
58a1e31f58 Allow JMP to work with ABX address mode 2018-02-21 21:46:41 -06:00
Peter Evans
8623945bbf Add the ability to INC or DEC the accumulator
This is an oversight from the 6502 processor that was rectified in the
65c02 model.
2018-02-21 21:20:05 -06:00
Peter Evans
7b65dc1657 Add new BIM instruction (BIt imMediate mode)
This is not a real instruction in the 65c02 processor; I invented it for
the sole purpose of handling the specialized logic that is performed by
BIT in IMM mode. To be fair--I can imagine this really _was_ implemented
as a "separate" instruction on the chip! But I don't know that for sure.
2018-02-21 21:01:46 -06:00
Peter Evans
5ba5f91442 Add new address modes for BIT 2018-02-21 20:46:28 -06:00
Peter Evans
e1f11fc266 Add cycle counts 2018-02-21 20:43:04 -06:00
Peter Evans
739451366f Add zero-page instructions 2018-02-21 20:42:05 -06:00
Peter Evans
48872cf8d1 Add docblock comment for apple2_dd_sector_num 2018-02-21 11:23:25 -06:00
Peter Evans
61eb880f49 Refactor code to pass image type in 2018-02-21 00:23:12 -06:00
Peter Evans
8706a81d1f Remove spurious printf 2018-02-20 15:55:40 -06:00
Peter Evans
1091ec6e2a Pass image type into enc_dos; use sector_num instead of a table pointer 2018-02-20 15:36:23 -06:00
Peter Evans
c2e90651ac Again, latch data must be > 128 (0x80) 2018-02-20 14:44:17 -06:00
Peter Evans
e826fc05d9 We can only write latch data that is > 128 2018-02-20 14:43:33 -06:00
Peter Evans
98f640f0d1 Use the proper sector header length (20 bytes) 2018-02-20 14:35:07 -06:00
Peter Evans
08f3899de4 Tracks don't move from shifting; sector work
The sector work being:

- We only wrap around if we go beyond the length of an encoded track, so
use ENC_ETRACK.
- If we DO wrap around, we don't use modulus; we simply reset to zero.
2018-02-20 14:33:36 -06:00
Peter Evans
c7fbb4aa50 Backward steps require adjacent phases 2018-02-20 14:30:20 -06:00
Peter Evans
28061c1d11 Adjust length/data for sectors; cleanup some magic numbers 2018-02-20 01:00:46 -06:00
Peter Evans
2318b1917a This form needs two RORs to work
That's because the first ROR pushes the 1 in bit0 into the carry bit;
the second moves the carry bit into the bit7 position, which will match
128.
2018-02-19 22:01:30 -06:00
Peter Evans
d590a809d8 Tests should reflect how carry is handled in ROL/R now 2018-02-19 21:59:55 -06:00
Peter Evans
65f13bb1e4 Add missing output and fix buffer size issue
We use BUFSIZ everywhere, except in setvbuf(), which kinda needs to know
the proper buffer size. Because we were passing 256, which is (much!)
lower than BUFSIZ, we were wrapping output around in an odd, unexpected
way.
2018-02-19 21:49:58 -06:00
Peter Evans
9f0d7f5413 Fix some compile failures due to changed params 2018-02-19 20:03:25 -06:00
Peter Evans
508be6458a Pass in sector table for logical-physical orders
We were not encoding data properly, because in DOS 3.3 and ProDOS,
sectors must be interleaved on disk media (whereas in the original image
form, data is laid out in a linear fashion).

This solves a bug where we erroneously encountered a "bad" opcode (a7)
in the program code.
2018-02-19 18:49:37 -06:00
Peter Evans
3ab654c306 Correct note on GBASL/H address 2018-02-19 13:53:48 -06:00
Peter Evans
96e4b5d9d8 Remove JSR WAIT to speed up disk II controller 2018-02-19 00:48:11 -06:00
Peter Evans
015104bd57 Self-sync bytes should be written after a sector header
Not after the data field marker, where the controller/RWTS don't expect
to find them.
2018-02-18 23:46:48 -06:00
Peter Evans
c89e855559 Update to use correct encoded sector length 2018-02-18 23:46:18 -06:00
Peter Evans
00854e74b9 Explain how the JSR call is handled in some impls 2018-02-18 19:49:34 -06:00
Peter Evans
0fccf552f2 Final comments 2018-02-18 11:16:09 -06:00
Peter Evans
7c2c6d5d54 Reformat and annotate disk II controller code 2018-02-18 00:50:50 -06:00
Peter Evans
0d1e949d13 Mask the result so it's never more than a byte
This is because the eff_addr variable is a 16bit one, and adding addr +
X or addr + Y can possibly result in a 9-bit value, which is not what we
want. (You'd be pulling data from the stack instead of the zero page.)
2018-02-16 00:44:55 -06:00
Peter Evans
e9164d9872 Very minor changes to make the code simpler 2018-02-16 00:19:14 -06:00
Peter Evans
058b45e7d1 Use 9-bit rotation, not 8-bit 2018-02-15 19:32:01 -06:00
Peter Evans
067c0cea2f Also check the N flag (i.e. set it to zero) 2018-02-15 13:01:58 -06:00
Peter Evans
e415b3e490 We should check only the first byte for zero
We need to accept values for result that are greater than a byte so that
we can determine if carry is set, but this causes an issue when an app
uses addition to force an overflow that would set the zero bit. Masking
result for only the LSB fixes that problem.
2018-02-15 00:26:21 -06:00
Peter Evans
08b0e2e648 Show effective address 2018-02-14 22:19:35 -06:00
Peter Evans
fe70cd1f71 Remove debugging, use ENC_ETRACK for sector pos max
Also, there's no need for a while statement; we can just reset to zero.
2018-02-14 22:09:21 -06:00
Peter Evans
7224698cd7 This should be EOR, not ADC
I might as well fix the bad opcode here, too!
2018-02-14 21:50:13 -06:00
Peter Evans
9a5c94bbbb The 49 opcode is EOR, not ADC.
Excuse me, I just need to scream now.

AHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH

Thank you for your indulgence. Please carry on.
2018-02-14 21:37:02 -06:00
Peter Evans
64b9cbefcb Several changes to phase and writes
1. The phaser algorithm was reworked, and it should be more accurate in
choosing when to step forward or backward.
2. Writes should be committed when the latch has bit 7 high. This hasn't
actually been a problem yet, since other things are broken! But we might
as well fix it now that we've seen it.
2018-02-14 16:49:20 -06:00
Peter Evans
100621a6c6 Show second-digit row mappings for gcr62 2018-02-12 21:20:09 -06:00
Peter Evans
5b1298bded Document the gcr62 table 2018-02-12 21:19:47 -06:00