2013-02-28 17:01:31 +00:00
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/*
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Package opcodes stores metadata/information about 6502 opcodes. It's
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used for disassembly, and (in the future) for building the opcode
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function tables.
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*/
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package opcodes
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// Opcode addressing modes.
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2014-03-05 01:42:51 +00:00
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type AddressingMode uint
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const MODE_UNKNOWN = 0
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2013-02-28 17:01:31 +00:00
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const (
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2014-03-05 01:42:51 +00:00
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MODE_IMPLIED AddressingMode = 1 << iota
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MODE_ABSOLUTE
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MODE_INDIRECT
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MODE_RELATIVE
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MODE_IMMEDIATE
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MODE_ABS_X
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MODE_ABS_Y
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MODE_ZP
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MODE_ZP_X
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MODE_ZP_Y
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MODE_INDIRECT_Y
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MODE_INDIRECT_X
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MODE_A
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)
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2014-03-05 01:42:51 +00:00
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// Logical OR of the three indirect modes
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const MODE_INDIRECT_ANY AddressingMode = MODE_INDIRECT | MODE_INDIRECT_X | MODE_INDIRECT_Y
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2013-03-01 00:33:39 +00:00
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// Opcode read/write semantics: does the opcode read, write, or
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// rmw. Useful to distinguish between instructions further than just
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// addressing mode.
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type ReadWrite int
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2013-02-28 17:01:31 +00:00
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const (
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2013-03-01 00:33:39 +00:00
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RW_X ReadWrite = 0 // Don't care
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RW_R ReadWrite = 1
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RW_W ReadWrite = 2
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RW_RMW ReadWrite = 3
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2013-02-28 17:01:31 +00:00
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)
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// Lengths of instructions for each addressing mode.
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2013-03-01 00:33:39 +00:00
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var ModeLengths = map[AddressingMode]int{
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2013-02-28 17:01:31 +00:00
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MODE_IMPLIED: 1,
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MODE_ABSOLUTE: 3,
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MODE_INDIRECT: 3,
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MODE_RELATIVE: 2,
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MODE_IMMEDIATE: 2,
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MODE_ABS_X: 3,
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MODE_ABS_Y: 3,
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MODE_ZP: 2,
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MODE_ZP_X: 2,
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MODE_ZP_Y: 2,
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MODE_INDIRECT_Y: 2,
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MODE_INDIRECT_X: 2,
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MODE_A: 1,
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}
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// Opcode stores information about instructions.
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type Opcode struct {
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Name string
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2013-03-01 00:33:39 +00:00
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Mode AddressingMode
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RW ReadWrite
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2013-02-28 17:01:31 +00:00
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}
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// Fake NoOp instruction used when disassembling.
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var NoOp = Opcode{"???", MODE_IMPLIED, RW_X}
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// The list of Opcodes.
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var Opcodes = map[byte]Opcode{
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// BUG(zellyn): Add 65C02 instructions.
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// Flag set and clear
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0x18: {"CLC", MODE_IMPLIED, RW_X}, // CLC
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0xD8: {"CLD", MODE_IMPLIED, RW_X}, // CLD
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0x58: {"CLI", MODE_IMPLIED, RW_X}, // CLI
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0xB8: {"CLV", MODE_IMPLIED, RW_X}, // CLV
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0x38: {"SEC", MODE_IMPLIED, RW_X}, // SEC
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0xF8: {"SED", MODE_IMPLIED, RW_X}, // SED
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0x78: {"SEI", MODE_IMPLIED, RW_X}, // SEI
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// Very simple 1-opcode instructions
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0xEA: {"NOP", MODE_IMPLIED, RW_X},
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0xAA: {"TAX", MODE_IMPLIED, RW_X},
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0xA8: {"TAY", MODE_IMPLIED, RW_X},
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0xBA: {"TSX", MODE_IMPLIED, RW_X},
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0x8A: {"TXA", MODE_IMPLIED, RW_X},
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0x9A: {"TXS", MODE_IMPLIED, RW_X},
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0x98: {"TYA", MODE_IMPLIED, RW_X},
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// Slightly more complex 1-opcode instructions
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0xCA: {"DEX", MODE_IMPLIED, RW_X},
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0x88: {"DEY", MODE_IMPLIED, RW_X},
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0xE8: {"INX", MODE_IMPLIED, RW_X},
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0xC8: {"INY", MODE_IMPLIED, RW_X},
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0x48: {"PHA", MODE_IMPLIED, RW_X},
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0x08: {"PHP", MODE_IMPLIED, RW_X},
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0x68: {"PLA", MODE_IMPLIED, RW_X},
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0x28: {"PLP", MODE_IMPLIED, RW_X},
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// Jumps, returns, etc.
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0x4C: {"JMP", MODE_ABSOLUTE, RW_X},
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0x6C: {"JMP", MODE_INDIRECT, RW_X},
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0x20: {"JSR", MODE_ABSOLUTE, RW_X},
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0x60: {"RTS", MODE_IMPLIED, RW_X},
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0x40: {"RTI", MODE_IMPLIED, RW_X},
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0x00: {"BRK", MODE_IMPLIED, RW_X},
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// Branches
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0x90: {"BCC", MODE_RELATIVE, RW_X}, // BCC
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0xB0: {"BCS", MODE_RELATIVE, RW_X}, // BCS
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0xF0: {"BEQ", MODE_RELATIVE, RW_X}, // BEQ
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0x30: {"BMI", MODE_RELATIVE, RW_X}, // BMI
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0xD0: {"BNE", MODE_RELATIVE, RW_X}, // BNE
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0x10: {"BPL", MODE_RELATIVE, RW_X}, // BPL
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0x50: {"BVC", MODE_RELATIVE, RW_X}, // BVC
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0x70: {"BVS", MODE_RELATIVE, RW_X}, // BVS
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// 2-opcode, 2-cycle immediate mode
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0x09: {"ORA", MODE_IMMEDIATE, RW_R},
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0x29: {"AND", MODE_IMMEDIATE, RW_R},
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0x49: {"EOR", MODE_IMMEDIATE, RW_R},
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0x69: {"ADC", MODE_IMMEDIATE, RW_R},
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0xC0: {"CPY", MODE_IMMEDIATE, RW_R},
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0xC9: {"CMP", MODE_IMMEDIATE, RW_R},
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0xA0: {"LDY", MODE_IMMEDIATE, RW_R},
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0xA2: {"LDX", MODE_IMMEDIATE, RW_R},
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0xA9: {"LDA", MODE_IMMEDIATE, RW_R},
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0xE0: {"CPX", MODE_IMMEDIATE, RW_R},
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0xE9: {"SBC", MODE_IMMEDIATE, RW_R},
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// 3-opcode, 4-cycle absolute mode
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0x8D: {"STA", MODE_ABSOLUTE, RW_W},
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0x8E: {"STX", MODE_ABSOLUTE, RW_W},
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0x8C: {"STY", MODE_ABSOLUTE, RW_W},
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0x6D: {"ADC", MODE_ABSOLUTE, RW_R},
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0x2D: {"AND", MODE_ABSOLUTE, RW_R},
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0x2C: {"BIT", MODE_ABSOLUTE, RW_R},
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0xCD: {"CMP", MODE_ABSOLUTE, RW_R},
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0xEC: {"CPX", MODE_ABSOLUTE, RW_R},
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0xCC: {"CPY", MODE_ABSOLUTE, RW_R},
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0x4D: {"EOR", MODE_ABSOLUTE, RW_R},
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0xAD: {"LDA", MODE_ABSOLUTE, RW_R},
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0xAE: {"LDX", MODE_ABSOLUTE, RW_R},
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0xAC: {"LDY", MODE_ABSOLUTE, RW_R},
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0x0D: {"ORA", MODE_ABSOLUTE, RW_R},
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0xED: {"SBC", MODE_ABSOLUTE, RW_R},
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// 2-opcode, 3-cycle zero page
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0x05: {"ORA", MODE_ZP, RW_R},
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0x24: {"BIT", MODE_ZP, RW_R},
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0x25: {"AND", MODE_ZP, RW_R},
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0x45: {"EOR", MODE_ZP, RW_R},
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0x65: {"ADC", MODE_ZP, RW_R},
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0x84: {"STY", MODE_ZP, RW_W},
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0x85: {"STA", MODE_ZP, RW_W},
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0x86: {"STX", MODE_ZP, RW_W},
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0xA4: {"LDY", MODE_ZP, RW_R},
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0xA5: {"LDA", MODE_ZP, RW_R},
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0xA6: {"LDX", MODE_ZP, RW_R},
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0xC4: {"CPY", MODE_ZP, RW_R},
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0xC5: {"CMP", MODE_ZP, RW_R},
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0xE4: {"CPX", MODE_ZP, RW_R},
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0xE5: {"SBC", MODE_ZP, RW_R},
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// 3-opcode, 4*-cycle abs,X/Y
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0x1D: {"ORA", MODE_ABS_X, RW_R},
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2014-03-05 01:42:51 +00:00
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0x19: {"ORA", MODE_ABS_Y, RW_R},
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0x39: {"AND", MODE_ABS_Y, RW_R},
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2013-02-28 17:01:31 +00:00
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0x3D: {"AND", MODE_ABS_X, RW_R},
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2014-03-05 01:42:51 +00:00
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0x59: {"EOR", MODE_ABS_Y, RW_R},
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2013-02-28 17:01:31 +00:00
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0x5D: {"EOR", MODE_ABS_X, RW_R},
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2014-03-05 01:42:51 +00:00
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0x79: {"ADC", MODE_ABS_Y, RW_R},
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2013-02-28 17:01:31 +00:00
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0x7D: {"ADC", MODE_ABS_X, RW_R},
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2014-03-05 01:42:51 +00:00
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0xB9: {"LDA", MODE_ABS_Y, RW_R},
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2013-02-28 17:01:31 +00:00
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0xBD: {"LDA", MODE_ABS_X, RW_R},
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2014-03-05 01:42:51 +00:00
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0xD9: {"CMP", MODE_ABS_Y, RW_R},
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2013-02-28 17:01:31 +00:00
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0xDD: {"CMP", MODE_ABS_X, RW_R},
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2014-03-05 01:42:51 +00:00
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0xF9: {"SBC", MODE_ABS_Y, RW_R},
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2013-02-28 17:01:31 +00:00
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0xFD: {"SBC", MODE_ABS_X, RW_R},
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2014-03-05 01:42:51 +00:00
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0xBE: {"LDX", MODE_ABS_Y, RW_R},
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2013-02-28 17:01:31 +00:00
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0xBC: {"LDY", MODE_ABS_X, RW_R},
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// 3-opcode, 5-cycle abs,X/Y
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0x99: {"STA", MODE_ABS_Y, RW_W},
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0x9D: {"STA", MODE_ABS_X, RW_W},
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// 2-opcode, 4-cycle zp,X/Y
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0x15: {"ORA", MODE_ZP_X, RW_R},
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0x35: {"AND", MODE_ZP_X, RW_R},
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0x55: {"EOR", MODE_ZP_X, RW_R},
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0x75: {"ADC", MODE_ZP_X, RW_R},
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0x95: {"STA", MODE_ZP_X, RW_W},
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0xB5: {"LDA", MODE_ZP_X, RW_R},
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0xD5: {"CMP", MODE_ZP_X, RW_R},
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0xF5: {"SBC", MODE_ZP_X, RW_R},
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0x96: {"STX", MODE_ZP_Y, RW_W},
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0xB6: {"LDX", MODE_ZP_Y, RW_R},
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0x94: {"STY", MODE_ZP_X, RW_W},
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0xB4: {"LDY", MODE_ZP_X, RW_R},
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// 2-opcode, 5*-cycle zero-page indirect Y
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0x11: {"ORA", MODE_INDIRECT_Y, RW_R},
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0x31: {"AND", MODE_INDIRECT_Y, RW_R},
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0x51: {"EOR", MODE_INDIRECT_Y, RW_R},
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0x71: {"ADC", MODE_INDIRECT_Y, RW_R},
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0x91: {"STA", MODE_INDIRECT_Y, RW_W},
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0xB1: {"LDA", MODE_INDIRECT_Y, RW_R},
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0xD1: {"CMP", MODE_INDIRECT_Y, RW_R},
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0xF1: {"SBC", MODE_INDIRECT_Y, RW_R},
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// 2-opcode, 6-cycle zero-page X indirect
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0x01: {"ORA", MODE_INDIRECT_X, RW_R},
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0x21: {"AND", MODE_INDIRECT_X, RW_R},
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0x41: {"EOR", MODE_INDIRECT_X, RW_R},
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0x61: {"ADC", MODE_INDIRECT_X, RW_R},
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0x81: {"STA", MODE_INDIRECT_X, RW_W},
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0xA1: {"LDA", MODE_INDIRECT_X, RW_R},
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0xC1: {"CMP", MODE_INDIRECT_X, RW_R},
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0xE1: {"SBC", MODE_INDIRECT_X, RW_R},
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// 1-opcode, 2-cycle, accumulator rmw
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0x0A: {"ASL", MODE_A, RW_RMW},
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0x2A: {"ROL", MODE_A, RW_RMW},
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0x4A: {"LSR", MODE_A, RW_RMW},
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0x6A: {"ROR", MODE_A, RW_RMW},
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// 2-opcode, 5-cycle, zp rmw
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0x06: {"ASL", MODE_ZP, RW_RMW},
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0x26: {"ROL", MODE_ZP, RW_RMW},
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0x46: {"LSR", MODE_ZP, RW_RMW},
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0x66: {"ROR", MODE_ZP, RW_RMW},
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0xC6: {"DEC", MODE_ZP, RW_RMW},
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0xE6: {"INC", MODE_ZP, RW_RMW},
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// 3-opcode, 6-cycle, abs rmw
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0x0E: {"ASL", MODE_ABSOLUTE, RW_RMW},
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0x2E: {"ROL", MODE_ABSOLUTE, RW_RMW},
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0x4E: {"LSR", MODE_ABSOLUTE, RW_RMW},
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0x6E: {"ROR", MODE_ABSOLUTE, RW_RMW},
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0xCE: {"DEC", MODE_ABSOLUTE, RW_RMW},
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0xEE: {"INC", MODE_ABSOLUTE, RW_RMW},
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// 2-opcode, 6-cycle, zp,X rmw
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0x16: {"ASL", MODE_ZP_X, RW_RMW},
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0x36: {"ROL", MODE_ZP_X, RW_RMW},
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0x56: {"LSR", MODE_ZP_X, RW_RMW},
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0x76: {"ROR", MODE_ZP_X, RW_RMW},
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0xD6: {"DEC", MODE_ZP_X, RW_RMW},
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0xF6: {"INC", MODE_ZP_X, RW_RMW},
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// 3-opcode, 7-cycle, abs,X rmw
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0x1E: {"ASL", MODE_ABS_X, RW_RMW},
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0x3E: {"ROL", MODE_ABS_X, RW_RMW},
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0x5E: {"LSR", MODE_ABS_X, RW_RMW},
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0x7E: {"ROR", MODE_ABS_X, RW_RMW},
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0xDE: {"DEC", MODE_ABS_X, RW_RMW},
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0xFE: {"INC", MODE_ABS_X, RW_RMW},
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|
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}
|
2014-03-05 01:42:51 +00:00
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|
|
// Information for lookup of opcodes by name and mode -------------------------
|
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|
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|
|
type OpInfo struct {
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|
Mode AddressingMode
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|
|
Length int
|
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|
|
Byte byte
|
|
|
|
|
}
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|
|
|
|
type OpSummary struct {
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|
|
Modes AddressingMode // bitmask of supported modes
|
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|
|
|
Ops []OpInfo
|
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|
|
}
|
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|
|
|
|
|
|
|
var ByName map[string]OpSummary
|
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|
|
|
|
|
|
|
|
func init() {
|
|
|
|
|
ByName = make(map[string]OpSummary)
|
|
|
|
|
for b, oc := range Opcodes {
|
|
|
|
|
info := OpInfo{oc.Mode, ModeLengths[oc.Mode], b}
|
|
|
|
|
summary := ByName[oc.Name]
|
|
|
|
|
summary.Modes |= oc.Mode
|
|
|
|
|
summary.Ops = append(summary.Ops, info)
|
|
|
|
|
ByName[oc.Name] = summary
|
|
|
|
|
}
|
|
|
|
|
}
|
|
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|
|
|
|
|
|
|
func (s OpSummary) AnyModes(modes AddressingMode) bool {
|
|
|
|
|
return modes&s.Modes != 0
|
|
|
|
|
}
|
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|
|
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|
|
|
|
|
func (s OpSummary) OpForMode(mode AddressingMode) (OpInfo, bool) {
|
|
|
|
|
for _, o := range s.Ops {
|
|
|
|
|
if o.Mode == mode {
|
|
|
|
|
return o, true
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return OpInfo{}, false
|
|
|
|
|
}
|
