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mirror of https://github.com/zellyn/go6502.git synced 2024-06-15 18:29:47 +00:00

Move opcode metadata to separate package.

This commit is contained in:
Zellyn Hunter 2013-02-28 09:01:31 -08:00
parent 59a789746e
commit f1299f6f7f
3 changed files with 275 additions and 252 deletions

View File

@ -5,6 +5,8 @@ package asm
import (
"fmt"
"github.com/zellyn/go6502/opcodes"
)
// bytesString takes three bytes and a length, returning the formatted
@ -27,31 +29,31 @@ func addrString(pc uint16, byte1, byte2 byte, length int, mode int) string {
addr16 := uint16(byte1) + uint16(byte2)<<8
addrRel := uint16(int32(pc+2) + int32(int8(byte1)))
switch mode {
case MODE_IMPLIED:
case opcodes.MODE_IMPLIED:
return " "
case MODE_ABSOLUTE:
case opcodes.MODE_ABSOLUTE:
return fmt.Sprintf("$%04X ", addr16)
case MODE_INDIRECT:
case opcodes.MODE_INDIRECT:
return fmt.Sprintf("($%04X)", addr16)
case MODE_RELATIVE:
case opcodes.MODE_RELATIVE:
return fmt.Sprintf("$%04X ", addrRel)
case MODE_IMMEDIATE:
case opcodes.MODE_IMMEDIATE:
return fmt.Sprintf("#$%02X ", byte1)
case MODE_ABS_X:
case opcodes.MODE_ABS_X:
return fmt.Sprintf("$%04X,X", addr16)
case MODE_ABS_Y:
case opcodes.MODE_ABS_Y:
return fmt.Sprintf("$%04X,Y", addr16)
case MODE_ZP:
case opcodes.MODE_ZP:
return fmt.Sprintf("$%02X ", byte1)
case MODE_ZP_X:
case opcodes.MODE_ZP_X:
return fmt.Sprintf("$%02X,X ", byte1)
case MODE_ZP_Y:
case opcodes.MODE_ZP_Y:
return fmt.Sprintf("$%02X,Y ", byte1)
case MODE_INDIRECT_Y:
case opcodes.MODE_INDIRECT_Y:
return fmt.Sprintf("($%02X),Y", byte1)
case MODE_INDIRECT_X:
case opcodes.MODE_INDIRECT_X:
return fmt.Sprintf("($%02X,X)", byte1)
case MODE_A:
case opcodes.MODE_A:
return " "
}
panic(fmt.Sprintf("Unknown op mode: %d", mode))
@ -62,11 +64,11 @@ func addrString(pc uint16, byte1, byte2 byte, length int, mode int) string {
// instruction and address, and the length. If it cannot find the
// instruction, it returns a 1-byte "???" instruction.
func Disasm(pc uint16, byte0, byte1, byte2 byte) (string, string, int) {
op, ok := Opcodes[byte0]
op, ok := opcodes.Opcodes[byte0]
if !ok {
op = NoOp
op = opcodes.NoOp
}
length := ModeLengths[op.Mode]
length := opcodes.ModeLengths[op.Mode]
bytes := bytesString(byte0, byte1, byte2, length)
addr := addrString(pc, byte1, byte2, length, op.Mode)
return bytes, op.Name + " " + addr, length

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@ -1,236 +0,0 @@
package asm
// Opcode addressing modes.
const (
MODE_IMPLIED = iota
MODE_ABSOLUTE
MODE_INDIRECT
MODE_RELATIVE
MODE_IMMEDIATE
MODE_ABS_X
MODE_ABS_Y
MODE_ZP
MODE_ZP_X
MODE_ZP_Y
MODE_INDIRECT_Y
MODE_INDIRECT_X
MODE_A
)
// Lengths of instructions for each addressing mode.
var ModeLengths = map[int]int{
MODE_IMPLIED: 1,
MODE_ABSOLUTE: 3,
MODE_INDIRECT: 3,
MODE_RELATIVE: 2,
MODE_IMMEDIATE: 2,
MODE_ABS_X: 3,
MODE_ABS_Y: 3,
MODE_ZP: 2,
MODE_ZP_X: 2,
MODE_ZP_Y: 2,
MODE_INDIRECT_Y: 2,
MODE_INDIRECT_X: 2,
MODE_A: 1,
}
// Opcode stores information about instructions.
type Opcode struct {
Name string
Mode int
}
// Fake NoOp instruction used when disassembling.
var NoOp = Opcode{"???", MODE_IMPLIED}
// The list of Opcodes.
var Opcodes = map[byte]Opcode{
// BUG(zellyn): Add 65C02 instructions.
// Flag set and clear
0x18: {"CLC", MODE_IMPLIED}, // CLC
0xD8: {"CLD", MODE_IMPLIED}, // CLD
0x58: {"CLI", MODE_IMPLIED}, // CLI
0xB8: {"CLV", MODE_IMPLIED}, // CLV
0x38: {"SEC", MODE_IMPLIED}, // SEC
0xF8: {"SED", MODE_IMPLIED}, // SED
0x78: {"SEI", MODE_IMPLIED}, // SEI
// Very simple 1-opcode instructions
0xEA: {"NOP", MODE_IMPLIED},
0xAA: {"TAX", MODE_IMPLIED},
0xA8: {"TAY", MODE_IMPLIED},
0xBA: {"TSX", MODE_IMPLIED},
0x8A: {"TXA", MODE_IMPLIED},
0x9A: {"TXS", MODE_IMPLIED},
0x98: {"TYA", MODE_IMPLIED},
// Slightly more complex 1-opcode instructions
0xCA: {"DEX", MODE_IMPLIED},
0x88: {"DEY", MODE_IMPLIED},
0xE8: {"INX", MODE_IMPLIED},
0xC8: {"INY", MODE_IMPLIED},
0x48: {"PHA", MODE_IMPLIED},
0x08: {"PHP", MODE_IMPLIED},
0x68: {"PLA", MODE_IMPLIED},
0x28: {"PLP", MODE_IMPLIED},
// Jumps, returns, etc.
0x4C: {"JMP", MODE_ABSOLUTE},
0x6C: {"JMP", MODE_INDIRECT},
0x20: {"JSR", MODE_ABSOLUTE},
0x60: {"RTS", MODE_IMPLIED},
0x40: {"RTI", MODE_IMPLIED},
0x00: {"BRK", MODE_IMPLIED},
// Branches
0x90: {"BCC", MODE_RELATIVE}, // BCC
0xB0: {"BCS", MODE_RELATIVE}, // BCS
0xF0: {"BEQ", MODE_RELATIVE}, // BEQ
0x30: {"BMI", MODE_RELATIVE}, // BMI
0xD0: {"BNE", MODE_RELATIVE}, // BNE
0x10: {"BPL", MODE_RELATIVE}, // BPL
0x50: {"BVC", MODE_RELATIVE}, // BVC
0x70: {"BVS", MODE_RELATIVE}, // BVS
// 2-opcode, 2-cycle immediate mode
0x09: {"ORA", MODE_IMMEDIATE},
0x29: {"AND", MODE_IMMEDIATE},
0x49: {"EOR", MODE_IMMEDIATE},
0x69: {"ADC", MODE_IMMEDIATE},
0xC0: {"CPY", MODE_IMMEDIATE},
0xC9: {"CMP", MODE_IMMEDIATE},
0xA0: {"LDY", MODE_IMMEDIATE},
0xA2: {"LDX", MODE_IMMEDIATE},
0xA9: {"LDA", MODE_IMMEDIATE},
0xE0: {"CPX", MODE_IMMEDIATE},
0xE9: {"SBC", MODE_IMMEDIATE},
// 3-opcode, 4-cycle absolute mode
0x8D: {"STA", MODE_ABSOLUTE},
0x8E: {"STX", MODE_ABSOLUTE},
0x8C: {"STY", MODE_ABSOLUTE},
0x6D: {"ADC", MODE_ABSOLUTE},
0x2D: {"AND", MODE_ABSOLUTE},
0x2C: {"BIT", MODE_ABSOLUTE},
0xCD: {"CMP", MODE_ABSOLUTE},
0xEC: {"CPX", MODE_ABSOLUTE},
0xCC: {"CPY", MODE_ABSOLUTE},
0x4D: {"EOR", MODE_ABSOLUTE},
0xAD: {"LDA", MODE_ABSOLUTE},
0xAE: {"LDX", MODE_ABSOLUTE},
0xAC: {"LDY", MODE_ABSOLUTE},
0x0D: {"ORA", MODE_ABSOLUTE},
0xED: {"SBC", MODE_ABSOLUTE},
// 2-opcode, 3-cycle zero page
0x05: {"ORA", MODE_ZP},
0x24: {"BIT", MODE_ZP},
0x25: {"AND", MODE_ZP},
0x45: {"EOR", MODE_ZP},
0x65: {"ADC", MODE_ZP},
0x84: {"STY", MODE_ZP},
0x85: {"STA", MODE_ZP},
0x86: {"STX", MODE_ZP},
0xA4: {"LDY", MODE_ZP},
0xA5: {"LDA", MODE_ZP},
0xA6: {"LDX", MODE_ZP},
0xC4: {"CPY", MODE_ZP},
0xC5: {"CMP", MODE_ZP},
0xE4: {"CPX", MODE_ZP},
0xE5: {"SBC", MODE_ZP},
// 3-opcode, 4*-cycle abs,X/Y
0x1D: {"ORA", MODE_ABS_X},
0x19: {"ORA", MODE_ABS_X},
0x39: {"AND", MODE_ABS_X},
0x3D: {"AND", MODE_ABS_X},
0x59: {"EOR", MODE_ABS_X},
0x5D: {"EOR", MODE_ABS_X},
0x79: {"ADC", MODE_ABS_X},
0x7D: {"ADC", MODE_ABS_X},
0xBD: {"LDA", MODE_ABS_X},
0xB9: {"LDA", MODE_ABS_X},
0xD9: {"CMP", MODE_ABS_X},
0xDD: {"CMP", MODE_ABS_X},
0xF9: {"SBC", MODE_ABS_X},
0xFD: {"SBC", MODE_ABS_X},
0xBE: {"LDX", MODE_ABS_X},
0xBC: {"LDY", MODE_ABS_X},
// 3-opcode, 5-cycle abs,X/Y
0x99: {"STA", MODE_ABS_Y},
0x9D: {"STA", MODE_ABS_X},
// 2-opcode, 4-cycle zp,X/Y
0x15: {"ORA", MODE_ZP_X},
0x35: {"AND", MODE_ZP_X},
0x55: {"EOR", MODE_ZP_X},
0x75: {"ADC", MODE_ZP_X},
0x95: {"STA", MODE_ZP_X},
0xB5: {"LDA", MODE_ZP_X},
0xD5: {"CMP", MODE_ZP_X},
0xF5: {"SBC", MODE_ZP_X},
0x96: {"STX", MODE_ZP_Y},
0xB6: {"LDX", MODE_ZP_Y},
0x94: {"STY", MODE_ZP_X},
0xB4: {"LDY", MODE_ZP_X},
// 2-opcode, 5*-cycle zero-page indirect Y
0x11: {"ORA", MODE_INDIRECT_Y},
0x31: {"AND", MODE_INDIRECT_Y},
0x51: {"EOR", MODE_INDIRECT_Y},
0x71: {"ADC", MODE_INDIRECT_Y},
0x91: {"STA", MODE_INDIRECT_Y},
0xB1: {"LDA", MODE_INDIRECT_Y},
0xD1: {"CMP", MODE_INDIRECT_Y},
0xF1: {"SBC", MODE_INDIRECT_Y},
// 2-opcode, 6-cycle zero-page X indirect
0x01: {"ORA", MODE_INDIRECT_X},
0x21: {"AND", MODE_INDIRECT_X},
0x41: {"EOR", MODE_INDIRECT_X},
0x61: {"ADC", MODE_INDIRECT_X},
0x81: {"STA", MODE_INDIRECT_X},
0xA1: {"LDA", MODE_INDIRECT_X},
0xC1: {"CMP", MODE_INDIRECT_X},
0xE1: {"SBC", MODE_INDIRECT_X},
// 1-opcode, 2-cycle, accumulator rmw
0x0A: {"ASL", MODE_A},
0x2A: {"ROL", MODE_A},
0x4A: {"LSR", MODE_A},
0x6A: {"ROR", MODE_A},
// 2-opcode, 5-cycle, zp rmw
0x06: {"ASL", MODE_ZP},
0x26: {"ROL", MODE_ZP},
0x46: {"LSR", MODE_ZP},
0x66: {"ROR", MODE_ZP},
0xC6: {"DEC", MODE_ZP},
0xE6: {"INC", MODE_ZP},
// 3-opcode, 6-cycle, abs rmw
0x0E: {"ASL", MODE_ABSOLUTE},
0x2E: {"ROL", MODE_ABSOLUTE},
0x4E: {"LSR", MODE_ABSOLUTE},
0x6E: {"ROR", MODE_ABSOLUTE},
0xCE: {"DEC", MODE_ABSOLUTE},
0xEE: {"INC", MODE_ABSOLUTE},
// 2-opcode, 6-cycle, zp,X rmw
0x16: {"ASL", MODE_ZP_X},
0x36: {"ROL", MODE_ZP_X},
0x56: {"LSR", MODE_ZP_X},
0x76: {"ROR", MODE_ZP_X},
0xD6: {"DEC", MODE_ZP_X},
0xF6: {"INC", MODE_ZP_X},
// 3-opcode, 7-cycle, abs,X rmw
0x1E: {"ASL", MODE_ABS_X},
0x3E: {"ROL", MODE_ABS_X},
0x5E: {"LSR", MODE_ABS_X},
0x7E: {"ROR", MODE_ABS_X},
0xDE: {"DEC", MODE_ABS_X},
0xFE: {"INC", MODE_ABS_X},
}

257
opcodes/opcodes.go Normal file
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@ -0,0 +1,257 @@
/*
Package opcodes stores metadata/information about 6502 opcodes. It's
used for disassembly, and (in the future) for building the opcode
function tables.
*/
package opcodes
// Opcode addressing modes.
const (
MODE_IMPLIED = iota
MODE_ABSOLUTE
MODE_INDIRECT
MODE_RELATIVE
MODE_IMMEDIATE
MODE_ABS_X
MODE_ABS_Y
MODE_ZP
MODE_ZP_X
MODE_ZP_Y
MODE_INDIRECT_Y
MODE_INDIRECT_X
MODE_A
)
// Opcode read/write semantics
const (
MEM_NONE = 0
MEM_R = 1
MEM_W = 2
MEM_RMW = 3
)
// Lengths of instructions for each addressing mode.
var ModeLengths = map[int]int{
MODE_IMPLIED: 1,
MODE_ABSOLUTE: 3,
MODE_INDIRECT: 3,
MODE_RELATIVE: 2,
MODE_IMMEDIATE: 2,
MODE_ABS_X: 3,
MODE_ABS_Y: 3,
MODE_ZP: 2,
MODE_ZP_X: 2,
MODE_ZP_Y: 2,
MODE_INDIRECT_Y: 2,
MODE_INDIRECT_X: 2,
MODE_A: 1,
}
const (
RW_X = 0 // Don't care
RW_R = 1
RW_W = 2
RW_RMW = 3
)
// Opcode stores information about instructions.
type Opcode struct {
Name string
Mode int
RW int
}
// Fake NoOp instruction used when disassembling.
var NoOp = Opcode{"???", MODE_IMPLIED, RW_X}
// The list of Opcodes.
var Opcodes = map[byte]Opcode{
// BUG(zellyn): Add 65C02 instructions.
// Flag set and clear
0x18: {"CLC", MODE_IMPLIED, RW_X}, // CLC
0xD8: {"CLD", MODE_IMPLIED, RW_X}, // CLD
0x58: {"CLI", MODE_IMPLIED, RW_X}, // CLI
0xB8: {"CLV", MODE_IMPLIED, RW_X}, // CLV
0x38: {"SEC", MODE_IMPLIED, RW_X}, // SEC
0xF8: {"SED", MODE_IMPLIED, RW_X}, // SED
0x78: {"SEI", MODE_IMPLIED, RW_X}, // SEI
// Very simple 1-opcode instructions
0xEA: {"NOP", MODE_IMPLIED, RW_X},
0xAA: {"TAX", MODE_IMPLIED, RW_X},
0xA8: {"TAY", MODE_IMPLIED, RW_X},
0xBA: {"TSX", MODE_IMPLIED, RW_X},
0x8A: {"TXA", MODE_IMPLIED, RW_X},
0x9A: {"TXS", MODE_IMPLIED, RW_X},
0x98: {"TYA", MODE_IMPLIED, RW_X},
// Slightly more complex 1-opcode instructions
0xCA: {"DEX", MODE_IMPLIED, RW_X},
0x88: {"DEY", MODE_IMPLIED, RW_X},
0xE8: {"INX", MODE_IMPLIED, RW_X},
0xC8: {"INY", MODE_IMPLIED, RW_X},
0x48: {"PHA", MODE_IMPLIED, RW_X},
0x08: {"PHP", MODE_IMPLIED, RW_X},
0x68: {"PLA", MODE_IMPLIED, RW_X},
0x28: {"PLP", MODE_IMPLIED, RW_X},
// Jumps, returns, etc.
0x4C: {"JMP", MODE_ABSOLUTE, RW_X},
0x6C: {"JMP", MODE_INDIRECT, RW_X},
0x20: {"JSR", MODE_ABSOLUTE, RW_X},
0x60: {"RTS", MODE_IMPLIED, RW_X},
0x40: {"RTI", MODE_IMPLIED, RW_X},
0x00: {"BRK", MODE_IMPLIED, RW_X},
// Branches
0x90: {"BCC", MODE_RELATIVE, RW_X}, // BCC
0xB0: {"BCS", MODE_RELATIVE, RW_X}, // BCS
0xF0: {"BEQ", MODE_RELATIVE, RW_X}, // BEQ
0x30: {"BMI", MODE_RELATIVE, RW_X}, // BMI
0xD0: {"BNE", MODE_RELATIVE, RW_X}, // BNE
0x10: {"BPL", MODE_RELATIVE, RW_X}, // BPL
0x50: {"BVC", MODE_RELATIVE, RW_X}, // BVC
0x70: {"BVS", MODE_RELATIVE, RW_X}, // BVS
// 2-opcode, 2-cycle immediate mode
0x09: {"ORA", MODE_IMMEDIATE, RW_R},
0x29: {"AND", MODE_IMMEDIATE, RW_R},
0x49: {"EOR", MODE_IMMEDIATE, RW_R},
0x69: {"ADC", MODE_IMMEDIATE, RW_R},
0xC0: {"CPY", MODE_IMMEDIATE, RW_R},
0xC9: {"CMP", MODE_IMMEDIATE, RW_R},
0xA0: {"LDY", MODE_IMMEDIATE, RW_R},
0xA2: {"LDX", MODE_IMMEDIATE, RW_R},
0xA9: {"LDA", MODE_IMMEDIATE, RW_R},
0xE0: {"CPX", MODE_IMMEDIATE, RW_R},
0xE9: {"SBC", MODE_IMMEDIATE, RW_R},
// 3-opcode, 4-cycle absolute mode
0x8D: {"STA", MODE_ABSOLUTE, RW_W},
0x8E: {"STX", MODE_ABSOLUTE, RW_W},
0x8C: {"STY", MODE_ABSOLUTE, RW_W},
0x6D: {"ADC", MODE_ABSOLUTE, RW_R},
0x2D: {"AND", MODE_ABSOLUTE, RW_R},
0x2C: {"BIT", MODE_ABSOLUTE, RW_R},
0xCD: {"CMP", MODE_ABSOLUTE, RW_R},
0xEC: {"CPX", MODE_ABSOLUTE, RW_R},
0xCC: {"CPY", MODE_ABSOLUTE, RW_R},
0x4D: {"EOR", MODE_ABSOLUTE, RW_R},
0xAD: {"LDA", MODE_ABSOLUTE, RW_R},
0xAE: {"LDX", MODE_ABSOLUTE, RW_R},
0xAC: {"LDY", MODE_ABSOLUTE, RW_R},
0x0D: {"ORA", MODE_ABSOLUTE, RW_R},
0xED: {"SBC", MODE_ABSOLUTE, RW_R},
// 2-opcode, 3-cycle zero page
0x05: {"ORA", MODE_ZP, RW_R},
0x24: {"BIT", MODE_ZP, RW_R},
0x25: {"AND", MODE_ZP, RW_R},
0x45: {"EOR", MODE_ZP, RW_R},
0x65: {"ADC", MODE_ZP, RW_R},
0x84: {"STY", MODE_ZP, RW_W},
0x85: {"STA", MODE_ZP, RW_W},
0x86: {"STX", MODE_ZP, RW_W},
0xA4: {"LDY", MODE_ZP, RW_R},
0xA5: {"LDA", MODE_ZP, RW_R},
0xA6: {"LDX", MODE_ZP, RW_R},
0xC4: {"CPY", MODE_ZP, RW_R},
0xC5: {"CMP", MODE_ZP, RW_R},
0xE4: {"CPX", MODE_ZP, RW_R},
0xE5: {"SBC", MODE_ZP, RW_R},
// 3-opcode, 4*-cycle abs,X/Y
0x1D: {"ORA", MODE_ABS_X, RW_R},
0x19: {"ORA", MODE_ABS_X, RW_R},
0x39: {"AND", MODE_ABS_X, RW_R},
0x3D: {"AND", MODE_ABS_X, RW_R},
0x59: {"EOR", MODE_ABS_X, RW_R},
0x5D: {"EOR", MODE_ABS_X, RW_R},
0x79: {"ADC", MODE_ABS_X, RW_R},
0x7D: {"ADC", MODE_ABS_X, RW_R},
0xBD: {"LDA", MODE_ABS_X, RW_R},
0xB9: {"LDA", MODE_ABS_X, RW_R},
0xD9: {"CMP", MODE_ABS_X, RW_R},
0xDD: {"CMP", MODE_ABS_X, RW_R},
0xF9: {"SBC", MODE_ABS_X, RW_R},
0xFD: {"SBC", MODE_ABS_X, RW_R},
0xBE: {"LDX", MODE_ABS_X, RW_R},
0xBC: {"LDY", MODE_ABS_X, RW_R},
// 3-opcode, 5-cycle abs,X/Y
0x99: {"STA", MODE_ABS_Y, RW_W},
0x9D: {"STA", MODE_ABS_X, RW_W},
// 2-opcode, 4-cycle zp,X/Y
0x15: {"ORA", MODE_ZP_X, RW_R},
0x35: {"AND", MODE_ZP_X, RW_R},
0x55: {"EOR", MODE_ZP_X, RW_R},
0x75: {"ADC", MODE_ZP_X, RW_R},
0x95: {"STA", MODE_ZP_X, RW_W},
0xB5: {"LDA", MODE_ZP_X, RW_R},
0xD5: {"CMP", MODE_ZP_X, RW_R},
0xF5: {"SBC", MODE_ZP_X, RW_R},
0x96: {"STX", MODE_ZP_Y, RW_W},
0xB6: {"LDX", MODE_ZP_Y, RW_R},
0x94: {"STY", MODE_ZP_X, RW_W},
0xB4: {"LDY", MODE_ZP_X, RW_R},
// 2-opcode, 5*-cycle zero-page indirect Y
0x11: {"ORA", MODE_INDIRECT_Y, RW_R},
0x31: {"AND", MODE_INDIRECT_Y, RW_R},
0x51: {"EOR", MODE_INDIRECT_Y, RW_R},
0x71: {"ADC", MODE_INDIRECT_Y, RW_R},
0x91: {"STA", MODE_INDIRECT_Y, RW_W},
0xB1: {"LDA", MODE_INDIRECT_Y, RW_R},
0xD1: {"CMP", MODE_INDIRECT_Y, RW_R},
0xF1: {"SBC", MODE_INDIRECT_Y, RW_R},
// 2-opcode, 6-cycle zero-page X indirect
0x01: {"ORA", MODE_INDIRECT_X, RW_R},
0x21: {"AND", MODE_INDIRECT_X, RW_R},
0x41: {"EOR", MODE_INDIRECT_X, RW_R},
0x61: {"ADC", MODE_INDIRECT_X, RW_R},
0x81: {"STA", MODE_INDIRECT_X, RW_W},
0xA1: {"LDA", MODE_INDIRECT_X, RW_R},
0xC1: {"CMP", MODE_INDIRECT_X, RW_R},
0xE1: {"SBC", MODE_INDIRECT_X, RW_R},
// 1-opcode, 2-cycle, accumulator rmw
0x0A: {"ASL", MODE_A, RW_RMW},
0x2A: {"ROL", MODE_A, RW_RMW},
0x4A: {"LSR", MODE_A, RW_RMW},
0x6A: {"ROR", MODE_A, RW_RMW},
// 2-opcode, 5-cycle, zp rmw
0x06: {"ASL", MODE_ZP, RW_RMW},
0x26: {"ROL", MODE_ZP, RW_RMW},
0x46: {"LSR", MODE_ZP, RW_RMW},
0x66: {"ROR", MODE_ZP, RW_RMW},
0xC6: {"DEC", MODE_ZP, RW_RMW},
0xE6: {"INC", MODE_ZP, RW_RMW},
// 3-opcode, 6-cycle, abs rmw
0x0E: {"ASL", MODE_ABSOLUTE, RW_RMW},
0x2E: {"ROL", MODE_ABSOLUTE, RW_RMW},
0x4E: {"LSR", MODE_ABSOLUTE, RW_RMW},
0x6E: {"ROR", MODE_ABSOLUTE, RW_RMW},
0xCE: {"DEC", MODE_ABSOLUTE, RW_RMW},
0xEE: {"INC", MODE_ABSOLUTE, RW_RMW},
// 2-opcode, 6-cycle, zp,X rmw
0x16: {"ASL", MODE_ZP_X, RW_RMW},
0x36: {"ROL", MODE_ZP_X, RW_RMW},
0x56: {"LSR", MODE_ZP_X, RW_RMW},
0x76: {"ROR", MODE_ZP_X, RW_RMW},
0xD6: {"DEC", MODE_ZP_X, RW_RMW},
0xF6: {"INC", MODE_ZP_X, RW_RMW},
// 3-opcode, 7-cycle, abs,X rmw
0x1E: {"ASL", MODE_ABS_X, RW_RMW},
0x3E: {"ROL", MODE_ABS_X, RW_RMW},
0x5E: {"LSR", MODE_ABS_X, RW_RMW},
0x7E: {"ROR", MODE_ABS_X, RW_RMW},
0xDE: {"DEC", MODE_ABS_X, RW_RMW},
0xFE: {"INC", MODE_ABS_X, RW_RMW},
}