mirror of https://github.com/zellyn/go6502.git
443 lines
8.5 KiB
Go
443 lines
8.5 KiB
Go
package cpu
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// BUG(zellyn): 6502 should do invalid reads when doing indexed
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// addressing across page boundaries. See
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// http://en.wikipedia.org/wiki/MOS_Technology_6502#Bugs_and_quirks.
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// BUG(zellyn): rmw instructions should write old data back on 6502,
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// read twice on 65C02. See
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// http://en.wikipedia.org/wiki/MOS_Technology_6502#Bugs_and_quirks.
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// BUG(zellyn): Instructions should do many more reads. See
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// http://users.telenet.be/kim1-6502/6502/hwman.html#AA and/or table
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// 4.1 of "Understanding the Apple II".
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// immediate2 performs 2-opcode, 2-cycle immediate mode instructions.
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func immediate2(f func(*cpu, byte)) func(*cpu) {
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return func(c *cpu) {
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// T1
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value := c.m.Read(c.r.PC)
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c.r.PC++
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f(c, value)
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c.t()
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}
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}
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// absolute4r performs 3-opcode, 4-cycle absolute mode read instructions.
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func absolute4r(f func(*cpu, byte)) func(*cpu) {
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return func(c *cpu) {
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// T1
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addr := uint16(c.m.Read(c.r.PC))
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c.r.PC++
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c.t()
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// T2
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addr |= (uint16(c.m.Read(c.r.PC)) << 8)
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c.r.PC++
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c.t()
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// T3
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value := c.m.Read(addr)
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f(c, value)
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c.t()
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}
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}
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// absolute4w performs 3-opcode, 4-cycle absolute mode write instructions.
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func absolute4w(f func(*cpu) byte) func(*cpu) {
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return func(c *cpu) {
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// T1
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addr := uint16(c.m.Read(c.r.PC))
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c.r.PC++
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c.t()
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// T2
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addr |= (uint16(c.m.Read(c.r.PC)) << 8)
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c.r.PC++
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c.t()
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// T3
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c.m.Write(addr, f(c))
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c.t()
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}
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}
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// zp3r performs 2-opcode, 3-cycle zero page read instructions.
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func zp3r(f func(*cpu, byte)) func(*cpu) {
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return func(c *cpu) {
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// T1
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addr := uint16(c.m.Read(c.r.PC))
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c.r.PC++
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c.t()
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// T2
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value := c.m.Read(addr)
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f(c, value)
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c.t()
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}
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}
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// zp3w performs 2-opcode, 3-cycle zero page write instructions.
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func zp3w(f func(*cpu) byte) func(*cpu) {
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return func(c *cpu) {
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// T1
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addr := uint16(c.m.Read(c.r.PC))
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c.r.PC++
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c.t()
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// T2
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c.m.Write(addr, f(c))
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c.t()
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}
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}
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// absx4r performs 3-opcode, 4*-cycle abs,X read instructions.
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func absx4r(f func(*cpu, byte)) func(*cpu) {
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return func(c *cpu) {
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// T1
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addr := uint16(c.m.Read(c.r.PC))
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c.r.PC++
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c.t()
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// T2
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addr |= (uint16(c.m.Read(c.r.PC)) << 8)
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addrX := addr + uint16(c.r.X)
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c.r.PC++
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c.t()
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// T3
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if !samePage(addr, addrX) {
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c.m.Read(addrX - 0x100)
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c.t()
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}
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// T3(cotd.) or T4
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value := c.m.Read(addrX)
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f(c, value)
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c.t()
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}
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}
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// absy4r performs 3-opcode, 4*-cycle abs,Y read instructions.
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func absy4r(f func(*cpu, byte)) func(*cpu) {
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return func(c *cpu) {
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// T1
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addr := uint16(c.m.Read(c.r.PC))
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c.r.PC++
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c.t()
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// T2
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addr |= (uint16(c.m.Read(c.r.PC)) << 8)
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addrY := addr + uint16(c.r.Y)
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c.r.PC++
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c.t()
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// T3
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if !samePage(addr, addrY) {
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c.m.Read(addrY - 0x100)
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c.t()
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}
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// T3(cotd.) or T4
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value := c.m.Read(addrY)
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f(c, value)
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c.t()
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}
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}
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// absx5w performs 3-opcode, 5-cycle abs,X write instructions.
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func absx5w(f func(*cpu) byte) func(*cpu) {
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return func(c *cpu) {
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// T1
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addr := uint16(c.m.Read(c.r.PC))
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c.r.PC++
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c.t()
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// T2
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addr |= (uint16(c.m.Read(c.r.PC)) << 8)
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addrX := addr + uint16(c.r.X)
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c.r.PC++
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c.t()
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// T3
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c.m.Read((addr & 0xFF00) | (addrX & 0x00FF))
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c.t()
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// T4
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c.m.Write(addrX, f(c))
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c.t()
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}
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}
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// absy5w performs 3-opcode, 5-cycle abs,Y write instructions.
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func absy5w(f func(*cpu) byte) func(*cpu) {
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return func(c *cpu) {
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// T1
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addr := uint16(c.m.Read(c.r.PC))
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c.r.PC++
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c.t()
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// T2
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addr |= (uint16(c.m.Read(c.r.PC)) << 8)
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addrY := addr + uint16(c.r.Y)
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c.r.PC++
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c.t()
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// T3
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c.m.Read((addr & 0xFF00) | (addrY & 0x00FF))
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c.t()
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// T4
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c.m.Write(addrY, f(c))
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c.t()
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}
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}
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// zpx4r performs 2-opcode, 4-cycle zp,X read instructions.
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func zpx4r(f func(*cpu, byte)) func(*cpu) {
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return func(c *cpu) {
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// T1
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addr := c.m.Read(c.r.PC)
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addrX := uint16(addr + c.r.X)
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c.r.PC++
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c.t()
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// T2
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c.m.Read(uint16(addr))
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c.t()
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// T3
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value := c.m.Read(addrX)
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f(c, value)
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c.t()
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}
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}
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// zpx4w performs 2-opcode, 4-cycle zp,X write instructions.
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func zpx4w(f func(*cpu) byte) func(*cpu) {
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return func(c *cpu) {
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// T1
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addr := c.m.Read(c.r.PC)
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addrX := uint16(addr + c.r.X)
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c.r.PC++
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c.t()
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// T2
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c.m.Read(uint16(addr))
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c.t()
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// T3
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c.m.Write(uint16(addrX), f(c))
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c.t()
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}
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}
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// zpy4r performs 2-opcode, 4-cycle zp,Y instructions.
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func zpy4r(f func(*cpu, byte)) func(*cpu) {
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return func(c *cpu) {
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// T1
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addr := c.m.Read(c.r.PC)
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addrY := uint16(addr + c.r.Y)
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c.r.PC++
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c.t()
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// T2
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c.m.Read(uint16(addr))
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c.t()
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// T3
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value := c.m.Read(uint16(addrY))
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f(c, value)
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c.t()
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}
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}
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// zpy4w performs 2-opcode, 4-cycle zp,Y write instructions.
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func zpy4w(f func(*cpu) byte) func(*cpu) {
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return func(c *cpu) {
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// T1
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addr := c.m.Read(c.r.PC)
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addrY := uint16(addr + c.r.Y)
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c.r.PC++
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c.t()
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// T2
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c.m.Read(uint16(addr))
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c.t()
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// T3
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c.m.Write(addrY, f(c))
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c.t()
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}
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}
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// zpiy5r performs 2-opcode, 5*-cycle zero-page indirect Y read instructions.
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func zpiy5r(f func(*cpu, byte)) func(*cpu) {
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return func(c *cpu) {
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// T1
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iAddr := c.m.Read(c.r.PC)
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c.r.PC++
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c.t()
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// T2
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addr := uint16(c.m.Read(uint16(iAddr)))
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c.t()
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// T3
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addr |= (uint16(c.m.Read(uint16(iAddr+1))) << 8)
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addrY := addr + uint16(c.r.Y)
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c.t()
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// T4
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if !samePage(addr, addrY) {
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c.m.Read((addr & 0xFF00) | (addrY & 0x00FF))
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c.t()
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}
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// T4(cotd.) or T5
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value := c.m.Read(addr + uint16(c.r.Y))
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f(c, value)
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c.t()
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}
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}
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// zpiy6w performs 2-opcode, 6-cycle zero-page indirect Y write instructions.
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func zpiy6w(f func(*cpu) byte) func(*cpu) {
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return func(c *cpu) {
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// T1
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iAddr := c.m.Read(c.r.PC)
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c.r.PC++
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c.t()
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// T2
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addr := uint16(uint16(c.m.Read(uint16(iAddr))))
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c.t()
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// T3
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addr |= (uint16(c.m.Read(uint16(iAddr+1))) << 8)
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addrY := addr + uint16(c.r.Y)
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c.t()
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// T4
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c.m.Read((addr & 0xFF00) | (addrY & 0x00FF))
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c.t()
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// T5
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c.m.Write(addr+uint16(c.r.Y), f(c))
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c.t()
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}
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}
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// zpxi6r performs 2-opcode, 6-cycle zero-page X indirect read instructions.
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func zpxi6r(f func(*cpu, byte)) func(*cpu) {
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return func(c *cpu) {
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// T1
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iAddr := c.m.Read(c.r.PC)
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c.r.PC++
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c.t()
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// T2
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c.m.Read(uint16(iAddr))
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c.t()
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// T3
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addr := uint16(uint16(c.m.Read(uint16(iAddr + c.r.X))))
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c.t()
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// T4
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addr |= (uint16(c.m.Read(uint16(iAddr+c.r.X+1))) << 8)
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c.t()
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// T5
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value := c.m.Read(addr)
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f(c, value)
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c.t()
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}
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}
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// zpxi6w performs 2-opcode, 6-cycle zero-page X indirect write instructions.
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func zpxi6w(f func(*cpu) byte) func(*cpu) {
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return func(c *cpu) {
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// T1
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iAddr := c.m.Read(c.r.PC)
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c.r.PC++
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c.t()
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// T2
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c.m.Read(uint16(iAddr))
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c.t()
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// T3
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addr := uint16(uint16(c.m.Read(uint16(iAddr + c.r.X))))
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c.t()
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// T4
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addr |= (uint16(c.m.Read(uint16(iAddr+c.r.X+1))) << 8)
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c.t()
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// T5
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c.m.Write(addr, f(c))
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c.t()
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}
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}
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// acc2rmw performs 1-opcode, 2-cycle, accumulator rmw instructions. eg. ASL
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func acc2rmw(f func(*cpu, byte) byte) func(*cpu) {
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return func(c *cpu) {
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// T1
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c.m.Read(c.r.PC)
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c.r.A = f(c, c.r.A)
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c.t()
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}
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}
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// zp5rmw performs 2-opcode, 5-cycle, zp rmw instructions. eg. ASL $70
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func zp5rmw(f func(*cpu, byte) byte) func(*cpu) {
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return func(c *cpu) {
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// T1
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addr := uint16(c.m.Read(c.r.PC))
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c.r.PC++
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c.t()
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// T2
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value := c.m.Read(addr)
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c.t()
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// T3
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c.m.Write(addr, value)
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c.t()
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// T4
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c.m.Write(addr, f(c, value))
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c.t()
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}
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}
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// abs6rmw performs 3-opcode, 6-cycle, abs rmw instructions. eg. ASL $5F72
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func abs6rmw(f func(*cpu, byte) byte) func(*cpu) {
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return func(c *cpu) {
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// T1
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addr := uint16(c.m.Read(c.r.PC))
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c.r.PC++
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c.t()
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// T2
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addr |= (uint16(c.m.Read(c.r.PC)) << 8)
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c.r.PC++
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c.t()
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// T3
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value := c.m.Read(addr)
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c.t()
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// T4
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c.m.Write(addr, value) // Spurious write...
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c.t()
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// T5
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c.m.Write(addr, f(c, value))
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c.t()
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}
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}
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// zpx6rmw performs 2-opcode, 6-cycle, zp,X rmw instructions. eg. ASL $70,X
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func zpx6rmw(f func(*cpu, byte) byte) func(*cpu) {
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return func(c *cpu) {
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// T1
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addr8 := c.m.Read(c.r.PC)
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c.r.PC++
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c.t()
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// T2
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c.m.Read(uint16(addr8))
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c.t()
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// T3
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addr := uint16(addr8 + c.r.X)
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value := c.m.Read(addr)
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c.t()
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// T4
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c.m.Write(addr, value)
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c.t()
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// T5
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c.m.Write(addr, f(c, value))
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c.t()
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}
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}
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// absx7rmw performs 3-opcode, 7-cycle, abs,X rmw instructions. eg. ASL $5F72,X
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func absx7rmw(f func(*cpu, byte) byte) func(*cpu) {
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return func(c *cpu) {
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// T1
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addr := uint16(c.m.Read(c.r.PC))
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c.r.PC++
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c.t()
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// T2
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addr |= (uint16(c.m.Read(c.r.PC)) << 8)
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addr += uint16(c.r.X)
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c.r.PC++
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c.t()
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// T3
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c.m.Read(addr)
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c.t()
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// T4
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value := c.m.Read(addr)
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c.t()
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// T5
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c.m.Write(addr, value) // Spurious write
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c.t()
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// T6
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c.m.Write(addr, f(c, value))
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c.t()
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}
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}
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