2019-03-22 18:50:20 +00:00
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Identified constant variable (byte*) dtvSetCpuBankSegment1::cpuBank
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Identified constant variable (byte*) DTV_BLITTER_ALU
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2018-05-14 21:53:03 +00:00
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Inlined call (byte~) vicSelectGfxBank::$0 ← call toDd00 (byte*) vicSelectGfxBank::gfx
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2018-04-15 21:32:49 +00:00
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2018-08-22 22:24:32 +00:00
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CONTROL FLOW GRAPH SSA
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2018-04-15 21:32:49 +00:00
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@begin: scope:[] from
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(byte*) PROCPORT_DDR#0 ← ((byte*)) (byte/signed byte/word/signed word/dword/signed dword) 0
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(byte) PROCPORT_DDR_MEMORY_MASK#0 ← (byte/signed byte/word/signed word/dword/signed dword) 7
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(byte*) PROCPORT#0 ← ((byte*)) (byte/signed byte/word/signed word/dword/signed dword) 1
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2019-03-08 05:54:45 +00:00
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(byte) PROCPORT_RAM_IO#0 ← (byte/signed byte/word/signed word/dword/signed dword) $35
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(byte*) RASTER#0 ← ((byte*)) (word/dword/signed dword) $d012
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(byte*) BORDERCOL#0 ← ((byte*)) (word/dword/signed dword) $d020
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(byte*) VIC_CONTROL#0 ← ((byte*)) (word/dword/signed dword) $d011
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(byte) VIC_ECM#0 ← (byte/signed byte/word/signed word/dword/signed dword) $40
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(byte) VIC_DEN#0 ← (byte/signed byte/word/signed word/dword/signed dword) $10
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2018-04-15 21:32:49 +00:00
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(byte) VIC_RSEL#0 ← (byte/signed byte/word/signed word/dword/signed dword) 8
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2019-03-08 05:54:45 +00:00
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(byte*) VIC_CONTROL2#0 ← ((byte*)) (word/dword/signed dword) $d016
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(byte) VIC_MCM#0 ← (byte/signed byte/word/signed word/dword/signed dword) $10
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2018-04-15 21:32:49 +00:00
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(byte) VIC_CSEL#0 ← (byte/signed byte/word/signed word/dword/signed dword) 8
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2019-03-08 05:54:45 +00:00
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(byte*) VIC_MEMORY#0 ← ((byte*)) (word/dword/signed dword) $d018
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(byte*) CIA2_PORT_A#0 ← ((byte*)) (word/dword/signed dword) $dd00
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(byte*) CIA2_PORT_A_DDR#0 ← ((byte*)) (word/dword/signed dword) $dd02
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2018-12-24 01:27:12 +00:00
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to:@4
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@4: scope:[] from @begin
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2019-03-08 05:54:45 +00:00
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(byte*) DTV_FEATURE#0 ← ((byte*)) (word/dword/signed dword) $d03f
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2018-04-15 21:32:49 +00:00
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(byte) DTV_FEATURE_ENABLE#0 ← (byte/signed byte/word/signed word/dword/signed dword) 1
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2019-03-08 05:54:45 +00:00
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(byte*) DTV_CONTROL#0 ← ((byte*)) (word/dword/signed dword) $d03c
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2018-04-15 21:32:49 +00:00
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(byte) DTV_LINEAR#0 ← (byte/signed byte/word/signed word/dword/signed dword) 1
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(byte) DTV_HIGHCOLOR#0 ← (byte/signed byte/word/signed word/dword/signed dword) 4
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2019-03-08 05:54:45 +00:00
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(byte) DTV_COLORRAM_OFF#0 ← (byte/signed byte/word/signed word/dword/signed dword) $10
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(byte) DTV_BADLINE_OFF#0 ← (byte/signed byte/word/signed word/dword/signed dword) $20
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(byte) DTV_CHUNKY#0 ← (byte/signed byte/word/signed word/dword/signed dword) $40
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(byte*) DTV_PALETTE#0 ← ((byte*)) (word/dword/signed dword) $d200
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(byte*) DTV_PLANEB_START_LO#0 ← ((byte*)) (word/dword/signed dword) $d049
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(byte*) DTV_PLANEB_START_MI#0 ← ((byte*)) (word/dword/signed dword) $d04a
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(byte*) DTV_PLANEB_START_HI#0 ← ((byte*)) (word/dword/signed dword) $d04b
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(byte*) DTV_PLANEB_STEP#0 ← ((byte*)) (word/dword/signed dword) $d04c
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(byte*) DTV_PLANEB_MODULO_LO#0 ← ((byte*)) (word/dword/signed dword) $d047
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(byte*) DTV_PLANEB_MODULO_HI#0 ← ((byte*)) (word/dword/signed dword) $d048
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2018-12-24 01:27:12 +00:00
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to:@5
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2018-04-15 21:32:49 +00:00
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dtvSetCpuBankSegment1: scope:[dtvSetCpuBankSegment1] from gfx_init_chunky gfx_init_chunky::@4 gfx_init_chunky::@6
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(byte) dtvSetCpuBankSegment1::cpuBankIdx#3 ← phi( gfx_init_chunky/(byte) dtvSetCpuBankSegment1::cpuBankIdx#0 gfx_init_chunky::@4/(byte) dtvSetCpuBankSegment1::cpuBankIdx#1 gfx_init_chunky::@6/(byte) dtvSetCpuBankSegment1::cpuBankIdx#2 )
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2019-03-08 05:54:45 +00:00
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(byte*) dtvSetCpuBankSegment1::cpuBank#0 ← ((byte*)) (byte/word/signed word/dword/signed dword) $ff
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2018-04-15 21:32:49 +00:00
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*((byte*) dtvSetCpuBankSegment1::cpuBank#0) ← (byte) dtvSetCpuBankSegment1::cpuBankIdx#3
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asm { .byte$32,$dd lda$ff .byte$32,$00 }
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to:dtvSetCpuBankSegment1::@return
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dtvSetCpuBankSegment1::@return: scope:[dtvSetCpuBankSegment1] from dtvSetCpuBankSegment1
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return
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to:@return
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2018-12-24 01:27:12 +00:00
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@5: scope:[] from @4
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2019-03-08 05:54:45 +00:00
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(byte*) CHUNKY#0 ← ((byte*)) (word/dword/signed dword) $8000
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2018-12-24 01:27:12 +00:00
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to:@7
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main: scope:[main] from @7
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2018-04-15 21:32:49 +00:00
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asm { sei }
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*((byte*) PROCPORT_DDR#0) ← (byte) PROCPORT_DDR_MEMORY_MASK#0
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*((byte*) PROCPORT#0) ← (byte) PROCPORT_RAM_IO#0
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2018-05-01 20:50:59 +00:00
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call gfx_init_chunky
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2018-04-15 21:32:49 +00:00
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to:main::@17
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main::@17: scope:[main] from main
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*((byte*) DTV_FEATURE#0) ← (byte) DTV_FEATURE_ENABLE#0
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(byte~) main::$1 ← (byte) DTV_HIGHCOLOR#0 | (byte) DTV_LINEAR#0
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(byte~) main::$2 ← (byte~) main::$1 | (byte) DTV_COLORRAM_OFF#0
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(byte~) main::$3 ← (byte~) main::$2 | (byte) DTV_CHUNKY#0
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(byte~) main::$4 ← (byte~) main::$3 | (byte) DTV_BADLINE_OFF#0
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*((byte*) DTV_CONTROL#0) ← (byte~) main::$4
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(byte~) main::$5 ← (byte) VIC_DEN#0 | (byte) VIC_ECM#0
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(byte~) main::$6 ← (byte~) main::$5 | (byte) VIC_RSEL#0
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(byte/word/dword~) main::$7 ← (byte~) main::$6 | (byte/signed byte/word/signed word/dword/signed dword) 3
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*((byte*) VIC_CONTROL#0) ← (byte/word/dword~) main::$7
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(byte~) main::$8 ← (byte) VIC_MCM#0 | (byte) VIC_CSEL#0
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*((byte*) VIC_CONTROL2#0) ← (byte~) main::$8
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(byte~) main::$9 ← < (byte*) CHUNKY#0
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*((byte*) DTV_PLANEB_START_LO#0) ← (byte~) main::$9
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(byte~) main::$10 ← > (byte*) CHUNKY#0
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*((byte*) DTV_PLANEB_START_MI#0) ← (byte~) main::$10
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*((byte*) DTV_PLANEB_START_HI#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0
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*((byte*) DTV_PLANEB_STEP#0) ← (byte/signed byte/word/signed word/dword/signed dword) 8
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*((byte*) DTV_PLANEB_MODULO_LO#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0
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*((byte*) DTV_PLANEB_MODULO_HI#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0
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*((byte*) CIA2_PORT_A_DDR#0) ← (byte/signed byte/word/signed word/dword/signed dword) 3
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(word~) main::$11 ← ((word)) (byte*) CHUNKY#0
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2019-03-08 05:54:45 +00:00
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(word/signed dword/dword~) main::$12 ← (word~) main::$11 / (word/signed word/dword/signed dword) $4000
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2018-04-15 21:32:49 +00:00
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(byte~) main::$13 ← ((byte)) (word/signed dword/dword~) main::$12
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(byte/word/dword~) main::$14 ← (byte/signed byte/word/signed word/dword/signed dword) 3 ^ (byte~) main::$13
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*((byte*) CIA2_PORT_A#0) ← (byte/word/dword~) main::$14
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(word~) main::$15 ← ((word)) (byte*) CHUNKY#0
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2019-03-08 05:54:45 +00:00
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(word~) main::$16 ← (word~) main::$15 & (word/signed word/dword/signed dword) $3fff
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2019-04-15 08:20:55 +00:00
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(word/signed dword/dword~) main::$17 ← (word~) main::$16 / (byte/signed byte/word/signed word/dword/signed dword) $40
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(byte~) main::$18 ← ((byte)) (word/signed dword/dword~) main::$17
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2018-04-15 21:32:49 +00:00
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(word~) main::$19 ← ((word)) (byte*) CHUNKY#0
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2019-03-08 05:54:45 +00:00
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(word~) main::$20 ← (word~) main::$19 & (word/signed word/dword/signed dword) $3fff
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2018-04-15 21:32:49 +00:00
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(byte~) main::$21 ← > (word~) main::$20
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2019-04-15 08:20:55 +00:00
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(byte/signed word/word/dword/signed dword~) main::$22 ← (byte~) main::$21 / (byte/signed byte/word/signed word/dword/signed dword) 4
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(byte/word/dword~) main::$23 ← (byte~) main::$18 | (byte/signed word/word/dword/signed dword~) main::$22
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*((byte*) VIC_MEMORY#0) ← (byte/word/dword~) main::$23
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2018-04-15 21:32:49 +00:00
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(byte) main::j#0 ← (byte/signed byte/word/signed word/dword/signed dword) 0
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2019-03-31 15:57:54 +00:00
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to:main::@1
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main::@1: scope:[main] from main::@1 main::@17
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(byte) main::j#2 ← phi( main::@1/(byte) main::j#1 main::@17/(byte) main::j#0 )
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2018-04-15 21:32:49 +00:00
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*((byte*) DTV_PALETTE#0 + (byte) main::j#2) ← (byte) main::j#2
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2019-03-08 05:54:45 +00:00
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(byte) main::j#1 ← (byte) main::j#2 + rangenext(0,$f)
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(bool~) main::$24 ← (byte) main::j#1 != rangelast(0,$f)
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2019-03-31 15:57:54 +00:00
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if((bool~) main::$24) goto main::@1
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to:main::@3
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main::@3: scope:[main] from main::@1 main::@12
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if(true) goto main::@4
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2018-04-15 21:32:49 +00:00
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to:main::@return
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2019-03-31 15:57:54 +00:00
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main::@4: scope:[main] from main::@3
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2018-04-15 21:32:49 +00:00
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asm { ldx#$ff rff: cpxRASTER bnerff stabilize: nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop cpxRASTER beqeat+0 eat: inx cpx#$08 bnestabilize }
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(byte~) main::$25 ← (byte) VIC_DEN#0 | (byte) VIC_ECM#0
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(byte~) main::$26 ← (byte~) main::$25 | (byte) VIC_RSEL#0
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(byte/word/dword~) main::$27 ← (byte~) main::$26 | (byte/signed byte/word/signed word/dword/signed dword) 3
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*((byte*) VIC_CONTROL#0) ← (byte/word/dword~) main::$27
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*((byte*) BORDERCOL#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0
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2019-03-08 05:54:45 +00:00
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(byte) main::rst#0 ← (byte/signed byte/word/signed word/dword/signed dword) $42
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2019-03-31 15:57:54 +00:00
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to:main::@6
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main::@6: scope:[main] from main::@4 main::@7
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(byte) main::rst#2 ← phi( main::@4/(byte) main::rst#0 main::@7/(byte) main::rst#3 )
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2018-04-28 06:41:05 +00:00
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(bool~) main::$28 ← *((byte*) RASTER#0) != (byte) main::rst#2
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2019-03-31 15:57:54 +00:00
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if((bool~) main::$28) goto main::@7
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2018-04-15 21:32:49 +00:00
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to:main::@8
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2019-03-31 15:57:54 +00:00
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main::@7: scope:[main] from main::@6
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(byte) main::rst#3 ← phi( main::@6/(byte) main::rst#2 )
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to:main::@6
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main::@8: scope:[main] from main::@6
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2019-03-29 23:15:53 +00:00
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asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
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2019-03-31 15:57:54 +00:00
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to:main::@12
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main::@12: scope:[main] from main::@12 main::@8
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2018-04-15 21:32:49 +00:00
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(byte) main::rst#1 ← *((byte*) RASTER#0)
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(byte~) main::$29 ← (byte) VIC_DEN#0 | (byte) VIC_ECM#0
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(byte~) main::$30 ← (byte~) main::$29 | (byte) VIC_RSEL#0
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(byte~) main::$31 ← (byte) main::rst#1 & (byte/signed byte/word/signed word/dword/signed dword) 7
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(byte~) main::$32 ← (byte~) main::$30 | (byte~) main::$31
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*((byte*) VIC_CONTROL#0) ← (byte~) main::$32
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2019-04-15 08:20:55 +00:00
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(byte/signed word/word/dword/signed dword~) main::$33 ← (byte) main::rst#1 * (byte/signed byte/word/signed word/dword/signed dword) $10
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*((byte*) BORDERCOL#0) ← (byte/signed word/word/dword/signed dword~) main::$33
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2018-04-15 21:32:49 +00:00
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asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
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2019-03-08 05:54:45 +00:00
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(bool~) main::$34 ← (byte) main::rst#1 != (byte/word/signed word/dword/signed dword) $f2
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2019-03-31 15:57:54 +00:00
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if((bool~) main::$34) goto main::@12
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to:main::@3
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main::@return: scope:[main] from main::@3
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2018-04-15 21:32:49 +00:00
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return
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to:@return
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gfx_init_chunky: scope:[gfx_init_chunky] from main
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2019-03-08 05:54:45 +00:00
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(byte*~) gfx_init_chunky::$0 ← (byte*) CHUNKY#0 / (word/signed word/dword/signed dword) $4000
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2018-04-15 21:32:49 +00:00
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(byte~) gfx_init_chunky::$1 ← ((byte)) (byte*~) gfx_init_chunky::$0
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(byte) gfx_init_chunky::gfxbCpuBank#0 ← (byte~) gfx_init_chunky::$1
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(byte) dtvSetCpuBankSegment1::cpuBankIdx#0 ← (byte) gfx_init_chunky::gfxbCpuBank#0
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2018-05-01 20:50:59 +00:00
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call dtvSetCpuBankSegment1
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2018-04-15 21:32:49 +00:00
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to:gfx_init_chunky::@7
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gfx_init_chunky::@7: scope:[gfx_init_chunky] from gfx_init_chunky
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(byte) gfx_init_chunky::gfxbCpuBank#3 ← phi( gfx_init_chunky/(byte) gfx_init_chunky::gfxbCpuBank#0 )
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(byte) gfx_init_chunky::gfxbCpuBank#1 ← ++ (byte) gfx_init_chunky::gfxbCpuBank#3
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2019-03-08 05:54:45 +00:00
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(byte*) gfx_init_chunky::gfxb#0 ← ((byte*)) (word/signed word/dword/signed dword) $4000
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2018-04-15 21:32:49 +00:00
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(byte) gfx_init_chunky::y#0 ← (byte/signed byte/word/signed word/dword/signed dword) 0
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to:gfx_init_chunky::@1
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gfx_init_chunky::@1: scope:[gfx_init_chunky] from gfx_init_chunky::@5 gfx_init_chunky::@7
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(byte) gfx_init_chunky::gfxbCpuBank#7 ← phi( gfx_init_chunky::@5/(byte) gfx_init_chunky::gfxbCpuBank#9 gfx_init_chunky::@7/(byte) gfx_init_chunky::gfxbCpuBank#1 )
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(byte) gfx_init_chunky::y#6 ← phi( gfx_init_chunky::@5/(byte) gfx_init_chunky::y#1 gfx_init_chunky::@7/(byte) gfx_init_chunky::y#0 )
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(byte*) gfx_init_chunky::gfxb#5 ← phi( gfx_init_chunky::@5/(byte*) gfx_init_chunky::gfxb#6 gfx_init_chunky::@7/(byte*) gfx_init_chunky::gfxb#0 )
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(word) gfx_init_chunky::x#0 ← (byte/signed byte/word/signed word/dword/signed dword) 0
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to:gfx_init_chunky::@2
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gfx_init_chunky::@2: scope:[gfx_init_chunky] from gfx_init_chunky::@1 gfx_init_chunky::@3
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(byte) gfx_init_chunky::gfxbCpuBank#6 ← phi( gfx_init_chunky::@1/(byte) gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::@3/(byte) gfx_init_chunky::gfxbCpuBank#8 )
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(byte) gfx_init_chunky::y#4 ← phi( gfx_init_chunky::@1/(byte) gfx_init_chunky::y#6 gfx_init_chunky::@3/(byte) gfx_init_chunky::y#2 )
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(word) gfx_init_chunky::x#3 ← phi( gfx_init_chunky::@1/(word) gfx_init_chunky::x#0 gfx_init_chunky::@3/(word) gfx_init_chunky::x#1 )
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(byte*) gfx_init_chunky::gfxb#3 ← phi( gfx_init_chunky::@1/(byte*) gfx_init_chunky::gfxb#5 gfx_init_chunky::@3/(byte*) gfx_init_chunky::gfxb#1 )
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2019-03-29 23:15:53 +00:00
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(bool~) gfx_init_chunky::$6 ← (byte*) gfx_init_chunky::gfxb#3 == (word/dword/signed dword) $8000
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(bool~) gfx_init_chunky::$7 ← ! (bool~) gfx_init_chunky::$6
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if((bool~) gfx_init_chunky::$7) goto gfx_init_chunky::@3
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2018-04-15 21:32:49 +00:00
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|
|
to:gfx_init_chunky::@4
|
|
|
|
gfx_init_chunky::@3: scope:[gfx_init_chunky] from gfx_init_chunky::@2 gfx_init_chunky::@8
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#8 ← phi( gfx_init_chunky::@2/(byte) gfx_init_chunky::gfxbCpuBank#6 gfx_init_chunky::@8/(byte) gfx_init_chunky::gfxbCpuBank#2 )
|
|
|
|
(byte*) gfx_init_chunky::gfxb#4 ← phi( gfx_init_chunky::@2/(byte*) gfx_init_chunky::gfxb#3 gfx_init_chunky::@8/(byte*) gfx_init_chunky::gfxb#2 )
|
|
|
|
(byte) gfx_init_chunky::y#2 ← phi( gfx_init_chunky::@2/(byte) gfx_init_chunky::y#4 gfx_init_chunky::@8/(byte) gfx_init_chunky::y#5 )
|
|
|
|
(word) gfx_init_chunky::x#2 ← phi( gfx_init_chunky::@2/(word) gfx_init_chunky::x#3 gfx_init_chunky::@8/(word) gfx_init_chunky::x#4 )
|
2019-03-29 23:15:53 +00:00
|
|
|
(word~) gfx_init_chunky::$9 ← (word) gfx_init_chunky::x#2 + (byte) gfx_init_chunky::y#2
|
|
|
|
(byte~) gfx_init_chunky::$10 ← ((byte)) (word~) gfx_init_chunky::$9
|
|
|
|
(byte) gfx_init_chunky::c#0 ← (byte~) gfx_init_chunky::$10
|
2018-04-15 21:32:49 +00:00
|
|
|
*((byte*) gfx_init_chunky::gfxb#4) ← (byte) gfx_init_chunky::c#0
|
|
|
|
(byte*) gfx_init_chunky::gfxb#1 ← ++ (byte*) gfx_init_chunky::gfxb#4
|
2019-03-08 05:54:45 +00:00
|
|
|
(word) gfx_init_chunky::x#1 ← (word) gfx_init_chunky::x#2 + rangenext(0,$13f)
|
2019-03-29 23:15:53 +00:00
|
|
|
(bool~) gfx_init_chunky::$11 ← (word) gfx_init_chunky::x#1 != rangelast(0,$13f)
|
|
|
|
if((bool~) gfx_init_chunky::$11) goto gfx_init_chunky::@2
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@5
|
|
|
|
gfx_init_chunky::@4: scope:[gfx_init_chunky] from gfx_init_chunky::@2
|
|
|
|
(byte) gfx_init_chunky::y#7 ← phi( gfx_init_chunky::@2/(byte) gfx_init_chunky::y#4 )
|
|
|
|
(word) gfx_init_chunky::x#5 ← phi( gfx_init_chunky::@2/(word) gfx_init_chunky::x#3 )
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#4 ← phi( gfx_init_chunky::@2/(byte) gfx_init_chunky::gfxbCpuBank#6 )
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#1 ← (byte) gfx_init_chunky::gfxbCpuBank#4
|
2018-05-01 20:50:59 +00:00
|
|
|
call dtvSetCpuBankSegment1
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@8
|
|
|
|
gfx_init_chunky::@8: scope:[gfx_init_chunky] from gfx_init_chunky::@4
|
|
|
|
(byte) gfx_init_chunky::y#5 ← phi( gfx_init_chunky::@4/(byte) gfx_init_chunky::y#7 )
|
|
|
|
(word) gfx_init_chunky::x#4 ← phi( gfx_init_chunky::@4/(word) gfx_init_chunky::x#5 )
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#5 ← phi( gfx_init_chunky::@4/(byte) gfx_init_chunky::gfxbCpuBank#4 )
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#2 ← ++ (byte) gfx_init_chunky::gfxbCpuBank#5
|
2019-03-08 05:54:45 +00:00
|
|
|
(byte*) gfx_init_chunky::gfxb#2 ← ((byte*)) (word/signed word/dword/signed dword) $4000
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@3
|
|
|
|
gfx_init_chunky::@5: scope:[gfx_init_chunky] from gfx_init_chunky::@3
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#9 ← phi( gfx_init_chunky::@3/(byte) gfx_init_chunky::gfxbCpuBank#8 )
|
|
|
|
(byte*) gfx_init_chunky::gfxb#6 ← phi( gfx_init_chunky::@3/(byte*) gfx_init_chunky::gfxb#1 )
|
|
|
|
(byte) gfx_init_chunky::y#3 ← phi( gfx_init_chunky::@3/(byte) gfx_init_chunky::y#2 )
|
2019-03-08 05:54:45 +00:00
|
|
|
(byte) gfx_init_chunky::y#1 ← (byte) gfx_init_chunky::y#3 + rangenext(0,$32)
|
2019-03-29 23:15:53 +00:00
|
|
|
(bool~) gfx_init_chunky::$12 ← (byte) gfx_init_chunky::y#1 != rangelast(0,$32)
|
|
|
|
if((bool~) gfx_init_chunky::$12) goto gfx_init_chunky::@1
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@6
|
|
|
|
gfx_init_chunky::@6: scope:[gfx_init_chunky] from gfx_init_chunky::@5
|
2019-03-29 23:15:53 +00:00
|
|
|
(byte/signed byte/word/signed word/dword/signed dword~) gfx_init_chunky::$3 ← (word/signed word/dword/signed dword) $4000 / (word/signed word/dword/signed dword) $4000
|
|
|
|
(byte~) gfx_init_chunky::$4 ← ((byte)) (byte/signed byte/word/signed word/dword/signed dword~) gfx_init_chunky::$3
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#2 ← (byte~) gfx_init_chunky::$4
|
2018-05-01 20:50:59 +00:00
|
|
|
call dtvSetCpuBankSegment1
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@9
|
|
|
|
gfx_init_chunky::@9: scope:[gfx_init_chunky] from gfx_init_chunky::@6
|
|
|
|
to:gfx_init_chunky::@return
|
|
|
|
gfx_init_chunky::@return: scope:[gfx_init_chunky] from gfx_init_chunky::@9
|
|
|
|
return
|
|
|
|
to:@return
|
2018-12-24 01:27:12 +00:00
|
|
|
@7: scope:[] from @5
|
2018-05-01 20:50:59 +00:00
|
|
|
call main
|
2018-12-24 01:27:12 +00:00
|
|
|
to:@8
|
|
|
|
@8: scope:[] from @7
|
2018-04-15 21:32:49 +00:00
|
|
|
to:@end
|
2018-12-24 01:27:12 +00:00
|
|
|
@end: scope:[] from @8
|
2018-04-15 21:32:49 +00:00
|
|
|
|
|
|
|
SYMBOL TABLE SSA
|
|
|
|
(label) @4
|
2018-12-24 01:27:12 +00:00
|
|
|
(label) @5
|
2018-05-14 21:53:03 +00:00
|
|
|
(label) @7
|
2018-12-24 01:27:12 +00:00
|
|
|
(label) @8
|
2018-04-15 21:32:49 +00:00
|
|
|
(label) @begin
|
|
|
|
(label) @end
|
|
|
|
(byte*) BORDERCOL
|
|
|
|
(byte*) BORDERCOL#0
|
|
|
|
(byte*) CHUNKY
|
|
|
|
(byte*) CHUNKY#0
|
|
|
|
(byte*) CIA2_PORT_A
|
|
|
|
(byte*) CIA2_PORT_A#0
|
|
|
|
(byte*) CIA2_PORT_A_DDR
|
|
|
|
(byte*) CIA2_PORT_A_DDR#0
|
|
|
|
(byte) DTV_BADLINE_OFF
|
|
|
|
(byte) DTV_BADLINE_OFF#0
|
|
|
|
(byte) DTV_CHUNKY
|
|
|
|
(byte) DTV_CHUNKY#0
|
|
|
|
(byte) DTV_COLORRAM_OFF
|
|
|
|
(byte) DTV_COLORRAM_OFF#0
|
|
|
|
(byte*) DTV_CONTROL
|
|
|
|
(byte*) DTV_CONTROL#0
|
|
|
|
(byte*) DTV_FEATURE
|
|
|
|
(byte*) DTV_FEATURE#0
|
|
|
|
(byte) DTV_FEATURE_ENABLE
|
|
|
|
(byte) DTV_FEATURE_ENABLE#0
|
|
|
|
(byte) DTV_HIGHCOLOR
|
|
|
|
(byte) DTV_HIGHCOLOR#0
|
|
|
|
(byte) DTV_LINEAR
|
|
|
|
(byte) DTV_LINEAR#0
|
|
|
|
(byte*) DTV_PALETTE
|
|
|
|
(byte*) DTV_PALETTE#0
|
|
|
|
(byte*) DTV_PLANEB_MODULO_HI
|
|
|
|
(byte*) DTV_PLANEB_MODULO_HI#0
|
|
|
|
(byte*) DTV_PLANEB_MODULO_LO
|
|
|
|
(byte*) DTV_PLANEB_MODULO_LO#0
|
|
|
|
(byte*) DTV_PLANEB_START_HI
|
|
|
|
(byte*) DTV_PLANEB_START_HI#0
|
|
|
|
(byte*) DTV_PLANEB_START_LO
|
|
|
|
(byte*) DTV_PLANEB_START_LO#0
|
|
|
|
(byte*) DTV_PLANEB_START_MI
|
|
|
|
(byte*) DTV_PLANEB_START_MI#0
|
|
|
|
(byte*) DTV_PLANEB_STEP
|
|
|
|
(byte*) DTV_PLANEB_STEP#0
|
|
|
|
(byte*) PROCPORT
|
|
|
|
(byte*) PROCPORT#0
|
|
|
|
(byte*) PROCPORT_DDR
|
|
|
|
(byte*) PROCPORT_DDR#0
|
|
|
|
(byte) PROCPORT_DDR_MEMORY_MASK
|
|
|
|
(byte) PROCPORT_DDR_MEMORY_MASK#0
|
|
|
|
(byte) PROCPORT_RAM_IO
|
|
|
|
(byte) PROCPORT_RAM_IO#0
|
|
|
|
(byte*) RASTER
|
|
|
|
(byte*) RASTER#0
|
|
|
|
(byte*) VIC_CONTROL
|
|
|
|
(byte*) VIC_CONTROL#0
|
|
|
|
(byte*) VIC_CONTROL2
|
|
|
|
(byte*) VIC_CONTROL2#0
|
|
|
|
(byte) VIC_CSEL
|
|
|
|
(byte) VIC_CSEL#0
|
|
|
|
(byte) VIC_DEN
|
|
|
|
(byte) VIC_DEN#0
|
|
|
|
(byte) VIC_ECM
|
|
|
|
(byte) VIC_ECM#0
|
|
|
|
(byte) VIC_MCM
|
|
|
|
(byte) VIC_MCM#0
|
|
|
|
(byte*) VIC_MEMORY
|
|
|
|
(byte*) VIC_MEMORY#0
|
|
|
|
(byte) VIC_RSEL
|
|
|
|
(byte) VIC_RSEL#0
|
|
|
|
(void()) dtvSetCpuBankSegment1((byte) dtvSetCpuBankSegment1::cpuBankIdx)
|
|
|
|
(label) dtvSetCpuBankSegment1::@return
|
|
|
|
(byte*) dtvSetCpuBankSegment1::cpuBank
|
|
|
|
(byte*) dtvSetCpuBankSegment1::cpuBank#0
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#0
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#1
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#2
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#3
|
|
|
|
(void()) gfx_init_chunky()
|
|
|
|
(byte*~) gfx_init_chunky::$0
|
|
|
|
(byte~) gfx_init_chunky::$1
|
2019-03-29 23:15:53 +00:00
|
|
|
(byte~) gfx_init_chunky::$10
|
|
|
|
(bool~) gfx_init_chunky::$11
|
|
|
|
(bool~) gfx_init_chunky::$12
|
|
|
|
(byte/signed byte/word/signed word/dword/signed dword~) gfx_init_chunky::$3
|
|
|
|
(byte~) gfx_init_chunky::$4
|
|
|
|
(bool~) gfx_init_chunky::$6
|
|
|
|
(bool~) gfx_init_chunky::$7
|
|
|
|
(word~) gfx_init_chunky::$9
|
2018-04-15 21:32:49 +00:00
|
|
|
(label) gfx_init_chunky::@1
|
|
|
|
(label) gfx_init_chunky::@2
|
|
|
|
(label) gfx_init_chunky::@3
|
|
|
|
(label) gfx_init_chunky::@4
|
|
|
|
(label) gfx_init_chunky::@5
|
|
|
|
(label) gfx_init_chunky::@6
|
|
|
|
(label) gfx_init_chunky::@7
|
|
|
|
(label) gfx_init_chunky::@8
|
|
|
|
(label) gfx_init_chunky::@9
|
|
|
|
(label) gfx_init_chunky::@return
|
|
|
|
(byte) gfx_init_chunky::c
|
|
|
|
(byte) gfx_init_chunky::c#0
|
|
|
|
(byte*) gfx_init_chunky::gfxb
|
|
|
|
(byte*) gfx_init_chunky::gfxb#0
|
|
|
|
(byte*) gfx_init_chunky::gfxb#1
|
|
|
|
(byte*) gfx_init_chunky::gfxb#2
|
|
|
|
(byte*) gfx_init_chunky::gfxb#3
|
|
|
|
(byte*) gfx_init_chunky::gfxb#4
|
|
|
|
(byte*) gfx_init_chunky::gfxb#5
|
|
|
|
(byte*) gfx_init_chunky::gfxb#6
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#0
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#1
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#2
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#3
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#4
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#5
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#6
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#7
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#8
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#9
|
|
|
|
(word) gfx_init_chunky::x
|
|
|
|
(word) gfx_init_chunky::x#0
|
|
|
|
(word) gfx_init_chunky::x#1
|
|
|
|
(word) gfx_init_chunky::x#2
|
|
|
|
(word) gfx_init_chunky::x#3
|
|
|
|
(word) gfx_init_chunky::x#4
|
|
|
|
(word) gfx_init_chunky::x#5
|
|
|
|
(byte) gfx_init_chunky::y
|
|
|
|
(byte) gfx_init_chunky::y#0
|
|
|
|
(byte) gfx_init_chunky::y#1
|
|
|
|
(byte) gfx_init_chunky::y#2
|
|
|
|
(byte) gfx_init_chunky::y#3
|
|
|
|
(byte) gfx_init_chunky::y#4
|
|
|
|
(byte) gfx_init_chunky::y#5
|
|
|
|
(byte) gfx_init_chunky::y#6
|
|
|
|
(byte) gfx_init_chunky::y#7
|
|
|
|
(void()) main()
|
|
|
|
(byte~) main::$1
|
|
|
|
(byte~) main::$10
|
|
|
|
(word~) main::$11
|
|
|
|
(word/signed dword/dword~) main::$12
|
|
|
|
(byte~) main::$13
|
|
|
|
(byte/word/dword~) main::$14
|
|
|
|
(word~) main::$15
|
|
|
|
(word~) main::$16
|
2019-04-15 08:20:55 +00:00
|
|
|
(word/signed dword/dword~) main::$17
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte~) main::$18
|
|
|
|
(word~) main::$19
|
|
|
|
(byte~) main::$2
|
|
|
|
(word~) main::$20
|
|
|
|
(byte~) main::$21
|
2019-04-15 08:20:55 +00:00
|
|
|
(byte/signed word/word/dword/signed dword~) main::$22
|
|
|
|
(byte/word/dword~) main::$23
|
2018-04-28 06:41:05 +00:00
|
|
|
(bool~) main::$24
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte~) main::$25
|
|
|
|
(byte~) main::$26
|
|
|
|
(byte/word/dword~) main::$27
|
2018-04-28 06:41:05 +00:00
|
|
|
(bool~) main::$28
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte~) main::$29
|
|
|
|
(byte~) main::$3
|
|
|
|
(byte~) main::$30
|
|
|
|
(byte~) main::$31
|
|
|
|
(byte~) main::$32
|
2019-04-15 08:20:55 +00:00
|
|
|
(byte/signed word/word/dword/signed dword~) main::$33
|
2018-04-28 06:41:05 +00:00
|
|
|
(bool~) main::$34
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte~) main::$4
|
|
|
|
(byte~) main::$5
|
|
|
|
(byte~) main::$6
|
|
|
|
(byte/word/dword~) main::$7
|
|
|
|
(byte~) main::$8
|
|
|
|
(byte~) main::$9
|
|
|
|
(label) main::@1
|
2019-03-31 15:57:54 +00:00
|
|
|
(label) main::@12
|
2018-04-15 21:32:49 +00:00
|
|
|
(label) main::@17
|
2019-03-31 15:57:54 +00:00
|
|
|
(label) main::@3
|
|
|
|
(label) main::@4
|
2018-04-15 21:32:49 +00:00
|
|
|
(label) main::@6
|
2019-03-31 15:57:54 +00:00
|
|
|
(label) main::@7
|
2018-04-15 21:32:49 +00:00
|
|
|
(label) main::@8
|
|
|
|
(label) main::@return
|
|
|
|
(byte) main::j
|
|
|
|
(byte) main::j#0
|
|
|
|
(byte) main::j#1
|
|
|
|
(byte) main::j#2
|
|
|
|
(byte) main::rst
|
|
|
|
(byte) main::rst#0
|
|
|
|
(byte) main::rst#1
|
|
|
|
(byte) main::rst#2
|
|
|
|
(byte) main::rst#3
|
|
|
|
|
|
|
|
Culled Empty Block (label) gfx_init_chunky::@9
|
2018-12-24 01:27:12 +00:00
|
|
|
Culled Empty Block (label) @8
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2CullEmptyBlocks
|
2019-04-15 12:03:50 +00:00
|
|
|
Inversing boolean not [121] (bool~) gfx_init_chunky::$7 ← (byte*) gfx_init_chunky::gfxb#3 != (word/dword/signed dword) $8000 from [120] (bool~) gfx_init_chunky::$6 ← (byte*) gfx_init_chunky::gfxb#3 == (word/dword/signed dword) $8000
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2UnaryNotSimplification
|
2018-04-15 21:32:49 +00:00
|
|
|
Alias (byte) main::rst#2 = (byte) main::rst#3
|
|
|
|
Alias (byte) gfx_init_chunky::gfxbCpuBank#0 = (byte~) gfx_init_chunky::$1 (byte) gfx_init_chunky::gfxbCpuBank#3
|
2019-03-29 23:15:53 +00:00
|
|
|
Alias (byte) gfx_init_chunky::c#0 = (byte~) gfx_init_chunky::$10
|
2018-04-15 21:32:49 +00:00
|
|
|
Alias (byte) gfx_init_chunky::gfxbCpuBank#4 = (byte) gfx_init_chunky::gfxbCpuBank#6 (byte) gfx_init_chunky::gfxbCpuBank#5
|
|
|
|
Alias (word) gfx_init_chunky::x#3 = (word) gfx_init_chunky::x#5 (word) gfx_init_chunky::x#4
|
|
|
|
Alias (byte) gfx_init_chunky::y#4 = (byte) gfx_init_chunky::y#7 (byte) gfx_init_chunky::y#5
|
|
|
|
Alias (byte) gfx_init_chunky::y#2 = (byte) gfx_init_chunky::y#3
|
|
|
|
Alias (byte*) gfx_init_chunky::gfxb#1 = (byte*) gfx_init_chunky::gfxb#6
|
|
|
|
Alias (byte) gfx_init_chunky::gfxbCpuBank#8 = (byte) gfx_init_chunky::gfxbCpuBank#9
|
2019-03-29 23:15:53 +00:00
|
|
|
Alias (byte) dtvSetCpuBankSegment1::cpuBankIdx#2 = (byte~) gfx_init_chunky::$4
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2AliasElimination
|
2018-04-15 21:32:49 +00:00
|
|
|
Alias (word) gfx_init_chunky::x#2 = (word) gfx_init_chunky::x#3
|
|
|
|
Alias (byte) gfx_init_chunky::y#2 = (byte) gfx_init_chunky::y#4
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2AliasElimination
|
2018-04-15 21:32:49 +00:00
|
|
|
Self Phi Eliminated (byte) main::rst#2
|
|
|
|
Self Phi Eliminated (byte) gfx_init_chunky::y#2
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2SelfPhiElimination
|
2018-04-15 21:32:49 +00:00
|
|
|
Redundant Phi (byte) main::rst#2 (byte) main::rst#0
|
|
|
|
Redundant Phi (byte) gfx_init_chunky::y#2 (byte) gfx_init_chunky::y#6
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2RedundantPhiElimination
|
2019-04-15 12:03:50 +00:00
|
|
|
Simple Condition (bool~) main::$24 [82] if((byte) main::j#1!=rangelast(0,$f)) goto main::@1
|
|
|
|
Simple Condition (bool~) main::$28 [93] if(*((byte*) RASTER#0)!=(byte) main::rst#0) goto main::@7
|
|
|
|
Simple Condition (bool~) main::$34 [106] if((byte) main::rst#1!=(byte/word/signed word/dword/signed dword) $f2) goto main::@12
|
|
|
|
Simple Condition (bool~) gfx_init_chunky::$7 [122] if((byte*) gfx_init_chunky::gfxb#3!=(word/dword/signed dword) $8000) goto gfx_init_chunky::@3
|
|
|
|
Simple Condition (bool~) gfx_init_chunky::$11 [131] if((word) gfx_init_chunky::x#1!=rangelast(0,$13f)) goto gfx_init_chunky::@2
|
|
|
|
Simple Condition (bool~) gfx_init_chunky::$12 [141] if((byte) gfx_init_chunky::y#1!=rangelast(0,$32)) goto gfx_init_chunky::@1
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2ConditionalJumpSimplification
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant (const byte*) PROCPORT_DDR#0 = ((byte*))0
|
|
|
|
Constant (const byte) PROCPORT_DDR_MEMORY_MASK#0 = 7
|
|
|
|
Constant (const byte*) PROCPORT#0 = ((byte*))1
|
2019-03-08 05:54:45 +00:00
|
|
|
Constant (const byte) PROCPORT_RAM_IO#0 = $35
|
|
|
|
Constant (const byte*) RASTER#0 = ((byte*))$d012
|
|
|
|
Constant (const byte*) BORDERCOL#0 = ((byte*))$d020
|
|
|
|
Constant (const byte*) VIC_CONTROL#0 = ((byte*))$d011
|
|
|
|
Constant (const byte) VIC_ECM#0 = $40
|
|
|
|
Constant (const byte) VIC_DEN#0 = $10
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant (const byte) VIC_RSEL#0 = 8
|
2019-03-08 05:54:45 +00:00
|
|
|
Constant (const byte*) VIC_CONTROL2#0 = ((byte*))$d016
|
|
|
|
Constant (const byte) VIC_MCM#0 = $10
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant (const byte) VIC_CSEL#0 = 8
|
2019-03-08 05:54:45 +00:00
|
|
|
Constant (const byte*) VIC_MEMORY#0 = ((byte*))$d018
|
|
|
|
Constant (const byte*) CIA2_PORT_A#0 = ((byte*))$dd00
|
|
|
|
Constant (const byte*) CIA2_PORT_A_DDR#0 = ((byte*))$dd02
|
|
|
|
Constant (const byte*) DTV_FEATURE#0 = ((byte*))$d03f
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant (const byte) DTV_FEATURE_ENABLE#0 = 1
|
2019-03-08 05:54:45 +00:00
|
|
|
Constant (const byte*) DTV_CONTROL#0 = ((byte*))$d03c
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant (const byte) DTV_LINEAR#0 = 1
|
|
|
|
Constant (const byte) DTV_HIGHCOLOR#0 = 4
|
2019-03-08 05:54:45 +00:00
|
|
|
Constant (const byte) DTV_COLORRAM_OFF#0 = $10
|
|
|
|
Constant (const byte) DTV_BADLINE_OFF#0 = $20
|
|
|
|
Constant (const byte) DTV_CHUNKY#0 = $40
|
|
|
|
Constant (const byte*) DTV_PALETTE#0 = ((byte*))$d200
|
|
|
|
Constant (const byte*) DTV_PLANEB_START_LO#0 = ((byte*))$d049
|
|
|
|
Constant (const byte*) DTV_PLANEB_START_MI#0 = ((byte*))$d04a
|
|
|
|
Constant (const byte*) DTV_PLANEB_START_HI#0 = ((byte*))$d04b
|
|
|
|
Constant (const byte*) DTV_PLANEB_STEP#0 = ((byte*))$d04c
|
|
|
|
Constant (const byte*) DTV_PLANEB_MODULO_LO#0 = ((byte*))$d047
|
|
|
|
Constant (const byte*) DTV_PLANEB_MODULO_HI#0 = ((byte*))$d048
|
|
|
|
Constant (const byte*) dtvSetCpuBankSegment1::cpuBank#0 = ((byte*))$ff
|
|
|
|
Constant (const byte*) CHUNKY#0 = ((byte*))$8000
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant (const byte) main::j#0 = 0
|
2019-03-08 05:54:45 +00:00
|
|
|
Constant (const byte) main::rst#0 = $42
|
|
|
|
Constant (const byte*) gfx_init_chunky::gfxb#0 = ((byte*))$4000
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant (const byte) gfx_init_chunky::y#0 = 0
|
|
|
|
Constant (const word) gfx_init_chunky::x#0 = 0
|
2019-03-08 05:54:45 +00:00
|
|
|
Constant (const byte*) gfx_init_chunky::gfxb#2 = ((byte*))$4000
|
2019-03-29 23:15:53 +00:00
|
|
|
Constant (const byte/signed byte/word/signed word/dword/signed dword) gfx_init_chunky::$3 = $4000/$4000
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2ConstantIdentification
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant (const byte) main::$1 = DTV_HIGHCOLOR#0|DTV_LINEAR#0
|
|
|
|
Constant (const byte) main::$5 = VIC_DEN#0|VIC_ECM#0
|
|
|
|
Constant (const byte) main::$8 = VIC_MCM#0|VIC_CSEL#0
|
|
|
|
Constant (const byte) main::$9 = <CHUNKY#0
|
|
|
|
Constant (const byte) main::$10 = >CHUNKY#0
|
|
|
|
Constant (const word) main::$11 = ((word))CHUNKY#0
|
|
|
|
Constant (const word) main::$15 = ((word))CHUNKY#0
|
|
|
|
Constant (const word) main::$19 = ((word))CHUNKY#0
|
|
|
|
Constant (const byte) main::$25 = VIC_DEN#0|VIC_ECM#0
|
|
|
|
Constant (const byte) main::$29 = VIC_DEN#0|VIC_ECM#0
|
2019-03-08 05:54:45 +00:00
|
|
|
Constant (const byte*) gfx_init_chunky::$0 = CHUNKY#0/$4000
|
2019-03-29 23:15:53 +00:00
|
|
|
Constant (const byte) dtvSetCpuBankSegment1::cpuBankIdx#2 = ((byte))gfx_init_chunky::$3
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2ConstantIdentification
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant (const byte) main::$2 = main::$1|DTV_COLORRAM_OFF#0
|
|
|
|
Constant (const byte) main::$6 = main::$5|VIC_RSEL#0
|
2019-03-08 05:54:45 +00:00
|
|
|
Constant (const word/signed dword/dword) main::$12 = main::$11/$4000
|
|
|
|
Constant (const word) main::$16 = main::$15&$3fff
|
|
|
|
Constant (const word) main::$20 = main::$19&$3fff
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant (const byte) main::$26 = main::$25|VIC_RSEL#0
|
|
|
|
Constant (const byte) main::$30 = main::$29|VIC_RSEL#0
|
|
|
|
Constant (const byte) gfx_init_chunky::gfxbCpuBank#0 = ((byte))gfx_init_chunky::$0
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2ConstantIdentification
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant (const byte) main::$3 = main::$2|DTV_CHUNKY#0
|
|
|
|
Constant (const byte/word/dword) main::$7 = main::$6|3
|
|
|
|
Constant (const byte) main::$13 = ((byte))main::$12
|
2019-04-15 08:20:55 +00:00
|
|
|
Constant (const word/signed dword/dword) main::$17 = main::$16/$40
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant (const byte) main::$21 = >main::$20
|
|
|
|
Constant (const byte/word/dword) main::$27 = main::$26|3
|
|
|
|
Constant (const byte) dtvSetCpuBankSegment1::cpuBankIdx#0 = gfx_init_chunky::gfxbCpuBank#0
|
|
|
|
Constant (const byte) gfx_init_chunky::gfxbCpuBank#1 = ++gfx_init_chunky::gfxbCpuBank#0
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2ConstantIdentification
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant (const byte) main::$4 = main::$3|DTV_BADLINE_OFF#0
|
|
|
|
Constant (const byte/word/dword) main::$14 = 3^main::$13
|
|
|
|
Constant (const byte) main::$18 = ((byte))main::$17
|
2019-04-15 08:20:55 +00:00
|
|
|
Constant (const byte/signed word/word/dword/signed dword) main::$22 = main::$21/4
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2ConstantIdentification
|
2019-04-15 08:20:55 +00:00
|
|
|
Constant (const byte/word/dword) main::$23 = main::$18|main::$22
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2ConstantIdentification
|
2019-03-31 15:57:54 +00:00
|
|
|
if() condition always true - replacing block destination [25] if(true) goto main::@4
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2ConstantIfs
|
2018-04-18 21:19:25 +00:00
|
|
|
Removing unused block main::@return
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2EliminateUnusedBlocks
|
2018-07-12 12:42:45 +00:00
|
|
|
Resolved ranged next value main::j#1 ← ++ main::j#2 to ++
|
2019-03-31 15:57:54 +00:00
|
|
|
Resolved ranged comparison value if(main::j#1!=rangelast(0,$f)) goto main::@1 to (byte/signed byte/word/signed word/dword/signed dword) $10
|
2018-07-12 12:42:45 +00:00
|
|
|
Resolved ranged next value gfx_init_chunky::x#1 ← ++ gfx_init_chunky::x#2 to ++
|
2019-03-08 05:54:45 +00:00
|
|
|
Resolved ranged comparison value if(gfx_init_chunky::x#1!=rangelast(0,$13f)) goto gfx_init_chunky::@2 to (word/signed word/dword/signed dword) $140
|
2018-07-12 12:42:45 +00:00
|
|
|
Resolved ranged next value gfx_init_chunky::y#1 ← ++ gfx_init_chunky::y#6 to ++
|
2019-03-08 05:54:45 +00:00
|
|
|
Resolved ranged comparison value if(gfx_init_chunky::y#1!=rangelast(0,$32)) goto gfx_init_chunky::@1 to (byte/signed byte/word/signed word/dword/signed dword) $33
|
2019-04-15 08:20:55 +00:00
|
|
|
Rewriting multiplication to use shift (byte/signed word/word/dword/signed dword~) main::$33 ← (byte) main::rst#1 * (byte/signed byte/word/signed word/dword/signed dword) $10
|
|
|
|
Successful SSA optimization Pass2MultiplyToShiftRewriting
|
2018-05-14 21:53:03 +00:00
|
|
|
Culled Empty Block (label) @4
|
2018-12-24 01:27:12 +00:00
|
|
|
Culled Empty Block (label) @5
|
2019-03-31 15:57:54 +00:00
|
|
|
Culled Empty Block (label) main::@3
|
|
|
|
Culled Empty Block (label) main::@7
|
2018-04-15 21:32:49 +00:00
|
|
|
Culled Empty Block (label) gfx_init_chunky::@7
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2CullEmptyBlocks
|
2019-04-15 08:20:55 +00:00
|
|
|
Inferred type updated to byte in [34] (byte/signed word/word/dword/signed dword~) main::$33 ← (byte) main::rst#1 << (byte/signed byte/word/signed word/dword/signed dword) 4
|
2018-04-15 21:32:49 +00:00
|
|
|
Inlining constant with var siblings (const byte) dtvSetCpuBankSegment1::cpuBankIdx#2
|
|
|
|
Inlining constant with var siblings (const byte) dtvSetCpuBankSegment1::cpuBankIdx#0
|
|
|
|
Inlining constant with var siblings (const byte) main::j#0
|
|
|
|
Inlining constant with var siblings (const byte) main::rst#0
|
|
|
|
Inlining constant with var siblings (const byte*) gfx_init_chunky::gfxb#0
|
|
|
|
Inlining constant with var siblings (const byte) gfx_init_chunky::y#0
|
|
|
|
Inlining constant with var siblings (const word) gfx_init_chunky::x#0
|
|
|
|
Inlining constant with var siblings (const byte*) gfx_init_chunky::gfxb#2
|
|
|
|
Inlining constant with var siblings (const byte) gfx_init_chunky::gfxbCpuBank#0
|
|
|
|
Inlining constant with var siblings (const byte) gfx_init_chunky::gfxbCpuBank#1
|
2019-03-08 05:54:45 +00:00
|
|
|
Constant inlined dtvSetCpuBankSegment1::cpuBankIdx#0 = ((byte))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000
|
|
|
|
Constant inlined main::rst#0 = (byte/signed byte/word/signed word/dword/signed dword) $42
|
|
|
|
Constant inlined dtvSetCpuBankSegment1::cpuBankIdx#2 = ((byte))(word/signed word/dword/signed dword) $4000/(word/signed word/dword/signed dword) $4000
|
|
|
|
Constant inlined main::$12 = ((word))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000
|
|
|
|
Constant inlined main::$13 = ((byte))((word))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000
|
|
|
|
Constant inlined main::$14 = (byte/signed byte/word/signed word/dword/signed dword) 3^((byte))((word))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant inlined gfx_init_chunky::y#0 = (byte/signed byte/word/signed word/dword/signed dword) 0
|
|
|
|
Constant inlined main::$15 = ((word))(const byte*) CHUNKY#0
|
|
|
|
Constant inlined gfx_init_chunky::x#0 = (byte/signed byte/word/signed word/dword/signed dword) 0
|
|
|
|
Constant inlined main::$30 = (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0
|
|
|
|
Constant inlined main::$10 = >(const byte*) CHUNKY#0
|
|
|
|
Constant inlined main::$11 = ((word))(const byte*) CHUNKY#0
|
2019-03-08 05:54:45 +00:00
|
|
|
Constant inlined main::$16 = ((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff
|
2019-04-15 08:20:55 +00:00
|
|
|
Constant inlined main::$17 = ((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) $40
|
|
|
|
Constant inlined main::$18 = ((byte))((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) $40
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant inlined main::$19 = ((word))(const byte*) CHUNKY#0
|
|
|
|
Constant inlined main::j#0 = (byte/signed byte/word/signed word/dword/signed dword) 0
|
2019-04-15 08:20:55 +00:00
|
|
|
Constant inlined main::$23 = ((byte))((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) $40|>((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) 4
|
2019-03-08 05:54:45 +00:00
|
|
|
Constant inlined gfx_init_chunky::gfxbCpuBank#1 = ++((byte))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant inlined main::$25 = (const byte) VIC_DEN#0|(const byte) VIC_ECM#0
|
|
|
|
Constant inlined main::$26 = (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0
|
2019-03-08 05:54:45 +00:00
|
|
|
Constant inlined gfx_init_chunky::gfxb#2 = ((byte*))(word/signed word/dword/signed dword) $4000
|
|
|
|
Constant inlined main::$20 = ((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff
|
|
|
|
Constant inlined gfx_init_chunky::gfxb#0 = ((byte*))(word/signed word/dword/signed dword) $4000
|
|
|
|
Constant inlined main::$21 = >((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff
|
2019-04-15 08:20:55 +00:00
|
|
|
Constant inlined main::$22 = >((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) 4
|
2019-03-08 05:54:45 +00:00
|
|
|
Constant inlined gfx_init_chunky::gfxbCpuBank#0 = ((byte))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant inlined main::$1 = (const byte) DTV_HIGHCOLOR#0|(const byte) DTV_LINEAR#0
|
|
|
|
Constant inlined main::$27 = (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0|(byte/signed byte/word/signed word/dword/signed dword) 3
|
|
|
|
Constant inlined main::$2 = (const byte) DTV_HIGHCOLOR#0|(const byte) DTV_LINEAR#0|(const byte) DTV_COLORRAM_OFF#0
|
|
|
|
Constant inlined main::$29 = (const byte) VIC_DEN#0|(const byte) VIC_ECM#0
|
|
|
|
Constant inlined main::$5 = (const byte) VIC_DEN#0|(const byte) VIC_ECM#0
|
|
|
|
Constant inlined main::$6 = (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0
|
|
|
|
Constant inlined main::$3 = (const byte) DTV_HIGHCOLOR#0|(const byte) DTV_LINEAR#0|(const byte) DTV_COLORRAM_OFF#0|(const byte) DTV_CHUNKY#0
|
|
|
|
Constant inlined main::$4 = (const byte) DTV_HIGHCOLOR#0|(const byte) DTV_LINEAR#0|(const byte) DTV_COLORRAM_OFF#0|(const byte) DTV_CHUNKY#0|(const byte) DTV_BADLINE_OFF#0
|
2019-03-08 05:54:45 +00:00
|
|
|
Constant inlined gfx_init_chunky::$0 = (const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant inlined main::$9 = <(const byte*) CHUNKY#0
|
|
|
|
Constant inlined main::$7 = (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0|(byte/signed byte/word/signed word/dword/signed dword) 3
|
2019-03-29 23:15:53 +00:00
|
|
|
Constant inlined gfx_init_chunky::$3 = (word/signed word/dword/signed dword) $4000/(word/signed word/dword/signed dword) $4000
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant inlined main::$8 = (const byte) VIC_MCM#0|(const byte) VIC_CSEL#0
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2ConstantInlining
|
2019-03-31 15:57:54 +00:00
|
|
|
Added new block during phi lifting main::@18(between main::@1 and main::@1)
|
2018-04-15 21:32:49 +00:00
|
|
|
Added new block during phi lifting gfx_init_chunky::@10(between gfx_init_chunky::@5 and gfx_init_chunky::@1)
|
|
|
|
Added new block during phi lifting gfx_init_chunky::@11(between gfx_init_chunky::@3 and gfx_init_chunky::@2)
|
|
|
|
Added new block during phi lifting gfx_init_chunky::@12(between gfx_init_chunky::@2 and gfx_init_chunky::@3)
|
|
|
|
Adding NOP phi() at start of @begin
|
2018-12-24 01:27:12 +00:00
|
|
|
Adding NOP phi() at start of @7
|
2018-04-15 21:32:49 +00:00
|
|
|
Adding NOP phi() at start of @end
|
|
|
|
Adding NOP phi() at start of gfx_init_chunky
|
|
|
|
Adding NOP phi() at start of gfx_init_chunky::@6
|
|
|
|
CALL GRAPH
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|
|
|
Calls in [] to main:2
|
|
|
|
Calls in [main] to gfx_init_chunky:7
|
2018-04-18 21:19:25 +00:00
|
|
|
Calls in [gfx_init_chunky] to dtvSetCpuBankSegment1:40 dtvSetCpuBankSegment1:48 dtvSetCpuBankSegment1:61
|
2018-04-15 21:32:49 +00:00
|
|
|
|
|
|
|
Created 10 initial phi equivalence classes
|
2018-04-18 21:19:25 +00:00
|
|
|
Coalesced [38] main::j#3 ← main::j#1
|
|
|
|
Coalesced [42] gfx_init_chunky::gfxb#8 ← gfx_init_chunky::gfxb#5
|
|
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|
Coalesced [43] gfx_init_chunky::gfxbCpuBank#11 ← gfx_init_chunky::gfxbCpuBank#7
|
|
|
|
Coalesced [47] dtvSetCpuBankSegment1::cpuBankIdx#4 ← dtvSetCpuBankSegment1::cpuBankIdx#1
|
|
|
|
Coalesced [50] gfx_init_chunky::gfxbCpuBank#14 ← gfx_init_chunky::gfxbCpuBank#2
|
|
|
|
Coalesced [63] gfx_init_chunky::gfxb#7 ← gfx_init_chunky::gfxb#1
|
|
|
|
Coalesced [64] gfx_init_chunky::y#8 ← gfx_init_chunky::y#1
|
|
|
|
Coalesced [65] gfx_init_chunky::gfxbCpuBank#10 ← gfx_init_chunky::gfxbCpuBank#8
|
|
|
|
Coalesced (already) [66] gfx_init_chunky::gfxb#9 ← gfx_init_chunky::gfxb#1
|
|
|
|
Coalesced [67] gfx_init_chunky::x#6 ← gfx_init_chunky::x#1
|
|
|
|
Coalesced (already) [68] gfx_init_chunky::gfxbCpuBank#12 ← gfx_init_chunky::gfxbCpuBank#8
|
|
|
|
Coalesced [69] gfx_init_chunky::gfxb#10 ← gfx_init_chunky::gfxb#3
|
|
|
|
Coalesced (already) [70] gfx_init_chunky::gfxbCpuBank#13 ← gfx_init_chunky::gfxbCpuBank#4
|
2018-04-15 21:32:49 +00:00
|
|
|
Coalesced down to 6 phi equivalence classes
|
|
|
|
Culled Empty Block (label) main::@18
|
|
|
|
Culled Empty Block (label) gfx_init_chunky::@10
|
|
|
|
Culled Empty Block (label) gfx_init_chunky::@11
|
|
|
|
Culled Empty Block (label) gfx_init_chunky::@12
|
2019-03-31 15:10:41 +00:00
|
|
|
Renumbering block @7 to @1
|
2019-03-31 15:57:54 +00:00
|
|
|
Renumbering block main::@4 to main::@2
|
|
|
|
Renumbering block main::@6 to main::@3
|
|
|
|
Renumbering block main::@8 to main::@4
|
|
|
|
Renumbering block main::@12 to main::@5
|
2019-03-31 15:10:41 +00:00
|
|
|
Renumbering block main::@17 to main::@6
|
|
|
|
Renumbering block gfx_init_chunky::@8 to gfx_init_chunky::@7
|
2018-04-15 21:32:49 +00:00
|
|
|
Adding NOP phi() at start of @begin
|
2019-03-31 15:10:41 +00:00
|
|
|
Adding NOP phi() at start of @1
|
2018-04-15 21:32:49 +00:00
|
|
|
Adding NOP phi() at start of @end
|
|
|
|
Adding NOP phi() at start of gfx_init_chunky
|
|
|
|
Adding NOP phi() at start of gfx_init_chunky::@6
|
|
|
|
|
|
|
|
FINAL CONTROL FLOW GRAPH
|
|
|
|
@begin: scope:[] from
|
2018-11-11 20:51:36 +00:00
|
|
|
[0] phi()
|
2019-03-31 15:10:41 +00:00
|
|
|
to:@1
|
|
|
|
@1: scope:[] from @begin
|
2018-11-11 20:51:36 +00:00
|
|
|
[1] phi()
|
|
|
|
[2] call main
|
2018-04-15 21:32:49 +00:00
|
|
|
to:@end
|
2019-03-31 15:10:41 +00:00
|
|
|
@end: scope:[] from @1
|
2018-11-11 20:51:36 +00:00
|
|
|
[3] phi()
|
2019-03-31 15:10:41 +00:00
|
|
|
main: scope:[main] from @1
|
2018-04-15 21:32:49 +00:00
|
|
|
asm { sei }
|
2018-11-11 20:51:36 +00:00
|
|
|
[5] *((const byte*) PROCPORT_DDR#0) ← (const byte) PROCPORT_DDR_MEMORY_MASK#0
|
|
|
|
[6] *((const byte*) PROCPORT#0) ← (const byte) PROCPORT_RAM_IO#0
|
|
|
|
[7] call gfx_init_chunky
|
2019-03-31 15:10:41 +00:00
|
|
|
to:main::@6
|
|
|
|
main::@6: scope:[main] from main
|
2018-11-11 20:51:36 +00:00
|
|
|
[8] *((const byte*) DTV_FEATURE#0) ← (const byte) DTV_FEATURE_ENABLE#0
|
|
|
|
[9] *((const byte*) DTV_CONTROL#0) ← (const byte) DTV_HIGHCOLOR#0|(const byte) DTV_LINEAR#0|(const byte) DTV_COLORRAM_OFF#0|(const byte) DTV_CHUNKY#0|(const byte) DTV_BADLINE_OFF#0
|
|
|
|
[10] *((const byte*) VIC_CONTROL#0) ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0|(byte/signed byte/word/signed word/dword/signed dword) 3
|
|
|
|
[11] *((const byte*) VIC_CONTROL2#0) ← (const byte) VIC_MCM#0|(const byte) VIC_CSEL#0
|
|
|
|
[12] *((const byte*) DTV_PLANEB_START_LO#0) ← <(const byte*) CHUNKY#0
|
|
|
|
[13] *((const byte*) DTV_PLANEB_START_MI#0) ← >(const byte*) CHUNKY#0
|
|
|
|
[14] *((const byte*) DTV_PLANEB_START_HI#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0
|
|
|
|
[15] *((const byte*) DTV_PLANEB_STEP#0) ← (byte/signed byte/word/signed word/dword/signed dword) 8
|
|
|
|
[16] *((const byte*) DTV_PLANEB_MODULO_LO#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0
|
|
|
|
[17] *((const byte*) DTV_PLANEB_MODULO_HI#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0
|
|
|
|
[18] *((const byte*) CIA2_PORT_A_DDR#0) ← (byte/signed byte/word/signed word/dword/signed dword) 3
|
2019-03-08 05:54:45 +00:00
|
|
|
[19] *((const byte*) CIA2_PORT_A#0) ← (byte/signed byte/word/signed word/dword/signed dword) 3^((byte))((word))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000
|
2019-04-15 08:20:55 +00:00
|
|
|
[20] *((const byte*) VIC_MEMORY#0) ← ((byte))((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) $40|>((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) 4
|
2019-03-31 15:57:54 +00:00
|
|
|
to:main::@1
|
|
|
|
main::@1: scope:[main] from main::@1 main::@6
|
|
|
|
[21] (byte) main::j#2 ← phi( main::@1/(byte) main::j#1 main::@6/(byte/signed byte/word/signed word/dword/signed dword) 0 )
|
2018-11-11 20:51:36 +00:00
|
|
|
[22] *((const byte*) DTV_PALETTE#0 + (byte) main::j#2) ← (byte) main::j#2
|
|
|
|
[23] (byte) main::j#1 ← ++ (byte) main::j#2
|
2019-03-31 15:57:54 +00:00
|
|
|
[24] if((byte) main::j#1!=(byte/signed byte/word/signed word/dword/signed dword) $10) goto main::@1
|
|
|
|
to:main::@2
|
|
|
|
main::@2: scope:[main] from main::@1 main::@5
|
2018-04-15 21:32:49 +00:00
|
|
|
asm { ldx#$ff rff: cpxRASTER bnerff stabilize: nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop cpxRASTER beqeat+0 eat: inx cpx#$08 bnestabilize }
|
2018-11-11 20:51:36 +00:00
|
|
|
[26] *((const byte*) VIC_CONTROL#0) ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0|(byte/signed byte/word/signed word/dword/signed dword) 3
|
|
|
|
[27] *((const byte*) BORDERCOL#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0
|
2019-03-31 15:10:41 +00:00
|
|
|
to:main::@3
|
2019-03-31 15:57:54 +00:00
|
|
|
main::@3: scope:[main] from main::@2 main::@3
|
2019-03-31 15:10:41 +00:00
|
|
|
[28] if(*((const byte*) RASTER#0)!=(byte/signed byte/word/signed word/dword/signed dword) $42) goto main::@3
|
|
|
|
to:main::@4
|
|
|
|
main::@4: scope:[main] from main::@3
|
2019-03-29 23:15:53 +00:00
|
|
|
asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
|
2019-03-31 15:10:41 +00:00
|
|
|
to:main::@5
|
|
|
|
main::@5: scope:[main] from main::@4 main::@5
|
2018-11-11 20:51:36 +00:00
|
|
|
[30] (byte) main::rst#1 ← *((const byte*) RASTER#0)
|
|
|
|
[31] (byte~) main::$31 ← (byte) main::rst#1 & (byte/signed byte/word/signed word/dword/signed dword) 7
|
|
|
|
[32] (byte~) main::$32 ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0 | (byte~) main::$31
|
|
|
|
[33] *((const byte*) VIC_CONTROL#0) ← (byte~) main::$32
|
|
|
|
[34] (byte~) main::$33 ← (byte) main::rst#1 << (byte/signed byte/word/signed word/dword/signed dword) 4
|
|
|
|
[35] *((const byte*) BORDERCOL#0) ← (byte~) main::$33
|
2018-04-15 21:32:49 +00:00
|
|
|
asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
|
2019-03-31 15:10:41 +00:00
|
|
|
[37] if((byte) main::rst#1!=(byte/word/signed word/dword/signed dword) $f2) goto main::@5
|
2019-03-31 15:57:54 +00:00
|
|
|
to:main::@2
|
2018-04-15 21:32:49 +00:00
|
|
|
gfx_init_chunky: scope:[gfx_init_chunky] from main
|
2018-11-11 20:51:36 +00:00
|
|
|
[38] phi()
|
|
|
|
[39] call dtvSetCpuBankSegment1
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@1
|
|
|
|
gfx_init_chunky::@1: scope:[gfx_init_chunky] from gfx_init_chunky gfx_init_chunky::@5
|
2019-03-08 05:54:45 +00:00
|
|
|
[40] (byte) gfx_init_chunky::gfxbCpuBank#7 ← phi( gfx_init_chunky::@5/(byte) gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky/++((byte))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000 )
|
2018-11-11 20:51:36 +00:00
|
|
|
[40] (byte) gfx_init_chunky::y#6 ← phi( gfx_init_chunky::@5/(byte) gfx_init_chunky::y#1 gfx_init_chunky/(byte/signed byte/word/signed word/dword/signed dword) 0 )
|
2019-03-08 05:54:45 +00:00
|
|
|
[40] (byte*) gfx_init_chunky::gfxb#5 ← phi( gfx_init_chunky::@5/(byte*) gfx_init_chunky::gfxb#1 gfx_init_chunky/((byte*))(word/signed word/dword/signed dword) $4000 )
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@2
|
|
|
|
gfx_init_chunky::@2: scope:[gfx_init_chunky] from gfx_init_chunky::@1 gfx_init_chunky::@3
|
2018-11-11 20:51:36 +00:00
|
|
|
[41] (byte) gfx_init_chunky::gfxbCpuBank#4 ← phi( gfx_init_chunky::@1/(byte) gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::@3/(byte) gfx_init_chunky::gfxbCpuBank#8 )
|
|
|
|
[41] (word) gfx_init_chunky::x#2 ← phi( gfx_init_chunky::@1/(byte/signed byte/word/signed word/dword/signed dword) 0 gfx_init_chunky::@3/(word) gfx_init_chunky::x#1 )
|
|
|
|
[41] (byte*) gfx_init_chunky::gfxb#3 ← phi( gfx_init_chunky::@1/(byte*) gfx_init_chunky::gfxb#5 gfx_init_chunky::@3/(byte*) gfx_init_chunky::gfxb#1 )
|
2019-03-08 05:54:45 +00:00
|
|
|
[42] if((byte*) gfx_init_chunky::gfxb#3!=(word/dword/signed dword) $8000) goto gfx_init_chunky::@3
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@4
|
|
|
|
gfx_init_chunky::@4: scope:[gfx_init_chunky] from gfx_init_chunky::@2
|
2018-11-11 20:51:36 +00:00
|
|
|
[43] (byte) dtvSetCpuBankSegment1::cpuBankIdx#1 ← (byte) gfx_init_chunky::gfxbCpuBank#4
|
|
|
|
[44] call dtvSetCpuBankSegment1
|
2019-03-31 15:10:41 +00:00
|
|
|
to:gfx_init_chunky::@7
|
|
|
|
gfx_init_chunky::@7: scope:[gfx_init_chunky] from gfx_init_chunky::@4
|
2018-11-11 20:51:36 +00:00
|
|
|
[45] (byte) gfx_init_chunky::gfxbCpuBank#2 ← ++ (byte) gfx_init_chunky::gfxbCpuBank#4
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@3
|
2019-03-31 15:10:41 +00:00
|
|
|
gfx_init_chunky::@3: scope:[gfx_init_chunky] from gfx_init_chunky::@2 gfx_init_chunky::@7
|
|
|
|
[46] (byte) gfx_init_chunky::gfxbCpuBank#8 ← phi( gfx_init_chunky::@2/(byte) gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::@7/(byte) gfx_init_chunky::gfxbCpuBank#2 )
|
|
|
|
[46] (byte*) gfx_init_chunky::gfxb#4 ← phi( gfx_init_chunky::@2/(byte*) gfx_init_chunky::gfxb#3 gfx_init_chunky::@7/((byte*))(word/signed word/dword/signed dword) $4000 )
|
2019-03-29 23:15:53 +00:00
|
|
|
[47] (word~) gfx_init_chunky::$9 ← (word) gfx_init_chunky::x#2 + (byte) gfx_init_chunky::y#6
|
|
|
|
[48] (byte) gfx_init_chunky::c#0 ← ((byte)) (word~) gfx_init_chunky::$9
|
2018-11-11 20:51:36 +00:00
|
|
|
[49] *((byte*) gfx_init_chunky::gfxb#4) ← (byte) gfx_init_chunky::c#0
|
|
|
|
[50] (byte*) gfx_init_chunky::gfxb#1 ← ++ (byte*) gfx_init_chunky::gfxb#4
|
|
|
|
[51] (word) gfx_init_chunky::x#1 ← ++ (word) gfx_init_chunky::x#2
|
2019-03-08 05:54:45 +00:00
|
|
|
[52] if((word) gfx_init_chunky::x#1!=(word/signed word/dword/signed dword) $140) goto gfx_init_chunky::@2
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@5
|
|
|
|
gfx_init_chunky::@5: scope:[gfx_init_chunky] from gfx_init_chunky::@3
|
2018-11-11 20:51:36 +00:00
|
|
|
[53] (byte) gfx_init_chunky::y#1 ← ++ (byte) gfx_init_chunky::y#6
|
2019-03-08 05:54:45 +00:00
|
|
|
[54] if((byte) gfx_init_chunky::y#1!=(byte/signed byte/word/signed word/dword/signed dword) $33) goto gfx_init_chunky::@1
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@6
|
|
|
|
gfx_init_chunky::@6: scope:[gfx_init_chunky] from gfx_init_chunky::@5
|
2018-11-11 20:51:36 +00:00
|
|
|
[55] phi()
|
|
|
|
[56] call dtvSetCpuBankSegment1
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@return
|
|
|
|
gfx_init_chunky::@return: scope:[gfx_init_chunky] from gfx_init_chunky::@6
|
2018-11-11 20:51:36 +00:00
|
|
|
[57] return
|
2018-04-15 21:32:49 +00:00
|
|
|
to:@return
|
|
|
|
dtvSetCpuBankSegment1: scope:[dtvSetCpuBankSegment1] from gfx_init_chunky gfx_init_chunky::@4 gfx_init_chunky::@6
|
2019-03-08 05:54:45 +00:00
|
|
|
[58] (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 ← phi( gfx_init_chunky/((byte))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000 gfx_init_chunky::@4/(byte) dtvSetCpuBankSegment1::cpuBankIdx#1 gfx_init_chunky::@6/((byte))(word/signed word/dword/signed dword) $4000/(word/signed word/dword/signed dword) $4000 )
|
2018-11-11 20:51:36 +00:00
|
|
|
[59] *((const byte*) dtvSetCpuBankSegment1::cpuBank#0) ← (byte) dtvSetCpuBankSegment1::cpuBankIdx#3
|
2018-04-15 21:32:49 +00:00
|
|
|
asm { .byte$32,$dd lda$ff .byte$32,$00 }
|
|
|
|
to:dtvSetCpuBankSegment1::@return
|
|
|
|
dtvSetCpuBankSegment1::@return: scope:[dtvSetCpuBankSegment1] from dtvSetCpuBankSegment1
|
2018-11-11 20:51:36 +00:00
|
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|
[61] return
|
2018-04-15 21:32:49 +00:00
|
|
|
to:@return
|
|
|
|
|
|
|
|
|
|
|
|
VARIABLE REGISTER WEIGHTS
|
|
|
|
(byte*) BORDERCOL
|
|
|
|
(byte*) CHUNKY
|
|
|
|
(byte*) CIA2_PORT_A
|
|
|
|
(byte*) CIA2_PORT_A_DDR
|
|
|
|
(byte) DTV_BADLINE_OFF
|
|
|
|
(byte) DTV_CHUNKY
|
|
|
|
(byte) DTV_COLORRAM_OFF
|
|
|
|
(byte*) DTV_CONTROL
|
|
|
|
(byte*) DTV_FEATURE
|
|
|
|
(byte) DTV_FEATURE_ENABLE
|
|
|
|
(byte) DTV_HIGHCOLOR
|
|
|
|
(byte) DTV_LINEAR
|
|
|
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(byte*) DTV_PALETTE
|
|
|
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(byte*) DTV_PLANEB_MODULO_HI
|
|
|
|
(byte*) DTV_PLANEB_MODULO_LO
|
|
|
|
(byte*) DTV_PLANEB_START_HI
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|
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|
(byte*) DTV_PLANEB_START_LO
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|
(byte*) DTV_PLANEB_START_MI
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(byte*) DTV_PLANEB_STEP
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|
|
|
(byte*) PROCPORT
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|
|
|
(byte*) PROCPORT_DDR
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|
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|
(byte) PROCPORT_DDR_MEMORY_MASK
|
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(byte) PROCPORT_RAM_IO
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(byte*) RASTER
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|
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|
(byte*) VIC_CONTROL
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|
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|
(byte*) VIC_CONTROL2
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|
(byte) VIC_CSEL
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|
(byte) VIC_DEN
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|
(byte) VIC_ECM
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|
(byte) VIC_MCM
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|
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(byte*) VIC_MEMORY
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|
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|
(byte) VIC_RSEL
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|
|
|
(void()) dtvSetCpuBankSegment1((byte) dtvSetCpuBankSegment1::cpuBankIdx)
|
|
|
|
(byte*) dtvSetCpuBankSegment1::cpuBank
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#1 202.0
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#3 103.0
|
|
|
|
(void()) gfx_init_chunky()
|
2019-03-29 23:15:53 +00:00
|
|
|
(word~) gfx_init_chunky::$9 202.0
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) gfx_init_chunky::c
|
|
|
|
(byte) gfx_init_chunky::c#0 202.0
|
|
|
|
(byte*) gfx_init_chunky::gfxb
|
|
|
|
(byte*) gfx_init_chunky::gfxb#1 42.599999999999994
|
|
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|
(byte*) gfx_init_chunky::gfxb#3 157.0
|
|
|
|
(byte*) gfx_init_chunky::gfxb#4 75.75
|
|
|
|
(byte*) gfx_init_chunky::gfxb#5 22.0
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#2 202.0
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#4 103.75
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#7 22.0
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#8 34.888888888888886
|
|
|
|
(word) gfx_init_chunky::x
|
|
|
|
(word) gfx_init_chunky::x#1 151.5
|
|
|
|
(word) gfx_init_chunky::x#2 30.299999999999997
|
|
|
|
(byte) gfx_init_chunky::y
|
|
|
|
(byte) gfx_init_chunky::y#1 16.5
|
|
|
|
(byte) gfx_init_chunky::y#6 9.461538461538462
|
|
|
|
(void()) main()
|
|
|
|
(byte~) main::$31 202.0
|
|
|
|
(byte~) main::$32 202.0
|
|
|
|
(byte~) main::$33 202.0
|
|
|
|
(byte) main::j
|
|
|
|
(byte) main::j#1 16.5
|
|
|
|
(byte) main::j#2 22.0
|
|
|
|
(byte) main::rst
|
|
|
|
(byte) main::rst#1 57.714285714285715
|
|
|
|
|
|
|
|
Initial phi equivalence classes
|
|
|
|
[ main::j#2 main::j#1 ]
|
|
|
|
[ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
[ gfx_init_chunky::x#2 gfx_init_chunky::x#1 ]
|
|
|
|
[ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ]
|
|
|
|
[ gfx_init_chunky::gfxb#4 gfx_init_chunky::gfxb#3 gfx_init_chunky::gfxb#5 gfx_init_chunky::gfxb#1 ]
|
|
|
|
[ dtvSetCpuBankSegment1::cpuBankIdx#3 dtvSetCpuBankSegment1::cpuBankIdx#1 ]
|
|
|
|
Added variable main::rst#1 to zero page equivalence class [ main::rst#1 ]
|
|
|
|
Added variable main::$31 to zero page equivalence class [ main::$31 ]
|
|
|
|
Added variable main::$32 to zero page equivalence class [ main::$32 ]
|
|
|
|
Added variable main::$33 to zero page equivalence class [ main::$33 ]
|
2019-03-29 23:15:53 +00:00
|
|
|
Added variable gfx_init_chunky::$9 to zero page equivalence class [ gfx_init_chunky::$9 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
Added variable gfx_init_chunky::c#0 to zero page equivalence class [ gfx_init_chunky::c#0 ]
|
|
|
|
Complete equivalence classes
|
|
|
|
[ main::j#2 main::j#1 ]
|
|
|
|
[ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
[ gfx_init_chunky::x#2 gfx_init_chunky::x#1 ]
|
|
|
|
[ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ]
|
|
|
|
[ gfx_init_chunky::gfxb#4 gfx_init_chunky::gfxb#3 gfx_init_chunky::gfxb#5 gfx_init_chunky::gfxb#1 ]
|
|
|
|
[ dtvSetCpuBankSegment1::cpuBankIdx#3 dtvSetCpuBankSegment1::cpuBankIdx#1 ]
|
|
|
|
[ main::rst#1 ]
|
|
|
|
[ main::$31 ]
|
|
|
|
[ main::$32 ]
|
|
|
|
[ main::$33 ]
|
2019-03-29 23:15:53 +00:00
|
|
|
[ gfx_init_chunky::$9 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
[ gfx_init_chunky::c#0 ]
|
|
|
|
Allocated zp ZP_BYTE:2 [ main::j#2 main::j#1 ]
|
|
|
|
Allocated zp ZP_BYTE:3 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
Allocated zp ZP_WORD:4 [ gfx_init_chunky::x#2 gfx_init_chunky::x#1 ]
|
|
|
|
Allocated zp ZP_BYTE:6 [ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ]
|
|
|
|
Allocated zp ZP_WORD:7 [ gfx_init_chunky::gfxb#4 gfx_init_chunky::gfxb#3 gfx_init_chunky::gfxb#5 gfx_init_chunky::gfxb#1 ]
|
|
|
|
Allocated zp ZP_BYTE:9 [ dtvSetCpuBankSegment1::cpuBankIdx#3 dtvSetCpuBankSegment1::cpuBankIdx#1 ]
|
|
|
|
Allocated zp ZP_BYTE:10 [ main::rst#1 ]
|
|
|
|
Allocated zp ZP_BYTE:11 [ main::$31 ]
|
|
|
|
Allocated zp ZP_BYTE:12 [ main::$32 ]
|
|
|
|
Allocated zp ZP_BYTE:13 [ main::$33 ]
|
2019-03-29 23:15:53 +00:00
|
|
|
Allocated zp ZP_WORD:14 [ gfx_init_chunky::$9 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
Allocated zp ZP_BYTE:16 [ gfx_init_chunky::c#0 ]
|
|
|
|
|
|
|
|
INITIAL ASM
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG0 File Comments
|
2019-02-17 23:12:29 +00:00
|
|
|
// C64DTV 8bpp charmode stretcher
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG1 Basic Upstart
|
2018-04-15 21:32:49 +00:00
|
|
|
.pc = $801 "Basic"
|
2018-12-25 16:04:50 +00:00
|
|
|
:BasicUpstart(bbegin)
|
2018-04-15 21:32:49 +00:00
|
|
|
.pc = $80d "Program"
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG2 Global Constants & labels
|
2019-02-17 23:12:29 +00:00
|
|
|
// Processor port data direction register
|
2018-04-15 21:32:49 +00:00
|
|
|
.label PROCPORT_DDR = 0
|
2019-02-17 23:12:29 +00:00
|
|
|
// Mask for PROCESSOR_PORT_DDR which allows only memory configuration to be written
|
2018-04-15 21:32:49 +00:00
|
|
|
.const PROCPORT_DDR_MEMORY_MASK = 7
|
2019-02-17 23:12:29 +00:00
|
|
|
// Processor Port Register controlling RAM/ROM configuration and the datasette
|
2018-04-15 21:32:49 +00:00
|
|
|
.label PROCPORT = 1
|
2019-02-17 23:12:29 +00:00
|
|
|
// RAM in $A000, $E000 I/O in $D000
|
2018-04-15 21:32:49 +00:00
|
|
|
.const PROCPORT_RAM_IO = $35
|
|
|
|
.label RASTER = $d012
|
|
|
|
.label BORDERCOL = $d020
|
|
|
|
.label VIC_CONTROL = $d011
|
|
|
|
.const VIC_ECM = $40
|
|
|
|
.const VIC_DEN = $10
|
|
|
|
.const VIC_RSEL = 8
|
|
|
|
.label VIC_CONTROL2 = $d016
|
|
|
|
.const VIC_MCM = $10
|
|
|
|
.const VIC_CSEL = 8
|
|
|
|
.label VIC_MEMORY = $d018
|
2019-02-17 23:12:29 +00:00
|
|
|
// CIA#2 Port A: Serial bus, RS-232, VIC memory bank
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CIA2_PORT_A = $dd00
|
2019-02-17 23:12:29 +00:00
|
|
|
// CIA #2 Port A data direction register.
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CIA2_PORT_A_DDR = $dd02
|
2019-02-17 23:12:29 +00:00
|
|
|
// Feature enables or disables the extra C64 DTV features
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_FEATURE = $d03f
|
|
|
|
.const DTV_FEATURE_ENABLE = 1
|
2019-02-17 23:12:29 +00:00
|
|
|
// Controls the graphics modes of the C64 DTV
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_CONTROL = $d03c
|
|
|
|
.const DTV_LINEAR = 1
|
|
|
|
.const DTV_HIGHCOLOR = 4
|
|
|
|
.const DTV_COLORRAM_OFF = $10
|
|
|
|
.const DTV_BADLINE_OFF = $20
|
|
|
|
.const DTV_CHUNKY = $40
|
2019-02-17 23:12:29 +00:00
|
|
|
// Defines colors for the 16 first colors ($00-$0f)
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_PALETTE = $d200
|
2019-02-17 23:12:29 +00:00
|
|
|
// Linear Graphics Plane B Counter Control
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_PLANEB_START_LO = $d049
|
|
|
|
.label DTV_PLANEB_START_MI = $d04a
|
|
|
|
.label DTV_PLANEB_START_HI = $d04b
|
|
|
|
.label DTV_PLANEB_STEP = $d04c
|
|
|
|
.label DTV_PLANEB_MODULO_LO = $d047
|
|
|
|
.label DTV_PLANEB_MODULO_HI = $d048
|
2019-02-17 23:12:29 +00:00
|
|
|
// Plane with all pixels
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CHUNKY = $8000
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG3 @begin
|
2018-04-15 21:32:49 +00:00
|
|
|
bbegin:
|
2019-03-31 15:10:41 +00:00
|
|
|
//SEG4 [1] phi from @begin to @1 [phi:@begin->@1]
|
|
|
|
b1_from_bbegin:
|
|
|
|
jmp b1
|
|
|
|
//SEG5 @1
|
|
|
|
b1:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG6 [2] call main
|
2018-04-15 21:32:49 +00:00
|
|
|
jsr main
|
2019-03-31 15:10:41 +00:00
|
|
|
//SEG7 [3] phi from @1 to @end [phi:@1->@end]
|
|
|
|
bend_from_b1:
|
2018-04-15 21:32:49 +00:00
|
|
|
jmp bend
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG8 @end
|
2018-04-15 21:32:49 +00:00
|
|
|
bend:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG9 main
|
2018-04-15 21:32:49 +00:00
|
|
|
main: {
|
|
|
|
.label _31 = $b
|
|
|
|
.label _32 = $c
|
|
|
|
.label _33 = $d
|
|
|
|
.label j = 2
|
|
|
|
.label rst = $a
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG10 asm { sei }
|
2018-04-15 21:32:49 +00:00
|
|
|
sei
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG11 [5] *((const byte*) PROCPORT_DDR#0) ← (const byte) PROCPORT_DDR_MEMORY_MASK#0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Disable normal interrupt (prevent keyboard reading glitches and allows to hide basic/kernal)
|
|
|
|
// Disable kernal & basic
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #PROCPORT_DDR_MEMORY_MASK
|
|
|
|
sta PROCPORT_DDR
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG12 [6] *((const byte*) PROCPORT#0) ← (const byte) PROCPORT_RAM_IO#0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #PROCPORT_RAM_IO
|
|
|
|
sta PROCPORT
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG13 [7] call gfx_init_chunky
|
|
|
|
//SEG14 [38] phi from main to gfx_init_chunky [phi:main->gfx_init_chunky]
|
2018-04-15 21:32:49 +00:00
|
|
|
gfx_init_chunky_from_main:
|
|
|
|
jsr gfx_init_chunky
|
2019-03-31 15:10:41 +00:00
|
|
|
jmp b6
|
|
|
|
//SEG15 main::@6
|
|
|
|
b6:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG16 [8] *((const byte*) DTV_FEATURE#0) ← (const byte) DTV_FEATURE_ENABLE#0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Enable DTV extended modes
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #DTV_FEATURE_ENABLE
|
|
|
|
sta DTV_FEATURE
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG17 [9] *((const byte*) DTV_CONTROL#0) ← (const byte) DTV_HIGHCOLOR#0|(const byte) DTV_LINEAR#0|(const byte) DTV_COLORRAM_OFF#0|(const byte) DTV_CHUNKY#0|(const byte) DTV_BADLINE_OFF#0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// 8BPP Pixel Cell Mode
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #DTV_HIGHCOLOR|DTV_LINEAR|DTV_COLORRAM_OFF|DTV_CHUNKY|DTV_BADLINE_OFF
|
|
|
|
sta DTV_CONTROL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG18 [10] *((const byte*) VIC_CONTROL#0) ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0|(byte/signed byte/word/signed word/dword/signed dword) 3 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_DEN|VIC_ECM|VIC_RSEL|3
|
|
|
|
sta VIC_CONTROL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG19 [11] *((const byte*) VIC_CONTROL2#0) ← (const byte) VIC_MCM#0|(const byte) VIC_CSEL#0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_MCM|VIC_CSEL
|
|
|
|
sta VIC_CONTROL2
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG20 [12] *((const byte*) DTV_PLANEB_START_LO#0) ← <(const byte*) CHUNKY#0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Plane B: CHUNKY
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #<CHUNKY
|
|
|
|
sta DTV_PLANEB_START_LO
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG21 [13] *((const byte*) DTV_PLANEB_START_MI#0) ← >(const byte*) CHUNKY#0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #>CHUNKY
|
|
|
|
sta DTV_PLANEB_START_MI
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG22 [14] *((const byte*) DTV_PLANEB_START_HI#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta DTV_PLANEB_START_HI
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG23 [15] *((const byte*) DTV_PLANEB_STEP#0) ← (byte/signed byte/word/signed word/dword/signed dword) 8 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #8
|
|
|
|
sta DTV_PLANEB_STEP
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG24 [16] *((const byte*) DTV_PLANEB_MODULO_LO#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta DTV_PLANEB_MODULO_LO
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG25 [17] *((const byte*) DTV_PLANEB_MODULO_HI#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta DTV_PLANEB_MODULO_HI
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG26 [18] *((const byte*) CIA2_PORT_A_DDR#0) ← (byte/signed byte/word/signed word/dword/signed dword) 3 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// VIC Graphics Bank
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #3
|
|
|
|
sta CIA2_PORT_A_DDR
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG27 [19] *((const byte*) CIA2_PORT_A#0) ← (byte/signed byte/word/signed word/dword/signed dword) 3^((byte))((word))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set VIC Bank bits to output - all others to input
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #3^CHUNKY/$4000
|
|
|
|
sta CIA2_PORT_A
|
2019-04-15 08:20:55 +00:00
|
|
|
//SEG28 [20] *((const byte*) VIC_MEMORY#0) ← ((byte))((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) $40|>((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) 4 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set VIC Bank
|
|
|
|
// VIC memory
|
2019-04-15 08:20:55 +00:00
|
|
|
lda #(CHUNKY&$3fff)/$40|(0)/4
|
2018-04-15 21:32:49 +00:00
|
|
|
sta VIC_MEMORY
|
2019-03-31 15:57:54 +00:00
|
|
|
//SEG29 [21] phi from main::@6 to main::@1 [phi:main::@6->main::@1]
|
|
|
|
b1_from_b6:
|
|
|
|
//SEG30 [21] phi (byte) main::j#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:main::@6->main::@1#0] -- vbuz1=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta j
|
2019-03-31 15:57:54 +00:00
|
|
|
jmp b1
|
2019-02-17 23:12:29 +00:00
|
|
|
// DTV Palette - Grey Tones
|
2019-03-31 15:57:54 +00:00
|
|
|
//SEG31 [21] phi from main::@1 to main::@1 [phi:main::@1->main::@1]
|
|
|
|
b1_from_b1:
|
|
|
|
//SEG32 [21] phi (byte) main::j#2 = (byte) main::j#1 [phi:main::@1->main::@1#0] -- register_copy
|
|
|
|
jmp b1
|
|
|
|
//SEG33 main::@1
|
|
|
|
b1:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG34 [22] *((const byte*) DTV_PALETTE#0 + (byte) main::j#2) ← (byte) main::j#2 -- pbuc1_derefidx_vbuz1=vbuz1
|
2018-04-15 21:32:49 +00:00
|
|
|
ldy j
|
|
|
|
tya
|
|
|
|
sta DTV_PALETTE,y
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG35 [23] (byte) main::j#1 ← ++ (byte) main::j#2 -- vbuz1=_inc_vbuz1
|
2018-04-15 21:32:49 +00:00
|
|
|
inc j
|
2019-03-31 15:57:54 +00:00
|
|
|
//SEG36 [24] if((byte) main::j#1!=(byte/signed byte/word/signed word/dword/signed dword) $10) goto main::@1 -- vbuz1_neq_vbuc1_then_la1
|
2019-03-26 22:49:44 +00:00
|
|
|
lda #$10
|
|
|
|
cmp j
|
2019-03-31 15:57:54 +00:00
|
|
|
bne b1_from_b1
|
|
|
|
jmp b2
|
|
|
|
//SEG37 main::@2
|
|
|
|
b2:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG38 asm { ldx#$ff rff: cpxRASTER bnerff stabilize: nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop cpxRASTER beqeat+0 eat: inx cpx#$08 bnestabilize }
|
2019-02-17 23:12:29 +00:00
|
|
|
// Stabilize Raster
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx #$ff
|
|
|
|
rff:
|
|
|
|
cpx RASTER
|
|
|
|
bne rff
|
|
|
|
stabilize:
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
cpx RASTER
|
|
|
|
beq eat+0
|
|
|
|
eat:
|
|
|
|
inx
|
|
|
|
cpx #8
|
|
|
|
bne stabilize
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG39 [26] *((const byte*) VIC_CONTROL#0) ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0|(byte/signed byte/word/signed word/dword/signed dword) 3 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_DEN|VIC_ECM|VIC_RSEL|3
|
|
|
|
sta VIC_CONTROL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG40 [27] *((const byte*) BORDERCOL#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta BORDERCOL
|
2019-03-31 15:10:41 +00:00
|
|
|
jmp b3
|
|
|
|
//SEG41 main::@3
|
|
|
|
b3:
|
|
|
|
//SEG42 [28] if(*((const byte*) RASTER#0)!=(byte/signed byte/word/signed word/dword/signed dword) $42) goto main::@3 -- _deref_pbuc1_neq_vbuc2_then_la1
|
2019-03-26 22:49:44 +00:00
|
|
|
lda #$42
|
|
|
|
cmp RASTER
|
2019-03-31 15:10:41 +00:00
|
|
|
bne b3
|
|
|
|
jmp b4
|
|
|
|
//SEG43 main::@4
|
|
|
|
b4:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG44 asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
|
2018-04-15 21:32:49 +00:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2019-03-31 15:10:41 +00:00
|
|
|
jmp b5
|
|
|
|
//SEG45 main::@5
|
|
|
|
b5:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG46 [30] (byte) main::rst#1 ← *((const byte*) RASTER#0) -- vbuz1=_deref_pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda RASTER
|
|
|
|
sta rst
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG47 [31] (byte~) main::$31 ← (byte) main::rst#1 & (byte/signed byte/word/signed word/dword/signed dword) 7 -- vbuz1=vbuz2_band_vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #7
|
|
|
|
and rst
|
|
|
|
sta _31
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG48 [32] (byte~) main::$32 ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0 | (byte~) main::$31 -- vbuz1=vbuc1_bor_vbuz2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_DEN|VIC_ECM|VIC_RSEL
|
|
|
|
ora _31
|
|
|
|
sta _32
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG49 [33] *((const byte*) VIC_CONTROL#0) ← (byte~) main::$32 -- _deref_pbuc1=vbuz1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda _32
|
|
|
|
sta VIC_CONTROL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG50 [34] (byte~) main::$33 ← (byte) main::rst#1 << (byte/signed byte/word/signed word/dword/signed dword) 4 -- vbuz1=vbuz2_rol_4
|
2018-04-15 21:32:49 +00:00
|
|
|
lda rst
|
|
|
|
asl
|
|
|
|
asl
|
|
|
|
asl
|
|
|
|
asl
|
|
|
|
sta _33
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG51 [35] *((const byte*) BORDERCOL#0) ← (byte~) main::$33 -- _deref_pbuc1=vbuz1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda _33
|
|
|
|
sta BORDERCOL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG52 asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
|
2018-04-15 21:32:49 +00:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2019-03-31 15:10:41 +00:00
|
|
|
//SEG53 [37] if((byte) main::rst#1!=(byte/word/signed word/dword/signed dword) $f2) goto main::@5 -- vbuz1_neq_vbuc1_then_la1
|
2019-03-26 22:49:44 +00:00
|
|
|
lda #$f2
|
|
|
|
cmp rst
|
2019-03-31 15:10:41 +00:00
|
|
|
bne b5
|
2019-03-31 15:57:54 +00:00
|
|
|
jmp b2
|
2018-04-15 21:32:49 +00:00
|
|
|
}
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG54 gfx_init_chunky
|
2019-02-17 23:12:29 +00:00
|
|
|
// Initialize Plane with 8bpp chunky
|
2018-04-15 21:32:49 +00:00
|
|
|
gfx_init_chunky: {
|
2019-03-29 23:15:53 +00:00
|
|
|
.label _9 = $e
|
2018-04-15 21:32:49 +00:00
|
|
|
.label c = $10
|
|
|
|
.label gfxb = 7
|
|
|
|
.label x = 4
|
|
|
|
.label gfxbCpuBank = 6
|
|
|
|
.label y = 3
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG55 [39] call dtvSetCpuBankSegment1
|
|
|
|
//SEG56 [58] phi from gfx_init_chunky to dtvSetCpuBankSegment1 [phi:gfx_init_chunky->dtvSetCpuBankSegment1]
|
2018-04-15 21:32:49 +00:00
|
|
|
dtvSetCpuBankSegment1_from_gfx_init_chunky:
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG57 [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = ((byte))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000 [phi:gfx_init_chunky->dtvSetCpuBankSegment1#0] -- vbuz1=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #$ff&CHUNKY/$4000
|
|
|
|
sta dtvSetCpuBankSegment1.cpuBankIdx
|
|
|
|
jsr dtvSetCpuBankSegment1
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG58 [40] phi from gfx_init_chunky to gfx_init_chunky::@1 [phi:gfx_init_chunky->gfx_init_chunky::@1]
|
2018-04-15 21:32:49 +00:00
|
|
|
b1_from_gfx_init_chunky:
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG59 [40] phi (byte) gfx_init_chunky::gfxbCpuBank#7 = ++((byte))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000 [phi:gfx_init_chunky->gfx_init_chunky::@1#0] -- vbuz1=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #($ff&CHUNKY/$4000)+1
|
|
|
|
sta gfxbCpuBank
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG60 [40] phi (byte) gfx_init_chunky::y#6 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:gfx_init_chunky->gfx_init_chunky::@1#1] -- vbuz1=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta y
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG61 [40] phi (byte*) gfx_init_chunky::gfxb#5 = ((byte*))(word/signed word/dword/signed dword) $4000 [phi:gfx_init_chunky->gfx_init_chunky::@1#2] -- pbuz1=pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #<$4000
|
|
|
|
sta gfxb
|
|
|
|
lda #>$4000
|
|
|
|
sta gfxb+1
|
|
|
|
jmp b1
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG62 [40] phi from gfx_init_chunky::@5 to gfx_init_chunky::@1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1]
|
2018-04-15 21:32:49 +00:00
|
|
|
b1_from_b5:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG63 [40] phi (byte) gfx_init_chunky::gfxbCpuBank#7 = (byte) gfx_init_chunky::gfxbCpuBank#8 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#0] -- register_copy
|
|
|
|
//SEG64 [40] phi (byte) gfx_init_chunky::y#6 = (byte) gfx_init_chunky::y#1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#1] -- register_copy
|
|
|
|
//SEG65 [40] phi (byte*) gfx_init_chunky::gfxb#5 = (byte*) gfx_init_chunky::gfxb#1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#2] -- register_copy
|
2018-04-15 21:32:49 +00:00
|
|
|
jmp b1
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG66 gfx_init_chunky::@1
|
2018-04-15 21:32:49 +00:00
|
|
|
b1:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG67 [41] phi from gfx_init_chunky::@1 to gfx_init_chunky::@2 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2]
|
2018-04-15 21:32:49 +00:00
|
|
|
b2_from_b1:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG68 [41] phi (byte) gfx_init_chunky::gfxbCpuBank#4 = (byte) gfx_init_chunky::gfxbCpuBank#7 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#0] -- register_copy
|
|
|
|
//SEG69 [41] phi (word) gfx_init_chunky::x#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#1] -- vwuz1=vbuc1
|
2019-03-18 01:08:32 +00:00
|
|
|
lda #0
|
2018-04-15 21:32:49 +00:00
|
|
|
sta x
|
2019-03-18 01:08:32 +00:00
|
|
|
lda #0
|
2018-04-15 21:32:49 +00:00
|
|
|
sta x+1
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG70 [41] phi (byte*) gfx_init_chunky::gfxb#3 = (byte*) gfx_init_chunky::gfxb#5 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#2] -- register_copy
|
2018-04-15 21:32:49 +00:00
|
|
|
jmp b2
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG71 [41] phi from gfx_init_chunky::@3 to gfx_init_chunky::@2 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2]
|
2018-04-15 21:32:49 +00:00
|
|
|
b2_from_b3:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG72 [41] phi (byte) gfx_init_chunky::gfxbCpuBank#4 = (byte) gfx_init_chunky::gfxbCpuBank#8 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#0] -- register_copy
|
|
|
|
//SEG73 [41] phi (word) gfx_init_chunky::x#2 = (word) gfx_init_chunky::x#1 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#1] -- register_copy
|
|
|
|
//SEG74 [41] phi (byte*) gfx_init_chunky::gfxb#3 = (byte*) gfx_init_chunky::gfxb#1 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#2] -- register_copy
|
2018-04-15 21:32:49 +00:00
|
|
|
jmp b2
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG75 gfx_init_chunky::@2
|
2018-04-15 21:32:49 +00:00
|
|
|
b2:
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG76 [42] if((byte*) gfx_init_chunky::gfxb#3!=(word/dword/signed dword) $8000) goto gfx_init_chunky::@3 -- pbuz1_neq_vwuc1_then_la1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda gfxb+1
|
|
|
|
cmp #>$8000
|
|
|
|
bne b3_from_b2
|
|
|
|
lda gfxb
|
|
|
|
cmp #<$8000
|
|
|
|
bne b3_from_b2
|
|
|
|
jmp b4
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG77 gfx_init_chunky::@4
|
2018-04-15 21:32:49 +00:00
|
|
|
b4:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG78 [43] (byte) dtvSetCpuBankSegment1::cpuBankIdx#1 ← (byte) gfx_init_chunky::gfxbCpuBank#4 -- vbuz1=vbuz2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda gfxbCpuBank
|
|
|
|
sta dtvSetCpuBankSegment1.cpuBankIdx
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG79 [44] call dtvSetCpuBankSegment1
|
|
|
|
//SEG80 [58] phi from gfx_init_chunky::@4 to dtvSetCpuBankSegment1 [phi:gfx_init_chunky::@4->dtvSetCpuBankSegment1]
|
2018-04-15 21:32:49 +00:00
|
|
|
dtvSetCpuBankSegment1_from_b4:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG81 [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = (byte) dtvSetCpuBankSegment1::cpuBankIdx#1 [phi:gfx_init_chunky::@4->dtvSetCpuBankSegment1#0] -- register_copy
|
2018-04-15 21:32:49 +00:00
|
|
|
jsr dtvSetCpuBankSegment1
|
2019-03-31 15:10:41 +00:00
|
|
|
jmp b7
|
|
|
|
//SEG82 gfx_init_chunky::@7
|
|
|
|
b7:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG83 [45] (byte) gfx_init_chunky::gfxbCpuBank#2 ← ++ (byte) gfx_init_chunky::gfxbCpuBank#4 -- vbuz1=_inc_vbuz1
|
2018-04-15 21:32:49 +00:00
|
|
|
inc gfxbCpuBank
|
2019-03-31 15:10:41 +00:00
|
|
|
//SEG84 [46] phi from gfx_init_chunky::@7 to gfx_init_chunky::@3 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3]
|
|
|
|
b3_from_b7:
|
|
|
|
//SEG85 [46] phi (byte) gfx_init_chunky::gfxbCpuBank#8 = (byte) gfx_init_chunky::gfxbCpuBank#2 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3#0] -- register_copy
|
|
|
|
//SEG86 [46] phi (byte*) gfx_init_chunky::gfxb#4 = ((byte*))(word/signed word/dword/signed dword) $4000 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3#1] -- pbuz1=pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #<$4000
|
|
|
|
sta gfxb
|
|
|
|
lda #>$4000
|
|
|
|
sta gfxb+1
|
|
|
|
jmp b3
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG87 [46] phi from gfx_init_chunky::@2 to gfx_init_chunky::@3 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3]
|
2018-04-15 21:32:49 +00:00
|
|
|
b3_from_b2:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG88 [46] phi (byte) gfx_init_chunky::gfxbCpuBank#8 = (byte) gfx_init_chunky::gfxbCpuBank#4 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3#0] -- register_copy
|
|
|
|
//SEG89 [46] phi (byte*) gfx_init_chunky::gfxb#4 = (byte*) gfx_init_chunky::gfxb#3 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3#1] -- register_copy
|
2018-04-15 21:32:49 +00:00
|
|
|
jmp b3
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG90 gfx_init_chunky::@3
|
2018-04-15 21:32:49 +00:00
|
|
|
b3:
|
2019-03-29 23:15:53 +00:00
|
|
|
//SEG91 [47] (word~) gfx_init_chunky::$9 ← (word) gfx_init_chunky::x#2 + (byte) gfx_init_chunky::y#6 -- vwuz1=vwuz2_plus_vbuz3
|
2018-04-15 21:32:49 +00:00
|
|
|
lda y
|
|
|
|
clc
|
|
|
|
adc x
|
2019-03-29 23:15:53 +00:00
|
|
|
sta _9
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
adc x+1
|
2019-03-29 23:15:53 +00:00
|
|
|
sta _9+1
|
|
|
|
//SEG92 [48] (byte) gfx_init_chunky::c#0 ← ((byte)) (word~) gfx_init_chunky::$9 -- vbuz1=_byte_vwuz2
|
|
|
|
lda _9
|
2018-04-15 21:32:49 +00:00
|
|
|
sta c
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG93 [49] *((byte*) gfx_init_chunky::gfxb#4) ← (byte) gfx_init_chunky::c#0 -- _deref_pbuz1=vbuz2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda c
|
|
|
|
ldy #0
|
|
|
|
sta (gfxb),y
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG94 [50] (byte*) gfx_init_chunky::gfxb#1 ← ++ (byte*) gfx_init_chunky::gfxb#4 -- pbuz1=_inc_pbuz1
|
2018-04-15 21:32:49 +00:00
|
|
|
inc gfxb
|
|
|
|
bne !+
|
|
|
|
inc gfxb+1
|
|
|
|
!:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG95 [51] (word) gfx_init_chunky::x#1 ← ++ (word) gfx_init_chunky::x#2 -- vwuz1=_inc_vwuz1
|
2018-04-15 21:32:49 +00:00
|
|
|
inc x
|
|
|
|
bne !+
|
|
|
|
inc x+1
|
|
|
|
!:
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG96 [52] if((word) gfx_init_chunky::x#1!=(word/signed word/dword/signed dword) $140) goto gfx_init_chunky::@2 -- vwuz1_neq_vwuc1_then_la1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda x+1
|
|
|
|
cmp #>$140
|
|
|
|
bne b2_from_b3
|
|
|
|
lda x
|
|
|
|
cmp #<$140
|
|
|
|
bne b2_from_b3
|
|
|
|
jmp b5
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG97 gfx_init_chunky::@5
|
2018-04-15 21:32:49 +00:00
|
|
|
b5:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG98 [53] (byte) gfx_init_chunky::y#1 ← ++ (byte) gfx_init_chunky::y#6 -- vbuz1=_inc_vbuz1
|
2018-04-15 21:32:49 +00:00
|
|
|
inc y
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG99 [54] if((byte) gfx_init_chunky::y#1!=(byte/signed byte/word/signed word/dword/signed dword) $33) goto gfx_init_chunky::@1 -- vbuz1_neq_vbuc1_then_la1
|
2019-03-26 22:49:44 +00:00
|
|
|
lda #$33
|
|
|
|
cmp y
|
2018-04-15 21:32:49 +00:00
|
|
|
bne b1_from_b5
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG100 [55] phi from gfx_init_chunky::@5 to gfx_init_chunky::@6 [phi:gfx_init_chunky::@5->gfx_init_chunky::@6]
|
2018-04-15 21:32:49 +00:00
|
|
|
b6_from_b5:
|
|
|
|
jmp b6
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG101 gfx_init_chunky::@6
|
2018-04-15 21:32:49 +00:00
|
|
|
b6:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG102 [56] call dtvSetCpuBankSegment1
|
|
|
|
//SEG103 [58] phi from gfx_init_chunky::@6 to dtvSetCpuBankSegment1 [phi:gfx_init_chunky::@6->dtvSetCpuBankSegment1]
|
2018-04-15 21:32:49 +00:00
|
|
|
dtvSetCpuBankSegment1_from_b6:
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG104 [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = ((byte))(word/signed word/dword/signed dword) $4000/(word/signed word/dword/signed dword) $4000 [phi:gfx_init_chunky::@6->dtvSetCpuBankSegment1#0] -- vbuz1=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #$4000/$4000
|
|
|
|
sta dtvSetCpuBankSegment1.cpuBankIdx
|
|
|
|
jsr dtvSetCpuBankSegment1
|
|
|
|
jmp breturn
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG105 gfx_init_chunky::@return
|
2018-04-15 21:32:49 +00:00
|
|
|
breturn:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG106 [57] return
|
2018-04-15 21:32:49 +00:00
|
|
|
rts
|
|
|
|
}
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG107 dtvSetCpuBankSegment1
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set the memory pointed to by CPU BANK 1 SEGMENT ($4000-$7fff)
|
|
|
|
// This sets which actual memory is addressed when the CPU reads/writes to $4000-$7fff
|
|
|
|
// The actual memory addressed will be $4000*cpuSegmentIdx
|
2019-02-19 19:51:48 +00:00
|
|
|
// dtvSetCpuBankSegment1(byte zeropage(9) cpuBankIdx)
|
2018-04-15 21:32:49 +00:00
|
|
|
dtvSetCpuBankSegment1: {
|
2019-02-17 23:12:29 +00:00
|
|
|
// Move CPU BANK 1 SEGMENT ($4000-$7fff)
|
2018-04-15 21:32:49 +00:00
|
|
|
.label cpuBank = $ff
|
|
|
|
.label cpuBankIdx = 9
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG108 [59] *((const byte*) dtvSetCpuBankSegment1::cpuBank#0) ← (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 -- _deref_pbuc1=vbuz1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda cpuBankIdx
|
|
|
|
sta cpuBank
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG109 asm { .byte$32,$dd lda$ff .byte$32,$00 }
|
2018-04-15 21:32:49 +00:00
|
|
|
.byte $32, $dd
|
|
|
|
lda $ff
|
|
|
|
.byte $32, $00
|
|
|
|
jmp breturn
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG110 dtvSetCpuBankSegment1::@return
|
2018-04-15 21:32:49 +00:00
|
|
|
breturn:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG111 [61] return
|
2018-04-15 21:32:49 +00:00
|
|
|
rts
|
|
|
|
}
|
|
|
|
|
|
|
|
REGISTER UPLIFT POTENTIAL REGISTERS
|
|
|
|
Statement [5] *((const byte*) PROCPORT_DDR#0) ← (const byte) PROCPORT_DDR_MEMORY_MASK#0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [6] *((const byte*) PROCPORT#0) ← (const byte) PROCPORT_RAM_IO#0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [8] *((const byte*) DTV_FEATURE#0) ← (const byte) DTV_FEATURE_ENABLE#0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [9] *((const byte*) DTV_CONTROL#0) ← (const byte) DTV_HIGHCOLOR#0|(const byte) DTV_LINEAR#0|(const byte) DTV_COLORRAM_OFF#0|(const byte) DTV_CHUNKY#0|(const byte) DTV_BADLINE_OFF#0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [10] *((const byte*) VIC_CONTROL#0) ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0|(byte/signed byte/word/signed word/dword/signed dword) 3 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [11] *((const byte*) VIC_CONTROL2#0) ← (const byte) VIC_MCM#0|(const byte) VIC_CSEL#0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [12] *((const byte*) DTV_PLANEB_START_LO#0) ← <(const byte*) CHUNKY#0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [13] *((const byte*) DTV_PLANEB_START_MI#0) ← >(const byte*) CHUNKY#0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [14] *((const byte*) DTV_PLANEB_START_HI#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [15] *((const byte*) DTV_PLANEB_STEP#0) ← (byte/signed byte/word/signed word/dword/signed dword) 8 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [16] *((const byte*) DTV_PLANEB_MODULO_LO#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [17] *((const byte*) DTV_PLANEB_MODULO_HI#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [18] *((const byte*) CIA2_PORT_A_DDR#0) ← (byte/signed byte/word/signed word/dword/signed dword) 3 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
2019-03-08 05:54:45 +00:00
|
|
|
Statement [19] *((const byte*) CIA2_PORT_A#0) ← (byte/signed byte/word/signed word/dword/signed dword) 3^((byte))((word))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
2019-04-15 08:20:55 +00:00
|
|
|
Statement [20] *((const byte*) VIC_MEMORY#0) ← ((byte))((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) $40|>((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) 4 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
2018-04-15 21:32:49 +00:00
|
|
|
Statement asm { ldx#$ff rff: cpxRASTER bnerff stabilize: nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop cpxRASTER beqeat+0 eat: inx cpx#$08 bnestabilize } always clobbers reg byte x
|
2018-04-18 21:19:25 +00:00
|
|
|
Statement [26] *((const byte*) VIC_CONTROL#0) ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0|(byte/signed byte/word/signed word/dword/signed dword) 3 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [27] *((const byte*) BORDERCOL#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
2019-03-31 15:10:41 +00:00
|
|
|
Statement [28] if(*((const byte*) RASTER#0)!=(byte/signed byte/word/signed word/dword/signed dword) $42) goto main::@3 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
2018-04-18 21:19:25 +00:00
|
|
|
Statement [32] (byte~) main::$32 ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0 | (byte~) main::$31 [ main::rst#1 main::$32 ] ( main:2 [ main::rst#1 main::$32 ] ) always clobbers reg byte a
|
2019-03-26 22:49:44 +00:00
|
|
|
Removing always clobbered register reg byte a as potential for zp ZP_BYTE:10 [ main::rst#1 ]
|
2018-04-18 21:19:25 +00:00
|
|
|
Statement [34] (byte~) main::$33 ← (byte) main::rst#1 << (byte/signed byte/word/signed word/dword/signed dword) 4 [ main::rst#1 main::$33 ] ( main:2 [ main::rst#1 main::$33 ] ) always clobbers reg byte a
|
2019-03-08 05:54:45 +00:00
|
|
|
Statement [42] if((byte*) gfx_init_chunky::gfxb#3!=(word/dword/signed dword) $8000) goto gfx_init_chunky::@3 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxb#3 gfx_init_chunky::x#2 gfx_init_chunky::gfxbCpuBank#4 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxb#3 gfx_init_chunky::x#2 gfx_init_chunky::gfxbCpuBank#4 ] ) always clobbers reg byte a
|
2018-04-15 21:32:49 +00:00
|
|
|
Removing always clobbered register reg byte a as potential for zp ZP_BYTE:3 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
Removing always clobbered register reg byte a as potential for zp ZP_BYTE:6 [ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ]
|
2019-03-29 23:15:53 +00:00
|
|
|
Statement [47] (word~) gfx_init_chunky::$9 ← (word) gfx_init_chunky::x#2 + (byte) gfx_init_chunky::y#6 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 gfx_init_chunky::$9 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 gfx_init_chunky::$9 ] ) always clobbers reg byte a
|
|
|
|
Statement [48] (byte) gfx_init_chunky::c#0 ← ((byte)) (word~) gfx_init_chunky::$9 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 gfx_init_chunky::c#0 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 gfx_init_chunky::c#0 ] ) always clobbers reg byte a
|
2018-04-18 21:19:25 +00:00
|
|
|
Statement [49] *((byte*) gfx_init_chunky::gfxb#4) ← (byte) gfx_init_chunky::c#0 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 ] ) always clobbers reg byte y
|
2018-04-15 21:32:49 +00:00
|
|
|
Removing always clobbered register reg byte y as potential for zp ZP_BYTE:3 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
Removing always clobbered register reg byte y as potential for zp ZP_BYTE:6 [ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ]
|
2019-03-08 05:54:45 +00:00
|
|
|
Statement [52] if((word) gfx_init_chunky::x#1!=(word/signed word/dword/signed dword) $140) goto gfx_init_chunky::@2 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxb#1 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#1 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxb#1 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#1 ] ) always clobbers reg byte a
|
2018-04-15 21:32:49 +00:00
|
|
|
Statement asm { .byte$32,$dd lda$ff .byte$32,$00 } always clobbers reg byte a
|
|
|
|
Statement [5] *((const byte*) PROCPORT_DDR#0) ← (const byte) PROCPORT_DDR_MEMORY_MASK#0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [6] *((const byte*) PROCPORT#0) ← (const byte) PROCPORT_RAM_IO#0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [8] *((const byte*) DTV_FEATURE#0) ← (const byte) DTV_FEATURE_ENABLE#0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [9] *((const byte*) DTV_CONTROL#0) ← (const byte) DTV_HIGHCOLOR#0|(const byte) DTV_LINEAR#0|(const byte) DTV_COLORRAM_OFF#0|(const byte) DTV_CHUNKY#0|(const byte) DTV_BADLINE_OFF#0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [10] *((const byte*) VIC_CONTROL#0) ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0|(byte/signed byte/word/signed word/dword/signed dword) 3 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [11] *((const byte*) VIC_CONTROL2#0) ← (const byte) VIC_MCM#0|(const byte) VIC_CSEL#0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [12] *((const byte*) DTV_PLANEB_START_LO#0) ← <(const byte*) CHUNKY#0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [13] *((const byte*) DTV_PLANEB_START_MI#0) ← >(const byte*) CHUNKY#0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [14] *((const byte*) DTV_PLANEB_START_HI#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [15] *((const byte*) DTV_PLANEB_STEP#0) ← (byte/signed byte/word/signed word/dword/signed dword) 8 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [16] *((const byte*) DTV_PLANEB_MODULO_LO#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [17] *((const byte*) DTV_PLANEB_MODULO_HI#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [18] *((const byte*) CIA2_PORT_A_DDR#0) ← (byte/signed byte/word/signed word/dword/signed dword) 3 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
2019-03-08 05:54:45 +00:00
|
|
|
Statement [19] *((const byte*) CIA2_PORT_A#0) ← (byte/signed byte/word/signed word/dword/signed dword) 3^((byte))((word))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
2019-04-15 08:20:55 +00:00
|
|
|
Statement [20] *((const byte*) VIC_MEMORY#0) ← ((byte))((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) $40|>((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) 4 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
2018-04-15 21:32:49 +00:00
|
|
|
Statement asm { ldx#$ff rff: cpxRASTER bnerff stabilize: nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop cpxRASTER beqeat+0 eat: inx cpx#$08 bnestabilize } always clobbers reg byte x
|
2018-04-18 21:19:25 +00:00
|
|
|
Statement [26] *((const byte*) VIC_CONTROL#0) ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0|(byte/signed byte/word/signed word/dword/signed dword) 3 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
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Statement [27] *((const byte*) BORDERCOL#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
2019-03-31 15:10:41 +00:00
|
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Statement [28] if(*((const byte*) RASTER#0)!=(byte/signed byte/word/signed word/dword/signed dword) $42) goto main::@3 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
2018-04-18 21:19:25 +00:00
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|
Statement [31] (byte~) main::$31 ← (byte) main::rst#1 & (byte/signed byte/word/signed word/dword/signed dword) 7 [ main::rst#1 main::$31 ] ( main:2 [ main::rst#1 main::$31 ] ) always clobbers reg byte a
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Statement [32] (byte~) main::$32 ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0 | (byte~) main::$31 [ main::rst#1 main::$32 ] ( main:2 [ main::rst#1 main::$32 ] ) always clobbers reg byte a
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Statement [34] (byte~) main::$33 ← (byte) main::rst#1 << (byte/signed byte/word/signed word/dword/signed dword) 4 [ main::rst#1 main::$33 ] ( main:2 [ main::rst#1 main::$33 ] ) always clobbers reg byte a
|
2019-03-08 05:54:45 +00:00
|
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Statement [42] if((byte*) gfx_init_chunky::gfxb#3!=(word/dword/signed dword) $8000) goto gfx_init_chunky::@3 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxb#3 gfx_init_chunky::x#2 gfx_init_chunky::gfxbCpuBank#4 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxb#3 gfx_init_chunky::x#2 gfx_init_chunky::gfxbCpuBank#4 ] ) always clobbers reg byte a
|
2019-03-29 23:15:53 +00:00
|
|
|
Statement [47] (word~) gfx_init_chunky::$9 ← (word) gfx_init_chunky::x#2 + (byte) gfx_init_chunky::y#6 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 gfx_init_chunky::$9 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 gfx_init_chunky::$9 ] ) always clobbers reg byte a
|
|
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Statement [48] (byte) gfx_init_chunky::c#0 ← ((byte)) (word~) gfx_init_chunky::$9 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 gfx_init_chunky::c#0 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 gfx_init_chunky::c#0 ] ) always clobbers reg byte a
|
2018-04-18 21:19:25 +00:00
|
|
|
Statement [49] *((byte*) gfx_init_chunky::gfxb#4) ← (byte) gfx_init_chunky::c#0 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 ] ) always clobbers reg byte y
|
2019-03-08 05:54:45 +00:00
|
|
|
Statement [52] if((word) gfx_init_chunky::x#1!=(word/signed word/dword/signed dword) $140) goto gfx_init_chunky::@2 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxb#1 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#1 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxb#1 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#1 ] ) always clobbers reg byte a
|
2018-04-15 21:32:49 +00:00
|
|
|
Statement asm { .byte$32,$dd lda$ff .byte$32,$00 } always clobbers reg byte a
|
|
|
|
Potential registers zp ZP_BYTE:2 [ main::j#2 main::j#1 ] : zp ZP_BYTE:2 , reg byte a , reg byte x , reg byte y ,
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|
|
|
Potential registers zp ZP_BYTE:3 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ] : zp ZP_BYTE:3 , reg byte x ,
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|
|
|
Potential registers zp ZP_WORD:4 [ gfx_init_chunky::x#2 gfx_init_chunky::x#1 ] : zp ZP_WORD:4 ,
|
|
|
|
Potential registers zp ZP_BYTE:6 [ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ] : zp ZP_BYTE:6 , reg byte x ,
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|
|
|
Potential registers zp ZP_WORD:7 [ gfx_init_chunky::gfxb#4 gfx_init_chunky::gfxb#3 gfx_init_chunky::gfxb#5 gfx_init_chunky::gfxb#1 ] : zp ZP_WORD:7 ,
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|
Potential registers zp ZP_BYTE:9 [ dtvSetCpuBankSegment1::cpuBankIdx#3 dtvSetCpuBankSegment1::cpuBankIdx#1 ] : zp ZP_BYTE:9 , reg byte a , reg byte x , reg byte y ,
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|
Potential registers zp ZP_BYTE:10 [ main::rst#1 ] : zp ZP_BYTE:10 , reg byte x , reg byte y ,
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|
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|
Potential registers zp ZP_BYTE:11 [ main::$31 ] : zp ZP_BYTE:11 , reg byte a , reg byte x , reg byte y ,
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|
Potential registers zp ZP_BYTE:12 [ main::$32 ] : zp ZP_BYTE:12 , reg byte a , reg byte x , reg byte y ,
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|
Potential registers zp ZP_BYTE:13 [ main::$33 ] : zp ZP_BYTE:13 , reg byte a , reg byte x , reg byte y ,
|
2019-03-29 23:15:53 +00:00
|
|
|
Potential registers zp ZP_WORD:14 [ gfx_init_chunky::$9 ] : zp ZP_WORD:14 ,
|
2018-04-15 21:32:49 +00:00
|
|
|
Potential registers zp ZP_BYTE:16 [ gfx_init_chunky::c#0 ] : zp ZP_BYTE:16 , reg byte a , reg byte x , reg byte y ,
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|
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|
|
REGISTER UPLIFT SCOPES
|
2019-03-29 23:15:53 +00:00
|
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|
Uplift Scope [gfx_init_chunky] 362.64: zp ZP_BYTE:6 [ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ] 297.35: zp ZP_WORD:7 [ gfx_init_chunky::gfxb#4 gfx_init_chunky::gfxb#3 gfx_init_chunky::gfxb#5 gfx_init_chunky::gfxb#1 ] 202: zp ZP_WORD:14 [ gfx_init_chunky::$9 ] 202: zp ZP_BYTE:16 [ gfx_init_chunky::c#0 ] 181.8: zp ZP_WORD:4 [ gfx_init_chunky::x#2 gfx_init_chunky::x#1 ] 25.96: zp ZP_BYTE:3 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
Uplift Scope [main] 202: zp ZP_BYTE:11 [ main::$31 ] 202: zp ZP_BYTE:12 [ main::$32 ] 202: zp ZP_BYTE:13 [ main::$33 ] 57.71: zp ZP_BYTE:10 [ main::rst#1 ] 38.5: zp ZP_BYTE:2 [ main::j#2 main::j#1 ]
|
|
|
|
Uplift Scope [dtvSetCpuBankSegment1] 305: zp ZP_BYTE:9 [ dtvSetCpuBankSegment1::cpuBankIdx#3 dtvSetCpuBankSegment1::cpuBankIdx#1 ]
|
|
|
|
Uplift Scope []
|
|
|
|
|
2019-03-29 23:15:53 +00:00
|
|
|
Uplifting [gfx_init_chunky] best 25250 combination reg byte x [ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ] zp ZP_WORD:7 [ gfx_init_chunky::gfxb#4 gfx_init_chunky::gfxb#3 gfx_init_chunky::gfxb#5 gfx_init_chunky::gfxb#1 ] zp ZP_WORD:14 [ gfx_init_chunky::$9 ] reg byte a [ gfx_init_chunky::c#0 ] zp ZP_WORD:4 [ gfx_init_chunky::x#2 gfx_init_chunky::x#1 ] zp ZP_BYTE:3 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
2018-04-18 21:19:25 +00:00
|
|
|
Uplifting [main] best 22650 combination reg byte a [ main::$31 ] reg byte a [ main::$32 ] reg byte a [ main::$33 ] reg byte x [ main::rst#1 ] zp ZP_BYTE:2 [ main::j#2 main::j#1 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
Limited combination testing to 100 combinations of 768 possible.
|
2018-04-18 21:19:25 +00:00
|
|
|
Uplifting [dtvSetCpuBankSegment1] best 22541 combination reg byte a [ dtvSetCpuBankSegment1::cpuBankIdx#3 dtvSetCpuBankSegment1::cpuBankIdx#1 ]
|
|
|
|
Uplifting [] best 22541 combination
|
2018-04-15 21:32:49 +00:00
|
|
|
Attempting to uplift remaining variables inzp ZP_BYTE:2 [ main::j#2 main::j#1 ]
|
2018-04-18 21:19:25 +00:00
|
|
|
Uplifting [main] best 22421 combination reg byte x [ main::j#2 main::j#1 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
Attempting to uplift remaining variables inzp ZP_BYTE:3 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
2018-04-18 21:19:25 +00:00
|
|
|
Uplifting [gfx_init_chunky] best 22421 combination zp ZP_BYTE:3 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
Allocated (was zp ZP_BYTE:3) zp ZP_BYTE:2 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
Allocated (was zp ZP_WORD:4) zp ZP_WORD:3 [ gfx_init_chunky::x#2 gfx_init_chunky::x#1 ]
|
|
|
|
Allocated (was zp ZP_WORD:7) zp ZP_WORD:5 [ gfx_init_chunky::gfxb#4 gfx_init_chunky::gfxb#3 gfx_init_chunky::gfxb#5 gfx_init_chunky::gfxb#1 ]
|
2019-03-29 23:15:53 +00:00
|
|
|
Allocated (was zp ZP_WORD:14) zp ZP_WORD:7 [ gfx_init_chunky::$9 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
|
|
|
|
ASSEMBLER BEFORE OPTIMIZATION
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG0 File Comments
|
2019-02-17 23:12:29 +00:00
|
|
|
// C64DTV 8bpp charmode stretcher
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG1 Basic Upstart
|
2018-04-15 21:32:49 +00:00
|
|
|
.pc = $801 "Basic"
|
2018-12-25 16:04:50 +00:00
|
|
|
:BasicUpstart(bbegin)
|
2018-04-15 21:32:49 +00:00
|
|
|
.pc = $80d "Program"
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG2 Global Constants & labels
|
2019-02-17 23:12:29 +00:00
|
|
|
// Processor port data direction register
|
2018-04-15 21:32:49 +00:00
|
|
|
.label PROCPORT_DDR = 0
|
2019-02-17 23:12:29 +00:00
|
|
|
// Mask for PROCESSOR_PORT_DDR which allows only memory configuration to be written
|
2018-04-15 21:32:49 +00:00
|
|
|
.const PROCPORT_DDR_MEMORY_MASK = 7
|
2019-02-17 23:12:29 +00:00
|
|
|
// Processor Port Register controlling RAM/ROM configuration and the datasette
|
2018-04-15 21:32:49 +00:00
|
|
|
.label PROCPORT = 1
|
2019-02-17 23:12:29 +00:00
|
|
|
// RAM in $A000, $E000 I/O in $D000
|
2018-04-15 21:32:49 +00:00
|
|
|
.const PROCPORT_RAM_IO = $35
|
|
|
|
.label RASTER = $d012
|
|
|
|
.label BORDERCOL = $d020
|
|
|
|
.label VIC_CONTROL = $d011
|
|
|
|
.const VIC_ECM = $40
|
|
|
|
.const VIC_DEN = $10
|
|
|
|
.const VIC_RSEL = 8
|
|
|
|
.label VIC_CONTROL2 = $d016
|
|
|
|
.const VIC_MCM = $10
|
|
|
|
.const VIC_CSEL = 8
|
|
|
|
.label VIC_MEMORY = $d018
|
2019-02-17 23:12:29 +00:00
|
|
|
// CIA#2 Port A: Serial bus, RS-232, VIC memory bank
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CIA2_PORT_A = $dd00
|
2019-02-17 23:12:29 +00:00
|
|
|
// CIA #2 Port A data direction register.
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CIA2_PORT_A_DDR = $dd02
|
2019-02-17 23:12:29 +00:00
|
|
|
// Feature enables or disables the extra C64 DTV features
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_FEATURE = $d03f
|
|
|
|
.const DTV_FEATURE_ENABLE = 1
|
2019-02-17 23:12:29 +00:00
|
|
|
// Controls the graphics modes of the C64 DTV
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_CONTROL = $d03c
|
|
|
|
.const DTV_LINEAR = 1
|
|
|
|
.const DTV_HIGHCOLOR = 4
|
|
|
|
.const DTV_COLORRAM_OFF = $10
|
|
|
|
.const DTV_BADLINE_OFF = $20
|
|
|
|
.const DTV_CHUNKY = $40
|
2019-02-17 23:12:29 +00:00
|
|
|
// Defines colors for the 16 first colors ($00-$0f)
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_PALETTE = $d200
|
2019-02-17 23:12:29 +00:00
|
|
|
// Linear Graphics Plane B Counter Control
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_PLANEB_START_LO = $d049
|
|
|
|
.label DTV_PLANEB_START_MI = $d04a
|
|
|
|
.label DTV_PLANEB_START_HI = $d04b
|
|
|
|
.label DTV_PLANEB_STEP = $d04c
|
|
|
|
.label DTV_PLANEB_MODULO_LO = $d047
|
|
|
|
.label DTV_PLANEB_MODULO_HI = $d048
|
2019-02-17 23:12:29 +00:00
|
|
|
// Plane with all pixels
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CHUNKY = $8000
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG3 @begin
|
2018-04-15 21:32:49 +00:00
|
|
|
bbegin:
|
2019-03-31 15:10:41 +00:00
|
|
|
//SEG4 [1] phi from @begin to @1 [phi:@begin->@1]
|
|
|
|
b1_from_bbegin:
|
|
|
|
jmp b1
|
|
|
|
//SEG5 @1
|
|
|
|
b1:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG6 [2] call main
|
2018-04-15 21:32:49 +00:00
|
|
|
jsr main
|
2019-03-31 15:10:41 +00:00
|
|
|
//SEG7 [3] phi from @1 to @end [phi:@1->@end]
|
|
|
|
bend_from_b1:
|
2018-04-15 21:32:49 +00:00
|
|
|
jmp bend
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG8 @end
|
2018-04-15 21:32:49 +00:00
|
|
|
bend:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG9 main
|
2018-04-15 21:32:49 +00:00
|
|
|
main: {
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG10 asm { sei }
|
2018-04-15 21:32:49 +00:00
|
|
|
sei
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG11 [5] *((const byte*) PROCPORT_DDR#0) ← (const byte) PROCPORT_DDR_MEMORY_MASK#0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Disable normal interrupt (prevent keyboard reading glitches and allows to hide basic/kernal)
|
|
|
|
// Disable kernal & basic
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #PROCPORT_DDR_MEMORY_MASK
|
|
|
|
sta PROCPORT_DDR
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG12 [6] *((const byte*) PROCPORT#0) ← (const byte) PROCPORT_RAM_IO#0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #PROCPORT_RAM_IO
|
|
|
|
sta PROCPORT
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG13 [7] call gfx_init_chunky
|
|
|
|
//SEG14 [38] phi from main to gfx_init_chunky [phi:main->gfx_init_chunky]
|
2018-04-15 21:32:49 +00:00
|
|
|
gfx_init_chunky_from_main:
|
|
|
|
jsr gfx_init_chunky
|
2019-03-31 15:10:41 +00:00
|
|
|
jmp b6
|
|
|
|
//SEG15 main::@6
|
|
|
|
b6:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG16 [8] *((const byte*) DTV_FEATURE#0) ← (const byte) DTV_FEATURE_ENABLE#0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Enable DTV extended modes
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #DTV_FEATURE_ENABLE
|
|
|
|
sta DTV_FEATURE
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG17 [9] *((const byte*) DTV_CONTROL#0) ← (const byte) DTV_HIGHCOLOR#0|(const byte) DTV_LINEAR#0|(const byte) DTV_COLORRAM_OFF#0|(const byte) DTV_CHUNKY#0|(const byte) DTV_BADLINE_OFF#0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// 8BPP Pixel Cell Mode
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #DTV_HIGHCOLOR|DTV_LINEAR|DTV_COLORRAM_OFF|DTV_CHUNKY|DTV_BADLINE_OFF
|
|
|
|
sta DTV_CONTROL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG18 [10] *((const byte*) VIC_CONTROL#0) ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0|(byte/signed byte/word/signed word/dword/signed dword) 3 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_DEN|VIC_ECM|VIC_RSEL|3
|
|
|
|
sta VIC_CONTROL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG19 [11] *((const byte*) VIC_CONTROL2#0) ← (const byte) VIC_MCM#0|(const byte) VIC_CSEL#0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_MCM|VIC_CSEL
|
|
|
|
sta VIC_CONTROL2
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG20 [12] *((const byte*) DTV_PLANEB_START_LO#0) ← <(const byte*) CHUNKY#0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Plane B: CHUNKY
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #<CHUNKY
|
|
|
|
sta DTV_PLANEB_START_LO
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG21 [13] *((const byte*) DTV_PLANEB_START_MI#0) ← >(const byte*) CHUNKY#0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #>CHUNKY
|
|
|
|
sta DTV_PLANEB_START_MI
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG22 [14] *((const byte*) DTV_PLANEB_START_HI#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta DTV_PLANEB_START_HI
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG23 [15] *((const byte*) DTV_PLANEB_STEP#0) ← (byte/signed byte/word/signed word/dword/signed dword) 8 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #8
|
|
|
|
sta DTV_PLANEB_STEP
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG24 [16] *((const byte*) DTV_PLANEB_MODULO_LO#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta DTV_PLANEB_MODULO_LO
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG25 [17] *((const byte*) DTV_PLANEB_MODULO_HI#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta DTV_PLANEB_MODULO_HI
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG26 [18] *((const byte*) CIA2_PORT_A_DDR#0) ← (byte/signed byte/word/signed word/dword/signed dword) 3 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// VIC Graphics Bank
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #3
|
|
|
|
sta CIA2_PORT_A_DDR
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG27 [19] *((const byte*) CIA2_PORT_A#0) ← (byte/signed byte/word/signed word/dword/signed dword) 3^((byte))((word))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set VIC Bank bits to output - all others to input
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #3^CHUNKY/$4000
|
|
|
|
sta CIA2_PORT_A
|
2019-04-15 08:20:55 +00:00
|
|
|
//SEG28 [20] *((const byte*) VIC_MEMORY#0) ← ((byte))((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) $40|>((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) 4 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set VIC Bank
|
|
|
|
// VIC memory
|
2019-04-15 08:20:55 +00:00
|
|
|
lda #(CHUNKY&$3fff)/$40|(0)/4
|
2018-04-15 21:32:49 +00:00
|
|
|
sta VIC_MEMORY
|
2019-03-31 15:57:54 +00:00
|
|
|
//SEG29 [21] phi from main::@6 to main::@1 [phi:main::@6->main::@1]
|
|
|
|
b1_from_b6:
|
|
|
|
//SEG30 [21] phi (byte) main::j#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:main::@6->main::@1#0] -- vbuxx=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx #0
|
2019-03-31 15:57:54 +00:00
|
|
|
jmp b1
|
2019-02-17 23:12:29 +00:00
|
|
|
// DTV Palette - Grey Tones
|
2019-03-31 15:57:54 +00:00
|
|
|
//SEG31 [21] phi from main::@1 to main::@1 [phi:main::@1->main::@1]
|
|
|
|
b1_from_b1:
|
|
|
|
//SEG32 [21] phi (byte) main::j#2 = (byte) main::j#1 [phi:main::@1->main::@1#0] -- register_copy
|
|
|
|
jmp b1
|
|
|
|
//SEG33 main::@1
|
|
|
|
b1:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG34 [22] *((const byte*) DTV_PALETTE#0 + (byte) main::j#2) ← (byte) main::j#2 -- pbuc1_derefidx_vbuxx=vbuxx
|
2018-04-15 21:32:49 +00:00
|
|
|
txa
|
|
|
|
sta DTV_PALETTE,x
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG35 [23] (byte) main::j#1 ← ++ (byte) main::j#2 -- vbuxx=_inc_vbuxx
|
2018-04-15 21:32:49 +00:00
|
|
|
inx
|
2019-03-31 15:57:54 +00:00
|
|
|
//SEG36 [24] if((byte) main::j#1!=(byte/signed byte/word/signed word/dword/signed dword) $10) goto main::@1 -- vbuxx_neq_vbuc1_then_la1
|
2018-04-15 21:32:49 +00:00
|
|
|
cpx #$10
|
2019-03-31 15:57:54 +00:00
|
|
|
bne b1_from_b1
|
|
|
|
jmp b2
|
|
|
|
//SEG37 main::@2
|
|
|
|
b2:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG38 asm { ldx#$ff rff: cpxRASTER bnerff stabilize: nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop cpxRASTER beqeat+0 eat: inx cpx#$08 bnestabilize }
|
2019-02-17 23:12:29 +00:00
|
|
|
// Stabilize Raster
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx #$ff
|
|
|
|
rff:
|
|
|
|
cpx RASTER
|
|
|
|
bne rff
|
|
|
|
stabilize:
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
cpx RASTER
|
|
|
|
beq eat+0
|
|
|
|
eat:
|
|
|
|
inx
|
|
|
|
cpx #8
|
|
|
|
bne stabilize
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG39 [26] *((const byte*) VIC_CONTROL#0) ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0|(byte/signed byte/word/signed word/dword/signed dword) 3 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_DEN|VIC_ECM|VIC_RSEL|3
|
|
|
|
sta VIC_CONTROL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG40 [27] *((const byte*) BORDERCOL#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta BORDERCOL
|
2019-03-31 15:10:41 +00:00
|
|
|
jmp b3
|
|
|
|
//SEG41 main::@3
|
|
|
|
b3:
|
|
|
|
//SEG42 [28] if(*((const byte*) RASTER#0)!=(byte/signed byte/word/signed word/dword/signed dword) $42) goto main::@3 -- _deref_pbuc1_neq_vbuc2_then_la1
|
2019-03-26 22:49:44 +00:00
|
|
|
lda #$42
|
|
|
|
cmp RASTER
|
2019-03-31 15:10:41 +00:00
|
|
|
bne b3
|
|
|
|
jmp b4
|
|
|
|
//SEG43 main::@4
|
|
|
|
b4:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG44 asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
|
2018-04-15 21:32:49 +00:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2019-03-31 15:10:41 +00:00
|
|
|
jmp b5
|
|
|
|
//SEG45 main::@5
|
|
|
|
b5:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG46 [30] (byte) main::rst#1 ← *((const byte*) RASTER#0) -- vbuxx=_deref_pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx RASTER
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG47 [31] (byte~) main::$31 ← (byte) main::rst#1 & (byte/signed byte/word/signed word/dword/signed dword) 7 -- vbuaa=vbuxx_band_vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
txa
|
|
|
|
and #7
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG48 [32] (byte~) main::$32 ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0 | (byte~) main::$31 -- vbuaa=vbuc1_bor_vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
ora #VIC_DEN|VIC_ECM|VIC_RSEL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG49 [33] *((const byte*) VIC_CONTROL#0) ← (byte~) main::$32 -- _deref_pbuc1=vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
sta VIC_CONTROL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG50 [34] (byte~) main::$33 ← (byte) main::rst#1 << (byte/signed byte/word/signed word/dword/signed dword) 4 -- vbuaa=vbuxx_rol_4
|
2018-04-15 21:32:49 +00:00
|
|
|
txa
|
|
|
|
asl
|
|
|
|
asl
|
|
|
|
asl
|
|
|
|
asl
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG51 [35] *((const byte*) BORDERCOL#0) ← (byte~) main::$33 -- _deref_pbuc1=vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
sta BORDERCOL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG52 asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
|
2018-04-15 21:32:49 +00:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2019-03-31 15:10:41 +00:00
|
|
|
//SEG53 [37] if((byte) main::rst#1!=(byte/word/signed word/dword/signed dword) $f2) goto main::@5 -- vbuxx_neq_vbuc1_then_la1
|
2018-04-15 21:32:49 +00:00
|
|
|
cpx #$f2
|
2019-03-31 15:10:41 +00:00
|
|
|
bne b5
|
2019-03-31 15:57:54 +00:00
|
|
|
jmp b2
|
2018-04-15 21:32:49 +00:00
|
|
|
}
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG54 gfx_init_chunky
|
2019-02-17 23:12:29 +00:00
|
|
|
// Initialize Plane with 8bpp chunky
|
2018-04-15 21:32:49 +00:00
|
|
|
gfx_init_chunky: {
|
2019-03-29 23:15:53 +00:00
|
|
|
.label _9 = 7
|
2018-04-15 21:32:49 +00:00
|
|
|
.label gfxb = 5
|
|
|
|
.label x = 3
|
|
|
|
.label y = 2
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG55 [39] call dtvSetCpuBankSegment1
|
|
|
|
//SEG56 [58] phi from gfx_init_chunky to dtvSetCpuBankSegment1 [phi:gfx_init_chunky->dtvSetCpuBankSegment1]
|
2018-04-15 21:32:49 +00:00
|
|
|
dtvSetCpuBankSegment1_from_gfx_init_chunky:
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG57 [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = ((byte))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000 [phi:gfx_init_chunky->dtvSetCpuBankSegment1#0] -- vbuaa=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #$ff&CHUNKY/$4000
|
|
|
|
jsr dtvSetCpuBankSegment1
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG58 [40] phi from gfx_init_chunky to gfx_init_chunky::@1 [phi:gfx_init_chunky->gfx_init_chunky::@1]
|
2018-04-15 21:32:49 +00:00
|
|
|
b1_from_gfx_init_chunky:
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG59 [40] phi (byte) gfx_init_chunky::gfxbCpuBank#7 = ++((byte))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000 [phi:gfx_init_chunky->gfx_init_chunky::@1#0] -- vbuxx=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx #($ff&CHUNKY/$4000)+1
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG60 [40] phi (byte) gfx_init_chunky::y#6 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:gfx_init_chunky->gfx_init_chunky::@1#1] -- vbuz1=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta y
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG61 [40] phi (byte*) gfx_init_chunky::gfxb#5 = ((byte*))(word/signed word/dword/signed dword) $4000 [phi:gfx_init_chunky->gfx_init_chunky::@1#2] -- pbuz1=pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #<$4000
|
|
|
|
sta gfxb
|
|
|
|
lda #>$4000
|
|
|
|
sta gfxb+1
|
|
|
|
jmp b1
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG62 [40] phi from gfx_init_chunky::@5 to gfx_init_chunky::@1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1]
|
2018-04-15 21:32:49 +00:00
|
|
|
b1_from_b5:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG63 [40] phi (byte) gfx_init_chunky::gfxbCpuBank#7 = (byte) gfx_init_chunky::gfxbCpuBank#8 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#0] -- register_copy
|
|
|
|
//SEG64 [40] phi (byte) gfx_init_chunky::y#6 = (byte) gfx_init_chunky::y#1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#1] -- register_copy
|
|
|
|
//SEG65 [40] phi (byte*) gfx_init_chunky::gfxb#5 = (byte*) gfx_init_chunky::gfxb#1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#2] -- register_copy
|
2018-04-15 21:32:49 +00:00
|
|
|
jmp b1
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG66 gfx_init_chunky::@1
|
2018-04-15 21:32:49 +00:00
|
|
|
b1:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG67 [41] phi from gfx_init_chunky::@1 to gfx_init_chunky::@2 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2]
|
2018-04-15 21:32:49 +00:00
|
|
|
b2_from_b1:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG68 [41] phi (byte) gfx_init_chunky::gfxbCpuBank#4 = (byte) gfx_init_chunky::gfxbCpuBank#7 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#0] -- register_copy
|
|
|
|
//SEG69 [41] phi (word) gfx_init_chunky::x#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#1] -- vwuz1=vbuc1
|
2019-03-18 01:08:32 +00:00
|
|
|
lda #0
|
2018-04-15 21:32:49 +00:00
|
|
|
sta x
|
2019-03-18 01:08:32 +00:00
|
|
|
lda #0
|
2018-04-15 21:32:49 +00:00
|
|
|
sta x+1
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG70 [41] phi (byte*) gfx_init_chunky::gfxb#3 = (byte*) gfx_init_chunky::gfxb#5 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#2] -- register_copy
|
2018-04-15 21:32:49 +00:00
|
|
|
jmp b2
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG71 [41] phi from gfx_init_chunky::@3 to gfx_init_chunky::@2 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2]
|
2018-04-15 21:32:49 +00:00
|
|
|
b2_from_b3:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG72 [41] phi (byte) gfx_init_chunky::gfxbCpuBank#4 = (byte) gfx_init_chunky::gfxbCpuBank#8 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#0] -- register_copy
|
|
|
|
//SEG73 [41] phi (word) gfx_init_chunky::x#2 = (word) gfx_init_chunky::x#1 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#1] -- register_copy
|
|
|
|
//SEG74 [41] phi (byte*) gfx_init_chunky::gfxb#3 = (byte*) gfx_init_chunky::gfxb#1 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#2] -- register_copy
|
2018-04-15 21:32:49 +00:00
|
|
|
jmp b2
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG75 gfx_init_chunky::@2
|
2018-04-15 21:32:49 +00:00
|
|
|
b2:
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG76 [42] if((byte*) gfx_init_chunky::gfxb#3!=(word/dword/signed dword) $8000) goto gfx_init_chunky::@3 -- pbuz1_neq_vwuc1_then_la1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda gfxb+1
|
|
|
|
cmp #>$8000
|
|
|
|
bne b3_from_b2
|
|
|
|
lda gfxb
|
|
|
|
cmp #<$8000
|
|
|
|
bne b3_from_b2
|
|
|
|
jmp b4
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG77 gfx_init_chunky::@4
|
2018-04-15 21:32:49 +00:00
|
|
|
b4:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG78 [43] (byte) dtvSetCpuBankSegment1::cpuBankIdx#1 ← (byte) gfx_init_chunky::gfxbCpuBank#4 -- vbuaa=vbuxx
|
2018-04-15 21:32:49 +00:00
|
|
|
txa
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG79 [44] call dtvSetCpuBankSegment1
|
|
|
|
//SEG80 [58] phi from gfx_init_chunky::@4 to dtvSetCpuBankSegment1 [phi:gfx_init_chunky::@4->dtvSetCpuBankSegment1]
|
2018-04-15 21:32:49 +00:00
|
|
|
dtvSetCpuBankSegment1_from_b4:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG81 [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = (byte) dtvSetCpuBankSegment1::cpuBankIdx#1 [phi:gfx_init_chunky::@4->dtvSetCpuBankSegment1#0] -- register_copy
|
2018-04-15 21:32:49 +00:00
|
|
|
jsr dtvSetCpuBankSegment1
|
2019-03-31 15:10:41 +00:00
|
|
|
jmp b7
|
|
|
|
//SEG82 gfx_init_chunky::@7
|
|
|
|
b7:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG83 [45] (byte) gfx_init_chunky::gfxbCpuBank#2 ← ++ (byte) gfx_init_chunky::gfxbCpuBank#4 -- vbuxx=_inc_vbuxx
|
2018-04-15 21:32:49 +00:00
|
|
|
inx
|
2019-03-31 15:10:41 +00:00
|
|
|
//SEG84 [46] phi from gfx_init_chunky::@7 to gfx_init_chunky::@3 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3]
|
|
|
|
b3_from_b7:
|
|
|
|
//SEG85 [46] phi (byte) gfx_init_chunky::gfxbCpuBank#8 = (byte) gfx_init_chunky::gfxbCpuBank#2 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3#0] -- register_copy
|
|
|
|
//SEG86 [46] phi (byte*) gfx_init_chunky::gfxb#4 = ((byte*))(word/signed word/dword/signed dword) $4000 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3#1] -- pbuz1=pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #<$4000
|
|
|
|
sta gfxb
|
|
|
|
lda #>$4000
|
|
|
|
sta gfxb+1
|
|
|
|
jmp b3
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG87 [46] phi from gfx_init_chunky::@2 to gfx_init_chunky::@3 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3]
|
2018-04-15 21:32:49 +00:00
|
|
|
b3_from_b2:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG88 [46] phi (byte) gfx_init_chunky::gfxbCpuBank#8 = (byte) gfx_init_chunky::gfxbCpuBank#4 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3#0] -- register_copy
|
|
|
|
//SEG89 [46] phi (byte*) gfx_init_chunky::gfxb#4 = (byte*) gfx_init_chunky::gfxb#3 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3#1] -- register_copy
|
2018-04-15 21:32:49 +00:00
|
|
|
jmp b3
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG90 gfx_init_chunky::@3
|
2018-04-15 21:32:49 +00:00
|
|
|
b3:
|
2019-03-29 23:15:53 +00:00
|
|
|
//SEG91 [47] (word~) gfx_init_chunky::$9 ← (word) gfx_init_chunky::x#2 + (byte) gfx_init_chunky::y#6 -- vwuz1=vwuz2_plus_vbuz3
|
2018-04-15 21:32:49 +00:00
|
|
|
lda y
|
|
|
|
clc
|
|
|
|
adc x
|
2019-03-29 23:15:53 +00:00
|
|
|
sta _9
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
adc x+1
|
2019-03-29 23:15:53 +00:00
|
|
|
sta _9+1
|
|
|
|
//SEG92 [48] (byte) gfx_init_chunky::c#0 ← ((byte)) (word~) gfx_init_chunky::$9 -- vbuaa=_byte_vwuz1
|
|
|
|
lda _9
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG93 [49] *((byte*) gfx_init_chunky::gfxb#4) ← (byte) gfx_init_chunky::c#0 -- _deref_pbuz1=vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
ldy #0
|
|
|
|
sta (gfxb),y
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG94 [50] (byte*) gfx_init_chunky::gfxb#1 ← ++ (byte*) gfx_init_chunky::gfxb#4 -- pbuz1=_inc_pbuz1
|
2018-04-15 21:32:49 +00:00
|
|
|
inc gfxb
|
|
|
|
bne !+
|
|
|
|
inc gfxb+1
|
|
|
|
!:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG95 [51] (word) gfx_init_chunky::x#1 ← ++ (word) gfx_init_chunky::x#2 -- vwuz1=_inc_vwuz1
|
2018-04-15 21:32:49 +00:00
|
|
|
inc x
|
|
|
|
bne !+
|
|
|
|
inc x+1
|
|
|
|
!:
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG96 [52] if((word) gfx_init_chunky::x#1!=(word/signed word/dword/signed dword) $140) goto gfx_init_chunky::@2 -- vwuz1_neq_vwuc1_then_la1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda x+1
|
|
|
|
cmp #>$140
|
|
|
|
bne b2_from_b3
|
|
|
|
lda x
|
|
|
|
cmp #<$140
|
|
|
|
bne b2_from_b3
|
|
|
|
jmp b5
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG97 gfx_init_chunky::@5
|
2018-04-15 21:32:49 +00:00
|
|
|
b5:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG98 [53] (byte) gfx_init_chunky::y#1 ← ++ (byte) gfx_init_chunky::y#6 -- vbuz1=_inc_vbuz1
|
2018-04-15 21:32:49 +00:00
|
|
|
inc y
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG99 [54] if((byte) gfx_init_chunky::y#1!=(byte/signed byte/word/signed word/dword/signed dword) $33) goto gfx_init_chunky::@1 -- vbuz1_neq_vbuc1_then_la1
|
2019-03-26 22:49:44 +00:00
|
|
|
lda #$33
|
|
|
|
cmp y
|
2018-04-15 21:32:49 +00:00
|
|
|
bne b1_from_b5
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG100 [55] phi from gfx_init_chunky::@5 to gfx_init_chunky::@6 [phi:gfx_init_chunky::@5->gfx_init_chunky::@6]
|
2018-04-15 21:32:49 +00:00
|
|
|
b6_from_b5:
|
|
|
|
jmp b6
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG101 gfx_init_chunky::@6
|
2018-04-15 21:32:49 +00:00
|
|
|
b6:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG102 [56] call dtvSetCpuBankSegment1
|
|
|
|
//SEG103 [58] phi from gfx_init_chunky::@6 to dtvSetCpuBankSegment1 [phi:gfx_init_chunky::@6->dtvSetCpuBankSegment1]
|
2018-04-15 21:32:49 +00:00
|
|
|
dtvSetCpuBankSegment1_from_b6:
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG104 [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = ((byte))(word/signed word/dword/signed dword) $4000/(word/signed word/dword/signed dword) $4000 [phi:gfx_init_chunky::@6->dtvSetCpuBankSegment1#0] -- vbuaa=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #$4000/$4000
|
|
|
|
jsr dtvSetCpuBankSegment1
|
|
|
|
jmp breturn
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG105 gfx_init_chunky::@return
|
2018-04-15 21:32:49 +00:00
|
|
|
breturn:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG106 [57] return
|
2018-04-15 21:32:49 +00:00
|
|
|
rts
|
|
|
|
}
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG107 dtvSetCpuBankSegment1
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set the memory pointed to by CPU BANK 1 SEGMENT ($4000-$7fff)
|
|
|
|
// This sets which actual memory is addressed when the CPU reads/writes to $4000-$7fff
|
|
|
|
// The actual memory addressed will be $4000*cpuSegmentIdx
|
2019-02-19 19:51:48 +00:00
|
|
|
// dtvSetCpuBankSegment1(byte register(A) cpuBankIdx)
|
2018-04-15 21:32:49 +00:00
|
|
|
dtvSetCpuBankSegment1: {
|
2019-02-17 23:12:29 +00:00
|
|
|
// Move CPU BANK 1 SEGMENT ($4000-$7fff)
|
2018-04-15 21:32:49 +00:00
|
|
|
.label cpuBank = $ff
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG108 [59] *((const byte*) dtvSetCpuBankSegment1::cpuBank#0) ← (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 -- _deref_pbuc1=vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
sta cpuBank
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG109 asm { .byte$32,$dd lda$ff .byte$32,$00 }
|
2018-04-15 21:32:49 +00:00
|
|
|
.byte $32, $dd
|
|
|
|
lda $ff
|
|
|
|
.byte $32, $00
|
|
|
|
jmp breturn
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG110 dtvSetCpuBankSegment1::@return
|
2018-04-15 21:32:49 +00:00
|
|
|
breturn:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG111 [61] return
|
2018-04-15 21:32:49 +00:00
|
|
|
rts
|
|
|
|
}
|
|
|
|
|
|
|
|
ASSEMBLER OPTIMIZATIONS
|
2019-03-31 15:10:41 +00:00
|
|
|
Removing instruction jmp b1
|
2018-04-15 21:32:49 +00:00
|
|
|
Removing instruction jmp bend
|
2019-03-29 23:15:53 +00:00
|
|
|
Removing instruction jmp b6
|
2019-03-31 15:10:41 +00:00
|
|
|
Removing instruction jmp b1
|
2019-03-31 15:57:54 +00:00
|
|
|
Removing instruction jmp b2
|
2019-03-31 15:10:41 +00:00
|
|
|
Removing instruction jmp b3
|
|
|
|
Removing instruction jmp b4
|
|
|
|
Removing instruction jmp b5
|
2018-04-15 21:32:49 +00:00
|
|
|
Removing instruction jmp b1
|
|
|
|
Removing instruction jmp b2
|
|
|
|
Removing instruction jmp b4
|
2019-03-31 15:10:41 +00:00
|
|
|
Removing instruction jmp b7
|
2018-04-15 21:32:49 +00:00
|
|
|
Removing instruction jmp b3
|
|
|
|
Removing instruction jmp b5
|
|
|
|
Removing instruction jmp b6
|
|
|
|
Removing instruction jmp breturn
|
|
|
|
Removing instruction jmp breturn
|
|
|
|
Succesful ASM optimization Pass5NextJumpElimination
|
|
|
|
Removing instruction lda #0
|
2019-03-18 01:08:32 +00:00
|
|
|
Removing instruction lda #0
|
2018-04-15 21:32:49 +00:00
|
|
|
Succesful ASM optimization Pass5UnnecesaryLoadElimination
|
2019-03-31 15:57:54 +00:00
|
|
|
Replacing label b1_from_b1 with b1
|
2018-04-15 21:32:49 +00:00
|
|
|
Replacing label b3_from_b2 with b3
|
|
|
|
Replacing label b3_from_b2 with b3
|
|
|
|
Replacing label b2_from_b3 with b2
|
|
|
|
Replacing label b2_from_b3 with b2
|
|
|
|
Replacing label b1_from_b5 with b1
|
2019-03-31 15:10:41 +00:00
|
|
|
Removing instruction b1_from_bbegin:
|
|
|
|
Removing instruction b1:
|
|
|
|
Removing instruction bend_from_b1:
|
2019-03-31 15:57:54 +00:00
|
|
|
Removing instruction b1_from_b1:
|
2018-04-15 21:32:49 +00:00
|
|
|
Removing instruction b1_from_b5:
|
|
|
|
Removing instruction b2_from_b1:
|
|
|
|
Removing instruction b2_from_b3:
|
|
|
|
Removing instruction b3_from_b2:
|
|
|
|
Removing instruction b6_from_b5:
|
|
|
|
Removing instruction dtvSetCpuBankSegment1_from_b6:
|
|
|
|
Succesful ASM optimization Pass5RedundantLabelElimination
|
|
|
|
Removing instruction bend:
|
|
|
|
Removing instruction gfx_init_chunky_from_main:
|
2019-03-31 15:10:41 +00:00
|
|
|
Removing instruction b6:
|
2019-03-31 15:57:54 +00:00
|
|
|
Removing instruction b1_from_b6:
|
2019-03-31 15:10:41 +00:00
|
|
|
Removing instruction b4:
|
2018-04-15 21:32:49 +00:00
|
|
|
Removing instruction dtvSetCpuBankSegment1_from_gfx_init_chunky:
|
|
|
|
Removing instruction b1_from_gfx_init_chunky:
|
|
|
|
Removing instruction b4:
|
|
|
|
Removing instruction dtvSetCpuBankSegment1_from_b4:
|
2019-03-31 15:10:41 +00:00
|
|
|
Removing instruction b7:
|
|
|
|
Removing instruction b3_from_b7:
|
2018-04-15 21:32:49 +00:00
|
|
|
Removing instruction b5:
|
|
|
|
Removing instruction b6:
|
|
|
|
Removing instruction breturn:
|
|
|
|
Removing instruction breturn:
|
|
|
|
Succesful ASM optimization Pass5UnusedLabelElimination
|
2018-12-25 16:04:50 +00:00
|
|
|
Updating BasicUpstart to call main directly
|
|
|
|
Removing instruction jsr main
|
|
|
|
Succesful ASM optimization Pass5SkipBegin
|
2019-03-31 15:57:54 +00:00
|
|
|
Removing instruction jmp b1
|
2018-04-15 21:32:49 +00:00
|
|
|
Removing instruction jmp b1
|
|
|
|
Removing instruction jmp b2
|
|
|
|
Removing instruction jmp b3
|
|
|
|
Succesful ASM optimization Pass5NextJumpElimination
|
2018-12-25 16:04:50 +00:00
|
|
|
Removing instruction bbegin:
|
|
|
|
Succesful ASM optimization Pass5UnusedLabelElimination
|
2018-04-15 21:32:49 +00:00
|
|
|
|
|
|
|
FINAL SYMBOL TABLE
|
2019-03-31 15:10:41 +00:00
|
|
|
(label) @1
|
2018-04-15 21:32:49 +00:00
|
|
|
(label) @begin
|
|
|
|
(label) @end
|
|
|
|
(byte*) BORDERCOL
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) BORDERCOL#0 BORDERCOL = ((byte*))(word/dword/signed dword) $d020
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte*) CHUNKY
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) CHUNKY#0 CHUNKY = ((byte*))(word/dword/signed dword) $8000
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte*) CIA2_PORT_A
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) CIA2_PORT_A#0 CIA2_PORT_A = ((byte*))(word/dword/signed dword) $dd00
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte*) CIA2_PORT_A_DDR
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) CIA2_PORT_A_DDR#0 CIA2_PORT_A_DDR = ((byte*))(word/dword/signed dword) $dd02
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) DTV_BADLINE_OFF
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte) DTV_BADLINE_OFF#0 DTV_BADLINE_OFF = (byte/signed byte/word/signed word/dword/signed dword) $20
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) DTV_CHUNKY
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte) DTV_CHUNKY#0 DTV_CHUNKY = (byte/signed byte/word/signed word/dword/signed dword) $40
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) DTV_COLORRAM_OFF
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte) DTV_COLORRAM_OFF#0 DTV_COLORRAM_OFF = (byte/signed byte/word/signed word/dword/signed dword) $10
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte*) DTV_CONTROL
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) DTV_CONTROL#0 DTV_CONTROL = ((byte*))(word/dword/signed dword) $d03c
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte*) DTV_FEATURE
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) DTV_FEATURE#0 DTV_FEATURE = ((byte*))(word/dword/signed dword) $d03f
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) DTV_FEATURE_ENABLE
|
|
|
|
(const byte) DTV_FEATURE_ENABLE#0 DTV_FEATURE_ENABLE = (byte/signed byte/word/signed word/dword/signed dword) 1
|
|
|
|
(byte) DTV_HIGHCOLOR
|
|
|
|
(const byte) DTV_HIGHCOLOR#0 DTV_HIGHCOLOR = (byte/signed byte/word/signed word/dword/signed dword) 4
|
|
|
|
(byte) DTV_LINEAR
|
|
|
|
(const byte) DTV_LINEAR#0 DTV_LINEAR = (byte/signed byte/word/signed word/dword/signed dword) 1
|
|
|
|
(byte*) DTV_PALETTE
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) DTV_PALETTE#0 DTV_PALETTE = ((byte*))(word/dword/signed dword) $d200
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte*) DTV_PLANEB_MODULO_HI
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) DTV_PLANEB_MODULO_HI#0 DTV_PLANEB_MODULO_HI = ((byte*))(word/dword/signed dword) $d048
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte*) DTV_PLANEB_MODULO_LO
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) DTV_PLANEB_MODULO_LO#0 DTV_PLANEB_MODULO_LO = ((byte*))(word/dword/signed dword) $d047
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte*) DTV_PLANEB_START_HI
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) DTV_PLANEB_START_HI#0 DTV_PLANEB_START_HI = ((byte*))(word/dword/signed dword) $d04b
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte*) DTV_PLANEB_START_LO
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) DTV_PLANEB_START_LO#0 DTV_PLANEB_START_LO = ((byte*))(word/dword/signed dword) $d049
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte*) DTV_PLANEB_START_MI
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) DTV_PLANEB_START_MI#0 DTV_PLANEB_START_MI = ((byte*))(word/dword/signed dword) $d04a
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte*) DTV_PLANEB_STEP
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) DTV_PLANEB_STEP#0 DTV_PLANEB_STEP = ((byte*))(word/dword/signed dword) $d04c
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte*) PROCPORT
|
|
|
|
(const byte*) PROCPORT#0 PROCPORT = ((byte*))(byte/signed byte/word/signed word/dword/signed dword) 1
|
|
|
|
(byte*) PROCPORT_DDR
|
|
|
|
(const byte*) PROCPORT_DDR#0 PROCPORT_DDR = ((byte*))(byte/signed byte/word/signed word/dword/signed dword) 0
|
|
|
|
(byte) PROCPORT_DDR_MEMORY_MASK
|
|
|
|
(const byte) PROCPORT_DDR_MEMORY_MASK#0 PROCPORT_DDR_MEMORY_MASK = (byte/signed byte/word/signed word/dword/signed dword) 7
|
|
|
|
(byte) PROCPORT_RAM_IO
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte) PROCPORT_RAM_IO#0 PROCPORT_RAM_IO = (byte/signed byte/word/signed word/dword/signed dword) $35
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte*) RASTER
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) RASTER#0 RASTER = ((byte*))(word/dword/signed dword) $d012
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte*) VIC_CONTROL
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) VIC_CONTROL#0 VIC_CONTROL = ((byte*))(word/dword/signed dword) $d011
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte*) VIC_CONTROL2
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) VIC_CONTROL2#0 VIC_CONTROL2 = ((byte*))(word/dword/signed dword) $d016
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) VIC_CSEL
|
|
|
|
(const byte) VIC_CSEL#0 VIC_CSEL = (byte/signed byte/word/signed word/dword/signed dword) 8
|
|
|
|
(byte) VIC_DEN
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte) VIC_DEN#0 VIC_DEN = (byte/signed byte/word/signed word/dword/signed dword) $10
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) VIC_ECM
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte) VIC_ECM#0 VIC_ECM = (byte/signed byte/word/signed word/dword/signed dword) $40
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) VIC_MCM
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte) VIC_MCM#0 VIC_MCM = (byte/signed byte/word/signed word/dword/signed dword) $10
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte*) VIC_MEMORY
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) VIC_MEMORY#0 VIC_MEMORY = ((byte*))(word/dword/signed dword) $d018
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) VIC_RSEL
|
|
|
|
(const byte) VIC_RSEL#0 VIC_RSEL = (byte/signed byte/word/signed word/dword/signed dword) 8
|
|
|
|
(void()) dtvSetCpuBankSegment1((byte) dtvSetCpuBankSegment1::cpuBankIdx)
|
|
|
|
(label) dtvSetCpuBankSegment1::@return
|
|
|
|
(byte*) dtvSetCpuBankSegment1::cpuBank
|
2019-03-08 05:54:45 +00:00
|
|
|
(const byte*) dtvSetCpuBankSegment1::cpuBank#0 cpuBank = ((byte*))(byte/word/signed word/dword/signed dword) $ff
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#1 reg byte a 202.0
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#3 reg byte a 103.0
|
|
|
|
(void()) gfx_init_chunky()
|
2019-03-29 23:15:53 +00:00
|
|
|
(word~) gfx_init_chunky::$9 $9 zp ZP_WORD:7 202.0
|
2018-04-15 21:32:49 +00:00
|
|
|
(label) gfx_init_chunky::@1
|
|
|
|
(label) gfx_init_chunky::@2
|
|
|
|
(label) gfx_init_chunky::@3
|
|
|
|
(label) gfx_init_chunky::@4
|
|
|
|
(label) gfx_init_chunky::@5
|
|
|
|
(label) gfx_init_chunky::@6
|
2019-03-31 15:10:41 +00:00
|
|
|
(label) gfx_init_chunky::@7
|
2018-04-15 21:32:49 +00:00
|
|
|
(label) gfx_init_chunky::@return
|
|
|
|
(byte) gfx_init_chunky::c
|
|
|
|
(byte) gfx_init_chunky::c#0 reg byte a 202.0
|
|
|
|
(byte*) gfx_init_chunky::gfxb
|
|
|
|
(byte*) gfx_init_chunky::gfxb#1 gfxb zp ZP_WORD:5 42.599999999999994
|
|
|
|
(byte*) gfx_init_chunky::gfxb#3 gfxb zp ZP_WORD:5 157.0
|
|
|
|
(byte*) gfx_init_chunky::gfxb#4 gfxb zp ZP_WORD:5 75.75
|
|
|
|
(byte*) gfx_init_chunky::gfxb#5 gfxb zp ZP_WORD:5 22.0
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#2 reg byte x 202.0
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#4 reg byte x 103.75
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#7 reg byte x 22.0
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#8 reg byte x 34.888888888888886
|
|
|
|
(word) gfx_init_chunky::x
|
|
|
|
(word) gfx_init_chunky::x#1 x zp ZP_WORD:3 151.5
|
|
|
|
(word) gfx_init_chunky::x#2 x zp ZP_WORD:3 30.299999999999997
|
|
|
|
(byte) gfx_init_chunky::y
|
|
|
|
(byte) gfx_init_chunky::y#1 y zp ZP_BYTE:2 16.5
|
|
|
|
(byte) gfx_init_chunky::y#6 y zp ZP_BYTE:2 9.461538461538462
|
|
|
|
(void()) main()
|
|
|
|
(byte~) main::$31 reg byte a 202.0
|
|
|
|
(byte~) main::$32 reg byte a 202.0
|
|
|
|
(byte~) main::$33 reg byte a 202.0
|
2019-03-31 15:10:41 +00:00
|
|
|
(label) main::@1
|
2019-03-29 23:15:53 +00:00
|
|
|
(label) main::@2
|
2019-03-31 15:10:41 +00:00
|
|
|
(label) main::@3
|
|
|
|
(label) main::@4
|
|
|
|
(label) main::@5
|
2019-03-29 23:15:53 +00:00
|
|
|
(label) main::@6
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) main::j
|
|
|
|
(byte) main::j#1 reg byte x 16.5
|
|
|
|
(byte) main::j#2 reg byte x 22.0
|
|
|
|
(byte) main::rst
|
|
|
|
(byte) main::rst#1 reg byte x 57.714285714285715
|
|
|
|
|
|
|
|
reg byte x [ main::j#2 main::j#1 ]
|
|
|
|
zp ZP_BYTE:2 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
zp ZP_WORD:3 [ gfx_init_chunky::x#2 gfx_init_chunky::x#1 ]
|
|
|
|
reg byte x [ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ]
|
|
|
|
zp ZP_WORD:5 [ gfx_init_chunky::gfxb#4 gfx_init_chunky::gfxb#3 gfx_init_chunky::gfxb#5 gfx_init_chunky::gfxb#1 ]
|
|
|
|
reg byte a [ dtvSetCpuBankSegment1::cpuBankIdx#3 dtvSetCpuBankSegment1::cpuBankIdx#1 ]
|
|
|
|
reg byte x [ main::rst#1 ]
|
|
|
|
reg byte a [ main::$31 ]
|
|
|
|
reg byte a [ main::$32 ]
|
|
|
|
reg byte a [ main::$33 ]
|
2019-03-29 23:15:53 +00:00
|
|
|
zp ZP_WORD:7 [ gfx_init_chunky::$9 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
reg byte a [ gfx_init_chunky::c#0 ]
|
|
|
|
|
|
|
|
|
|
|
|
FINAL ASSEMBLER
|
2018-12-25 16:04:50 +00:00
|
|
|
Score: 19882
|
2018-04-15 21:32:49 +00:00
|
|
|
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG0 File Comments
|
2019-02-17 23:12:29 +00:00
|
|
|
// C64DTV 8bpp charmode stretcher
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG1 Basic Upstart
|
2018-04-15 21:32:49 +00:00
|
|
|
.pc = $801 "Basic"
|
|
|
|
:BasicUpstart(main)
|
|
|
|
.pc = $80d "Program"
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG2 Global Constants & labels
|
2019-02-17 23:12:29 +00:00
|
|
|
// Processor port data direction register
|
2018-04-15 21:32:49 +00:00
|
|
|
.label PROCPORT_DDR = 0
|
2019-02-17 23:12:29 +00:00
|
|
|
// Mask for PROCESSOR_PORT_DDR which allows only memory configuration to be written
|
2018-04-15 21:32:49 +00:00
|
|
|
.const PROCPORT_DDR_MEMORY_MASK = 7
|
2019-02-17 23:12:29 +00:00
|
|
|
// Processor Port Register controlling RAM/ROM configuration and the datasette
|
2018-04-15 21:32:49 +00:00
|
|
|
.label PROCPORT = 1
|
2019-02-17 23:12:29 +00:00
|
|
|
// RAM in $A000, $E000 I/O in $D000
|
2018-04-15 21:32:49 +00:00
|
|
|
.const PROCPORT_RAM_IO = $35
|
|
|
|
.label RASTER = $d012
|
|
|
|
.label BORDERCOL = $d020
|
|
|
|
.label VIC_CONTROL = $d011
|
|
|
|
.const VIC_ECM = $40
|
|
|
|
.const VIC_DEN = $10
|
|
|
|
.const VIC_RSEL = 8
|
|
|
|
.label VIC_CONTROL2 = $d016
|
|
|
|
.const VIC_MCM = $10
|
|
|
|
.const VIC_CSEL = 8
|
|
|
|
.label VIC_MEMORY = $d018
|
2019-02-17 23:12:29 +00:00
|
|
|
// CIA#2 Port A: Serial bus, RS-232, VIC memory bank
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CIA2_PORT_A = $dd00
|
2019-02-17 23:12:29 +00:00
|
|
|
// CIA #2 Port A data direction register.
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CIA2_PORT_A_DDR = $dd02
|
2019-02-17 23:12:29 +00:00
|
|
|
// Feature enables or disables the extra C64 DTV features
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_FEATURE = $d03f
|
|
|
|
.const DTV_FEATURE_ENABLE = 1
|
2019-02-17 23:12:29 +00:00
|
|
|
// Controls the graphics modes of the C64 DTV
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_CONTROL = $d03c
|
|
|
|
.const DTV_LINEAR = 1
|
|
|
|
.const DTV_HIGHCOLOR = 4
|
|
|
|
.const DTV_COLORRAM_OFF = $10
|
|
|
|
.const DTV_BADLINE_OFF = $20
|
|
|
|
.const DTV_CHUNKY = $40
|
2019-02-17 23:12:29 +00:00
|
|
|
// Defines colors for the 16 first colors ($00-$0f)
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_PALETTE = $d200
|
2019-02-17 23:12:29 +00:00
|
|
|
// Linear Graphics Plane B Counter Control
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_PLANEB_START_LO = $d049
|
|
|
|
.label DTV_PLANEB_START_MI = $d04a
|
|
|
|
.label DTV_PLANEB_START_HI = $d04b
|
|
|
|
.label DTV_PLANEB_STEP = $d04c
|
|
|
|
.label DTV_PLANEB_MODULO_LO = $d047
|
|
|
|
.label DTV_PLANEB_MODULO_HI = $d048
|
2019-02-17 23:12:29 +00:00
|
|
|
// Plane with all pixels
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CHUNKY = $8000
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG3 @begin
|
2019-03-31 15:10:41 +00:00
|
|
|
//SEG4 [1] phi from @begin to @1 [phi:@begin->@1]
|
|
|
|
//SEG5 @1
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG6 [2] call main
|
2019-03-31 15:10:41 +00:00
|
|
|
//SEG7 [3] phi from @1 to @end [phi:@1->@end]
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG8 @end
|
|
|
|
//SEG9 main
|
2018-04-15 21:32:49 +00:00
|
|
|
main: {
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG10 asm { sei }
|
2018-04-15 21:32:49 +00:00
|
|
|
sei
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG11 [5] *((const byte*) PROCPORT_DDR#0) ← (const byte) PROCPORT_DDR_MEMORY_MASK#0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Disable normal interrupt (prevent keyboard reading glitches and allows to hide basic/kernal)
|
|
|
|
// Disable kernal & basic
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #PROCPORT_DDR_MEMORY_MASK
|
|
|
|
sta PROCPORT_DDR
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG12 [6] *((const byte*) PROCPORT#0) ← (const byte) PROCPORT_RAM_IO#0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #PROCPORT_RAM_IO
|
|
|
|
sta PROCPORT
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG13 [7] call gfx_init_chunky
|
|
|
|
//SEG14 [38] phi from main to gfx_init_chunky [phi:main->gfx_init_chunky]
|
2018-04-15 21:32:49 +00:00
|
|
|
jsr gfx_init_chunky
|
2019-03-31 15:10:41 +00:00
|
|
|
//SEG15 main::@6
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG16 [8] *((const byte*) DTV_FEATURE#0) ← (const byte) DTV_FEATURE_ENABLE#0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Enable DTV extended modes
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #DTV_FEATURE_ENABLE
|
|
|
|
sta DTV_FEATURE
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG17 [9] *((const byte*) DTV_CONTROL#0) ← (const byte) DTV_HIGHCOLOR#0|(const byte) DTV_LINEAR#0|(const byte) DTV_COLORRAM_OFF#0|(const byte) DTV_CHUNKY#0|(const byte) DTV_BADLINE_OFF#0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// 8BPP Pixel Cell Mode
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #DTV_HIGHCOLOR|DTV_LINEAR|DTV_COLORRAM_OFF|DTV_CHUNKY|DTV_BADLINE_OFF
|
|
|
|
sta DTV_CONTROL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG18 [10] *((const byte*) VIC_CONTROL#0) ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0|(byte/signed byte/word/signed word/dword/signed dword) 3 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_DEN|VIC_ECM|VIC_RSEL|3
|
|
|
|
sta VIC_CONTROL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG19 [11] *((const byte*) VIC_CONTROL2#0) ← (const byte) VIC_MCM#0|(const byte) VIC_CSEL#0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_MCM|VIC_CSEL
|
|
|
|
sta VIC_CONTROL2
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG20 [12] *((const byte*) DTV_PLANEB_START_LO#0) ← <(const byte*) CHUNKY#0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Plane B: CHUNKY
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #<CHUNKY
|
|
|
|
sta DTV_PLANEB_START_LO
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG21 [13] *((const byte*) DTV_PLANEB_START_MI#0) ← >(const byte*) CHUNKY#0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #>CHUNKY
|
|
|
|
sta DTV_PLANEB_START_MI
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG22 [14] *((const byte*) DTV_PLANEB_START_HI#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta DTV_PLANEB_START_HI
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG23 [15] *((const byte*) DTV_PLANEB_STEP#0) ← (byte/signed byte/word/signed word/dword/signed dword) 8 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #8
|
|
|
|
sta DTV_PLANEB_STEP
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG24 [16] *((const byte*) DTV_PLANEB_MODULO_LO#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta DTV_PLANEB_MODULO_LO
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG25 [17] *((const byte*) DTV_PLANEB_MODULO_HI#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
sta DTV_PLANEB_MODULO_HI
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG26 [18] *((const byte*) CIA2_PORT_A_DDR#0) ← (byte/signed byte/word/signed word/dword/signed dword) 3 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// VIC Graphics Bank
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #3
|
|
|
|
sta CIA2_PORT_A_DDR
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG27 [19] *((const byte*) CIA2_PORT_A#0) ← (byte/signed byte/word/signed word/dword/signed dword) 3^((byte))((word))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set VIC Bank bits to output - all others to input
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #3^CHUNKY/$4000
|
|
|
|
sta CIA2_PORT_A
|
2019-04-15 08:20:55 +00:00
|
|
|
//SEG28 [20] *((const byte*) VIC_MEMORY#0) ← ((byte))((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) $40|>((word))(const byte*) CHUNKY#0&(word/signed word/dword/signed dword) $3fff/(byte/signed byte/word/signed word/dword/signed dword) 4 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set VIC Bank
|
|
|
|
// VIC memory
|
2019-04-15 08:20:55 +00:00
|
|
|
lda #(CHUNKY&$3fff)/$40|(0)/4
|
2018-04-15 21:32:49 +00:00
|
|
|
sta VIC_MEMORY
|
2019-03-31 15:57:54 +00:00
|
|
|
//SEG29 [21] phi from main::@6 to main::@1 [phi:main::@6->main::@1]
|
|
|
|
//SEG30 [21] phi (byte) main::j#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:main::@6->main::@1#0] -- vbuxx=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx #0
|
2019-02-17 23:12:29 +00:00
|
|
|
// DTV Palette - Grey Tones
|
2019-03-31 15:57:54 +00:00
|
|
|
//SEG31 [21] phi from main::@1 to main::@1 [phi:main::@1->main::@1]
|
|
|
|
//SEG32 [21] phi (byte) main::j#2 = (byte) main::j#1 [phi:main::@1->main::@1#0] -- register_copy
|
|
|
|
//SEG33 main::@1
|
|
|
|
b1:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG34 [22] *((const byte*) DTV_PALETTE#0 + (byte) main::j#2) ← (byte) main::j#2 -- pbuc1_derefidx_vbuxx=vbuxx
|
2018-04-15 21:32:49 +00:00
|
|
|
txa
|
|
|
|
sta DTV_PALETTE,x
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG35 [23] (byte) main::j#1 ← ++ (byte) main::j#2 -- vbuxx=_inc_vbuxx
|
2018-04-15 21:32:49 +00:00
|
|
|
inx
|
2019-03-31 15:57:54 +00:00
|
|
|
//SEG36 [24] if((byte) main::j#1!=(byte/signed byte/word/signed word/dword/signed dword) $10) goto main::@1 -- vbuxx_neq_vbuc1_then_la1
|
2018-04-15 21:32:49 +00:00
|
|
|
cpx #$10
|
2019-03-31 15:57:54 +00:00
|
|
|
bne b1
|
|
|
|
//SEG37 main::@2
|
|
|
|
b2:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG38 asm { ldx#$ff rff: cpxRASTER bnerff stabilize: nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop cpxRASTER beqeat+0 eat: inx cpx#$08 bnestabilize }
|
2019-02-17 23:12:29 +00:00
|
|
|
// Stabilize Raster
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx #$ff
|
|
|
|
rff:
|
|
|
|
cpx RASTER
|
|
|
|
bne rff
|
|
|
|
stabilize:
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
cpx RASTER
|
|
|
|
beq eat+0
|
|
|
|
eat:
|
|
|
|
inx
|
|
|
|
cpx #8
|
|
|
|
bne stabilize
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG39 [26] *((const byte*) VIC_CONTROL#0) ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0|(byte/signed byte/word/signed word/dword/signed dword) 3 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_DEN|VIC_ECM|VIC_RSEL|3
|
|
|
|
sta VIC_CONTROL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG40 [27] *((const byte*) BORDERCOL#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta BORDERCOL
|
2019-03-31 15:10:41 +00:00
|
|
|
//SEG41 main::@3
|
|
|
|
b3:
|
|
|
|
//SEG42 [28] if(*((const byte*) RASTER#0)!=(byte/signed byte/word/signed word/dword/signed dword) $42) goto main::@3 -- _deref_pbuc1_neq_vbuc2_then_la1
|
2019-03-26 22:49:44 +00:00
|
|
|
lda #$42
|
|
|
|
cmp RASTER
|
2019-03-31 15:10:41 +00:00
|
|
|
bne b3
|
|
|
|
//SEG43 main::@4
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG44 asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
|
2018-04-15 21:32:49 +00:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2019-03-31 15:10:41 +00:00
|
|
|
//SEG45 main::@5
|
|
|
|
b5:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG46 [30] (byte) main::rst#1 ← *((const byte*) RASTER#0) -- vbuxx=_deref_pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx RASTER
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG47 [31] (byte~) main::$31 ← (byte) main::rst#1 & (byte/signed byte/word/signed word/dword/signed dword) 7 -- vbuaa=vbuxx_band_vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
txa
|
|
|
|
and #7
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG48 [32] (byte~) main::$32 ← (const byte) VIC_DEN#0|(const byte) VIC_ECM#0|(const byte) VIC_RSEL#0 | (byte~) main::$31 -- vbuaa=vbuc1_bor_vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
ora #VIC_DEN|VIC_ECM|VIC_RSEL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG49 [33] *((const byte*) VIC_CONTROL#0) ← (byte~) main::$32 -- _deref_pbuc1=vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
sta VIC_CONTROL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG50 [34] (byte~) main::$33 ← (byte) main::rst#1 << (byte/signed byte/word/signed word/dword/signed dword) 4 -- vbuaa=vbuxx_rol_4
|
2018-04-15 21:32:49 +00:00
|
|
|
txa
|
|
|
|
asl
|
|
|
|
asl
|
|
|
|
asl
|
|
|
|
asl
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG51 [35] *((const byte*) BORDERCOL#0) ← (byte~) main::$33 -- _deref_pbuc1=vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
sta BORDERCOL
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG52 asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
|
2018-04-15 21:32:49 +00:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2019-03-31 15:10:41 +00:00
|
|
|
//SEG53 [37] if((byte) main::rst#1!=(byte/word/signed word/dword/signed dword) $f2) goto main::@5 -- vbuxx_neq_vbuc1_then_la1
|
2018-04-15 21:32:49 +00:00
|
|
|
cpx #$f2
|
2019-03-31 15:10:41 +00:00
|
|
|
bne b5
|
2019-03-31 15:57:54 +00:00
|
|
|
jmp b2
|
2018-04-15 21:32:49 +00:00
|
|
|
}
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG54 gfx_init_chunky
|
2019-02-17 23:12:29 +00:00
|
|
|
// Initialize Plane with 8bpp chunky
|
2018-04-15 21:32:49 +00:00
|
|
|
gfx_init_chunky: {
|
2019-03-29 23:15:53 +00:00
|
|
|
.label _9 = 7
|
2018-04-15 21:32:49 +00:00
|
|
|
.label gfxb = 5
|
|
|
|
.label x = 3
|
|
|
|
.label y = 2
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG55 [39] call dtvSetCpuBankSegment1
|
|
|
|
//SEG56 [58] phi from gfx_init_chunky to dtvSetCpuBankSegment1 [phi:gfx_init_chunky->dtvSetCpuBankSegment1]
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG57 [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = ((byte))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000 [phi:gfx_init_chunky->dtvSetCpuBankSegment1#0] -- vbuaa=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #$ff&CHUNKY/$4000
|
|
|
|
jsr dtvSetCpuBankSegment1
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG58 [40] phi from gfx_init_chunky to gfx_init_chunky::@1 [phi:gfx_init_chunky->gfx_init_chunky::@1]
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG59 [40] phi (byte) gfx_init_chunky::gfxbCpuBank#7 = ++((byte))(const byte*) CHUNKY#0/(word/signed word/dword/signed dword) $4000 [phi:gfx_init_chunky->gfx_init_chunky::@1#0] -- vbuxx=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx #($ff&CHUNKY/$4000)+1
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG60 [40] phi (byte) gfx_init_chunky::y#6 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:gfx_init_chunky->gfx_init_chunky::@1#1] -- vbuz1=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta y
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG61 [40] phi (byte*) gfx_init_chunky::gfxb#5 = ((byte*))(word/signed word/dword/signed dword) $4000 [phi:gfx_init_chunky->gfx_init_chunky::@1#2] -- pbuz1=pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #<$4000
|
|
|
|
sta gfxb
|
|
|
|
lda #>$4000
|
|
|
|
sta gfxb+1
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG62 [40] phi from gfx_init_chunky::@5 to gfx_init_chunky::@1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1]
|
|
|
|
//SEG63 [40] phi (byte) gfx_init_chunky::gfxbCpuBank#7 = (byte) gfx_init_chunky::gfxbCpuBank#8 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#0] -- register_copy
|
|
|
|
//SEG64 [40] phi (byte) gfx_init_chunky::y#6 = (byte) gfx_init_chunky::y#1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#1] -- register_copy
|
|
|
|
//SEG65 [40] phi (byte*) gfx_init_chunky::gfxb#5 = (byte*) gfx_init_chunky::gfxb#1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#2] -- register_copy
|
|
|
|
//SEG66 gfx_init_chunky::@1
|
2018-04-15 21:32:49 +00:00
|
|
|
b1:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG67 [41] phi from gfx_init_chunky::@1 to gfx_init_chunky::@2 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2]
|
|
|
|
//SEG68 [41] phi (byte) gfx_init_chunky::gfxbCpuBank#4 = (byte) gfx_init_chunky::gfxbCpuBank#7 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#0] -- register_copy
|
|
|
|
//SEG69 [41] phi (word) gfx_init_chunky::x#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#1] -- vwuz1=vbuc1
|
2019-03-18 01:08:32 +00:00
|
|
|
lda #0
|
2018-04-15 21:32:49 +00:00
|
|
|
sta x
|
|
|
|
sta x+1
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG70 [41] phi (byte*) gfx_init_chunky::gfxb#3 = (byte*) gfx_init_chunky::gfxb#5 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#2] -- register_copy
|
|
|
|
//SEG71 [41] phi from gfx_init_chunky::@3 to gfx_init_chunky::@2 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2]
|
|
|
|
//SEG72 [41] phi (byte) gfx_init_chunky::gfxbCpuBank#4 = (byte) gfx_init_chunky::gfxbCpuBank#8 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#0] -- register_copy
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//SEG73 [41] phi (word) gfx_init_chunky::x#2 = (word) gfx_init_chunky::x#1 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#1] -- register_copy
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//SEG74 [41] phi (byte*) gfx_init_chunky::gfxb#3 = (byte*) gfx_init_chunky::gfxb#1 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#2] -- register_copy
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//SEG75 gfx_init_chunky::@2
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2018-04-15 21:32:49 +00:00
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b2:
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2019-03-08 05:54:45 +00:00
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//SEG76 [42] if((byte*) gfx_init_chunky::gfxb#3!=(word/dword/signed dword) $8000) goto gfx_init_chunky::@3 -- pbuz1_neq_vwuc1_then_la1
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2018-04-15 21:32:49 +00:00
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|
|
lda gfxb+1
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|
cmp #>$8000
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bne b3
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|
lda gfxb
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|
cmp #<$8000
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|
bne b3
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2019-02-17 10:03:55 +00:00
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//SEG77 gfx_init_chunky::@4
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//SEG78 [43] (byte) dtvSetCpuBankSegment1::cpuBankIdx#1 ← (byte) gfx_init_chunky::gfxbCpuBank#4 -- vbuaa=vbuxx
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2018-04-15 21:32:49 +00:00
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|
|
txa
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2019-02-17 10:03:55 +00:00
|
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//SEG79 [44] call dtvSetCpuBankSegment1
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//SEG80 [58] phi from gfx_init_chunky::@4 to dtvSetCpuBankSegment1 [phi:gfx_init_chunky::@4->dtvSetCpuBankSegment1]
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//SEG81 [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = (byte) dtvSetCpuBankSegment1::cpuBankIdx#1 [phi:gfx_init_chunky::@4->dtvSetCpuBankSegment1#0] -- register_copy
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2018-04-15 21:32:49 +00:00
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|
|
jsr dtvSetCpuBankSegment1
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2019-03-31 15:10:41 +00:00
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//SEG82 gfx_init_chunky::@7
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2019-02-17 10:03:55 +00:00
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//SEG83 [45] (byte) gfx_init_chunky::gfxbCpuBank#2 ← ++ (byte) gfx_init_chunky::gfxbCpuBank#4 -- vbuxx=_inc_vbuxx
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2018-04-15 21:32:49 +00:00
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|
inx
|
2019-03-31 15:10:41 +00:00
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//SEG84 [46] phi from gfx_init_chunky::@7 to gfx_init_chunky::@3 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3]
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//SEG85 [46] phi (byte) gfx_init_chunky::gfxbCpuBank#8 = (byte) gfx_init_chunky::gfxbCpuBank#2 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3#0] -- register_copy
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//SEG86 [46] phi (byte*) gfx_init_chunky::gfxb#4 = ((byte*))(word/signed word/dword/signed dword) $4000 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3#1] -- pbuz1=pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #<$4000
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|
|
|
sta gfxb
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|
|
|
lda #>$4000
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|
|
|
sta gfxb+1
|
2019-02-17 10:03:55 +00:00
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|
|
//SEG87 [46] phi from gfx_init_chunky::@2 to gfx_init_chunky::@3 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3]
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//SEG88 [46] phi (byte) gfx_init_chunky::gfxbCpuBank#8 = (byte) gfx_init_chunky::gfxbCpuBank#4 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3#0] -- register_copy
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//SEG89 [46] phi (byte*) gfx_init_chunky::gfxb#4 = (byte*) gfx_init_chunky::gfxb#3 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3#1] -- register_copy
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|
|
//SEG90 gfx_init_chunky::@3
|
2018-04-15 21:32:49 +00:00
|
|
|
b3:
|
2019-03-29 23:15:53 +00:00
|
|
|
//SEG91 [47] (word~) gfx_init_chunky::$9 ← (word) gfx_init_chunky::x#2 + (byte) gfx_init_chunky::y#6 -- vwuz1=vwuz2_plus_vbuz3
|
2018-04-15 21:32:49 +00:00
|
|
|
lda y
|
|
|
|
clc
|
|
|
|
adc x
|
2019-03-29 23:15:53 +00:00
|
|
|
sta _9
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
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|
|
|
adc x+1
|
2019-03-29 23:15:53 +00:00
|
|
|
sta _9+1
|
|
|
|
//SEG92 [48] (byte) gfx_init_chunky::c#0 ← ((byte)) (word~) gfx_init_chunky::$9 -- vbuaa=_byte_vwuz1
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|
|
|
lda _9
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG93 [49] *((byte*) gfx_init_chunky::gfxb#4) ← (byte) gfx_init_chunky::c#0 -- _deref_pbuz1=vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
ldy #0
|
|
|
|
sta (gfxb),y
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG94 [50] (byte*) gfx_init_chunky::gfxb#1 ← ++ (byte*) gfx_init_chunky::gfxb#4 -- pbuz1=_inc_pbuz1
|
2018-04-15 21:32:49 +00:00
|
|
|
inc gfxb
|
|
|
|
bne !+
|
|
|
|
inc gfxb+1
|
|
|
|
!:
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG95 [51] (word) gfx_init_chunky::x#1 ← ++ (word) gfx_init_chunky::x#2 -- vwuz1=_inc_vwuz1
|
2018-04-15 21:32:49 +00:00
|
|
|
inc x
|
|
|
|
bne !+
|
|
|
|
inc x+1
|
|
|
|
!:
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG96 [52] if((word) gfx_init_chunky::x#1!=(word/signed word/dword/signed dword) $140) goto gfx_init_chunky::@2 -- vwuz1_neq_vwuc1_then_la1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda x+1
|
|
|
|
cmp #>$140
|
|
|
|
bne b2
|
|
|
|
lda x
|
|
|
|
cmp #<$140
|
|
|
|
bne b2
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG97 gfx_init_chunky::@5
|
|
|
|
//SEG98 [53] (byte) gfx_init_chunky::y#1 ← ++ (byte) gfx_init_chunky::y#6 -- vbuz1=_inc_vbuz1
|
2018-04-15 21:32:49 +00:00
|
|
|
inc y
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG99 [54] if((byte) gfx_init_chunky::y#1!=(byte/signed byte/word/signed word/dword/signed dword) $33) goto gfx_init_chunky::@1 -- vbuz1_neq_vbuc1_then_la1
|
2019-03-26 22:49:44 +00:00
|
|
|
lda #$33
|
|
|
|
cmp y
|
2018-04-15 21:32:49 +00:00
|
|
|
bne b1
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG100 [55] phi from gfx_init_chunky::@5 to gfx_init_chunky::@6 [phi:gfx_init_chunky::@5->gfx_init_chunky::@6]
|
|
|
|
//SEG101 gfx_init_chunky::@6
|
|
|
|
//SEG102 [56] call dtvSetCpuBankSegment1
|
|
|
|
//SEG103 [58] phi from gfx_init_chunky::@6 to dtvSetCpuBankSegment1 [phi:gfx_init_chunky::@6->dtvSetCpuBankSegment1]
|
2019-03-08 05:54:45 +00:00
|
|
|
//SEG104 [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = ((byte))(word/signed word/dword/signed dword) $4000/(word/signed word/dword/signed dword) $4000 [phi:gfx_init_chunky::@6->dtvSetCpuBankSegment1#0] -- vbuaa=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #$4000/$4000
|
|
|
|
jsr dtvSetCpuBankSegment1
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG105 gfx_init_chunky::@return
|
|
|
|
//SEG106 [57] return
|
2018-04-15 21:32:49 +00:00
|
|
|
rts
|
|
|
|
}
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG107 dtvSetCpuBankSegment1
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set the memory pointed to by CPU BANK 1 SEGMENT ($4000-$7fff)
|
|
|
|
// This sets which actual memory is addressed when the CPU reads/writes to $4000-$7fff
|
|
|
|
// The actual memory addressed will be $4000*cpuSegmentIdx
|
2019-02-19 19:51:48 +00:00
|
|
|
// dtvSetCpuBankSegment1(byte register(A) cpuBankIdx)
|
2018-04-15 21:32:49 +00:00
|
|
|
dtvSetCpuBankSegment1: {
|
2019-02-17 23:12:29 +00:00
|
|
|
// Move CPU BANK 1 SEGMENT ($4000-$7fff)
|
2018-04-15 21:32:49 +00:00
|
|
|
.label cpuBank = $ff
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG108 [59] *((const byte*) dtvSetCpuBankSegment1::cpuBank#0) ← (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 -- _deref_pbuc1=vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
sta cpuBank
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG109 asm { .byte$32,$dd lda$ff .byte$32,$00 }
|
2018-04-15 21:32:49 +00:00
|
|
|
.byte $32, $dd
|
|
|
|
lda $ff
|
|
|
|
.byte $32, $00
|
2019-02-17 10:03:55 +00:00
|
|
|
//SEG110 dtvSetCpuBankSegment1::@return
|
|
|
|
//SEG111 [61] return
|
2018-04-15 21:32:49 +00:00
|
|
|
rts
|
|
|
|
}
|
|
|
|
|