2018-08-10 10:46:44 +00:00
|
|
|
@begin: scope:[] from
|
2018-11-11 20:51:36 +00:00
|
|
|
[0] phi()
|
2019-03-31 15:10:41 +00:00
|
|
|
to:@1
|
|
|
|
@1: scope:[] from @begin
|
2018-11-11 20:51:36 +00:00
|
|
|
[1] phi()
|
|
|
|
[2] call main
|
2018-08-10 10:46:44 +00:00
|
|
|
to:@end
|
2019-03-31 15:10:41 +00:00
|
|
|
@end: scope:[] from @1
|
2018-11-11 20:51:36 +00:00
|
|
|
[3] phi()
|
2019-03-31 15:10:41 +00:00
|
|
|
main: scope:[main] from @1
|
2018-08-10 10:46:44 +00:00
|
|
|
asm { sei }
|
2018-11-11 20:51:36 +00:00
|
|
|
[5] *((const byte*) PROCPORT_DDR#0) ← (const byte) PROCPORT_DDR_MEMORY_MASK#0
|
|
|
|
[6] *((const byte*) PROCPORT#0) ← (const byte) PROCPORT_RAM_IO#0
|
|
|
|
[7] *((const byte*) CIA1_INTERRUPT#0) ← (const byte) CIA_INTERRUPT_CLEAR#0
|
2019-03-08 05:54:45 +00:00
|
|
|
[8] *((const byte*) VIC_CONTROL#0) ← *((const byte*) VIC_CONTROL#0) | (byte/word/signed word/dword/signed dword) $80
|
2018-11-11 20:51:36 +00:00
|
|
|
[9] *((const byte*) RASTER#0) ← (byte/signed byte/word/signed word/dword/signed dword) 0
|
|
|
|
[10] *((const byte*) IRQ_ENABLE#0) ← (const byte) IRQ_RASTER#0
|
|
|
|
[11] *((const void()**) HARDWARE_IRQ#0) ← &interrupt(HARDWARE_ALL)(void()) irq()
|
2018-08-10 10:46:44 +00:00
|
|
|
asm { cli }
|
2019-03-31 15:10:41 +00:00
|
|
|
to:main::@1
|
|
|
|
main::@1: scope:[main] from main main::@1
|
2018-11-11 20:51:36 +00:00
|
|
|
[13] *((const byte*) FGCOL#0) ← ++ *((const byte*) FGCOL#0)
|
2019-03-31 15:10:41 +00:00
|
|
|
to:main::@1
|
2018-08-10 10:46:44 +00:00
|
|
|
irq: scope:[irq] from
|
2018-11-11 20:51:36 +00:00
|
|
|
[14] *((const byte*) BGCOL#0) ← (const byte) WHITE#0
|
|
|
|
[15] *((const byte*) BGCOL#0) ← (const byte) BLACK#0
|
|
|
|
[16] *((const byte*) IRQ_STATUS#0) ← (const byte) IRQ_RASTER#0
|
2018-08-10 10:46:44 +00:00
|
|
|
to:irq::@return
|
|
|
|
irq::@return: scope:[irq] from irq
|
2018-11-11 20:51:36 +00:00
|
|
|
[17] return
|
2018-08-10 10:46:44 +00:00
|
|
|
to:@return
|