2019-03-22 18:50:20 +00:00
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Identified constant variable (byte*) dtvSetCpuBankSegment1::cpuBank
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Identified constant variable (byte*) DTV_BLITTER_ALU
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2019-06-12 23:15:34 +00:00
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Inlined call (byte~) vicSelectGfxBank::$0 ← call toDd00 (byte*) vicSelectGfxBank::gfx
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2019-05-30 20:29:04 +00:00
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Culled Empty Block (label) @1
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Culled Empty Block (label) @2
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Culled Empty Block (label) @3
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2019-11-03 16:05:55 +00:00
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Culled Empty Block (label) @4
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Culled Empty Block (label) @5
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2019-05-30 20:29:04 +00:00
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Culled Empty Block (label) main::@2
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Culled Empty Block (label) main::@15
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Culled Empty Block (label) main::@5
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Culled Empty Block (label) main::@16
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Culled Empty Block (label) main::@7
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Culled Empty Block (label) main::@9
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Culled Empty Block (label) main::@10
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Culled Empty Block (label) main::@11
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Culled Empty Block (label) main::@13
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Culled Empty Block (label) main::@14
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Culled Empty Block (label) @6
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2018-04-15 21:32:49 +00:00
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2018-08-22 22:24:32 +00:00
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CONTROL FLOW GRAPH SSA
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2018-04-15 21:32:49 +00:00
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@begin: scope:[] from
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2019-11-03 16:05:55 +00:00
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to:@7
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2019-09-18 21:00:30 +00:00
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(void()) dtvSetCpuBankSegment1((byte) dtvSetCpuBankSegment1::cpuBankIdx)
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2018-04-15 21:32:49 +00:00
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dtvSetCpuBankSegment1: scope:[dtvSetCpuBankSegment1] from gfx_init_chunky gfx_init_chunky::@4 gfx_init_chunky::@6
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(byte) dtvSetCpuBankSegment1::cpuBankIdx#3 ← phi( gfx_init_chunky/(byte) dtvSetCpuBankSegment1::cpuBankIdx#0 gfx_init_chunky::@4/(byte) dtvSetCpuBankSegment1::cpuBankIdx#1 gfx_init_chunky::@6/(byte) dtvSetCpuBankSegment1::cpuBankIdx#2 )
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2019-11-03 16:05:55 +00:00
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*((const byte*) dtvSetCpuBankSegment1::cpuBank) ← (byte) dtvSetCpuBankSegment1::cpuBankIdx#3
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2018-04-15 21:32:49 +00:00
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asm { .byte$32,$dd lda$ff .byte$32,$00 }
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to:dtvSetCpuBankSegment1::@return
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dtvSetCpuBankSegment1::@return: scope:[dtvSetCpuBankSegment1] from dtvSetCpuBankSegment1
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return
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to:@return
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2019-09-18 21:00:30 +00:00
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(void()) main()
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2018-12-24 01:27:12 +00:00
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main: scope:[main] from @7
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2018-04-15 21:32:49 +00:00
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asm { sei }
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2019-11-03 16:05:55 +00:00
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*((const byte*) PROCPORT_DDR) ← (const byte) PROCPORT_DDR_MEMORY_MASK
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*((const byte*) PROCPORT) ← (const byte) PROCPORT_RAM_IO
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2018-05-01 20:50:59 +00:00
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call gfx_init_chunky
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2018-04-15 21:32:49 +00:00
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to:main::@17
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main::@17: scope:[main] from main
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2019-11-03 16:05:55 +00:00
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*((const byte*) DTV_FEATURE) ← (const byte) DTV_FEATURE_ENABLE
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*((const byte*) DTV_CONTROL) ← (const byte) DTV_HIGHCOLOR|(const byte) DTV_LINEAR|(const byte) DTV_COLORRAM_OFF|(const byte) DTV_CHUNKY|(const byte) DTV_BADLINE_OFF
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*((const byte*) VIC_CONTROL) ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(number) 3
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*((const byte*) VIC_CONTROL2) ← (const byte) VIC_MCM|(const byte) VIC_CSEL
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*((const byte*) DTV_PLANEB_START_LO) ← <(const byte*) CHUNKY
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*((const byte*) DTV_PLANEB_START_MI) ← >(const byte*) CHUNKY
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*((const byte*) DTV_PLANEB_START_HI) ← (number) 0
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*((const byte*) DTV_PLANEB_STEP) ← (number) 8
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*((const byte*) DTV_PLANEB_MODULO_LO) ← (number) 0
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*((const byte*) DTV_PLANEB_MODULO_HI) ← (number) 0
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*((const byte*) CIA2_PORT_A_DDR) ← (number) 3
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(word~) main::$1 ← ((word)) (const byte*) CHUNKY
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(number~) main::$2 ← (word~) main::$1 / (number) $4000
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(byte~) main::$3 ← ((byte)) (number~) main::$2
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(number~) main::$4 ← (number) 3 ^ (byte~) main::$3
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*((const byte*) CIA2_PORT_A) ← (number~) main::$4
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(word~) main::$5 ← ((word)) (const byte*) CHUNKY
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(number~) main::$6 ← (word~) main::$5 & (number) $3fff
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(number~) main::$7 ← (number~) main::$6 / (number) $40
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(byte~) main::$8 ← ((byte)) (number~) main::$7
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(word~) main::$9 ← ((word)) (const byte*) CHUNKY
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(number~) main::$10 ← (word~) main::$9 & (number) $3fff
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(number~) main::$11 ← > (number~) main::$10
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(number~) main::$12 ← (number~) main::$11 / (number) 4
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(number~) main::$13 ← (byte~) main::$8 | (number~) main::$12
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*((const byte*) VIC_MEMORY) ← (number~) main::$13
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2019-06-02 22:44:46 +00:00
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(byte) main::j#0 ← (byte) 0
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2019-03-31 15:57:54 +00:00
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to:main::@1
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main::@1: scope:[main] from main::@1 main::@17
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(byte) main::j#2 ← phi( main::@1/(byte) main::j#1 main::@17/(byte) main::j#0 )
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2019-11-03 16:05:55 +00:00
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*((const byte*) DTV_PALETTE + (byte) main::j#2) ← (byte) main::j#2
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2019-03-08 05:54:45 +00:00
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(byte) main::j#1 ← (byte) main::j#2 + rangenext(0,$f)
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2019-11-03 16:05:55 +00:00
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(bool~) main::$14 ← (byte) main::j#1 != rangelast(0,$f)
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if((bool~) main::$14) goto main::@1
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2019-03-31 15:57:54 +00:00
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to:main::@3
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main::@3: scope:[main] from main::@1 main::@12
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if(true) goto main::@4
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2018-04-15 21:32:49 +00:00
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to:main::@return
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2019-03-31 15:57:54 +00:00
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main::@4: scope:[main] from main::@3
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2018-04-15 21:32:49 +00:00
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asm { ldx#$ff rff: cpxRASTER bnerff stabilize: nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop cpxRASTER beqeat+0 eat: inx cpx#$08 bnestabilize }
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2019-11-03 16:05:55 +00:00
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*((const byte*) VIC_CONTROL) ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(number) 3
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*((const byte*) BORDERCOL) ← (number) 0
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2019-05-30 20:29:04 +00:00
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(byte) main::rst#0 ← (number) $42
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2019-03-31 15:57:54 +00:00
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to:main::@6
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2019-05-30 20:29:04 +00:00
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main::@6: scope:[main] from main::@4 main::@6
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(byte) main::rst#2 ← phi( main::@4/(byte) main::rst#0 main::@6/(byte) main::rst#2 )
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2019-11-03 16:05:55 +00:00
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(bool~) main::$15 ← *((const byte*) RASTER) != (byte) main::rst#2
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if((bool~) main::$15) goto main::@6
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2018-04-15 21:32:49 +00:00
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to:main::@8
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2019-03-31 15:57:54 +00:00
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main::@8: scope:[main] from main::@6
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2019-03-29 23:15:53 +00:00
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asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
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2019-03-31 15:57:54 +00:00
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to:main::@12
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main::@12: scope:[main] from main::@12 main::@8
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2019-11-03 16:05:55 +00:00
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(byte) main::rst#1 ← *((const byte*) RASTER)
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(number~) main::$16 ← (byte) main::rst#1 & (number) 7
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(number~) main::$17 ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL | (number~) main::$16
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*((const byte*) VIC_CONTROL) ← (number~) main::$17
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(number~) main::$18 ← (byte) main::rst#1 * (number) $10
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*((const byte*) BORDERCOL) ← (number~) main::$18
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2018-04-15 21:32:49 +00:00
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asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
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2019-11-03 16:05:55 +00:00
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(bool~) main::$19 ← (byte) main::rst#1 != (number) $f2
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if((bool~) main::$19) goto main::@12
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2019-03-31 15:57:54 +00:00
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to:main::@3
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main::@return: scope:[main] from main::@3
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2018-04-15 21:32:49 +00:00
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return
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to:@return
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2019-09-18 21:00:30 +00:00
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(void()) gfx_init_chunky()
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2018-04-15 21:32:49 +00:00
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gfx_init_chunky: scope:[gfx_init_chunky] from main
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2019-11-03 16:05:55 +00:00
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(byte~) gfx_init_chunky::$0 ← ((byte)) (const byte*) CHUNKY/(number) $4000
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(byte) gfx_init_chunky::gfxbCpuBank#0 ← (byte~) gfx_init_chunky::$0
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2018-04-15 21:32:49 +00:00
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(byte) dtvSetCpuBankSegment1::cpuBankIdx#0 ← (byte) gfx_init_chunky::gfxbCpuBank#0
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2018-05-01 20:50:59 +00:00
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call dtvSetCpuBankSegment1
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2018-04-15 21:32:49 +00:00
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to:gfx_init_chunky::@7
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gfx_init_chunky::@7: scope:[gfx_init_chunky] from gfx_init_chunky
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(byte) gfx_init_chunky::gfxbCpuBank#3 ← phi( gfx_init_chunky/(byte) gfx_init_chunky::gfxbCpuBank#0 )
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(byte) gfx_init_chunky::gfxbCpuBank#1 ← ++ (byte) gfx_init_chunky::gfxbCpuBank#3
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2019-05-30 20:29:04 +00:00
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(byte*) gfx_init_chunky::gfxb#0 ← ((byte*)) (number) $4000
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2019-06-02 22:44:46 +00:00
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(byte) gfx_init_chunky::y#0 ← (byte) 0
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2018-04-15 21:32:49 +00:00
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to:gfx_init_chunky::@1
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gfx_init_chunky::@1: scope:[gfx_init_chunky] from gfx_init_chunky::@5 gfx_init_chunky::@7
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(byte) gfx_init_chunky::gfxbCpuBank#7 ← phi( gfx_init_chunky::@5/(byte) gfx_init_chunky::gfxbCpuBank#9 gfx_init_chunky::@7/(byte) gfx_init_chunky::gfxbCpuBank#1 )
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(byte) gfx_init_chunky::y#6 ← phi( gfx_init_chunky::@5/(byte) gfx_init_chunky::y#1 gfx_init_chunky::@7/(byte) gfx_init_chunky::y#0 )
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(byte*) gfx_init_chunky::gfxb#5 ← phi( gfx_init_chunky::@5/(byte*) gfx_init_chunky::gfxb#6 gfx_init_chunky::@7/(byte*) gfx_init_chunky::gfxb#0 )
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2019-06-02 22:44:46 +00:00
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(word) gfx_init_chunky::x#0 ← (word) 0
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2018-04-15 21:32:49 +00:00
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to:gfx_init_chunky::@2
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gfx_init_chunky::@2: scope:[gfx_init_chunky] from gfx_init_chunky::@1 gfx_init_chunky::@3
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(byte) gfx_init_chunky::gfxbCpuBank#6 ← phi( gfx_init_chunky::@1/(byte) gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::@3/(byte) gfx_init_chunky::gfxbCpuBank#8 )
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(byte) gfx_init_chunky::y#4 ← phi( gfx_init_chunky::@1/(byte) gfx_init_chunky::y#6 gfx_init_chunky::@3/(byte) gfx_init_chunky::y#2 )
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(word) gfx_init_chunky::x#3 ← phi( gfx_init_chunky::@1/(word) gfx_init_chunky::x#0 gfx_init_chunky::@3/(word) gfx_init_chunky::x#1 )
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(byte*) gfx_init_chunky::gfxb#3 ← phi( gfx_init_chunky::@1/(byte*) gfx_init_chunky::gfxb#5 gfx_init_chunky::@3/(byte*) gfx_init_chunky::gfxb#1 )
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2019-11-03 16:05:55 +00:00
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(bool~) gfx_init_chunky::$4 ← (byte*) gfx_init_chunky::gfxb#3 == (number) $8000
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(bool~) gfx_init_chunky::$5 ← ! (bool~) gfx_init_chunky::$4
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if((bool~) gfx_init_chunky::$5) goto gfx_init_chunky::@3
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2018-04-15 21:32:49 +00:00
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to:gfx_init_chunky::@4
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gfx_init_chunky::@3: scope:[gfx_init_chunky] from gfx_init_chunky::@2 gfx_init_chunky::@8
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(byte) gfx_init_chunky::gfxbCpuBank#8 ← phi( gfx_init_chunky::@2/(byte) gfx_init_chunky::gfxbCpuBank#6 gfx_init_chunky::@8/(byte) gfx_init_chunky::gfxbCpuBank#2 )
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(byte*) gfx_init_chunky::gfxb#4 ← phi( gfx_init_chunky::@2/(byte*) gfx_init_chunky::gfxb#3 gfx_init_chunky::@8/(byte*) gfx_init_chunky::gfxb#2 )
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(byte) gfx_init_chunky::y#2 ← phi( gfx_init_chunky::@2/(byte) gfx_init_chunky::y#4 gfx_init_chunky::@8/(byte) gfx_init_chunky::y#5 )
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(word) gfx_init_chunky::x#2 ← phi( gfx_init_chunky::@2/(word) gfx_init_chunky::x#3 gfx_init_chunky::@8/(word) gfx_init_chunky::x#4 )
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2019-11-03 16:05:55 +00:00
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(word~) gfx_init_chunky::$7 ← (word) gfx_init_chunky::x#2 + (byte) gfx_init_chunky::y#2
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(byte~) gfx_init_chunky::$8 ← ((byte)) (word~) gfx_init_chunky::$7
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(byte) gfx_init_chunky::c#0 ← (byte~) gfx_init_chunky::$8
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2018-04-15 21:32:49 +00:00
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*((byte*) gfx_init_chunky::gfxb#4) ← (byte) gfx_init_chunky::c#0
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(byte*) gfx_init_chunky::gfxb#1 ← ++ (byte*) gfx_init_chunky::gfxb#4
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2019-03-08 05:54:45 +00:00
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(word) gfx_init_chunky::x#1 ← (word) gfx_init_chunky::x#2 + rangenext(0,$13f)
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2019-11-03 16:05:55 +00:00
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(bool~) gfx_init_chunky::$9 ← (word) gfx_init_chunky::x#1 != rangelast(0,$13f)
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if((bool~) gfx_init_chunky::$9) goto gfx_init_chunky::@2
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2018-04-15 21:32:49 +00:00
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to:gfx_init_chunky::@5
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gfx_init_chunky::@4: scope:[gfx_init_chunky] from gfx_init_chunky::@2
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(byte) gfx_init_chunky::y#7 ← phi( gfx_init_chunky::@2/(byte) gfx_init_chunky::y#4 )
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(word) gfx_init_chunky::x#5 ← phi( gfx_init_chunky::@2/(word) gfx_init_chunky::x#3 )
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(byte) gfx_init_chunky::gfxbCpuBank#4 ← phi( gfx_init_chunky::@2/(byte) gfx_init_chunky::gfxbCpuBank#6 )
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(byte) dtvSetCpuBankSegment1::cpuBankIdx#1 ← (byte) gfx_init_chunky::gfxbCpuBank#4
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2018-05-01 20:50:59 +00:00
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call dtvSetCpuBankSegment1
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2018-04-15 21:32:49 +00:00
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to:gfx_init_chunky::@8
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gfx_init_chunky::@8: scope:[gfx_init_chunky] from gfx_init_chunky::@4
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(byte) gfx_init_chunky::y#5 ← phi( gfx_init_chunky::@4/(byte) gfx_init_chunky::y#7 )
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(word) gfx_init_chunky::x#4 ← phi( gfx_init_chunky::@4/(word) gfx_init_chunky::x#5 )
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(byte) gfx_init_chunky::gfxbCpuBank#5 ← phi( gfx_init_chunky::@4/(byte) gfx_init_chunky::gfxbCpuBank#4 )
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(byte) gfx_init_chunky::gfxbCpuBank#2 ← ++ (byte) gfx_init_chunky::gfxbCpuBank#5
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2019-05-30 20:29:04 +00:00
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(byte*) gfx_init_chunky::gfxb#2 ← ((byte*)) (number) $4000
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2018-04-15 21:32:49 +00:00
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to:gfx_init_chunky::@3
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gfx_init_chunky::@5: scope:[gfx_init_chunky] from gfx_init_chunky::@3
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(byte) gfx_init_chunky::gfxbCpuBank#9 ← phi( gfx_init_chunky::@3/(byte) gfx_init_chunky::gfxbCpuBank#8 )
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(byte*) gfx_init_chunky::gfxb#6 ← phi( gfx_init_chunky::@3/(byte*) gfx_init_chunky::gfxb#1 )
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(byte) gfx_init_chunky::y#3 ← phi( gfx_init_chunky::@3/(byte) gfx_init_chunky::y#2 )
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2019-03-08 05:54:45 +00:00
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(byte) gfx_init_chunky::y#1 ← (byte) gfx_init_chunky::y#3 + rangenext(0,$32)
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2019-11-03 16:05:55 +00:00
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(bool~) gfx_init_chunky::$10 ← (byte) gfx_init_chunky::y#1 != rangelast(0,$32)
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if((bool~) gfx_init_chunky::$10) goto gfx_init_chunky::@1
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2018-04-15 21:32:49 +00:00
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to:gfx_init_chunky::@6
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gfx_init_chunky::@6: scope:[gfx_init_chunky] from gfx_init_chunky::@5
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2019-11-03 16:05:55 +00:00
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(byte~) gfx_init_chunky::$2 ← ((byte)) (number) $4000/(number) $4000
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(byte) dtvSetCpuBankSegment1::cpuBankIdx#2 ← (byte~) gfx_init_chunky::$2
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2018-05-01 20:50:59 +00:00
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call dtvSetCpuBankSegment1
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@9
|
|
|
|
gfx_init_chunky::@9: scope:[gfx_init_chunky] from gfx_init_chunky::@6
|
|
|
|
to:gfx_init_chunky::@return
|
|
|
|
gfx_init_chunky::@return: scope:[gfx_init_chunky] from gfx_init_chunky::@9
|
|
|
|
return
|
|
|
|
to:@return
|
2019-11-03 16:05:55 +00:00
|
|
|
@7: scope:[] from @begin
|
2018-05-01 20:50:59 +00:00
|
|
|
call main
|
2018-12-24 01:27:12 +00:00
|
|
|
to:@8
|
|
|
|
@8: scope:[] from @7
|
2018-04-15 21:32:49 +00:00
|
|
|
to:@end
|
2018-12-24 01:27:12 +00:00
|
|
|
@end: scope:[] from @8
|
2018-04-15 21:32:49 +00:00
|
|
|
|
|
|
|
SYMBOL TABLE SSA
|
2018-05-14 21:53:03 +00:00
|
|
|
(label) @7
|
2018-12-24 01:27:12 +00:00
|
|
|
(label) @8
|
2018-04-15 21:32:49 +00:00
|
|
|
(label) @begin
|
|
|
|
(label) @end
|
2019-11-03 16:05:55 +00:00
|
|
|
(const byte*) BORDERCOL = (byte*)(number) $d020
|
|
|
|
(const byte*) CHUNKY = (byte*)(number) $8000
|
|
|
|
(const byte*) CIA2_PORT_A = (byte*)(number) $dd00
|
|
|
|
(const byte*) CIA2_PORT_A_DDR = (byte*)(number) $dd02
|
|
|
|
(const byte) DTV_BADLINE_OFF = (number) $20
|
|
|
|
(const byte) DTV_CHUNKY = (number) $40
|
|
|
|
(const byte) DTV_COLORRAM_OFF = (number) $10
|
|
|
|
(const byte*) DTV_CONTROL = (byte*)(number) $d03c
|
|
|
|
(const byte*) DTV_FEATURE = (byte*)(number) $d03f
|
|
|
|
(const byte) DTV_FEATURE_ENABLE = (number) 1
|
|
|
|
(const byte) DTV_HIGHCOLOR = (number) 4
|
|
|
|
(const byte) DTV_LINEAR = (number) 1
|
|
|
|
(const byte*) DTV_PALETTE = (byte*)(number) $d200
|
|
|
|
(const byte*) DTV_PLANEB_MODULO_HI = (byte*)(number) $d048
|
|
|
|
(const byte*) DTV_PLANEB_MODULO_LO = (byte*)(number) $d047
|
|
|
|
(const byte*) DTV_PLANEB_START_HI = (byte*)(number) $d04b
|
|
|
|
(const byte*) DTV_PLANEB_START_LO = (byte*)(number) $d049
|
|
|
|
(const byte*) DTV_PLANEB_START_MI = (byte*)(number) $d04a
|
|
|
|
(const byte*) DTV_PLANEB_STEP = (byte*)(number) $d04c
|
|
|
|
(const byte*) PROCPORT = (byte*)(number) 1
|
|
|
|
(const byte*) PROCPORT_DDR = (byte*)(number) 0
|
|
|
|
(const byte) PROCPORT_DDR_MEMORY_MASK = (number) 7
|
|
|
|
(const byte) PROCPORT_RAM_IO = (number) 5
|
|
|
|
(const byte*) RASTER = (byte*)(number) $d012
|
|
|
|
(const byte*) VIC_CONTROL = (byte*)(number) $d011
|
|
|
|
(const byte*) VIC_CONTROL2 = (byte*)(number) $d016
|
|
|
|
(const byte) VIC_CSEL = (number) 8
|
|
|
|
(const byte) VIC_DEN = (number) $10
|
|
|
|
(const byte) VIC_ECM = (number) $40
|
|
|
|
(const byte) VIC_MCM = (number) $10
|
|
|
|
(const byte*) VIC_MEMORY = (byte*)(number) $d018
|
|
|
|
(const byte) VIC_RSEL = (number) 8
|
2018-04-15 21:32:49 +00:00
|
|
|
(void()) dtvSetCpuBankSegment1((byte) dtvSetCpuBankSegment1::cpuBankIdx)
|
|
|
|
(label) dtvSetCpuBankSegment1::@return
|
2019-11-03 16:05:55 +00:00
|
|
|
(const byte*) dtvSetCpuBankSegment1::cpuBank = (byte*)(number) $ff
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#0
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#1
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#2
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#3
|
|
|
|
(void()) gfx_init_chunky()
|
2019-11-03 16:05:55 +00:00
|
|
|
(byte~) gfx_init_chunky::$0
|
2019-06-18 23:23:27 +00:00
|
|
|
(bool~) gfx_init_chunky::$10
|
2019-11-03 16:05:55 +00:00
|
|
|
(byte~) gfx_init_chunky::$2
|
|
|
|
(bool~) gfx_init_chunky::$4
|
2019-06-18 23:23:27 +00:00
|
|
|
(bool~) gfx_init_chunky::$5
|
2019-11-03 16:05:55 +00:00
|
|
|
(word~) gfx_init_chunky::$7
|
|
|
|
(byte~) gfx_init_chunky::$8
|
|
|
|
(bool~) gfx_init_chunky::$9
|
2018-04-15 21:32:49 +00:00
|
|
|
(label) gfx_init_chunky::@1
|
|
|
|
(label) gfx_init_chunky::@2
|
|
|
|
(label) gfx_init_chunky::@3
|
|
|
|
(label) gfx_init_chunky::@4
|
|
|
|
(label) gfx_init_chunky::@5
|
|
|
|
(label) gfx_init_chunky::@6
|
|
|
|
(label) gfx_init_chunky::@7
|
|
|
|
(label) gfx_init_chunky::@8
|
|
|
|
(label) gfx_init_chunky::@9
|
|
|
|
(label) gfx_init_chunky::@return
|
|
|
|
(byte) gfx_init_chunky::c
|
|
|
|
(byte) gfx_init_chunky::c#0
|
|
|
|
(byte*) gfx_init_chunky::gfxb
|
|
|
|
(byte*) gfx_init_chunky::gfxb#0
|
|
|
|
(byte*) gfx_init_chunky::gfxb#1
|
|
|
|
(byte*) gfx_init_chunky::gfxb#2
|
|
|
|
(byte*) gfx_init_chunky::gfxb#3
|
|
|
|
(byte*) gfx_init_chunky::gfxb#4
|
|
|
|
(byte*) gfx_init_chunky::gfxb#5
|
|
|
|
(byte*) gfx_init_chunky::gfxb#6
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#0
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#1
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#2
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#3
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#4
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#5
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#6
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#7
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#8
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#9
|
|
|
|
(word) gfx_init_chunky::x
|
|
|
|
(word) gfx_init_chunky::x#0
|
|
|
|
(word) gfx_init_chunky::x#1
|
|
|
|
(word) gfx_init_chunky::x#2
|
|
|
|
(word) gfx_init_chunky::x#3
|
|
|
|
(word) gfx_init_chunky::x#4
|
|
|
|
(word) gfx_init_chunky::x#5
|
|
|
|
(byte) gfx_init_chunky::y
|
|
|
|
(byte) gfx_init_chunky::y#0
|
|
|
|
(byte) gfx_init_chunky::y#1
|
|
|
|
(byte) gfx_init_chunky::y#2
|
|
|
|
(byte) gfx_init_chunky::y#3
|
|
|
|
(byte) gfx_init_chunky::y#4
|
|
|
|
(byte) gfx_init_chunky::y#5
|
|
|
|
(byte) gfx_init_chunky::y#6
|
|
|
|
(byte) gfx_init_chunky::y#7
|
|
|
|
(void()) main()
|
2019-11-03 16:05:55 +00:00
|
|
|
(word~) main::$1
|
|
|
|
(number~) main::$10
|
|
|
|
(number~) main::$11
|
2019-05-30 20:29:04 +00:00
|
|
|
(number~) main::$12
|
2019-11-03 16:05:55 +00:00
|
|
|
(number~) main::$13
|
|
|
|
(bool~) main::$14
|
|
|
|
(bool~) main::$15
|
2019-05-30 20:29:04 +00:00
|
|
|
(number~) main::$16
|
|
|
|
(number~) main::$17
|
2019-11-03 16:05:55 +00:00
|
|
|
(number~) main::$18
|
|
|
|
(bool~) main::$19
|
|
|
|
(number~) main::$2
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte~) main::$3
|
2019-11-03 16:05:55 +00:00
|
|
|
(number~) main::$4
|
|
|
|
(word~) main::$5
|
|
|
|
(number~) main::$6
|
2019-05-30 20:29:04 +00:00
|
|
|
(number~) main::$7
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte~) main::$8
|
2019-11-03 16:05:55 +00:00
|
|
|
(word~) main::$9
|
2018-04-15 21:32:49 +00:00
|
|
|
(label) main::@1
|
2019-03-31 15:57:54 +00:00
|
|
|
(label) main::@12
|
2018-04-15 21:32:49 +00:00
|
|
|
(label) main::@17
|
2019-03-31 15:57:54 +00:00
|
|
|
(label) main::@3
|
|
|
|
(label) main::@4
|
2018-04-15 21:32:49 +00:00
|
|
|
(label) main::@6
|
|
|
|
(label) main::@8
|
|
|
|
(label) main::@return
|
|
|
|
(byte) main::j
|
|
|
|
(byte) main::j#0
|
|
|
|
(byte) main::j#1
|
|
|
|
(byte) main::j#2
|
|
|
|
(byte) main::rst
|
|
|
|
(byte) main::rst#0
|
|
|
|
(byte) main::rst#1
|
|
|
|
(byte) main::rst#2
|
|
|
|
|
2019-11-03 16:05:55 +00:00
|
|
|
Adding number conversion cast (unumber) VIC_DEN|VIC_ECM|VIC_RSEL|3 in *((const byte*) VIC_CONTROL) ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(number) 3
|
|
|
|
Adding number conversion cast (unumber) 3 in *((const byte*) VIC_CONTROL) ← ((unumber)) (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(number) 3
|
|
|
|
Adding number conversion cast (unumber) 0 in *((const byte*) DTV_PLANEB_START_HI) ← (number) 0
|
|
|
|
Adding number conversion cast (unumber) 8 in *((const byte*) DTV_PLANEB_STEP) ← (number) 8
|
|
|
|
Adding number conversion cast (unumber) 0 in *((const byte*) DTV_PLANEB_MODULO_LO) ← (number) 0
|
|
|
|
Adding number conversion cast (unumber) 0 in *((const byte*) DTV_PLANEB_MODULO_HI) ← (number) 0
|
|
|
|
Adding number conversion cast (unumber) 3 in *((const byte*) CIA2_PORT_A_DDR) ← (number) 3
|
|
|
|
Adding number conversion cast (unumber) $4000 in (number~) main::$2 ← (word~) main::$1 / (number) $4000
|
|
|
|
Adding number conversion cast (unumber) main::$2 in (number~) main::$2 ← (word~) main::$1 / (unumber)(number) $4000
|
|
|
|
Adding number conversion cast (unumber) 3 in (number~) main::$4 ← (number) 3 ^ (byte~) main::$3
|
|
|
|
Adding number conversion cast (unumber) main::$4 in (number~) main::$4 ← (unumber)(number) 3 ^ (byte~) main::$3
|
|
|
|
Adding number conversion cast (unumber) $3fff in (number~) main::$6 ← (word~) main::$5 & (number) $3fff
|
|
|
|
Adding number conversion cast (unumber) main::$6 in (number~) main::$6 ← (word~) main::$5 & (unumber)(number) $3fff
|
|
|
|
Adding number conversion cast (unumber) $40 in (number~) main::$7 ← (unumber~) main::$6 / (number) $40
|
|
|
|
Adding number conversion cast (unumber) main::$7 in (number~) main::$7 ← (unumber~) main::$6 / (unumber)(number) $40
|
|
|
|
Adding number conversion cast (unumber) $3fff in (number~) main::$10 ← (word~) main::$9 & (number) $3fff
|
|
|
|
Adding number conversion cast (unumber) main::$10 in (number~) main::$10 ← (word~) main::$9 & (unumber)(number) $3fff
|
|
|
|
Adding number conversion cast (unumber) main::$11 in (number~) main::$11 ← > (unumber~) main::$10
|
|
|
|
Adding number conversion cast (unumber) 4 in (number~) main::$12 ← (unumber~) main::$11 / (number) 4
|
|
|
|
Adding number conversion cast (unumber) main::$12 in (number~) main::$12 ← (unumber~) main::$11 / (unumber)(number) 4
|
|
|
|
Adding number conversion cast (unumber) main::$13 in (number~) main::$13 ← (byte~) main::$8 | (unumber~) main::$12
|
|
|
|
Adding number conversion cast (unumber) VIC_DEN|VIC_ECM|VIC_RSEL|3 in *((const byte*) VIC_CONTROL) ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(number) 3
|
|
|
|
Adding number conversion cast (unumber) 3 in *((const byte*) VIC_CONTROL) ← ((unumber)) (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(number) 3
|
|
|
|
Adding number conversion cast (unumber) 0 in *((const byte*) BORDERCOL) ← (number) 0
|
2019-05-30 20:29:04 +00:00
|
|
|
Adding number conversion cast (unumber) $42 in (byte) main::rst#0 ← (number) $42
|
2019-11-03 16:05:55 +00:00
|
|
|
Adding number conversion cast (unumber) 7 in (number~) main::$16 ← (byte) main::rst#1 & (number) 7
|
|
|
|
Adding number conversion cast (unumber) main::$16 in (number~) main::$16 ← (byte) main::rst#1 & (unumber)(number) 7
|
|
|
|
Adding number conversion cast (unumber) main::$17 in (number~) main::$17 ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL | (unumber~) main::$16
|
|
|
|
Adding number conversion cast (unumber) $10 in (number~) main::$18 ← (byte) main::rst#1 * (number) $10
|
|
|
|
Adding number conversion cast (unumber) main::$18 in (number~) main::$18 ← (byte) main::rst#1 * (unumber)(number) $10
|
|
|
|
Adding number conversion cast (unumber) $f2 in (bool~) main::$19 ← (byte) main::rst#1 != (number) $f2
|
|
|
|
Adding number conversion cast (unumber) $4000 in (byte~) gfx_init_chunky::$0 ← ((byte)) (const byte*) CHUNKY/(number) $4000
|
|
|
|
Adding number conversion cast (unumber) $8000 in (bool~) gfx_init_chunky::$4 ← (byte*) gfx_init_chunky::gfxb#3 == (number) $8000
|
2019-05-30 20:29:04 +00:00
|
|
|
Successful SSA optimization PassNAddNumberTypeConversions
|
2019-11-03 16:05:55 +00:00
|
|
|
Inlining cast *((const byte*) VIC_CONTROL) ← (unumber)(const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(unumber)(number) 3
|
|
|
|
Inlining cast *((const byte*) DTV_PLANEB_START_HI) ← (unumber)(number) 0
|
|
|
|
Inlining cast *((const byte*) DTV_PLANEB_STEP) ← (unumber)(number) 8
|
|
|
|
Inlining cast *((const byte*) DTV_PLANEB_MODULO_LO) ← (unumber)(number) 0
|
|
|
|
Inlining cast *((const byte*) DTV_PLANEB_MODULO_HI) ← (unumber)(number) 0
|
|
|
|
Inlining cast *((const byte*) CIA2_PORT_A_DDR) ← (unumber)(number) 3
|
|
|
|
Inlining cast (word~) main::$1 ← (word)(const byte*) CHUNKY
|
|
|
|
Inlining cast (byte~) main::$3 ← (byte)(unumber~) main::$2
|
|
|
|
Inlining cast (word~) main::$5 ← (word)(const byte*) CHUNKY
|
|
|
|
Inlining cast (byte~) main::$8 ← (byte)(unumber~) main::$7
|
|
|
|
Inlining cast (word~) main::$9 ← (word)(const byte*) CHUNKY
|
|
|
|
Inlining cast *((const byte*) VIC_CONTROL) ← (unumber)(const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(unumber)(number) 3
|
|
|
|
Inlining cast *((const byte*) BORDERCOL) ← (unumber)(number) 0
|
2019-05-30 20:29:04 +00:00
|
|
|
Inlining cast (byte) main::rst#0 ← (unumber)(number) $42
|
2019-11-03 16:05:55 +00:00
|
|
|
Inlining cast (byte~) gfx_init_chunky::$0 ← (byte)(const byte*) CHUNKY/(unumber)(number) $4000
|
2019-05-30 20:29:04 +00:00
|
|
|
Inlining cast (byte*) gfx_init_chunky::gfxb#0 ← (byte*)(number) $4000
|
2019-11-03 16:05:55 +00:00
|
|
|
Inlining cast (byte~) gfx_init_chunky::$8 ← (byte)(word~) gfx_init_chunky::$7
|
2019-05-30 20:29:04 +00:00
|
|
|
Inlining cast (byte*) gfx_init_chunky::gfxb#2 ← (byte*)(number) $4000
|
2019-11-03 16:05:55 +00:00
|
|
|
Inlining cast (byte~) gfx_init_chunky::$2 ← (byte)(number) $4000/(number) $4000
|
2019-05-30 20:29:04 +00:00
|
|
|
Successful SSA optimization Pass2InlineCast
|
|
|
|
Simplifying constant pointer cast (byte*) 0
|
|
|
|
Simplifying constant pointer cast (byte*) 1
|
|
|
|
Simplifying constant pointer cast (byte*) 53266
|
|
|
|
Simplifying constant pointer cast (byte*) 53280
|
|
|
|
Simplifying constant pointer cast (byte*) 53265
|
|
|
|
Simplifying constant pointer cast (byte*) 53270
|
|
|
|
Simplifying constant pointer cast (byte*) 53272
|
|
|
|
Simplifying constant pointer cast (byte*) 56576
|
|
|
|
Simplifying constant pointer cast (byte*) 56578
|
|
|
|
Simplifying constant pointer cast (byte*) 53311
|
|
|
|
Simplifying constant pointer cast (byte*) 53308
|
|
|
|
Simplifying constant pointer cast (byte*) 53760
|
|
|
|
Simplifying constant pointer cast (byte*) 53321
|
|
|
|
Simplifying constant pointer cast (byte*) 53322
|
|
|
|
Simplifying constant pointer cast (byte*) 53323
|
|
|
|
Simplifying constant pointer cast (byte*) 53324
|
|
|
|
Simplifying constant pointer cast (byte*) 53319
|
|
|
|
Simplifying constant pointer cast (byte*) 53320
|
|
|
|
Simplifying constant pointer cast (byte*) 255
|
|
|
|
Simplifying constant pointer cast (byte*) 32768
|
2019-11-03 16:05:55 +00:00
|
|
|
Simplifying constant integer cast (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(unumber)(number) 3
|
2019-05-30 20:29:04 +00:00
|
|
|
Simplifying constant integer cast 3
|
|
|
|
Simplifying constant integer cast 0
|
|
|
|
Simplifying constant integer cast 8
|
|
|
|
Simplifying constant integer cast 0
|
|
|
|
Simplifying constant integer cast 0
|
|
|
|
Simplifying constant integer cast 3
|
|
|
|
Simplifying constant integer cast $4000
|
|
|
|
Simplifying constant integer cast 3
|
|
|
|
Simplifying constant integer cast $3fff
|
|
|
|
Simplifying constant integer cast $40
|
|
|
|
Simplifying constant integer cast $3fff
|
|
|
|
Simplifying constant integer cast 4
|
2019-11-03 16:05:55 +00:00
|
|
|
Simplifying constant integer cast (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(unumber)(number) 3
|
2019-05-30 20:29:04 +00:00
|
|
|
Simplifying constant integer cast 3
|
|
|
|
Simplifying constant integer cast 0
|
|
|
|
Simplifying constant integer cast $42
|
|
|
|
Simplifying constant integer cast 7
|
|
|
|
Simplifying constant integer cast $10
|
|
|
|
Simplifying constant integer cast $f2
|
|
|
|
Simplifying constant integer cast $4000
|
|
|
|
Simplifying constant pointer cast (byte*) 16384
|
|
|
|
Simplifying constant integer cast $8000
|
|
|
|
Simplifying constant pointer cast (byte*) 16384
|
|
|
|
Successful SSA optimization PassNCastSimplification
|
|
|
|
Finalized unsigned number type (byte) 3
|
|
|
|
Finalized unsigned number type (byte) 0
|
|
|
|
Finalized unsigned number type (byte) 8
|
|
|
|
Finalized unsigned number type (byte) 0
|
|
|
|
Finalized unsigned number type (byte) 0
|
|
|
|
Finalized unsigned number type (byte) 3
|
|
|
|
Finalized unsigned number type (word) $4000
|
|
|
|
Finalized unsigned number type (byte) 3
|
|
|
|
Finalized unsigned number type (word) $3fff
|
|
|
|
Finalized unsigned number type (byte) $40
|
|
|
|
Finalized unsigned number type (word) $3fff
|
|
|
|
Finalized unsigned number type (byte) 4
|
|
|
|
Finalized unsigned number type (byte) 3
|
|
|
|
Finalized unsigned number type (byte) 0
|
|
|
|
Finalized unsigned number type (byte) $42
|
|
|
|
Finalized unsigned number type (byte) 7
|
|
|
|
Finalized unsigned number type (byte) $10
|
|
|
|
Finalized unsigned number type (byte) $f2
|
|
|
|
Finalized unsigned number type (word) $4000
|
|
|
|
Finalized unsigned number type (word) $8000
|
|
|
|
Successful SSA optimization PassNFinalizeNumberTypeConversions
|
2019-11-03 16:05:55 +00:00
|
|
|
Inferred type updated to word in (unumber~) main::$2 ← (word~) main::$1 / (word) $4000
|
|
|
|
Inferred type updated to byte in (unumber~) main::$4 ← (byte) 3 ^ (byte~) main::$3
|
|
|
|
Inferred type updated to word in (unumber~) main::$6 ← (word~) main::$5 & (word) $3fff
|
|
|
|
Inferred type updated to word in (unumber~) main::$7 ← (word~) main::$6 / (byte) $40
|
|
|
|
Inferred type updated to word in (unumber~) main::$10 ← (word~) main::$9 & (word) $3fff
|
|
|
|
Inferred type updated to byte in (unumber~) main::$11 ← > (word~) main::$10
|
|
|
|
Inferred type updated to byte in (unumber~) main::$12 ← (byte~) main::$11 / (byte) 4
|
|
|
|
Inferred type updated to byte in (unumber~) main::$13 ← (byte~) main::$8 | (byte~) main::$12
|
|
|
|
Inferred type updated to byte in (unumber~) main::$16 ← (byte) main::rst#1 & (byte) 7
|
|
|
|
Inferred type updated to byte in (unumber~) main::$17 ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL | (byte~) main::$16
|
|
|
|
Inferred type updated to byte in (unumber~) main::$18 ← (byte) main::rst#1 * (byte) $10
|
|
|
|
Inversing boolean not [71] (bool~) gfx_init_chunky::$5 ← (byte*) gfx_init_chunky::gfxb#3 != (word) $8000 from [70] (bool~) gfx_init_chunky::$4 ← (byte*) gfx_init_chunky::gfxb#3 == (word) $8000
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2UnaryNotSimplification
|
2019-11-03 16:05:55 +00:00
|
|
|
Alias (byte) gfx_init_chunky::gfxbCpuBank#0 = (byte~) gfx_init_chunky::$0 (byte) gfx_init_chunky::gfxbCpuBank#3
|
|
|
|
Alias (byte) gfx_init_chunky::c#0 = (byte~) gfx_init_chunky::$8
|
2018-04-15 21:32:49 +00:00
|
|
|
Alias (byte) gfx_init_chunky::gfxbCpuBank#4 = (byte) gfx_init_chunky::gfxbCpuBank#6 (byte) gfx_init_chunky::gfxbCpuBank#5
|
|
|
|
Alias (word) gfx_init_chunky::x#3 = (word) gfx_init_chunky::x#5 (word) gfx_init_chunky::x#4
|
|
|
|
Alias (byte) gfx_init_chunky::y#4 = (byte) gfx_init_chunky::y#7 (byte) gfx_init_chunky::y#5
|
|
|
|
Alias (byte) gfx_init_chunky::y#2 = (byte) gfx_init_chunky::y#3
|
|
|
|
Alias (byte*) gfx_init_chunky::gfxb#1 = (byte*) gfx_init_chunky::gfxb#6
|
|
|
|
Alias (byte) gfx_init_chunky::gfxbCpuBank#8 = (byte) gfx_init_chunky::gfxbCpuBank#9
|
2019-11-03 16:05:55 +00:00
|
|
|
Alias (byte) dtvSetCpuBankSegment1::cpuBankIdx#2 = (byte~) gfx_init_chunky::$2
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2AliasElimination
|
2018-04-15 21:32:49 +00:00
|
|
|
Alias (word) gfx_init_chunky::x#2 = (word) gfx_init_chunky::x#3
|
|
|
|
Alias (byte) gfx_init_chunky::y#2 = (byte) gfx_init_chunky::y#4
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2AliasElimination
|
2019-05-30 20:29:04 +00:00
|
|
|
Identical Phi Values (byte) main::rst#2 (byte) main::rst#0
|
|
|
|
Identical Phi Values (byte) gfx_init_chunky::y#2 (byte) gfx_init_chunky::y#6
|
|
|
|
Successful SSA optimization Pass2IdenticalPhiElimination
|
2019-11-03 16:05:55 +00:00
|
|
|
Simple Condition (bool~) main::$14 [39] if((byte) main::j#1!=rangelast(0,$f)) goto main::@1
|
|
|
|
Simple Condition (bool~) main::$15 [47] if(*((const byte*) RASTER)!=(byte) main::rst#0) goto main::@6
|
|
|
|
Simple Condition (bool~) main::$19 [57] if((byte) main::rst#1!=(byte) $f2) goto main::@12
|
|
|
|
Simple Condition (bool~) gfx_init_chunky::$5 [72] if((byte*) gfx_init_chunky::gfxb#3!=(word) $8000) goto gfx_init_chunky::@3
|
|
|
|
Simple Condition (bool~) gfx_init_chunky::$9 [81] if((word) gfx_init_chunky::x#1!=rangelast(0,$13f)) goto gfx_init_chunky::@2
|
|
|
|
Simple Condition (bool~) gfx_init_chunky::$10 [91] if((byte) gfx_init_chunky::y#1!=rangelast(0,$32)) goto gfx_init_chunky::@1
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2ConditionalJumpSimplification
|
2019-11-03 16:05:55 +00:00
|
|
|
Constant right-side identified [19] (word~) main::$1 ← (word)(const byte*) CHUNKY
|
|
|
|
Constant right-side identified [24] (word~) main::$5 ← (word)(const byte*) CHUNKY
|
|
|
|
Constant right-side identified [28] (word~) main::$9 ← (word)(const byte*) CHUNKY
|
|
|
|
Constant right-side identified [59] (byte) gfx_init_chunky::gfxbCpuBank#0 ← (byte)(const byte*) CHUNKY/(word) $4000
|
|
|
|
Constant right-side identified [92] (byte) dtvSetCpuBankSegment1::cpuBankIdx#2 ← (byte)(number) $4000/(number) $4000
|
2019-05-30 20:29:04 +00:00
|
|
|
Successful SSA optimization Pass2ConstantRValueConsolidation
|
2019-11-03 16:05:55 +00:00
|
|
|
Constant (const word) main::$1 = (word)CHUNKY
|
|
|
|
Constant (const word) main::$5 = (word)CHUNKY
|
|
|
|
Constant (const word) main::$9 = (word)CHUNKY
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant (const byte) main::j#0 = 0
|
2019-03-08 05:54:45 +00:00
|
|
|
Constant (const byte) main::rst#0 = $42
|
2019-11-03 16:05:55 +00:00
|
|
|
Constant (const byte) gfx_init_chunky::gfxbCpuBank#0 = (byte)CHUNKY/$4000
|
2019-05-30 20:29:04 +00:00
|
|
|
Constant (const byte*) gfx_init_chunky::gfxb#0 = (byte*) 16384
|
2018-04-15 21:32:49 +00:00
|
|
|
Constant (const byte) gfx_init_chunky::y#0 = 0
|
|
|
|
Constant (const word) gfx_init_chunky::x#0 = 0
|
2019-05-30 20:29:04 +00:00
|
|
|
Constant (const byte*) gfx_init_chunky::gfxb#2 = (byte*) 16384
|
2019-06-18 23:23:27 +00:00
|
|
|
Constant (const byte) dtvSetCpuBankSegment1::cpuBankIdx#2 = (byte)$4000/$4000
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2ConstantIdentification
|
2019-11-03 16:05:55 +00:00
|
|
|
Constant (const byte) dtvSetCpuBankSegment1::cpuBankIdx#0 = gfx_init_chunky::gfxbCpuBank#0
|
2019-10-20 15:06:17 +00:00
|
|
|
Successful SSA optimization Pass2ConstantIdentification
|
2019-11-03 16:05:55 +00:00
|
|
|
if() condition always true - replacing block destination [40] if(true) goto main::@4
|
2019-05-30 20:29:04 +00:00
|
|
|
Successful SSA optimization Pass2ConstantIfs
|
2019-11-03 16:05:55 +00:00
|
|
|
Resolved ranged next value [37] main::j#1 ← ++ main::j#2 to ++
|
|
|
|
Resolved ranged comparison value [39] if(main::j#1!=rangelast(0,$f)) goto main::@1 to (number) $10
|
|
|
|
Resolved ranged next value [79] gfx_init_chunky::x#1 ← ++ gfx_init_chunky::x#2 to ++
|
|
|
|
Resolved ranged comparison value [81] if(gfx_init_chunky::x#1!=rangelast(0,$13f)) goto gfx_init_chunky::@2 to (number) $140
|
|
|
|
Resolved ranged next value [89] gfx_init_chunky::y#1 ← ++ gfx_init_chunky::y#6 to ++
|
|
|
|
Resolved ranged comparison value [91] if(gfx_init_chunky::y#1!=rangelast(0,$32)) goto gfx_init_chunky::@1 to (number) $33
|
|
|
|
Simplifying constant evaluating to zero <(const byte*) CHUNKY in [12] *((const byte*) DTV_PLANEB_START_LO) ← <(const byte*) CHUNKY
|
|
|
|
Successful SSA optimization PassNSimplifyConstantZero
|
2019-05-30 20:29:04 +00:00
|
|
|
Removing unused block main::@return
|
|
|
|
Successful SSA optimization Pass2EliminateUnusedBlocks
|
|
|
|
Adding number conversion cast (unumber) $10 in if((byte) main::j#1!=(number) $10) goto main::@1
|
|
|
|
Adding number conversion cast (unumber) $140 in if((word) gfx_init_chunky::x#1!=(number) $140) goto gfx_init_chunky::@2
|
|
|
|
Adding number conversion cast (unumber) $33 in if((byte) gfx_init_chunky::y#1!=(number) $33) goto gfx_init_chunky::@1
|
|
|
|
Successful SSA optimization PassNAddNumberTypeConversions
|
|
|
|
Simplifying constant integer cast $10
|
|
|
|
Simplifying constant integer cast $140
|
|
|
|
Simplifying constant integer cast $33
|
|
|
|
Successful SSA optimization PassNCastSimplification
|
|
|
|
Finalized unsigned number type (byte) $10
|
|
|
|
Finalized unsigned number type (word) $140
|
|
|
|
Finalized unsigned number type (byte) $33
|
|
|
|
Successful SSA optimization PassNFinalizeNumberTypeConversions
|
2019-11-03 16:05:55 +00:00
|
|
|
Constant right-side identified [19] (word~) main::$2 ← (const word) main::$1 / (word) $4000
|
|
|
|
Constant right-side identified [23] (word~) main::$6 ← (const word) main::$5 & (word) $3fff
|
|
|
|
Constant right-side identified [26] (word~) main::$10 ← (const word) main::$9 & (word) $3fff
|
|
|
|
Constant right-side identified [49] (byte) gfx_init_chunky::gfxbCpuBank#1 ← ++ (const byte) gfx_init_chunky::gfxbCpuBank#0
|
2019-05-30 20:29:04 +00:00
|
|
|
Successful SSA optimization Pass2ConstantRValueConsolidation
|
2019-11-03 16:05:55 +00:00
|
|
|
Constant (const word) main::$2 = main::$1/$4000
|
|
|
|
Constant (const word) main::$6 = main::$5&$3fff
|
|
|
|
Constant (const word) main::$10 = main::$9&$3fff
|
|
|
|
Constant (const byte) gfx_init_chunky::gfxbCpuBank#1 = ++gfx_init_chunky::gfxbCpuBank#0
|
2019-05-30 20:29:04 +00:00
|
|
|
Successful SSA optimization Pass2ConstantIdentification
|
2019-11-03 16:05:55 +00:00
|
|
|
Constant (const byte) main::$3 = (byte)main::$2
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2ConstantIdentification
|
2019-11-03 16:05:55 +00:00
|
|
|
Simplifying constant evaluating to zero (const word) main::$5&(word) $3fff in
|
|
|
|
Simplifying constant evaluating to zero (const word) main::$9&(word) $3fff in
|
2019-05-30 20:29:04 +00:00
|
|
|
Successful SSA optimization PassNSimplifyConstantZero
|
2019-11-03 16:05:55 +00:00
|
|
|
Eliminating unused constant (const word) main::$5
|
|
|
|
Eliminating unused constant (const word) main::$9
|
2019-05-30 20:29:04 +00:00
|
|
|
Successful SSA optimization PassNEliminateUnusedVars
|
2019-11-03 16:05:55 +00:00
|
|
|
Constant right-side identified [19] (byte~) main::$4 ← (byte) 3 ^ (const byte) main::$3
|
|
|
|
Constant right-side identified [21] (word~) main::$7 ← (const word) main::$6 / (byte) $40
|
|
|
|
Constant right-side identified [23] (byte~) main::$11 ← > (const word) main::$10
|
2019-05-30 20:29:04 +00:00
|
|
|
Successful SSA optimization Pass2ConstantRValueConsolidation
|
2019-11-03 16:05:55 +00:00
|
|
|
Constant (const byte) main::$4 = 3^main::$3
|
|
|
|
Constant (const word) main::$7 = main::$6/$40
|
|
|
|
Constant (const byte) main::$11 = >main::$10
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2ConstantIdentification
|
2019-11-03 16:05:55 +00:00
|
|
|
Constant (const byte) main::$8 = (byte)main::$7
|
2019-10-20 15:06:17 +00:00
|
|
|
Successful SSA optimization Pass2ConstantIdentification
|
2019-11-03 16:05:55 +00:00
|
|
|
Simplifying constant evaluating to zero (const word) main::$6/(byte) $40 in
|
|
|
|
Simplifying constant evaluating to zero >(const word) main::$10 in
|
|
|
|
Simplifying constant evaluating to zero (byte)(const word) main::$7 in
|
2019-05-30 20:29:04 +00:00
|
|
|
Successful SSA optimization PassNSimplifyConstantZero
|
2019-11-03 16:05:55 +00:00
|
|
|
Simplifying expression containing zero main::$12 in [25] (byte~) main::$13 ← (const byte) main::$8 | (byte~) main::$12
|
2019-10-20 15:06:17 +00:00
|
|
|
Successful SSA optimization PassNSimplifyExpressionWithZero
|
2019-11-03 16:05:55 +00:00
|
|
|
Eliminating unused constant (const word) main::$6
|
|
|
|
Eliminating unused constant (const word) main::$10
|
|
|
|
Eliminating unused constant (const word) main::$7
|
|
|
|
Eliminating unused constant (const byte) main::$8
|
2019-05-30 20:29:04 +00:00
|
|
|
Successful SSA optimization PassNEliminateUnusedVars
|
2019-11-03 16:05:55 +00:00
|
|
|
Alias (byte~) main::$13 = (byte~) main::$12
|
2019-10-20 15:06:17 +00:00
|
|
|
Successful SSA optimization Pass2AliasElimination
|
2019-11-03 16:05:55 +00:00
|
|
|
Constant right-side identified [20] (byte~) main::$13 ← (const byte) main::$11 / (byte) 4
|
2019-05-30 20:29:04 +00:00
|
|
|
Successful SSA optimization Pass2ConstantRValueConsolidation
|
2019-11-03 16:05:55 +00:00
|
|
|
Constant (const byte) main::$13 = main::$11/4
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2ConstantIdentification
|
2019-11-03 16:05:55 +00:00
|
|
|
Simplifying constant evaluating to zero (const byte) main::$11/(byte) 4 in
|
2019-05-30 20:29:04 +00:00
|
|
|
Successful SSA optimization PassNSimplifyConstantZero
|
2019-11-03 16:05:55 +00:00
|
|
|
Eliminating unused constant (const byte) main::$11
|
2019-05-30 20:29:04 +00:00
|
|
|
Successful SSA optimization PassNEliminateUnusedVars
|
2019-11-03 16:05:55 +00:00
|
|
|
Rewriting multiplication to use shift [34] (byte~) main::$18 ← (byte) main::rst#1 * (byte) $10
|
2019-04-15 08:20:55 +00:00
|
|
|
Successful SSA optimization Pass2MultiplyToShiftRewriting
|
2018-04-15 21:32:49 +00:00
|
|
|
Inlining constant with var siblings (const byte) dtvSetCpuBankSegment1::cpuBankIdx#2
|
|
|
|
Inlining constant with var siblings (const byte) dtvSetCpuBankSegment1::cpuBankIdx#0
|
|
|
|
Inlining constant with var siblings (const byte) main::j#0
|
|
|
|
Inlining constant with var siblings (const byte) main::rst#0
|
2019-11-03 16:05:55 +00:00
|
|
|
Inlining constant with var siblings (const byte) gfx_init_chunky::gfxbCpuBank#0
|
2018-04-15 21:32:49 +00:00
|
|
|
Inlining constant with var siblings (const byte*) gfx_init_chunky::gfxb#0
|
|
|
|
Inlining constant with var siblings (const byte) gfx_init_chunky::y#0
|
|
|
|
Inlining constant with var siblings (const word) gfx_init_chunky::x#0
|
|
|
|
Inlining constant with var siblings (const byte*) gfx_init_chunky::gfxb#2
|
|
|
|
Inlining constant with var siblings (const byte) gfx_init_chunky::gfxbCpuBank#1
|
2019-09-29 18:57:23 +00:00
|
|
|
Constant inlined dtvSetCpuBankSegment1::cpuBankIdx#0 = (byte)(const byte*) CHUNKY/(word) $4000
|
2019-05-30 20:29:04 +00:00
|
|
|
Constant inlined main::rst#0 = (byte) $42
|
|
|
|
Constant inlined dtvSetCpuBankSegment1::cpuBankIdx#2 = (byte)(number) $4000/(number) $4000
|
2019-11-03 16:05:55 +00:00
|
|
|
Constant inlined gfx_init_chunky::gfxbCpuBank#1 = ++(byte)(const byte*) CHUNKY/(word) $4000
|
|
|
|
Constant inlined main::$13 = (byte) 0
|
2019-05-30 20:29:04 +00:00
|
|
|
Constant inlined gfx_init_chunky::y#0 = (byte) 0
|
2019-06-02 22:44:46 +00:00
|
|
|
Constant inlined gfx_init_chunky::x#0 = (word) 0
|
2019-05-30 20:29:04 +00:00
|
|
|
Constant inlined gfx_init_chunky::gfxb#2 = (byte*) 16384
|
|
|
|
Constant inlined gfx_init_chunky::gfxb#0 = (byte*) 16384
|
2019-09-29 18:57:23 +00:00
|
|
|
Constant inlined gfx_init_chunky::gfxbCpuBank#0 = (byte)(const byte*) CHUNKY/(word) $4000
|
2019-11-03 16:05:55 +00:00
|
|
|
Constant inlined main::$1 = (word)(const byte*) CHUNKY
|
|
|
|
Constant inlined main::$2 = (word)(const byte*) CHUNKY/(word) $4000
|
|
|
|
Constant inlined main::$3 = (byte)(word)(const byte*) CHUNKY/(word) $4000
|
|
|
|
Constant inlined main::$4 = (byte) 3^(byte)(word)(const byte*) CHUNKY/(word) $4000
|
|
|
|
Constant inlined main::j#0 = (byte) 0
|
2018-08-22 20:23:42 +00:00
|
|
|
Successful SSA optimization Pass2ConstantInlining
|
2019-03-31 15:57:54 +00:00
|
|
|
Added new block during phi lifting main::@18(between main::@1 and main::@1)
|
2018-04-15 21:32:49 +00:00
|
|
|
Added new block during phi lifting gfx_init_chunky::@10(between gfx_init_chunky::@5 and gfx_init_chunky::@1)
|
|
|
|
Added new block during phi lifting gfx_init_chunky::@11(between gfx_init_chunky::@3 and gfx_init_chunky::@2)
|
|
|
|
Added new block during phi lifting gfx_init_chunky::@12(between gfx_init_chunky::@2 and gfx_init_chunky::@3)
|
|
|
|
Adding NOP phi() at start of @begin
|
2018-12-24 01:27:12 +00:00
|
|
|
Adding NOP phi() at start of @7
|
2019-05-30 20:29:04 +00:00
|
|
|
Adding NOP phi() at start of @8
|
2018-04-15 21:32:49 +00:00
|
|
|
Adding NOP phi() at start of @end
|
2019-05-30 20:29:04 +00:00
|
|
|
Adding NOP phi() at start of main::@3
|
2018-04-15 21:32:49 +00:00
|
|
|
Adding NOP phi() at start of gfx_init_chunky
|
2019-05-30 20:29:04 +00:00
|
|
|
Adding NOP phi() at start of gfx_init_chunky::@7
|
2018-04-15 21:32:49 +00:00
|
|
|
Adding NOP phi() at start of gfx_init_chunky::@6
|
2019-05-30 20:29:04 +00:00
|
|
|
Adding NOP phi() at start of gfx_init_chunky::@9
|
2018-04-15 21:32:49 +00:00
|
|
|
CALL GRAPH
|
2019-11-03 16:05:55 +00:00
|
|
|
Calls in [] to main:2
|
|
|
|
Calls in [main] to gfx_init_chunky:8
|
|
|
|
Calls in [gfx_init_chunky] to dtvSetCpuBankSegment1:42 dtvSetCpuBankSegment1:51 dtvSetCpuBankSegment1:64
|
2018-04-15 21:32:49 +00:00
|
|
|
|
|
|
|
Created 10 initial phi equivalence classes
|
2019-11-03 16:05:55 +00:00
|
|
|
Coalesced [40] main::j#3 ← main::j#1
|
|
|
|
Coalesced [45] gfx_init_chunky::gfxb#8 ← gfx_init_chunky::gfxb#5
|
|
|
|
Coalesced [46] gfx_init_chunky::gfxbCpuBank#11 ← gfx_init_chunky::gfxbCpuBank#7
|
|
|
|
Coalesced [50] dtvSetCpuBankSegment1::cpuBankIdx#4 ← dtvSetCpuBankSegment1::cpuBankIdx#1
|
|
|
|
Coalesced [53] gfx_init_chunky::gfxbCpuBank#14 ← gfx_init_chunky::gfxbCpuBank#2
|
|
|
|
Coalesced [67] gfx_init_chunky::gfxb#7 ← gfx_init_chunky::gfxb#1
|
|
|
|
Coalesced [68] gfx_init_chunky::y#8 ← gfx_init_chunky::y#1
|
|
|
|
Coalesced [69] gfx_init_chunky::gfxbCpuBank#10 ← gfx_init_chunky::gfxbCpuBank#8
|
|
|
|
Coalesced (already) [70] gfx_init_chunky::gfxb#9 ← gfx_init_chunky::gfxb#1
|
|
|
|
Coalesced [71] gfx_init_chunky::x#6 ← gfx_init_chunky::x#1
|
|
|
|
Coalesced (already) [72] gfx_init_chunky::gfxbCpuBank#12 ← gfx_init_chunky::gfxbCpuBank#8
|
|
|
|
Coalesced [73] gfx_init_chunky::gfxb#10 ← gfx_init_chunky::gfxb#3
|
|
|
|
Coalesced (already) [74] gfx_init_chunky::gfxbCpuBank#13 ← gfx_init_chunky::gfxbCpuBank#4
|
2018-04-15 21:32:49 +00:00
|
|
|
Coalesced down to 6 phi equivalence classes
|
2019-05-30 20:29:04 +00:00
|
|
|
Culled Empty Block (label) @8
|
|
|
|
Culled Empty Block (label) main::@3
|
2018-04-15 21:32:49 +00:00
|
|
|
Culled Empty Block (label) main::@18
|
2019-05-30 20:29:04 +00:00
|
|
|
Culled Empty Block (label) gfx_init_chunky::@7
|
|
|
|
Culled Empty Block (label) gfx_init_chunky::@9
|
2018-04-15 21:32:49 +00:00
|
|
|
Culled Empty Block (label) gfx_init_chunky::@10
|
|
|
|
Culled Empty Block (label) gfx_init_chunky::@11
|
|
|
|
Culled Empty Block (label) gfx_init_chunky::@12
|
2019-03-31 15:10:41 +00:00
|
|
|
Renumbering block @7 to @1
|
2019-03-31 15:57:54 +00:00
|
|
|
Renumbering block main::@4 to main::@2
|
|
|
|
Renumbering block main::@6 to main::@3
|
|
|
|
Renumbering block main::@8 to main::@4
|
|
|
|
Renumbering block main::@12 to main::@5
|
2019-03-31 15:10:41 +00:00
|
|
|
Renumbering block main::@17 to main::@6
|
|
|
|
Renumbering block gfx_init_chunky::@8 to gfx_init_chunky::@7
|
2018-04-15 21:32:49 +00:00
|
|
|
Adding NOP phi() at start of @begin
|
2019-03-31 15:10:41 +00:00
|
|
|
Adding NOP phi() at start of @1
|
2018-04-15 21:32:49 +00:00
|
|
|
Adding NOP phi() at start of @end
|
|
|
|
Adding NOP phi() at start of gfx_init_chunky
|
|
|
|
Adding NOP phi() at start of gfx_init_chunky::@6
|
|
|
|
|
|
|
|
FINAL CONTROL FLOW GRAPH
|
|
|
|
@begin: scope:[] from
|
2018-11-11 20:51:36 +00:00
|
|
|
[0] phi()
|
2019-03-31 15:10:41 +00:00
|
|
|
to:@1
|
|
|
|
@1: scope:[] from @begin
|
2018-11-11 20:51:36 +00:00
|
|
|
[1] phi()
|
|
|
|
[2] call main
|
2018-04-15 21:32:49 +00:00
|
|
|
to:@end
|
2019-03-31 15:10:41 +00:00
|
|
|
@end: scope:[] from @1
|
2018-11-11 20:51:36 +00:00
|
|
|
[3] phi()
|
2019-09-18 21:00:30 +00:00
|
|
|
|
|
|
|
(void()) main()
|
2019-03-31 15:10:41 +00:00
|
|
|
main: scope:[main] from @1
|
2018-04-15 21:32:49 +00:00
|
|
|
asm { sei }
|
2019-09-29 18:57:23 +00:00
|
|
|
[5] *((const byte*) PROCPORT_DDR) ← (const byte) PROCPORT_DDR_MEMORY_MASK
|
|
|
|
[6] *((const byte*) PROCPORT) ← (const byte) PROCPORT_RAM_IO
|
2018-11-11 20:51:36 +00:00
|
|
|
[7] call gfx_init_chunky
|
2019-03-31 15:10:41 +00:00
|
|
|
to:main::@6
|
|
|
|
main::@6: scope:[main] from main
|
2019-09-29 18:57:23 +00:00
|
|
|
[8] *((const byte*) DTV_FEATURE) ← (const byte) DTV_FEATURE_ENABLE
|
|
|
|
[9] *((const byte*) DTV_CONTROL) ← (const byte) DTV_HIGHCOLOR|(const byte) DTV_LINEAR|(const byte) DTV_COLORRAM_OFF|(const byte) DTV_CHUNKY|(const byte) DTV_BADLINE_OFF
|
|
|
|
[10] *((const byte*) VIC_CONTROL) ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(byte) 3
|
|
|
|
[11] *((const byte*) VIC_CONTROL2) ← (const byte) VIC_MCM|(const byte) VIC_CSEL
|
|
|
|
[12] *((const byte*) DTV_PLANEB_START_LO) ← (byte) 0
|
|
|
|
[13] *((const byte*) DTV_PLANEB_START_MI) ← >(const byte*) CHUNKY
|
|
|
|
[14] *((const byte*) DTV_PLANEB_START_HI) ← (byte) 0
|
|
|
|
[15] *((const byte*) DTV_PLANEB_STEP) ← (byte) 8
|
|
|
|
[16] *((const byte*) DTV_PLANEB_MODULO_LO) ← (byte) 0
|
|
|
|
[17] *((const byte*) DTV_PLANEB_MODULO_HI) ← (byte) 0
|
|
|
|
[18] *((const byte*) CIA2_PORT_A_DDR) ← (byte) 3
|
|
|
|
[19] *((const byte*) CIA2_PORT_A) ← (byte) 3^(byte)(word)(const byte*) CHUNKY/(word) $4000
|
|
|
|
[20] *((const byte*) VIC_MEMORY) ← (byte) 0
|
2019-03-31 15:57:54 +00:00
|
|
|
to:main::@1
|
|
|
|
main::@1: scope:[main] from main::@1 main::@6
|
2019-05-30 20:29:04 +00:00
|
|
|
[21] (byte) main::j#2 ← phi( main::@1/(byte) main::j#1 main::@6/(byte) 0 )
|
2019-09-29 18:57:23 +00:00
|
|
|
[22] *((const byte*) DTV_PALETTE + (byte) main::j#2) ← (byte) main::j#2
|
2018-11-11 20:51:36 +00:00
|
|
|
[23] (byte) main::j#1 ← ++ (byte) main::j#2
|
2019-05-30 20:29:04 +00:00
|
|
|
[24] if((byte) main::j#1!=(byte) $10) goto main::@1
|
2019-03-31 15:57:54 +00:00
|
|
|
to:main::@2
|
|
|
|
main::@2: scope:[main] from main::@1 main::@5
|
2018-04-15 21:32:49 +00:00
|
|
|
asm { ldx#$ff rff: cpxRASTER bnerff stabilize: nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop cpxRASTER beqeat+0 eat: inx cpx#$08 bnestabilize }
|
2019-09-29 18:57:23 +00:00
|
|
|
[26] *((const byte*) VIC_CONTROL) ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(byte) 3
|
|
|
|
[27] *((const byte*) BORDERCOL) ← (byte) 0
|
2019-03-31 15:10:41 +00:00
|
|
|
to:main::@3
|
2019-03-31 15:57:54 +00:00
|
|
|
main::@3: scope:[main] from main::@2 main::@3
|
2019-09-29 18:57:23 +00:00
|
|
|
[28] if(*((const byte*) RASTER)!=(byte) $42) goto main::@3
|
2019-03-31 15:10:41 +00:00
|
|
|
to:main::@4
|
|
|
|
main::@4: scope:[main] from main::@3
|
2019-03-29 23:15:53 +00:00
|
|
|
asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
|
2019-03-31 15:10:41 +00:00
|
|
|
to:main::@5
|
|
|
|
main::@5: scope:[main] from main::@4 main::@5
|
2019-09-29 18:57:23 +00:00
|
|
|
[30] (byte) main::rst#1 ← *((const byte*) RASTER)
|
2019-11-03 16:05:55 +00:00
|
|
|
[31] (byte~) main::$16 ← (byte) main::rst#1 & (byte) 7
|
|
|
|
[32] (byte~) main::$17 ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL | (byte~) main::$16
|
|
|
|
[33] *((const byte*) VIC_CONTROL) ← (byte~) main::$17
|
|
|
|
[34] (byte~) main::$18 ← (byte) main::rst#1 << (byte) 4
|
|
|
|
[35] *((const byte*) BORDERCOL) ← (byte~) main::$18
|
2018-04-15 21:32:49 +00:00
|
|
|
asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
|
2019-05-30 20:29:04 +00:00
|
|
|
[37] if((byte) main::rst#1!=(byte) $f2) goto main::@5
|
2019-03-31 15:57:54 +00:00
|
|
|
to:main::@2
|
2019-09-18 21:00:30 +00:00
|
|
|
|
|
|
|
(void()) gfx_init_chunky()
|
2018-04-15 21:32:49 +00:00
|
|
|
gfx_init_chunky: scope:[gfx_init_chunky] from main
|
2018-11-11 20:51:36 +00:00
|
|
|
[38] phi()
|
|
|
|
[39] call dtvSetCpuBankSegment1
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@1
|
|
|
|
gfx_init_chunky::@1: scope:[gfx_init_chunky] from gfx_init_chunky gfx_init_chunky::@5
|
2019-09-29 18:57:23 +00:00
|
|
|
[40] (byte) gfx_init_chunky::gfxbCpuBank#7 ← phi( gfx_init_chunky::@5/(byte) gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky/++(byte)(const byte*) CHUNKY/(word) $4000 )
|
2019-05-30 20:29:04 +00:00
|
|
|
[40] (byte) gfx_init_chunky::y#6 ← phi( gfx_init_chunky::@5/(byte) gfx_init_chunky::y#1 gfx_init_chunky/(byte) 0 )
|
|
|
|
[40] (byte*) gfx_init_chunky::gfxb#5 ← phi( gfx_init_chunky::@5/(byte*) gfx_init_chunky::gfxb#1 gfx_init_chunky/(byte*) 16384 )
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@2
|
|
|
|
gfx_init_chunky::@2: scope:[gfx_init_chunky] from gfx_init_chunky::@1 gfx_init_chunky::@3
|
2018-11-11 20:51:36 +00:00
|
|
|
[41] (byte) gfx_init_chunky::gfxbCpuBank#4 ← phi( gfx_init_chunky::@1/(byte) gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::@3/(byte) gfx_init_chunky::gfxbCpuBank#8 )
|
2019-06-02 22:44:46 +00:00
|
|
|
[41] (word) gfx_init_chunky::x#2 ← phi( gfx_init_chunky::@1/(word) 0 gfx_init_chunky::@3/(word) gfx_init_chunky::x#1 )
|
2018-11-11 20:51:36 +00:00
|
|
|
[41] (byte*) gfx_init_chunky::gfxb#3 ← phi( gfx_init_chunky::@1/(byte*) gfx_init_chunky::gfxb#5 gfx_init_chunky::@3/(byte*) gfx_init_chunky::gfxb#1 )
|
2019-05-30 20:29:04 +00:00
|
|
|
[42] if((byte*) gfx_init_chunky::gfxb#3!=(word) $8000) goto gfx_init_chunky::@3
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@4
|
|
|
|
gfx_init_chunky::@4: scope:[gfx_init_chunky] from gfx_init_chunky::@2
|
2018-11-11 20:51:36 +00:00
|
|
|
[43] (byte) dtvSetCpuBankSegment1::cpuBankIdx#1 ← (byte) gfx_init_chunky::gfxbCpuBank#4
|
|
|
|
[44] call dtvSetCpuBankSegment1
|
2019-03-31 15:10:41 +00:00
|
|
|
to:gfx_init_chunky::@7
|
|
|
|
gfx_init_chunky::@7: scope:[gfx_init_chunky] from gfx_init_chunky::@4
|
2018-11-11 20:51:36 +00:00
|
|
|
[45] (byte) gfx_init_chunky::gfxbCpuBank#2 ← ++ (byte) gfx_init_chunky::gfxbCpuBank#4
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@3
|
2019-03-31 15:10:41 +00:00
|
|
|
gfx_init_chunky::@3: scope:[gfx_init_chunky] from gfx_init_chunky::@2 gfx_init_chunky::@7
|
|
|
|
[46] (byte) gfx_init_chunky::gfxbCpuBank#8 ← phi( gfx_init_chunky::@2/(byte) gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::@7/(byte) gfx_init_chunky::gfxbCpuBank#2 )
|
2019-05-30 20:29:04 +00:00
|
|
|
[46] (byte*) gfx_init_chunky::gfxb#4 ← phi( gfx_init_chunky::@2/(byte*) gfx_init_chunky::gfxb#3 gfx_init_chunky::@7/(byte*) 16384 )
|
2019-11-03 16:05:55 +00:00
|
|
|
[47] (word~) gfx_init_chunky::$7 ← (word) gfx_init_chunky::x#2 + (byte) gfx_init_chunky::y#6
|
|
|
|
[48] (byte) gfx_init_chunky::c#0 ← (byte)(word~) gfx_init_chunky::$7
|
2018-11-11 20:51:36 +00:00
|
|
|
[49] *((byte*) gfx_init_chunky::gfxb#4) ← (byte) gfx_init_chunky::c#0
|
|
|
|
[50] (byte*) gfx_init_chunky::gfxb#1 ← ++ (byte*) gfx_init_chunky::gfxb#4
|
|
|
|
[51] (word) gfx_init_chunky::x#1 ← ++ (word) gfx_init_chunky::x#2
|
2019-05-30 20:29:04 +00:00
|
|
|
[52] if((word) gfx_init_chunky::x#1!=(word) $140) goto gfx_init_chunky::@2
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@5
|
|
|
|
gfx_init_chunky::@5: scope:[gfx_init_chunky] from gfx_init_chunky::@3
|
2018-11-11 20:51:36 +00:00
|
|
|
[53] (byte) gfx_init_chunky::y#1 ← ++ (byte) gfx_init_chunky::y#6
|
2019-05-30 20:29:04 +00:00
|
|
|
[54] if((byte) gfx_init_chunky::y#1!=(byte) $33) goto gfx_init_chunky::@1
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@6
|
|
|
|
gfx_init_chunky::@6: scope:[gfx_init_chunky] from gfx_init_chunky::@5
|
2018-11-11 20:51:36 +00:00
|
|
|
[55] phi()
|
|
|
|
[56] call dtvSetCpuBankSegment1
|
2018-04-15 21:32:49 +00:00
|
|
|
to:gfx_init_chunky::@return
|
|
|
|
gfx_init_chunky::@return: scope:[gfx_init_chunky] from gfx_init_chunky::@6
|
2018-11-11 20:51:36 +00:00
|
|
|
[57] return
|
2018-04-15 21:32:49 +00:00
|
|
|
to:@return
|
2019-09-18 21:00:30 +00:00
|
|
|
|
|
|
|
(void()) dtvSetCpuBankSegment1((byte) dtvSetCpuBankSegment1::cpuBankIdx)
|
2018-04-15 21:32:49 +00:00
|
|
|
dtvSetCpuBankSegment1: scope:[dtvSetCpuBankSegment1] from gfx_init_chunky gfx_init_chunky::@4 gfx_init_chunky::@6
|
2019-09-29 18:57:23 +00:00
|
|
|
[58] (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 ← phi( gfx_init_chunky/(byte)(const byte*) CHUNKY/(word) $4000 gfx_init_chunky::@4/(byte) dtvSetCpuBankSegment1::cpuBankIdx#1 gfx_init_chunky::@6/(byte)(number) $4000/(number) $4000 )
|
2019-09-29 20:36:00 +00:00
|
|
|
[59] *((const byte*) dtvSetCpuBankSegment1::cpuBank) ← (byte) dtvSetCpuBankSegment1::cpuBankIdx#3
|
2018-04-15 21:32:49 +00:00
|
|
|
asm { .byte$32,$dd lda$ff .byte$32,$00 }
|
|
|
|
to:dtvSetCpuBankSegment1::@return
|
|
|
|
dtvSetCpuBankSegment1::@return: scope:[dtvSetCpuBankSegment1] from dtvSetCpuBankSegment1
|
2018-11-11 20:51:36 +00:00
|
|
|
[61] return
|
2018-04-15 21:32:49 +00:00
|
|
|
to:@return
|
|
|
|
|
|
|
|
|
|
|
|
VARIABLE REGISTER WEIGHTS
|
|
|
|
(void()) dtvSetCpuBankSegment1((byte) dtvSetCpuBankSegment1::cpuBankIdx)
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#1 202.0
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#3 103.0
|
|
|
|
(void()) gfx_init_chunky()
|
2019-11-03 16:05:55 +00:00
|
|
|
(word~) gfx_init_chunky::$7 101.0
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) gfx_init_chunky::c
|
|
|
|
(byte) gfx_init_chunky::c#0 202.0
|
|
|
|
(byte*) gfx_init_chunky::gfxb
|
|
|
|
(byte*) gfx_init_chunky::gfxb#1 42.599999999999994
|
|
|
|
(byte*) gfx_init_chunky::gfxb#3 157.0
|
|
|
|
(byte*) gfx_init_chunky::gfxb#4 75.75
|
|
|
|
(byte*) gfx_init_chunky::gfxb#5 22.0
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#2 202.0
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#4 103.75
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#7 22.0
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#8 34.888888888888886
|
|
|
|
(word) gfx_init_chunky::x
|
|
|
|
(word) gfx_init_chunky::x#1 151.5
|
|
|
|
(word) gfx_init_chunky::x#2 30.299999999999997
|
|
|
|
(byte) gfx_init_chunky::y
|
|
|
|
(byte) gfx_init_chunky::y#1 16.5
|
|
|
|
(byte) gfx_init_chunky::y#6 9.461538461538462
|
|
|
|
(void()) main()
|
2019-11-03 16:05:55 +00:00
|
|
|
(byte~) main::$16 202.0
|
|
|
|
(byte~) main::$17 202.0
|
|
|
|
(byte~) main::$18 202.0
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) main::j
|
|
|
|
(byte) main::j#1 16.5
|
|
|
|
(byte) main::j#2 22.0
|
|
|
|
(byte) main::rst
|
|
|
|
(byte) main::rst#1 57.714285714285715
|
|
|
|
|
|
|
|
Initial phi equivalence classes
|
|
|
|
[ main::j#2 main::j#1 ]
|
|
|
|
[ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
[ gfx_init_chunky::x#2 gfx_init_chunky::x#1 ]
|
|
|
|
[ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ]
|
|
|
|
[ gfx_init_chunky::gfxb#4 gfx_init_chunky::gfxb#3 gfx_init_chunky::gfxb#5 gfx_init_chunky::gfxb#1 ]
|
|
|
|
[ dtvSetCpuBankSegment1::cpuBankIdx#3 dtvSetCpuBankSegment1::cpuBankIdx#1 ]
|
|
|
|
Added variable main::rst#1 to zero page equivalence class [ main::rst#1 ]
|
2019-11-03 16:05:55 +00:00
|
|
|
Added variable main::$16 to zero page equivalence class [ main::$16 ]
|
|
|
|
Added variable main::$17 to zero page equivalence class [ main::$17 ]
|
|
|
|
Added variable main::$18 to zero page equivalence class [ main::$18 ]
|
|
|
|
Added variable gfx_init_chunky::$7 to zero page equivalence class [ gfx_init_chunky::$7 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
Added variable gfx_init_chunky::c#0 to zero page equivalence class [ gfx_init_chunky::c#0 ]
|
|
|
|
Complete equivalence classes
|
|
|
|
[ main::j#2 main::j#1 ]
|
|
|
|
[ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
[ gfx_init_chunky::x#2 gfx_init_chunky::x#1 ]
|
|
|
|
[ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ]
|
|
|
|
[ gfx_init_chunky::gfxb#4 gfx_init_chunky::gfxb#3 gfx_init_chunky::gfxb#5 gfx_init_chunky::gfxb#1 ]
|
|
|
|
[ dtvSetCpuBankSegment1::cpuBankIdx#3 dtvSetCpuBankSegment1::cpuBankIdx#1 ]
|
|
|
|
[ main::rst#1 ]
|
2019-11-03 16:05:55 +00:00
|
|
|
[ main::$16 ]
|
|
|
|
[ main::$17 ]
|
|
|
|
[ main::$18 ]
|
|
|
|
[ gfx_init_chunky::$7 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
[ gfx_init_chunky::c#0 ]
|
2019-10-12 09:40:36 +00:00
|
|
|
Allocated zp[1]:2 [ main::j#2 main::j#1 ]
|
|
|
|
Allocated zp[1]:3 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
Allocated zp[2]:4 [ gfx_init_chunky::x#2 gfx_init_chunky::x#1 ]
|
|
|
|
Allocated zp[1]:6 [ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ]
|
|
|
|
Allocated zp[2]:7 [ gfx_init_chunky::gfxb#4 gfx_init_chunky::gfxb#3 gfx_init_chunky::gfxb#5 gfx_init_chunky::gfxb#1 ]
|
|
|
|
Allocated zp[1]:9 [ dtvSetCpuBankSegment1::cpuBankIdx#3 dtvSetCpuBankSegment1::cpuBankIdx#1 ]
|
|
|
|
Allocated zp[1]:10 [ main::rst#1 ]
|
2019-11-03 16:05:55 +00:00
|
|
|
Allocated zp[1]:11 [ main::$16 ]
|
|
|
|
Allocated zp[1]:12 [ main::$17 ]
|
|
|
|
Allocated zp[1]:13 [ main::$18 ]
|
|
|
|
Allocated zp[2]:14 [ gfx_init_chunky::$7 ]
|
2019-10-12 09:40:36 +00:00
|
|
|
Allocated zp[1]:16 [ gfx_init_chunky::c#0 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
|
|
|
|
INITIAL ASM
|
2019-09-08 00:29:17 +00:00
|
|
|
Target platform is c64basic / MOS6502X
|
2019-07-08 14:43:09 +00:00
|
|
|
// File Comments
|
2019-02-17 23:12:29 +00:00
|
|
|
// C64DTV 8bpp charmode stretcher
|
2019-07-25 15:06:17 +00:00
|
|
|
// Upstart
|
2018-04-15 21:32:49 +00:00
|
|
|
.pc = $801 "Basic"
|
2019-09-29 21:13:37 +00:00
|
|
|
:BasicUpstart(__bbegin)
|
2018-04-15 21:32:49 +00:00
|
|
|
.pc = $80d "Program"
|
2019-07-08 14:43:09 +00:00
|
|
|
// Global Constants & labels
|
2019-02-17 23:12:29 +00:00
|
|
|
// Processor port data direction register
|
2018-04-15 21:32:49 +00:00
|
|
|
.label PROCPORT_DDR = 0
|
2019-02-17 23:12:29 +00:00
|
|
|
// Mask for PROCESSOR_PORT_DDR which allows only memory configuration to be written
|
2018-04-15 21:32:49 +00:00
|
|
|
.const PROCPORT_DDR_MEMORY_MASK = 7
|
2019-02-17 23:12:29 +00:00
|
|
|
// Processor Port Register controlling RAM/ROM configuration and the datasette
|
2018-04-15 21:32:49 +00:00
|
|
|
.label PROCPORT = 1
|
2019-02-17 23:12:29 +00:00
|
|
|
// RAM in $A000, $E000 I/O in $D000
|
2019-07-30 13:01:43 +00:00
|
|
|
.const PROCPORT_RAM_IO = 5
|
2018-04-15 21:32:49 +00:00
|
|
|
.label RASTER = $d012
|
|
|
|
.label BORDERCOL = $d020
|
|
|
|
.label VIC_CONTROL = $d011
|
|
|
|
.const VIC_ECM = $40
|
|
|
|
.const VIC_DEN = $10
|
|
|
|
.const VIC_RSEL = 8
|
|
|
|
.label VIC_CONTROL2 = $d016
|
|
|
|
.const VIC_MCM = $10
|
|
|
|
.const VIC_CSEL = 8
|
|
|
|
.label VIC_MEMORY = $d018
|
2019-02-17 23:12:29 +00:00
|
|
|
// CIA#2 Port A: Serial bus, RS-232, VIC memory bank
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CIA2_PORT_A = $dd00
|
2019-02-17 23:12:29 +00:00
|
|
|
// CIA #2 Port A data direction register.
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CIA2_PORT_A_DDR = $dd02
|
2019-02-17 23:12:29 +00:00
|
|
|
// Feature enables or disables the extra C64 DTV features
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_FEATURE = $d03f
|
|
|
|
.const DTV_FEATURE_ENABLE = 1
|
2019-02-17 23:12:29 +00:00
|
|
|
// Controls the graphics modes of the C64 DTV
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_CONTROL = $d03c
|
|
|
|
.const DTV_LINEAR = 1
|
|
|
|
.const DTV_HIGHCOLOR = 4
|
|
|
|
.const DTV_COLORRAM_OFF = $10
|
|
|
|
.const DTV_BADLINE_OFF = $20
|
|
|
|
.const DTV_CHUNKY = $40
|
2019-02-17 23:12:29 +00:00
|
|
|
// Defines colors for the 16 first colors ($00-$0f)
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_PALETTE = $d200
|
2019-02-17 23:12:29 +00:00
|
|
|
// Linear Graphics Plane B Counter Control
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_PLANEB_START_LO = $d049
|
|
|
|
.label DTV_PLANEB_START_MI = $d04a
|
|
|
|
.label DTV_PLANEB_START_HI = $d04b
|
|
|
|
.label DTV_PLANEB_STEP = $d04c
|
|
|
|
.label DTV_PLANEB_MODULO_LO = $d047
|
|
|
|
.label DTV_PLANEB_MODULO_HI = $d048
|
2019-02-17 23:12:29 +00:00
|
|
|
// Plane with all pixels
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CHUNKY = $8000
|
2019-07-08 14:43:09 +00:00
|
|
|
// @begin
|
2019-09-29 21:13:37 +00:00
|
|
|
__bbegin:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [1] phi from @begin to @1 [phi:@begin->@1]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1_from___bbegin:
|
|
|
|
jmp __b1
|
2019-07-08 14:43:09 +00:00
|
|
|
// @1
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [2] call main
|
2018-04-15 21:32:49 +00:00
|
|
|
jsr main
|
2019-07-08 14:43:09 +00:00
|
|
|
// [3] phi from @1 to @end [phi:@1->@end]
|
2019-09-29 21:13:37 +00:00
|
|
|
__bend_from___b1:
|
|
|
|
jmp __bend
|
2019-07-08 14:43:09 +00:00
|
|
|
// @end
|
2019-09-29 21:13:37 +00:00
|
|
|
__bend:
|
2019-07-08 14:43:09 +00:00
|
|
|
// main
|
2018-04-15 21:32:49 +00:00
|
|
|
main: {
|
2019-11-03 16:05:55 +00:00
|
|
|
.label __16 = $b
|
|
|
|
.label __17 = $c
|
|
|
|
.label __18 = $d
|
2018-04-15 21:32:49 +00:00
|
|
|
.label j = 2
|
|
|
|
.label rst = $a
|
2019-07-08 14:43:09 +00:00
|
|
|
// asm { sei }
|
2018-04-15 21:32:49 +00:00
|
|
|
sei
|
2019-09-29 18:57:23 +00:00
|
|
|
// [5] *((const byte*) PROCPORT_DDR) ← (const byte) PROCPORT_DDR_MEMORY_MASK -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Disable normal interrupt (prevent keyboard reading glitches and allows to hide basic/kernal)
|
|
|
|
// Disable kernal & basic
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #PROCPORT_DDR_MEMORY_MASK
|
|
|
|
sta PROCPORT_DDR
|
2019-09-29 18:57:23 +00:00
|
|
|
// [6] *((const byte*) PROCPORT) ← (const byte) PROCPORT_RAM_IO -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #PROCPORT_RAM_IO
|
|
|
|
sta PROCPORT
|
2019-07-08 14:43:09 +00:00
|
|
|
// [7] call gfx_init_chunky
|
|
|
|
// [38] phi from main to gfx_init_chunky [phi:main->gfx_init_chunky]
|
2018-04-15 21:32:49 +00:00
|
|
|
gfx_init_chunky_from_main:
|
|
|
|
jsr gfx_init_chunky
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b6
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@6
|
2019-09-29 21:13:37 +00:00
|
|
|
__b6:
|
2019-09-29 18:57:23 +00:00
|
|
|
// [8] *((const byte*) DTV_FEATURE) ← (const byte) DTV_FEATURE_ENABLE -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Enable DTV extended modes
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #DTV_FEATURE_ENABLE
|
|
|
|
sta DTV_FEATURE
|
2019-09-29 18:57:23 +00:00
|
|
|
// [9] *((const byte*) DTV_CONTROL) ← (const byte) DTV_HIGHCOLOR|(const byte) DTV_LINEAR|(const byte) DTV_COLORRAM_OFF|(const byte) DTV_CHUNKY|(const byte) DTV_BADLINE_OFF -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// 8BPP Pixel Cell Mode
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #DTV_HIGHCOLOR|DTV_LINEAR|DTV_COLORRAM_OFF|DTV_CHUNKY|DTV_BADLINE_OFF
|
|
|
|
sta DTV_CONTROL
|
2019-09-29 18:57:23 +00:00
|
|
|
// [10] *((const byte*) VIC_CONTROL) ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(byte) 3 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_DEN|VIC_ECM|VIC_RSEL|3
|
|
|
|
sta VIC_CONTROL
|
2019-09-29 18:57:23 +00:00
|
|
|
// [11] *((const byte*) VIC_CONTROL2) ← (const byte) VIC_MCM|(const byte) VIC_CSEL -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_MCM|VIC_CSEL
|
|
|
|
sta VIC_CONTROL2
|
2019-09-29 18:57:23 +00:00
|
|
|
// [12] *((const byte*) DTV_PLANEB_START_LO) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Plane B: CHUNKY
|
2019-05-30 20:29:04 +00:00
|
|
|
lda #0
|
2018-04-15 21:32:49 +00:00
|
|
|
sta DTV_PLANEB_START_LO
|
2019-09-29 18:57:23 +00:00
|
|
|
// [13] *((const byte*) DTV_PLANEB_START_MI) ← >(const byte*) CHUNKY -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #>CHUNKY
|
|
|
|
sta DTV_PLANEB_START_MI
|
2019-09-29 18:57:23 +00:00
|
|
|
// [14] *((const byte*) DTV_PLANEB_START_HI) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta DTV_PLANEB_START_HI
|
2019-09-29 18:57:23 +00:00
|
|
|
// [15] *((const byte*) DTV_PLANEB_STEP) ← (byte) 8 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #8
|
|
|
|
sta DTV_PLANEB_STEP
|
2019-09-29 18:57:23 +00:00
|
|
|
// [16] *((const byte*) DTV_PLANEB_MODULO_LO) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta DTV_PLANEB_MODULO_LO
|
2019-09-29 18:57:23 +00:00
|
|
|
// [17] *((const byte*) DTV_PLANEB_MODULO_HI) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta DTV_PLANEB_MODULO_HI
|
2019-09-29 18:57:23 +00:00
|
|
|
// [18] *((const byte*) CIA2_PORT_A_DDR) ← (byte) 3 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// VIC Graphics Bank
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #3
|
|
|
|
sta CIA2_PORT_A_DDR
|
2019-09-29 18:57:23 +00:00
|
|
|
// [19] *((const byte*) CIA2_PORT_A) ← (byte) 3^(byte)(word)(const byte*) CHUNKY/(word) $4000 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set VIC Bank bits to output - all others to input
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #3^CHUNKY/$4000
|
|
|
|
sta CIA2_PORT_A
|
2019-09-29 18:57:23 +00:00
|
|
|
// [20] *((const byte*) VIC_MEMORY) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set VIC Bank
|
|
|
|
// VIC memory
|
2019-05-30 20:29:04 +00:00
|
|
|
lda #0
|
2018-04-15 21:32:49 +00:00
|
|
|
sta VIC_MEMORY
|
2019-07-08 14:43:09 +00:00
|
|
|
// [21] phi from main::@6 to main::@1 [phi:main::@6->main::@1]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1_from___b6:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [21] phi (byte) main::j#2 = (byte) 0 [phi:main::@6->main::@1#0] -- vbuz1=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z j
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b1
|
2019-02-17 23:12:29 +00:00
|
|
|
// DTV Palette - Grey Tones
|
2019-07-08 14:43:09 +00:00
|
|
|
// [21] phi from main::@1 to main::@1 [phi:main::@1->main::@1]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1_from___b1:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [21] phi (byte) main::j#2 = (byte) main::j#1 [phi:main::@1->main::@1#0] -- register_copy
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b1
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@1
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1:
|
2019-09-29 18:57:23 +00:00
|
|
|
// [22] *((const byte*) DTV_PALETTE + (byte) main::j#2) ← (byte) main::j#2 -- pbuc1_derefidx_vbuz1=vbuz1
|
2019-08-07 19:00:19 +00:00
|
|
|
ldy.z j
|
2018-04-15 21:32:49 +00:00
|
|
|
tya
|
|
|
|
sta DTV_PALETTE,y
|
2019-07-08 14:43:09 +00:00
|
|
|
// [23] (byte) main::j#1 ← ++ (byte) main::j#2 -- vbuz1=_inc_vbuz1
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z j
|
2019-07-08 14:43:09 +00:00
|
|
|
// [24] if((byte) main::j#1!=(byte) $10) goto main::@1 -- vbuz1_neq_vbuc1_then_la1
|
2019-03-26 22:49:44 +00:00
|
|
|
lda #$10
|
2019-08-07 19:00:19 +00:00
|
|
|
cmp.z j
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b1_from___b1
|
|
|
|
jmp __b2
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@2
|
2019-09-29 21:13:37 +00:00
|
|
|
__b2:
|
2019-07-08 14:43:09 +00:00
|
|
|
// asm { ldx#$ff rff: cpxRASTER bnerff stabilize: nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop cpxRASTER beqeat+0 eat: inx cpx#$08 bnestabilize }
|
2019-02-17 23:12:29 +00:00
|
|
|
// Stabilize Raster
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx #$ff
|
|
|
|
rff:
|
|
|
|
cpx RASTER
|
|
|
|
bne rff
|
|
|
|
stabilize:
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
cpx RASTER
|
|
|
|
beq eat+0
|
|
|
|
eat:
|
|
|
|
inx
|
|
|
|
cpx #8
|
|
|
|
bne stabilize
|
2019-09-29 18:57:23 +00:00
|
|
|
// [26] *((const byte*) VIC_CONTROL) ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(byte) 3 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_DEN|VIC_ECM|VIC_RSEL|3
|
|
|
|
sta VIC_CONTROL
|
2019-09-29 18:57:23 +00:00
|
|
|
// [27] *((const byte*) BORDERCOL) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta BORDERCOL
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b3
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@3
|
2019-09-29 21:13:37 +00:00
|
|
|
__b3:
|
2019-09-29 18:57:23 +00:00
|
|
|
// [28] if(*((const byte*) RASTER)!=(byte) $42) goto main::@3 -- _deref_pbuc1_neq_vbuc2_then_la1
|
2019-03-26 22:49:44 +00:00
|
|
|
lda #$42
|
|
|
|
cmp RASTER
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b3
|
|
|
|
jmp __b4
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@4
|
2019-09-29 21:13:37 +00:00
|
|
|
__b4:
|
2019-07-08 14:43:09 +00:00
|
|
|
// asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
|
2018-04-15 21:32:49 +00:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b5
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@5
|
2019-09-29 21:13:37 +00:00
|
|
|
__b5:
|
2019-09-29 18:57:23 +00:00
|
|
|
// [30] (byte) main::rst#1 ← *((const byte*) RASTER) -- vbuz1=_deref_pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda RASTER
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z rst
|
2019-11-03 16:05:55 +00:00
|
|
|
// [31] (byte~) main::$16 ← (byte) main::rst#1 & (byte) 7 -- vbuz1=vbuz2_band_vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #7
|
2019-08-07 19:00:19 +00:00
|
|
|
and.z rst
|
2019-11-03 16:05:55 +00:00
|
|
|
sta.z __16
|
|
|
|
// [32] (byte~) main::$17 ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL | (byte~) main::$16 -- vbuz1=vbuc1_bor_vbuz2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_DEN|VIC_ECM|VIC_RSEL
|
2019-11-03 16:05:55 +00:00
|
|
|
ora.z __16
|
|
|
|
sta.z __17
|
|
|
|
// [33] *((const byte*) VIC_CONTROL) ← (byte~) main::$17 -- _deref_pbuc1=vbuz1
|
|
|
|
lda.z __17
|
2018-04-15 21:32:49 +00:00
|
|
|
sta VIC_CONTROL
|
2019-11-03 16:05:55 +00:00
|
|
|
// [34] (byte~) main::$18 ← (byte) main::rst#1 << (byte) 4 -- vbuz1=vbuz2_rol_4
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z rst
|
2018-04-15 21:32:49 +00:00
|
|
|
asl
|
|
|
|
asl
|
|
|
|
asl
|
|
|
|
asl
|
2019-11-03 16:05:55 +00:00
|
|
|
sta.z __18
|
|
|
|
// [35] *((const byte*) BORDERCOL) ← (byte~) main::$18 -- _deref_pbuc1=vbuz1
|
|
|
|
lda.z __18
|
2018-04-15 21:32:49 +00:00
|
|
|
sta BORDERCOL
|
2019-07-08 14:43:09 +00:00
|
|
|
// asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
|
2018-04-15 21:32:49 +00:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2019-07-08 14:43:09 +00:00
|
|
|
// [37] if((byte) main::rst#1!=(byte) $f2) goto main::@5 -- vbuz1_neq_vbuc1_then_la1
|
2019-03-26 22:49:44 +00:00
|
|
|
lda #$f2
|
2019-08-07 19:00:19 +00:00
|
|
|
cmp.z rst
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b5
|
|
|
|
jmp __b2
|
2018-04-15 21:32:49 +00:00
|
|
|
}
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky
|
2019-02-17 23:12:29 +00:00
|
|
|
// Initialize Plane with 8bpp chunky
|
2018-04-15 21:32:49 +00:00
|
|
|
gfx_init_chunky: {
|
2019-11-03 16:05:55 +00:00
|
|
|
.label __7 = $e
|
2018-04-15 21:32:49 +00:00
|
|
|
.label c = $10
|
|
|
|
.label gfxb = 7
|
|
|
|
.label x = 4
|
|
|
|
.label gfxbCpuBank = 6
|
|
|
|
.label y = 3
|
2019-07-08 14:43:09 +00:00
|
|
|
// [39] call dtvSetCpuBankSegment1
|
|
|
|
// [58] phi from gfx_init_chunky to dtvSetCpuBankSegment1 [phi:gfx_init_chunky->dtvSetCpuBankSegment1]
|
2018-04-15 21:32:49 +00:00
|
|
|
dtvSetCpuBankSegment1_from_gfx_init_chunky:
|
2019-09-29 18:57:23 +00:00
|
|
|
// [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = (byte)(const byte*) CHUNKY/(word) $4000 [phi:gfx_init_chunky->dtvSetCpuBankSegment1#0] -- vbuz1=vbuc1
|
2019-05-30 20:29:04 +00:00
|
|
|
lda #CHUNKY/$4000
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z dtvSetCpuBankSegment1.cpuBankIdx
|
2018-04-15 21:32:49 +00:00
|
|
|
jsr dtvSetCpuBankSegment1
|
2019-07-08 14:43:09 +00:00
|
|
|
// [40] phi from gfx_init_chunky to gfx_init_chunky::@1 [phi:gfx_init_chunky->gfx_init_chunky::@1]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1_from_gfx_init_chunky:
|
2019-09-29 18:57:23 +00:00
|
|
|
// [40] phi (byte) gfx_init_chunky::gfxbCpuBank#7 = ++(byte)(const byte*) CHUNKY/(word) $4000 [phi:gfx_init_chunky->gfx_init_chunky::@1#0] -- vbuz1=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #($ff&CHUNKY/$4000)+1
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z gfxbCpuBank
|
2019-07-08 14:43:09 +00:00
|
|
|
// [40] phi (byte) gfx_init_chunky::y#6 = (byte) 0 [phi:gfx_init_chunky->gfx_init_chunky::@1#1] -- vbuz1=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z y
|
2019-07-08 14:43:09 +00:00
|
|
|
// [40] phi (byte*) gfx_init_chunky::gfxb#5 = (byte*) 16384 [phi:gfx_init_chunky->gfx_init_chunky::@1#2] -- pbuz1=pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #<$4000
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z gfxb
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #>$4000
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z gfxb+1
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b1
|
2019-07-08 14:43:09 +00:00
|
|
|
// [40] phi from gfx_init_chunky::@5 to gfx_init_chunky::@1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1_from___b5:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [40] phi (byte) gfx_init_chunky::gfxbCpuBank#7 = (byte) gfx_init_chunky::gfxbCpuBank#8 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#0] -- register_copy
|
|
|
|
// [40] phi (byte) gfx_init_chunky::y#6 = (byte) gfx_init_chunky::y#1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#1] -- register_copy
|
|
|
|
// [40] phi (byte*) gfx_init_chunky::gfxb#5 = (byte*) gfx_init_chunky::gfxb#1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#2] -- register_copy
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b1
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@1
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [41] phi from gfx_init_chunky::@1 to gfx_init_chunky::@2 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b2_from___b1:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [41] phi (byte) gfx_init_chunky::gfxbCpuBank#4 = (byte) gfx_init_chunky::gfxbCpuBank#7 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#0] -- register_copy
|
|
|
|
// [41] phi (word) gfx_init_chunky::x#2 = (word) 0 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#1] -- vwuz1=vwuc1
|
2019-06-02 22:44:46 +00:00
|
|
|
lda #<0
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z x
|
2019-06-02 22:44:46 +00:00
|
|
|
lda #>0
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z x+1
|
2019-07-08 14:43:09 +00:00
|
|
|
// [41] phi (byte*) gfx_init_chunky::gfxb#3 = (byte*) gfx_init_chunky::gfxb#5 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#2] -- register_copy
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b2
|
2019-07-08 14:43:09 +00:00
|
|
|
// [41] phi from gfx_init_chunky::@3 to gfx_init_chunky::@2 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b2_from___b3:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [41] phi (byte) gfx_init_chunky::gfxbCpuBank#4 = (byte) gfx_init_chunky::gfxbCpuBank#8 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#0] -- register_copy
|
|
|
|
// [41] phi (word) gfx_init_chunky::x#2 = (word) gfx_init_chunky::x#1 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#1] -- register_copy
|
|
|
|
// [41] phi (byte*) gfx_init_chunky::gfxb#3 = (byte*) gfx_init_chunky::gfxb#1 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#2] -- register_copy
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b2
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@2
|
2019-09-29 21:13:37 +00:00
|
|
|
__b2:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [42] if((byte*) gfx_init_chunky::gfxb#3!=(word) $8000) goto gfx_init_chunky::@3 -- pbuz1_neq_vwuc1_then_la1
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z gfxb+1
|
2018-04-15 21:32:49 +00:00
|
|
|
cmp #>$8000
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b3_from___b2
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z gfxb
|
2018-04-15 21:32:49 +00:00
|
|
|
cmp #<$8000
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b3_from___b2
|
|
|
|
jmp __b4
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@4
|
2019-09-29 21:13:37 +00:00
|
|
|
__b4:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [43] (byte) dtvSetCpuBankSegment1::cpuBankIdx#1 ← (byte) gfx_init_chunky::gfxbCpuBank#4 -- vbuz1=vbuz2
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z gfxbCpuBank
|
|
|
|
sta.z dtvSetCpuBankSegment1.cpuBankIdx
|
2019-07-08 14:43:09 +00:00
|
|
|
// [44] call dtvSetCpuBankSegment1
|
|
|
|
// [58] phi from gfx_init_chunky::@4 to dtvSetCpuBankSegment1 [phi:gfx_init_chunky::@4->dtvSetCpuBankSegment1]
|
2019-09-29 21:13:37 +00:00
|
|
|
dtvSetCpuBankSegment1_from___b4:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = (byte) dtvSetCpuBankSegment1::cpuBankIdx#1 [phi:gfx_init_chunky::@4->dtvSetCpuBankSegment1#0] -- register_copy
|
2018-04-15 21:32:49 +00:00
|
|
|
jsr dtvSetCpuBankSegment1
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b7
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@7
|
2019-09-29 21:13:37 +00:00
|
|
|
__b7:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [45] (byte) gfx_init_chunky::gfxbCpuBank#2 ← ++ (byte) gfx_init_chunky::gfxbCpuBank#4 -- vbuz1=_inc_vbuz1
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z gfxbCpuBank
|
2019-07-08 14:43:09 +00:00
|
|
|
// [46] phi from gfx_init_chunky::@7 to gfx_init_chunky::@3 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b3_from___b7:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [46] phi (byte) gfx_init_chunky::gfxbCpuBank#8 = (byte) gfx_init_chunky::gfxbCpuBank#2 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3#0] -- register_copy
|
|
|
|
// [46] phi (byte*) gfx_init_chunky::gfxb#4 = (byte*) 16384 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3#1] -- pbuz1=pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #<$4000
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z gfxb
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #>$4000
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z gfxb+1
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b3
|
2019-07-08 14:43:09 +00:00
|
|
|
// [46] phi from gfx_init_chunky::@2 to gfx_init_chunky::@3 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b3_from___b2:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [46] phi (byte) gfx_init_chunky::gfxbCpuBank#8 = (byte) gfx_init_chunky::gfxbCpuBank#4 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3#0] -- register_copy
|
|
|
|
// [46] phi (byte*) gfx_init_chunky::gfxb#4 = (byte*) gfx_init_chunky::gfxb#3 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3#1] -- register_copy
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b3
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@3
|
2019-09-29 21:13:37 +00:00
|
|
|
__b3:
|
2019-11-03 16:05:55 +00:00
|
|
|
// [47] (word~) gfx_init_chunky::$7 ← (word) gfx_init_chunky::x#2 + (byte) gfx_init_chunky::y#6 -- vwuz1=vwuz2_plus_vbuz3
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z y
|
2018-04-15 21:32:49 +00:00
|
|
|
clc
|
2019-08-07 19:00:19 +00:00
|
|
|
adc.z x
|
2019-11-03 16:05:55 +00:00
|
|
|
sta.z __7
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
2019-08-07 19:00:19 +00:00
|
|
|
adc.z x+1
|
2019-11-03 16:05:55 +00:00
|
|
|
sta.z __7+1
|
|
|
|
// [48] (byte) gfx_init_chunky::c#0 ← (byte)(word~) gfx_init_chunky::$7 -- vbuz1=_byte_vwuz2
|
|
|
|
lda.z __7
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z c
|
2019-07-08 14:43:09 +00:00
|
|
|
// [49] *((byte*) gfx_init_chunky::gfxb#4) ← (byte) gfx_init_chunky::c#0 -- _deref_pbuz1=vbuz2
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z c
|
2018-04-15 21:32:49 +00:00
|
|
|
ldy #0
|
|
|
|
sta (gfxb),y
|
2019-07-08 14:43:09 +00:00
|
|
|
// [50] (byte*) gfx_init_chunky::gfxb#1 ← ++ (byte*) gfx_init_chunky::gfxb#4 -- pbuz1=_inc_pbuz1
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z gfxb
|
2018-04-15 21:32:49 +00:00
|
|
|
bne !+
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z gfxb+1
|
2018-04-15 21:32:49 +00:00
|
|
|
!:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [51] (word) gfx_init_chunky::x#1 ← ++ (word) gfx_init_chunky::x#2 -- vwuz1=_inc_vwuz1
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z x
|
2018-04-15 21:32:49 +00:00
|
|
|
bne !+
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z x+1
|
2018-04-15 21:32:49 +00:00
|
|
|
!:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [52] if((word) gfx_init_chunky::x#1!=(word) $140) goto gfx_init_chunky::@2 -- vwuz1_neq_vwuc1_then_la1
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z x+1
|
2018-04-15 21:32:49 +00:00
|
|
|
cmp #>$140
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b2_from___b3
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z x
|
2018-04-15 21:32:49 +00:00
|
|
|
cmp #<$140
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b2_from___b3
|
|
|
|
jmp __b5
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@5
|
2019-09-29 21:13:37 +00:00
|
|
|
__b5:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [53] (byte) gfx_init_chunky::y#1 ← ++ (byte) gfx_init_chunky::y#6 -- vbuz1=_inc_vbuz1
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z y
|
2019-07-08 14:43:09 +00:00
|
|
|
// [54] if((byte) gfx_init_chunky::y#1!=(byte) $33) goto gfx_init_chunky::@1 -- vbuz1_neq_vbuc1_then_la1
|
2019-03-26 22:49:44 +00:00
|
|
|
lda #$33
|
2019-08-07 19:00:19 +00:00
|
|
|
cmp.z y
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b1_from___b5
|
2019-07-08 14:43:09 +00:00
|
|
|
// [55] phi from gfx_init_chunky::@5 to gfx_init_chunky::@6 [phi:gfx_init_chunky::@5->gfx_init_chunky::@6]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b6_from___b5:
|
|
|
|
jmp __b6
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@6
|
2019-09-29 21:13:37 +00:00
|
|
|
__b6:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [56] call dtvSetCpuBankSegment1
|
|
|
|
// [58] phi from gfx_init_chunky::@6 to dtvSetCpuBankSegment1 [phi:gfx_init_chunky::@6->dtvSetCpuBankSegment1]
|
2019-09-29 21:13:37 +00:00
|
|
|
dtvSetCpuBankSegment1_from___b6:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = (byte)(number) $4000/(number) $4000 [phi:gfx_init_chunky::@6->dtvSetCpuBankSegment1#0] -- vbuz1=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #$4000/$4000
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z dtvSetCpuBankSegment1.cpuBankIdx
|
2018-04-15 21:32:49 +00:00
|
|
|
jsr dtvSetCpuBankSegment1
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __breturn
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@return
|
2019-09-29 21:13:37 +00:00
|
|
|
__breturn:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [57] return
|
2018-04-15 21:32:49 +00:00
|
|
|
rts
|
|
|
|
}
|
2019-07-08 14:43:09 +00:00
|
|
|
// dtvSetCpuBankSegment1
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set the memory pointed to by CPU BANK 1 SEGMENT ($4000-$7fff)
|
|
|
|
// This sets which actual memory is addressed when the CPU reads/writes to $4000-$7fff
|
|
|
|
// The actual memory addressed will be $4000*cpuSegmentIdx
|
2019-02-19 19:51:48 +00:00
|
|
|
// dtvSetCpuBankSegment1(byte zeropage(9) cpuBankIdx)
|
2018-04-15 21:32:49 +00:00
|
|
|
dtvSetCpuBankSegment1: {
|
2019-02-17 23:12:29 +00:00
|
|
|
// Move CPU BANK 1 SEGMENT ($4000-$7fff)
|
2018-04-15 21:32:49 +00:00
|
|
|
.label cpuBank = $ff
|
|
|
|
.label cpuBankIdx = 9
|
2019-09-29 20:36:00 +00:00
|
|
|
// [59] *((const byte*) dtvSetCpuBankSegment1::cpuBank) ← (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 -- _deref_pbuc1=vbuz1
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z cpuBankIdx
|
2018-04-15 21:32:49 +00:00
|
|
|
sta cpuBank
|
2019-07-08 14:43:09 +00:00
|
|
|
// asm { .byte$32,$dd lda$ff .byte$32,$00 }
|
2018-04-15 21:32:49 +00:00
|
|
|
.byte $32, $dd
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z $ff
|
2018-04-15 21:32:49 +00:00
|
|
|
.byte $32, $00
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __breturn
|
2019-07-08 14:43:09 +00:00
|
|
|
// dtvSetCpuBankSegment1::@return
|
2019-09-29 21:13:37 +00:00
|
|
|
__breturn:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [61] return
|
2018-04-15 21:32:49 +00:00
|
|
|
rts
|
|
|
|
}
|
2019-07-08 14:43:09 +00:00
|
|
|
// File Data
|
2018-04-15 21:32:49 +00:00
|
|
|
|
|
|
|
REGISTER UPLIFT POTENTIAL REGISTERS
|
2019-09-29 18:57:23 +00:00
|
|
|
Statement [5] *((const byte*) PROCPORT_DDR) ← (const byte) PROCPORT_DDR_MEMORY_MASK [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [6] *((const byte*) PROCPORT) ← (const byte) PROCPORT_RAM_IO [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [8] *((const byte*) DTV_FEATURE) ← (const byte) DTV_FEATURE_ENABLE [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [9] *((const byte*) DTV_CONTROL) ← (const byte) DTV_HIGHCOLOR|(const byte) DTV_LINEAR|(const byte) DTV_COLORRAM_OFF|(const byte) DTV_CHUNKY|(const byte) DTV_BADLINE_OFF [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [10] *((const byte*) VIC_CONTROL) ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(byte) 3 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [11] *((const byte*) VIC_CONTROL2) ← (const byte) VIC_MCM|(const byte) VIC_CSEL [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [12] *((const byte*) DTV_PLANEB_START_LO) ← (byte) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [13] *((const byte*) DTV_PLANEB_START_MI) ← >(const byte*) CHUNKY [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [14] *((const byte*) DTV_PLANEB_START_HI) ← (byte) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [15] *((const byte*) DTV_PLANEB_STEP) ← (byte) 8 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [16] *((const byte*) DTV_PLANEB_MODULO_LO) ← (byte) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [17] *((const byte*) DTV_PLANEB_MODULO_HI) ← (byte) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [18] *((const byte*) CIA2_PORT_A_DDR) ← (byte) 3 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [19] *((const byte*) CIA2_PORT_A) ← (byte) 3^(byte)(word)(const byte*) CHUNKY/(word) $4000 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [20] *((const byte*) VIC_MEMORY) ← (byte) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
2018-04-15 21:32:49 +00:00
|
|
|
Statement asm { ldx#$ff rff: cpxRASTER bnerff stabilize: nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop cpxRASTER beqeat+0 eat: inx cpx#$08 bnestabilize } always clobbers reg byte x
|
2019-09-29 18:57:23 +00:00
|
|
|
Statement [26] *((const byte*) VIC_CONTROL) ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(byte) 3 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [27] *((const byte*) BORDERCOL) ← (byte) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [28] if(*((const byte*) RASTER)!=(byte) $42) goto main::@3 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
2019-11-03 16:05:55 +00:00
|
|
|
Statement [32] (byte~) main::$17 ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL | (byte~) main::$16 [ main::rst#1 main::$17 ] ( main:2 [ main::rst#1 main::$17 ] ) always clobbers reg byte a
|
2019-10-12 09:40:36 +00:00
|
|
|
Removing always clobbered register reg byte a as potential for zp[1]:10 [ main::rst#1 ]
|
2019-11-03 16:05:55 +00:00
|
|
|
Statement [34] (byte~) main::$18 ← (byte) main::rst#1 << (byte) 4 [ main::rst#1 main::$18 ] ( main:2 [ main::rst#1 main::$18 ] ) always clobbers reg byte a
|
2019-05-30 20:29:04 +00:00
|
|
|
Statement [42] if((byte*) gfx_init_chunky::gfxb#3!=(word) $8000) goto gfx_init_chunky::@3 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxb#3 gfx_init_chunky::x#2 gfx_init_chunky::gfxbCpuBank#4 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxb#3 gfx_init_chunky::x#2 gfx_init_chunky::gfxbCpuBank#4 ] ) always clobbers reg byte a
|
2019-10-12 09:40:36 +00:00
|
|
|
Removing always clobbered register reg byte a as potential for zp[1]:3 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
Removing always clobbered register reg byte a as potential for zp[1]:6 [ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ]
|
2019-11-03 16:05:55 +00:00
|
|
|
Statement [47] (word~) gfx_init_chunky::$7 ← (word) gfx_init_chunky::x#2 + (byte) gfx_init_chunky::y#6 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 gfx_init_chunky::$7 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 gfx_init_chunky::$7 ] ) always clobbers reg byte a
|
|
|
|
Statement [48] (byte) gfx_init_chunky::c#0 ← (byte)(word~) gfx_init_chunky::$7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 gfx_init_chunky::c#0 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 gfx_init_chunky::c#0 ] ) always clobbers reg byte a
|
2018-04-18 21:19:25 +00:00
|
|
|
Statement [49] *((byte*) gfx_init_chunky::gfxb#4) ← (byte) gfx_init_chunky::c#0 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 ] ) always clobbers reg byte y
|
2019-10-12 09:40:36 +00:00
|
|
|
Removing always clobbered register reg byte y as potential for zp[1]:3 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
Removing always clobbered register reg byte y as potential for zp[1]:6 [ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ]
|
2019-05-30 20:29:04 +00:00
|
|
|
Statement [52] if((word) gfx_init_chunky::x#1!=(word) $140) goto gfx_init_chunky::@2 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxb#1 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#1 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxb#1 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#1 ] ) always clobbers reg byte a
|
2018-04-15 21:32:49 +00:00
|
|
|
Statement asm { .byte$32,$dd lda$ff .byte$32,$00 } always clobbers reg byte a
|
2019-09-29 18:57:23 +00:00
|
|
|
Statement [5] *((const byte*) PROCPORT_DDR) ← (const byte) PROCPORT_DDR_MEMORY_MASK [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [6] *((const byte*) PROCPORT) ← (const byte) PROCPORT_RAM_IO [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [8] *((const byte*) DTV_FEATURE) ← (const byte) DTV_FEATURE_ENABLE [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [9] *((const byte*) DTV_CONTROL) ← (const byte) DTV_HIGHCOLOR|(const byte) DTV_LINEAR|(const byte) DTV_COLORRAM_OFF|(const byte) DTV_CHUNKY|(const byte) DTV_BADLINE_OFF [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [10] *((const byte*) VIC_CONTROL) ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(byte) 3 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [11] *((const byte*) VIC_CONTROL2) ← (const byte) VIC_MCM|(const byte) VIC_CSEL [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [12] *((const byte*) DTV_PLANEB_START_LO) ← (byte) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [13] *((const byte*) DTV_PLANEB_START_MI) ← >(const byte*) CHUNKY [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [14] *((const byte*) DTV_PLANEB_START_HI) ← (byte) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [15] *((const byte*) DTV_PLANEB_STEP) ← (byte) 8 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [16] *((const byte*) DTV_PLANEB_MODULO_LO) ← (byte) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [17] *((const byte*) DTV_PLANEB_MODULO_HI) ← (byte) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [18] *((const byte*) CIA2_PORT_A_DDR) ← (byte) 3 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [19] *((const byte*) CIA2_PORT_A) ← (byte) 3^(byte)(word)(const byte*) CHUNKY/(word) $4000 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [20] *((const byte*) VIC_MEMORY) ← (byte) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
2018-04-15 21:32:49 +00:00
|
|
|
Statement asm { ldx#$ff rff: cpxRASTER bnerff stabilize: nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop cpxRASTER beqeat+0 eat: inx cpx#$08 bnestabilize } always clobbers reg byte x
|
2019-09-29 18:57:23 +00:00
|
|
|
Statement [26] *((const byte*) VIC_CONTROL) ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(byte) 3 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [27] *((const byte*) BORDERCOL) ← (byte) 0 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
|
|
|
Statement [28] if(*((const byte*) RASTER)!=(byte) $42) goto main::@3 [ ] ( main:2 [ ] ) always clobbers reg byte a
|
2019-11-03 16:05:55 +00:00
|
|
|
Statement [31] (byte~) main::$16 ← (byte) main::rst#1 & (byte) 7 [ main::rst#1 main::$16 ] ( main:2 [ main::rst#1 main::$16 ] ) always clobbers reg byte a
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|
|
|
Statement [32] (byte~) main::$17 ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL | (byte~) main::$16 [ main::rst#1 main::$17 ] ( main:2 [ main::rst#1 main::$17 ] ) always clobbers reg byte a
|
|
|
|
Statement [34] (byte~) main::$18 ← (byte) main::rst#1 << (byte) 4 [ main::rst#1 main::$18 ] ( main:2 [ main::rst#1 main::$18 ] ) always clobbers reg byte a
|
2019-05-30 20:29:04 +00:00
|
|
|
Statement [42] if((byte*) gfx_init_chunky::gfxb#3!=(word) $8000) goto gfx_init_chunky::@3 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxb#3 gfx_init_chunky::x#2 gfx_init_chunky::gfxbCpuBank#4 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxb#3 gfx_init_chunky::x#2 gfx_init_chunky::gfxbCpuBank#4 ] ) always clobbers reg byte a
|
2019-11-03 16:05:55 +00:00
|
|
|
Statement [47] (word~) gfx_init_chunky::$7 ← (word) gfx_init_chunky::x#2 + (byte) gfx_init_chunky::y#6 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 gfx_init_chunky::$7 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 gfx_init_chunky::$7 ] ) always clobbers reg byte a
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|
|
|
Statement [48] (byte) gfx_init_chunky::c#0 ← (byte)(word~) gfx_init_chunky::$7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 gfx_init_chunky::c#0 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 gfx_init_chunky::c#0 ] ) always clobbers reg byte a
|
2018-04-18 21:19:25 +00:00
|
|
|
Statement [49] *((byte*) gfx_init_chunky::gfxb#4) ← (byte) gfx_init_chunky::c#0 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#2 gfx_init_chunky::gfxb#4 ] ) always clobbers reg byte y
|
2019-05-30 20:29:04 +00:00
|
|
|
Statement [52] if((word) gfx_init_chunky::x#1!=(word) $140) goto gfx_init_chunky::@2 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxb#1 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#1 ] ( main:2::gfx_init_chunky:7 [ gfx_init_chunky::y#6 gfx_init_chunky::gfxb#1 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::x#1 ] ) always clobbers reg byte a
|
2018-04-15 21:32:49 +00:00
|
|
|
Statement asm { .byte$32,$dd lda$ff .byte$32,$00 } always clobbers reg byte a
|
2019-10-12 09:40:36 +00:00
|
|
|
Potential registers zp[1]:2 [ main::j#2 main::j#1 ] : zp[1]:2 , reg byte a , reg byte x , reg byte y ,
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|
|
|
Potential registers zp[1]:3 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ] : zp[1]:3 , reg byte x ,
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|
|
Potential registers zp[2]:4 [ gfx_init_chunky::x#2 gfx_init_chunky::x#1 ] : zp[2]:4 ,
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|
|
|
Potential registers zp[1]:6 [ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ] : zp[1]:6 , reg byte x ,
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|
|
|
Potential registers zp[2]:7 [ gfx_init_chunky::gfxb#4 gfx_init_chunky::gfxb#3 gfx_init_chunky::gfxb#5 gfx_init_chunky::gfxb#1 ] : zp[2]:7 ,
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|
|
Potential registers zp[1]:9 [ dtvSetCpuBankSegment1::cpuBankIdx#3 dtvSetCpuBankSegment1::cpuBankIdx#1 ] : zp[1]:9 , reg byte a , reg byte x , reg byte y ,
|
|
|
|
Potential registers zp[1]:10 [ main::rst#1 ] : zp[1]:10 , reg byte x , reg byte y ,
|
2019-11-03 16:05:55 +00:00
|
|
|
Potential registers zp[1]:11 [ main::$16 ] : zp[1]:11 , reg byte a , reg byte x , reg byte y ,
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|
|
|
Potential registers zp[1]:12 [ main::$17 ] : zp[1]:12 , reg byte a , reg byte x , reg byte y ,
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|
|
Potential registers zp[1]:13 [ main::$18 ] : zp[1]:13 , reg byte a , reg byte x , reg byte y ,
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|
|
|
Potential registers zp[2]:14 [ gfx_init_chunky::$7 ] : zp[2]:14 ,
|
2019-10-12 09:40:36 +00:00
|
|
|
Potential registers zp[1]:16 [ gfx_init_chunky::c#0 ] : zp[1]:16 , reg byte a , reg byte x , reg byte y ,
|
2018-04-15 21:32:49 +00:00
|
|
|
|
|
|
|
REGISTER UPLIFT SCOPES
|
2019-11-03 16:05:55 +00:00
|
|
|
Uplift Scope [gfx_init_chunky] 362.64: zp[1]:6 [ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ] 297.35: zp[2]:7 [ gfx_init_chunky::gfxb#4 gfx_init_chunky::gfxb#3 gfx_init_chunky::gfxb#5 gfx_init_chunky::gfxb#1 ] 202: zp[1]:16 [ gfx_init_chunky::c#0 ] 181.8: zp[2]:4 [ gfx_init_chunky::x#2 gfx_init_chunky::x#1 ] 101: zp[2]:14 [ gfx_init_chunky::$7 ] 25.96: zp[1]:3 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
Uplift Scope [main] 202: zp[1]:11 [ main::$16 ] 202: zp[1]:12 [ main::$17 ] 202: zp[1]:13 [ main::$18 ] 57.71: zp[1]:10 [ main::rst#1 ] 38.5: zp[1]:2 [ main::j#2 main::j#1 ]
|
2019-10-12 09:40:36 +00:00
|
|
|
Uplift Scope [dtvSetCpuBankSegment1] 305: zp[1]:9 [ dtvSetCpuBankSegment1::cpuBankIdx#3 dtvSetCpuBankSegment1::cpuBankIdx#1 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
Uplift Scope []
|
|
|
|
|
2019-11-03 16:05:55 +00:00
|
|
|
Uplifting [gfx_init_chunky] best 25250 combination reg byte x [ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ] zp[2]:7 [ gfx_init_chunky::gfxb#4 gfx_init_chunky::gfxb#3 gfx_init_chunky::gfxb#5 gfx_init_chunky::gfxb#1 ] reg byte a [ gfx_init_chunky::c#0 ] zp[2]:4 [ gfx_init_chunky::x#2 gfx_init_chunky::x#1 ] zp[2]:14 [ gfx_init_chunky::$7 ] zp[1]:3 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
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|
|
|
Uplifting [main] best 22650 combination reg byte a [ main::$16 ] reg byte a [ main::$17 ] reg byte a [ main::$18 ] reg byte x [ main::rst#1 ] zp[1]:2 [ main::j#2 main::j#1 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
Limited combination testing to 100 combinations of 768 possible.
|
2018-04-18 21:19:25 +00:00
|
|
|
Uplifting [dtvSetCpuBankSegment1] best 22541 combination reg byte a [ dtvSetCpuBankSegment1::cpuBankIdx#3 dtvSetCpuBankSegment1::cpuBankIdx#1 ]
|
|
|
|
Uplifting [] best 22541 combination
|
2019-10-12 09:40:36 +00:00
|
|
|
Attempting to uplift remaining variables inzp[1]:2 [ main::j#2 main::j#1 ]
|
2018-04-18 21:19:25 +00:00
|
|
|
Uplifting [main] best 22421 combination reg byte x [ main::j#2 main::j#1 ]
|
2019-10-12 09:40:36 +00:00
|
|
|
Attempting to uplift remaining variables inzp[1]:3 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
Uplifting [gfx_init_chunky] best 22421 combination zp[1]:3 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
Allocated (was zp[1]:3) zp[1]:2 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
Allocated (was zp[2]:4) zp[2]:3 [ gfx_init_chunky::x#2 gfx_init_chunky::x#1 ]
|
|
|
|
Allocated (was zp[2]:7) zp[2]:5 [ gfx_init_chunky::gfxb#4 gfx_init_chunky::gfxb#3 gfx_init_chunky::gfxb#5 gfx_init_chunky::gfxb#1 ]
|
2019-11-03 16:05:55 +00:00
|
|
|
Allocated (was zp[2]:14) zp[2]:7 [ gfx_init_chunky::$7 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
|
|
|
|
ASSEMBLER BEFORE OPTIMIZATION
|
2019-07-08 14:43:09 +00:00
|
|
|
// File Comments
|
2019-02-17 23:12:29 +00:00
|
|
|
// C64DTV 8bpp charmode stretcher
|
2019-07-25 15:06:17 +00:00
|
|
|
// Upstart
|
2018-04-15 21:32:49 +00:00
|
|
|
.pc = $801 "Basic"
|
2019-09-29 21:13:37 +00:00
|
|
|
:BasicUpstart(__bbegin)
|
2018-04-15 21:32:49 +00:00
|
|
|
.pc = $80d "Program"
|
2019-07-08 14:43:09 +00:00
|
|
|
// Global Constants & labels
|
2019-02-17 23:12:29 +00:00
|
|
|
// Processor port data direction register
|
2018-04-15 21:32:49 +00:00
|
|
|
.label PROCPORT_DDR = 0
|
2019-02-17 23:12:29 +00:00
|
|
|
// Mask for PROCESSOR_PORT_DDR which allows only memory configuration to be written
|
2018-04-15 21:32:49 +00:00
|
|
|
.const PROCPORT_DDR_MEMORY_MASK = 7
|
2019-02-17 23:12:29 +00:00
|
|
|
// Processor Port Register controlling RAM/ROM configuration and the datasette
|
2018-04-15 21:32:49 +00:00
|
|
|
.label PROCPORT = 1
|
2019-02-17 23:12:29 +00:00
|
|
|
// RAM in $A000, $E000 I/O in $D000
|
2019-07-30 13:01:43 +00:00
|
|
|
.const PROCPORT_RAM_IO = 5
|
2018-04-15 21:32:49 +00:00
|
|
|
.label RASTER = $d012
|
|
|
|
.label BORDERCOL = $d020
|
|
|
|
.label VIC_CONTROL = $d011
|
|
|
|
.const VIC_ECM = $40
|
|
|
|
.const VIC_DEN = $10
|
|
|
|
.const VIC_RSEL = 8
|
|
|
|
.label VIC_CONTROL2 = $d016
|
|
|
|
.const VIC_MCM = $10
|
|
|
|
.const VIC_CSEL = 8
|
|
|
|
.label VIC_MEMORY = $d018
|
2019-02-17 23:12:29 +00:00
|
|
|
// CIA#2 Port A: Serial bus, RS-232, VIC memory bank
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CIA2_PORT_A = $dd00
|
2019-02-17 23:12:29 +00:00
|
|
|
// CIA #2 Port A data direction register.
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CIA2_PORT_A_DDR = $dd02
|
2019-02-17 23:12:29 +00:00
|
|
|
// Feature enables or disables the extra C64 DTV features
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_FEATURE = $d03f
|
|
|
|
.const DTV_FEATURE_ENABLE = 1
|
2019-02-17 23:12:29 +00:00
|
|
|
// Controls the graphics modes of the C64 DTV
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_CONTROL = $d03c
|
|
|
|
.const DTV_LINEAR = 1
|
|
|
|
.const DTV_HIGHCOLOR = 4
|
|
|
|
.const DTV_COLORRAM_OFF = $10
|
|
|
|
.const DTV_BADLINE_OFF = $20
|
|
|
|
.const DTV_CHUNKY = $40
|
2019-02-17 23:12:29 +00:00
|
|
|
// Defines colors for the 16 first colors ($00-$0f)
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_PALETTE = $d200
|
2019-02-17 23:12:29 +00:00
|
|
|
// Linear Graphics Plane B Counter Control
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_PLANEB_START_LO = $d049
|
|
|
|
.label DTV_PLANEB_START_MI = $d04a
|
|
|
|
.label DTV_PLANEB_START_HI = $d04b
|
|
|
|
.label DTV_PLANEB_STEP = $d04c
|
|
|
|
.label DTV_PLANEB_MODULO_LO = $d047
|
|
|
|
.label DTV_PLANEB_MODULO_HI = $d048
|
2019-02-17 23:12:29 +00:00
|
|
|
// Plane with all pixels
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CHUNKY = $8000
|
2019-07-08 14:43:09 +00:00
|
|
|
// @begin
|
2019-09-29 21:13:37 +00:00
|
|
|
__bbegin:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [1] phi from @begin to @1 [phi:@begin->@1]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1_from___bbegin:
|
|
|
|
jmp __b1
|
2019-07-08 14:43:09 +00:00
|
|
|
// @1
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [2] call main
|
2018-04-15 21:32:49 +00:00
|
|
|
jsr main
|
2019-07-08 14:43:09 +00:00
|
|
|
// [3] phi from @1 to @end [phi:@1->@end]
|
2019-09-29 21:13:37 +00:00
|
|
|
__bend_from___b1:
|
|
|
|
jmp __bend
|
2019-07-08 14:43:09 +00:00
|
|
|
// @end
|
2019-09-29 21:13:37 +00:00
|
|
|
__bend:
|
2019-07-08 14:43:09 +00:00
|
|
|
// main
|
2018-04-15 21:32:49 +00:00
|
|
|
main: {
|
2019-07-08 14:43:09 +00:00
|
|
|
// asm { sei }
|
2018-04-15 21:32:49 +00:00
|
|
|
sei
|
2019-09-29 18:57:23 +00:00
|
|
|
// [5] *((const byte*) PROCPORT_DDR) ← (const byte) PROCPORT_DDR_MEMORY_MASK -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Disable normal interrupt (prevent keyboard reading glitches and allows to hide basic/kernal)
|
|
|
|
// Disable kernal & basic
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #PROCPORT_DDR_MEMORY_MASK
|
|
|
|
sta PROCPORT_DDR
|
2019-09-29 18:57:23 +00:00
|
|
|
// [6] *((const byte*) PROCPORT) ← (const byte) PROCPORT_RAM_IO -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #PROCPORT_RAM_IO
|
|
|
|
sta PROCPORT
|
2019-07-08 14:43:09 +00:00
|
|
|
// [7] call gfx_init_chunky
|
|
|
|
// [38] phi from main to gfx_init_chunky [phi:main->gfx_init_chunky]
|
2018-04-15 21:32:49 +00:00
|
|
|
gfx_init_chunky_from_main:
|
|
|
|
jsr gfx_init_chunky
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b6
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@6
|
2019-09-29 21:13:37 +00:00
|
|
|
__b6:
|
2019-09-29 18:57:23 +00:00
|
|
|
// [8] *((const byte*) DTV_FEATURE) ← (const byte) DTV_FEATURE_ENABLE -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Enable DTV extended modes
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #DTV_FEATURE_ENABLE
|
|
|
|
sta DTV_FEATURE
|
2019-09-29 18:57:23 +00:00
|
|
|
// [9] *((const byte*) DTV_CONTROL) ← (const byte) DTV_HIGHCOLOR|(const byte) DTV_LINEAR|(const byte) DTV_COLORRAM_OFF|(const byte) DTV_CHUNKY|(const byte) DTV_BADLINE_OFF -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// 8BPP Pixel Cell Mode
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #DTV_HIGHCOLOR|DTV_LINEAR|DTV_COLORRAM_OFF|DTV_CHUNKY|DTV_BADLINE_OFF
|
|
|
|
sta DTV_CONTROL
|
2019-09-29 18:57:23 +00:00
|
|
|
// [10] *((const byte*) VIC_CONTROL) ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(byte) 3 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_DEN|VIC_ECM|VIC_RSEL|3
|
|
|
|
sta VIC_CONTROL
|
2019-09-29 18:57:23 +00:00
|
|
|
// [11] *((const byte*) VIC_CONTROL2) ← (const byte) VIC_MCM|(const byte) VIC_CSEL -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_MCM|VIC_CSEL
|
|
|
|
sta VIC_CONTROL2
|
2019-09-29 18:57:23 +00:00
|
|
|
// [12] *((const byte*) DTV_PLANEB_START_LO) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Plane B: CHUNKY
|
2019-05-30 20:29:04 +00:00
|
|
|
lda #0
|
2018-04-15 21:32:49 +00:00
|
|
|
sta DTV_PLANEB_START_LO
|
2019-09-29 18:57:23 +00:00
|
|
|
// [13] *((const byte*) DTV_PLANEB_START_MI) ← >(const byte*) CHUNKY -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #>CHUNKY
|
|
|
|
sta DTV_PLANEB_START_MI
|
2019-09-29 18:57:23 +00:00
|
|
|
// [14] *((const byte*) DTV_PLANEB_START_HI) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta DTV_PLANEB_START_HI
|
2019-09-29 18:57:23 +00:00
|
|
|
// [15] *((const byte*) DTV_PLANEB_STEP) ← (byte) 8 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #8
|
|
|
|
sta DTV_PLANEB_STEP
|
2019-09-29 18:57:23 +00:00
|
|
|
// [16] *((const byte*) DTV_PLANEB_MODULO_LO) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta DTV_PLANEB_MODULO_LO
|
2019-09-29 18:57:23 +00:00
|
|
|
// [17] *((const byte*) DTV_PLANEB_MODULO_HI) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta DTV_PLANEB_MODULO_HI
|
2019-09-29 18:57:23 +00:00
|
|
|
// [18] *((const byte*) CIA2_PORT_A_DDR) ← (byte) 3 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// VIC Graphics Bank
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #3
|
|
|
|
sta CIA2_PORT_A_DDR
|
2019-09-29 18:57:23 +00:00
|
|
|
// [19] *((const byte*) CIA2_PORT_A) ← (byte) 3^(byte)(word)(const byte*) CHUNKY/(word) $4000 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set VIC Bank bits to output - all others to input
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #3^CHUNKY/$4000
|
|
|
|
sta CIA2_PORT_A
|
2019-09-29 18:57:23 +00:00
|
|
|
// [20] *((const byte*) VIC_MEMORY) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set VIC Bank
|
|
|
|
// VIC memory
|
2019-05-30 20:29:04 +00:00
|
|
|
lda #0
|
2018-04-15 21:32:49 +00:00
|
|
|
sta VIC_MEMORY
|
2019-07-08 14:43:09 +00:00
|
|
|
// [21] phi from main::@6 to main::@1 [phi:main::@6->main::@1]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1_from___b6:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [21] phi (byte) main::j#2 = (byte) 0 [phi:main::@6->main::@1#0] -- vbuxx=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx #0
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b1
|
2019-02-17 23:12:29 +00:00
|
|
|
// DTV Palette - Grey Tones
|
2019-07-08 14:43:09 +00:00
|
|
|
// [21] phi from main::@1 to main::@1 [phi:main::@1->main::@1]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1_from___b1:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [21] phi (byte) main::j#2 = (byte) main::j#1 [phi:main::@1->main::@1#0] -- register_copy
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b1
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@1
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1:
|
2019-09-29 18:57:23 +00:00
|
|
|
// [22] *((const byte*) DTV_PALETTE + (byte) main::j#2) ← (byte) main::j#2 -- pbuc1_derefidx_vbuxx=vbuxx
|
2018-04-15 21:32:49 +00:00
|
|
|
txa
|
|
|
|
sta DTV_PALETTE,x
|
2019-07-08 14:43:09 +00:00
|
|
|
// [23] (byte) main::j#1 ← ++ (byte) main::j#2 -- vbuxx=_inc_vbuxx
|
2018-04-15 21:32:49 +00:00
|
|
|
inx
|
2019-07-08 14:43:09 +00:00
|
|
|
// [24] if((byte) main::j#1!=(byte) $10) goto main::@1 -- vbuxx_neq_vbuc1_then_la1
|
2018-04-15 21:32:49 +00:00
|
|
|
cpx #$10
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b1_from___b1
|
|
|
|
jmp __b2
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@2
|
2019-09-29 21:13:37 +00:00
|
|
|
__b2:
|
2019-07-08 14:43:09 +00:00
|
|
|
// asm { ldx#$ff rff: cpxRASTER bnerff stabilize: nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop cpxRASTER beqeat+0 eat: inx cpx#$08 bnestabilize }
|
2019-02-17 23:12:29 +00:00
|
|
|
// Stabilize Raster
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx #$ff
|
|
|
|
rff:
|
|
|
|
cpx RASTER
|
|
|
|
bne rff
|
|
|
|
stabilize:
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
cpx RASTER
|
|
|
|
beq eat+0
|
|
|
|
eat:
|
|
|
|
inx
|
|
|
|
cpx #8
|
|
|
|
bne stabilize
|
2019-09-29 18:57:23 +00:00
|
|
|
// [26] *((const byte*) VIC_CONTROL) ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(byte) 3 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_DEN|VIC_ECM|VIC_RSEL|3
|
|
|
|
sta VIC_CONTROL
|
2019-09-29 18:57:23 +00:00
|
|
|
// [27] *((const byte*) BORDERCOL) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta BORDERCOL
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b3
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@3
|
2019-09-29 21:13:37 +00:00
|
|
|
__b3:
|
2019-09-29 18:57:23 +00:00
|
|
|
// [28] if(*((const byte*) RASTER)!=(byte) $42) goto main::@3 -- _deref_pbuc1_neq_vbuc2_then_la1
|
2019-03-26 22:49:44 +00:00
|
|
|
lda #$42
|
|
|
|
cmp RASTER
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b3
|
|
|
|
jmp __b4
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@4
|
2019-09-29 21:13:37 +00:00
|
|
|
__b4:
|
2019-07-08 14:43:09 +00:00
|
|
|
// asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
|
2018-04-15 21:32:49 +00:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b5
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@5
|
2019-09-29 21:13:37 +00:00
|
|
|
__b5:
|
2019-09-29 18:57:23 +00:00
|
|
|
// [30] (byte) main::rst#1 ← *((const byte*) RASTER) -- vbuxx=_deref_pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx RASTER
|
2019-11-03 16:05:55 +00:00
|
|
|
// [31] (byte~) main::$16 ← (byte) main::rst#1 & (byte) 7 -- vbuaa=vbuxx_band_vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
txa
|
|
|
|
and #7
|
2019-11-03 16:05:55 +00:00
|
|
|
// [32] (byte~) main::$17 ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL | (byte~) main::$16 -- vbuaa=vbuc1_bor_vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
ora #VIC_DEN|VIC_ECM|VIC_RSEL
|
2019-11-03 16:05:55 +00:00
|
|
|
// [33] *((const byte*) VIC_CONTROL) ← (byte~) main::$17 -- _deref_pbuc1=vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
sta VIC_CONTROL
|
2019-11-03 16:05:55 +00:00
|
|
|
// [34] (byte~) main::$18 ← (byte) main::rst#1 << (byte) 4 -- vbuaa=vbuxx_rol_4
|
2018-04-15 21:32:49 +00:00
|
|
|
txa
|
|
|
|
asl
|
|
|
|
asl
|
|
|
|
asl
|
|
|
|
asl
|
2019-11-03 16:05:55 +00:00
|
|
|
// [35] *((const byte*) BORDERCOL) ← (byte~) main::$18 -- _deref_pbuc1=vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
sta BORDERCOL
|
2019-07-08 14:43:09 +00:00
|
|
|
// asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
|
2018-04-15 21:32:49 +00:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2019-07-08 14:43:09 +00:00
|
|
|
// [37] if((byte) main::rst#1!=(byte) $f2) goto main::@5 -- vbuxx_neq_vbuc1_then_la1
|
2018-04-15 21:32:49 +00:00
|
|
|
cpx #$f2
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b5
|
|
|
|
jmp __b2
|
2018-04-15 21:32:49 +00:00
|
|
|
}
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky
|
2019-02-17 23:12:29 +00:00
|
|
|
// Initialize Plane with 8bpp chunky
|
2018-04-15 21:32:49 +00:00
|
|
|
gfx_init_chunky: {
|
2019-11-03 16:05:55 +00:00
|
|
|
.label __7 = 7
|
2018-04-15 21:32:49 +00:00
|
|
|
.label gfxb = 5
|
|
|
|
.label x = 3
|
|
|
|
.label y = 2
|
2019-07-08 14:43:09 +00:00
|
|
|
// [39] call dtvSetCpuBankSegment1
|
|
|
|
// [58] phi from gfx_init_chunky to dtvSetCpuBankSegment1 [phi:gfx_init_chunky->dtvSetCpuBankSegment1]
|
2018-04-15 21:32:49 +00:00
|
|
|
dtvSetCpuBankSegment1_from_gfx_init_chunky:
|
2019-09-29 18:57:23 +00:00
|
|
|
// [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = (byte)(const byte*) CHUNKY/(word) $4000 [phi:gfx_init_chunky->dtvSetCpuBankSegment1#0] -- vbuaa=vbuc1
|
2019-05-30 20:29:04 +00:00
|
|
|
lda #CHUNKY/$4000
|
2018-04-15 21:32:49 +00:00
|
|
|
jsr dtvSetCpuBankSegment1
|
2019-07-08 14:43:09 +00:00
|
|
|
// [40] phi from gfx_init_chunky to gfx_init_chunky::@1 [phi:gfx_init_chunky->gfx_init_chunky::@1]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1_from_gfx_init_chunky:
|
2019-09-29 18:57:23 +00:00
|
|
|
// [40] phi (byte) gfx_init_chunky::gfxbCpuBank#7 = ++(byte)(const byte*) CHUNKY/(word) $4000 [phi:gfx_init_chunky->gfx_init_chunky::@1#0] -- vbuxx=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx #($ff&CHUNKY/$4000)+1
|
2019-07-08 14:43:09 +00:00
|
|
|
// [40] phi (byte) gfx_init_chunky::y#6 = (byte) 0 [phi:gfx_init_chunky->gfx_init_chunky::@1#1] -- vbuz1=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z y
|
2019-07-08 14:43:09 +00:00
|
|
|
// [40] phi (byte*) gfx_init_chunky::gfxb#5 = (byte*) 16384 [phi:gfx_init_chunky->gfx_init_chunky::@1#2] -- pbuz1=pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #<$4000
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z gfxb
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #>$4000
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z gfxb+1
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b1
|
2019-07-08 14:43:09 +00:00
|
|
|
// [40] phi from gfx_init_chunky::@5 to gfx_init_chunky::@1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1_from___b5:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [40] phi (byte) gfx_init_chunky::gfxbCpuBank#7 = (byte) gfx_init_chunky::gfxbCpuBank#8 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#0] -- register_copy
|
|
|
|
// [40] phi (byte) gfx_init_chunky::y#6 = (byte) gfx_init_chunky::y#1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#1] -- register_copy
|
|
|
|
// [40] phi (byte*) gfx_init_chunky::gfxb#5 = (byte*) gfx_init_chunky::gfxb#1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#2] -- register_copy
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b1
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@1
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [41] phi from gfx_init_chunky::@1 to gfx_init_chunky::@2 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b2_from___b1:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [41] phi (byte) gfx_init_chunky::gfxbCpuBank#4 = (byte) gfx_init_chunky::gfxbCpuBank#7 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#0] -- register_copy
|
|
|
|
// [41] phi (word) gfx_init_chunky::x#2 = (word) 0 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#1] -- vwuz1=vwuc1
|
2019-06-02 22:44:46 +00:00
|
|
|
lda #<0
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z x
|
2019-06-02 22:44:46 +00:00
|
|
|
lda #>0
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z x+1
|
2019-07-08 14:43:09 +00:00
|
|
|
// [41] phi (byte*) gfx_init_chunky::gfxb#3 = (byte*) gfx_init_chunky::gfxb#5 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#2] -- register_copy
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b2
|
2019-07-08 14:43:09 +00:00
|
|
|
// [41] phi from gfx_init_chunky::@3 to gfx_init_chunky::@2 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b2_from___b3:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [41] phi (byte) gfx_init_chunky::gfxbCpuBank#4 = (byte) gfx_init_chunky::gfxbCpuBank#8 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#0] -- register_copy
|
|
|
|
// [41] phi (word) gfx_init_chunky::x#2 = (word) gfx_init_chunky::x#1 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#1] -- register_copy
|
|
|
|
// [41] phi (byte*) gfx_init_chunky::gfxb#3 = (byte*) gfx_init_chunky::gfxb#1 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#2] -- register_copy
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b2
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@2
|
2019-09-29 21:13:37 +00:00
|
|
|
__b2:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [42] if((byte*) gfx_init_chunky::gfxb#3!=(word) $8000) goto gfx_init_chunky::@3 -- pbuz1_neq_vwuc1_then_la1
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z gfxb+1
|
2018-04-15 21:32:49 +00:00
|
|
|
cmp #>$8000
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b3_from___b2
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z gfxb
|
2018-04-15 21:32:49 +00:00
|
|
|
cmp #<$8000
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b3_from___b2
|
|
|
|
jmp __b4
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@4
|
2019-09-29 21:13:37 +00:00
|
|
|
__b4:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [43] (byte) dtvSetCpuBankSegment1::cpuBankIdx#1 ← (byte) gfx_init_chunky::gfxbCpuBank#4 -- vbuaa=vbuxx
|
2018-04-15 21:32:49 +00:00
|
|
|
txa
|
2019-07-08 14:43:09 +00:00
|
|
|
// [44] call dtvSetCpuBankSegment1
|
|
|
|
// [58] phi from gfx_init_chunky::@4 to dtvSetCpuBankSegment1 [phi:gfx_init_chunky::@4->dtvSetCpuBankSegment1]
|
2019-09-29 21:13:37 +00:00
|
|
|
dtvSetCpuBankSegment1_from___b4:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = (byte) dtvSetCpuBankSegment1::cpuBankIdx#1 [phi:gfx_init_chunky::@4->dtvSetCpuBankSegment1#0] -- register_copy
|
2018-04-15 21:32:49 +00:00
|
|
|
jsr dtvSetCpuBankSegment1
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b7
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@7
|
2019-09-29 21:13:37 +00:00
|
|
|
__b7:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [45] (byte) gfx_init_chunky::gfxbCpuBank#2 ← ++ (byte) gfx_init_chunky::gfxbCpuBank#4 -- vbuxx=_inc_vbuxx
|
2018-04-15 21:32:49 +00:00
|
|
|
inx
|
2019-07-08 14:43:09 +00:00
|
|
|
// [46] phi from gfx_init_chunky::@7 to gfx_init_chunky::@3 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b3_from___b7:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [46] phi (byte) gfx_init_chunky::gfxbCpuBank#8 = (byte) gfx_init_chunky::gfxbCpuBank#2 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3#0] -- register_copy
|
|
|
|
// [46] phi (byte*) gfx_init_chunky::gfxb#4 = (byte*) 16384 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3#1] -- pbuz1=pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #<$4000
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z gfxb
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #>$4000
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z gfxb+1
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b3
|
2019-07-08 14:43:09 +00:00
|
|
|
// [46] phi from gfx_init_chunky::@2 to gfx_init_chunky::@3 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b3_from___b2:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [46] phi (byte) gfx_init_chunky::gfxbCpuBank#8 = (byte) gfx_init_chunky::gfxbCpuBank#4 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3#0] -- register_copy
|
|
|
|
// [46] phi (byte*) gfx_init_chunky::gfxb#4 = (byte*) gfx_init_chunky::gfxb#3 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3#1] -- register_copy
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __b3
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@3
|
2019-09-29 21:13:37 +00:00
|
|
|
__b3:
|
2019-11-03 16:05:55 +00:00
|
|
|
// [47] (word~) gfx_init_chunky::$7 ← (word) gfx_init_chunky::x#2 + (byte) gfx_init_chunky::y#6 -- vwuz1=vwuz2_plus_vbuz3
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z y
|
2018-04-15 21:32:49 +00:00
|
|
|
clc
|
2019-08-07 19:00:19 +00:00
|
|
|
adc.z x
|
2019-11-03 16:05:55 +00:00
|
|
|
sta.z __7
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
2019-08-07 19:00:19 +00:00
|
|
|
adc.z x+1
|
2019-11-03 16:05:55 +00:00
|
|
|
sta.z __7+1
|
|
|
|
// [48] (byte) gfx_init_chunky::c#0 ← (byte)(word~) gfx_init_chunky::$7 -- vbuaa=_byte_vwuz1
|
|
|
|
lda.z __7
|
2019-07-08 14:43:09 +00:00
|
|
|
// [49] *((byte*) gfx_init_chunky::gfxb#4) ← (byte) gfx_init_chunky::c#0 -- _deref_pbuz1=vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
ldy #0
|
|
|
|
sta (gfxb),y
|
2019-07-08 14:43:09 +00:00
|
|
|
// [50] (byte*) gfx_init_chunky::gfxb#1 ← ++ (byte*) gfx_init_chunky::gfxb#4 -- pbuz1=_inc_pbuz1
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z gfxb
|
2018-04-15 21:32:49 +00:00
|
|
|
bne !+
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z gfxb+1
|
2018-04-15 21:32:49 +00:00
|
|
|
!:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [51] (word) gfx_init_chunky::x#1 ← ++ (word) gfx_init_chunky::x#2 -- vwuz1=_inc_vwuz1
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z x
|
2018-04-15 21:32:49 +00:00
|
|
|
bne !+
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z x+1
|
2018-04-15 21:32:49 +00:00
|
|
|
!:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [52] if((word) gfx_init_chunky::x#1!=(word) $140) goto gfx_init_chunky::@2 -- vwuz1_neq_vwuc1_then_la1
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z x+1
|
2018-04-15 21:32:49 +00:00
|
|
|
cmp #>$140
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b2_from___b3
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z x
|
2018-04-15 21:32:49 +00:00
|
|
|
cmp #<$140
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b2_from___b3
|
|
|
|
jmp __b5
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@5
|
2019-09-29 21:13:37 +00:00
|
|
|
__b5:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [53] (byte) gfx_init_chunky::y#1 ← ++ (byte) gfx_init_chunky::y#6 -- vbuz1=_inc_vbuz1
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z y
|
2019-07-08 14:43:09 +00:00
|
|
|
// [54] if((byte) gfx_init_chunky::y#1!=(byte) $33) goto gfx_init_chunky::@1 -- vbuz1_neq_vbuc1_then_la1
|
2019-03-26 22:49:44 +00:00
|
|
|
lda #$33
|
2019-08-07 19:00:19 +00:00
|
|
|
cmp.z y
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b1_from___b5
|
2019-07-08 14:43:09 +00:00
|
|
|
// [55] phi from gfx_init_chunky::@5 to gfx_init_chunky::@6 [phi:gfx_init_chunky::@5->gfx_init_chunky::@6]
|
2019-09-29 21:13:37 +00:00
|
|
|
__b6_from___b5:
|
|
|
|
jmp __b6
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@6
|
2019-09-29 21:13:37 +00:00
|
|
|
__b6:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [56] call dtvSetCpuBankSegment1
|
|
|
|
// [58] phi from gfx_init_chunky::@6 to dtvSetCpuBankSegment1 [phi:gfx_init_chunky::@6->dtvSetCpuBankSegment1]
|
2019-09-29 21:13:37 +00:00
|
|
|
dtvSetCpuBankSegment1_from___b6:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = (byte)(number) $4000/(number) $4000 [phi:gfx_init_chunky::@6->dtvSetCpuBankSegment1#0] -- vbuaa=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #$4000/$4000
|
|
|
|
jsr dtvSetCpuBankSegment1
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __breturn
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@return
|
2019-09-29 21:13:37 +00:00
|
|
|
__breturn:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [57] return
|
2018-04-15 21:32:49 +00:00
|
|
|
rts
|
|
|
|
}
|
2019-07-08 14:43:09 +00:00
|
|
|
// dtvSetCpuBankSegment1
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set the memory pointed to by CPU BANK 1 SEGMENT ($4000-$7fff)
|
|
|
|
// This sets which actual memory is addressed when the CPU reads/writes to $4000-$7fff
|
|
|
|
// The actual memory addressed will be $4000*cpuSegmentIdx
|
2019-02-19 19:51:48 +00:00
|
|
|
// dtvSetCpuBankSegment1(byte register(A) cpuBankIdx)
|
2018-04-15 21:32:49 +00:00
|
|
|
dtvSetCpuBankSegment1: {
|
2019-02-17 23:12:29 +00:00
|
|
|
// Move CPU BANK 1 SEGMENT ($4000-$7fff)
|
2018-04-15 21:32:49 +00:00
|
|
|
.label cpuBank = $ff
|
2019-09-29 20:36:00 +00:00
|
|
|
// [59] *((const byte*) dtvSetCpuBankSegment1::cpuBank) ← (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 -- _deref_pbuc1=vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
sta cpuBank
|
2019-07-08 14:43:09 +00:00
|
|
|
// asm { .byte$32,$dd lda$ff .byte$32,$00 }
|
2018-04-15 21:32:49 +00:00
|
|
|
.byte $32, $dd
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z $ff
|
2018-04-15 21:32:49 +00:00
|
|
|
.byte $32, $00
|
2019-09-29 21:13:37 +00:00
|
|
|
jmp __breturn
|
2019-07-08 14:43:09 +00:00
|
|
|
// dtvSetCpuBankSegment1::@return
|
2019-09-29 21:13:37 +00:00
|
|
|
__breturn:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [61] return
|
2018-04-15 21:32:49 +00:00
|
|
|
rts
|
|
|
|
}
|
2019-07-08 14:43:09 +00:00
|
|
|
// File Data
|
2018-04-15 21:32:49 +00:00
|
|
|
|
|
|
|
ASSEMBLER OPTIMIZATIONS
|
2019-09-29 21:13:37 +00:00
|
|
|
Removing instruction jmp __b1
|
|
|
|
Removing instruction jmp __bend
|
|
|
|
Removing instruction jmp __b6
|
|
|
|
Removing instruction jmp __b1
|
|
|
|
Removing instruction jmp __b2
|
|
|
|
Removing instruction jmp __b3
|
|
|
|
Removing instruction jmp __b4
|
|
|
|
Removing instruction jmp __b5
|
|
|
|
Removing instruction jmp __b1
|
|
|
|
Removing instruction jmp __b2
|
|
|
|
Removing instruction jmp __b4
|
|
|
|
Removing instruction jmp __b7
|
|
|
|
Removing instruction jmp __b3
|
|
|
|
Removing instruction jmp __b5
|
|
|
|
Removing instruction jmp __b6
|
|
|
|
Removing instruction jmp __breturn
|
|
|
|
Removing instruction jmp __breturn
|
2018-04-15 21:32:49 +00:00
|
|
|
Succesful ASM optimization Pass5NextJumpElimination
|
|
|
|
Removing instruction lda #0
|
2019-06-02 22:44:46 +00:00
|
|
|
Removing instruction lda #>0
|
2018-04-15 21:32:49 +00:00
|
|
|
Succesful ASM optimization Pass5UnnecesaryLoadElimination
|
2019-09-29 21:13:37 +00:00
|
|
|
Replacing label __bbegin with __b1
|
|
|
|
Replacing label __b1_from___b1 with __b1
|
|
|
|
Replacing label __b3_from___b2 with __b3
|
|
|
|
Replacing label __b3_from___b2 with __b3
|
|
|
|
Replacing label __b2_from___b3 with __b2
|
|
|
|
Replacing label __b2_from___b3 with __b2
|
|
|
|
Replacing label __b1_from___b5 with __b1
|
|
|
|
Removing instruction __bbegin:
|
|
|
|
Removing instruction __b1_from___bbegin:
|
|
|
|
Removing instruction __bend_from___b1:
|
|
|
|
Removing instruction __b1_from___b1:
|
|
|
|
Removing instruction __b1_from___b5:
|
|
|
|
Removing instruction __b2_from___b1:
|
|
|
|
Removing instruction __b2_from___b3:
|
|
|
|
Removing instruction __b3_from___b2:
|
|
|
|
Removing instruction __b6_from___b5:
|
|
|
|
Removing instruction dtvSetCpuBankSegment1_from___b6:
|
2018-04-15 21:32:49 +00:00
|
|
|
Succesful ASM optimization Pass5RedundantLabelElimination
|
2019-09-29 21:13:37 +00:00
|
|
|
Removing instruction __bend:
|
2018-04-15 21:32:49 +00:00
|
|
|
Removing instruction gfx_init_chunky_from_main:
|
2019-09-29 21:13:37 +00:00
|
|
|
Removing instruction __b6:
|
|
|
|
Removing instruction __b1_from___b6:
|
|
|
|
Removing instruction __b4:
|
2018-04-15 21:32:49 +00:00
|
|
|
Removing instruction dtvSetCpuBankSegment1_from_gfx_init_chunky:
|
2019-09-29 21:13:37 +00:00
|
|
|
Removing instruction __b1_from_gfx_init_chunky:
|
|
|
|
Removing instruction __b4:
|
|
|
|
Removing instruction dtvSetCpuBankSegment1_from___b4:
|
|
|
|
Removing instruction __b7:
|
|
|
|
Removing instruction __b3_from___b7:
|
|
|
|
Removing instruction __b5:
|
|
|
|
Removing instruction __b6:
|
|
|
|
Removing instruction __breturn:
|
|
|
|
Removing instruction __breturn:
|
2018-04-15 21:32:49 +00:00
|
|
|
Succesful ASM optimization Pass5UnusedLabelElimination
|
2018-12-25 16:04:50 +00:00
|
|
|
Updating BasicUpstart to call main directly
|
|
|
|
Removing instruction jsr main
|
|
|
|
Succesful ASM optimization Pass5SkipBegin
|
2019-09-29 21:13:37 +00:00
|
|
|
Removing instruction jmp __b1
|
|
|
|
Removing instruction jmp __b1
|
|
|
|
Removing instruction jmp __b2
|
|
|
|
Removing instruction jmp __b3
|
2018-04-15 21:32:49 +00:00
|
|
|
Succesful ASM optimization Pass5NextJumpElimination
|
2019-05-30 20:29:04 +00:00
|
|
|
Replacing instruction ldx #0 with TAX
|
2019-09-29 21:13:37 +00:00
|
|
|
Removing instruction __b1:
|
2018-12-25 16:04:50 +00:00
|
|
|
Succesful ASM optimization Pass5UnusedLabelElimination
|
2018-04-15 21:32:49 +00:00
|
|
|
|
|
|
|
FINAL SYMBOL TABLE
|
2019-03-31 15:10:41 +00:00
|
|
|
(label) @1
|
2018-04-15 21:32:49 +00:00
|
|
|
(label) @begin
|
|
|
|
(label) @end
|
2019-10-13 22:51:15 +00:00
|
|
|
(const byte*) BORDERCOL = (byte*) 53280
|
|
|
|
(const byte*) CHUNKY = (byte*) 32768
|
|
|
|
(const byte*) CIA2_PORT_A = (byte*) 56576
|
|
|
|
(const byte*) CIA2_PORT_A_DDR = (byte*) 56578
|
2019-11-03 16:05:55 +00:00
|
|
|
(const byte) DTV_BADLINE_OFF = (number) $20
|
|
|
|
(const byte) DTV_CHUNKY = (number) $40
|
|
|
|
(const byte) DTV_COLORRAM_OFF = (number) $10
|
2019-10-13 22:51:15 +00:00
|
|
|
(const byte*) DTV_CONTROL = (byte*) 53308
|
|
|
|
(const byte*) DTV_FEATURE = (byte*) 53311
|
2019-11-03 16:05:55 +00:00
|
|
|
(const byte) DTV_FEATURE_ENABLE = (number) 1
|
|
|
|
(const byte) DTV_HIGHCOLOR = (number) 4
|
|
|
|
(const byte) DTV_LINEAR = (number) 1
|
2019-10-13 22:51:15 +00:00
|
|
|
(const byte*) DTV_PALETTE = (byte*) 53760
|
|
|
|
(const byte*) DTV_PLANEB_MODULO_HI = (byte*) 53320
|
|
|
|
(const byte*) DTV_PLANEB_MODULO_LO = (byte*) 53319
|
|
|
|
(const byte*) DTV_PLANEB_START_HI = (byte*) 53323
|
|
|
|
(const byte*) DTV_PLANEB_START_LO = (byte*) 53321
|
|
|
|
(const byte*) DTV_PLANEB_START_MI = (byte*) 53322
|
|
|
|
(const byte*) DTV_PLANEB_STEP = (byte*) 53324
|
|
|
|
(const byte*) PROCPORT = (byte*) 1
|
|
|
|
(const byte*) PROCPORT_DDR = (byte*) 0
|
2019-11-03 16:05:55 +00:00
|
|
|
(const byte) PROCPORT_DDR_MEMORY_MASK = (number) 7
|
|
|
|
(const byte) PROCPORT_RAM_IO = (number) 5
|
2019-10-13 22:51:15 +00:00
|
|
|
(const byte*) RASTER = (byte*) 53266
|
|
|
|
(const byte*) VIC_CONTROL = (byte*) 53265
|
|
|
|
(const byte*) VIC_CONTROL2 = (byte*) 53270
|
2019-11-03 16:05:55 +00:00
|
|
|
(const byte) VIC_CSEL = (number) 8
|
|
|
|
(const byte) VIC_DEN = (number) $10
|
|
|
|
(const byte) VIC_ECM = (number) $40
|
|
|
|
(const byte) VIC_MCM = (number) $10
|
2019-10-13 22:51:15 +00:00
|
|
|
(const byte*) VIC_MEMORY = (byte*) 53272
|
2019-11-03 16:05:55 +00:00
|
|
|
(const byte) VIC_RSEL = (number) 8
|
2018-04-15 21:32:49 +00:00
|
|
|
(void()) dtvSetCpuBankSegment1((byte) dtvSetCpuBankSegment1::cpuBankIdx)
|
|
|
|
(label) dtvSetCpuBankSegment1::@return
|
2019-10-13 22:51:15 +00:00
|
|
|
(const byte*) dtvSetCpuBankSegment1::cpuBank = (byte*) 255
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#1 reg byte a 202.0
|
|
|
|
(byte) dtvSetCpuBankSegment1::cpuBankIdx#3 reg byte a 103.0
|
|
|
|
(void()) gfx_init_chunky()
|
2019-11-03 16:05:55 +00:00
|
|
|
(word~) gfx_init_chunky::$7 zp[2]:7 101.0
|
2018-04-15 21:32:49 +00:00
|
|
|
(label) gfx_init_chunky::@1
|
|
|
|
(label) gfx_init_chunky::@2
|
|
|
|
(label) gfx_init_chunky::@3
|
|
|
|
(label) gfx_init_chunky::@4
|
|
|
|
(label) gfx_init_chunky::@5
|
|
|
|
(label) gfx_init_chunky::@6
|
2019-03-31 15:10:41 +00:00
|
|
|
(label) gfx_init_chunky::@7
|
2018-04-15 21:32:49 +00:00
|
|
|
(label) gfx_init_chunky::@return
|
|
|
|
(byte) gfx_init_chunky::c
|
|
|
|
(byte) gfx_init_chunky::c#0 reg byte a 202.0
|
|
|
|
(byte*) gfx_init_chunky::gfxb
|
2019-10-12 09:40:36 +00:00
|
|
|
(byte*) gfx_init_chunky::gfxb#1 gfxb zp[2]:5 42.599999999999994
|
|
|
|
(byte*) gfx_init_chunky::gfxb#3 gfxb zp[2]:5 157.0
|
|
|
|
(byte*) gfx_init_chunky::gfxb#4 gfxb zp[2]:5 75.75
|
|
|
|
(byte*) gfx_init_chunky::gfxb#5 gfxb zp[2]:5 22.0
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#2 reg byte x 202.0
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#4 reg byte x 103.75
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#7 reg byte x 22.0
|
|
|
|
(byte) gfx_init_chunky::gfxbCpuBank#8 reg byte x 34.888888888888886
|
|
|
|
(word) gfx_init_chunky::x
|
2019-10-12 09:40:36 +00:00
|
|
|
(word) gfx_init_chunky::x#1 x zp[2]:3 151.5
|
|
|
|
(word) gfx_init_chunky::x#2 x zp[2]:3 30.299999999999997
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) gfx_init_chunky::y
|
2019-10-12 09:40:36 +00:00
|
|
|
(byte) gfx_init_chunky::y#1 y zp[1]:2 16.5
|
|
|
|
(byte) gfx_init_chunky::y#6 y zp[1]:2 9.461538461538462
|
2018-04-15 21:32:49 +00:00
|
|
|
(void()) main()
|
2019-11-03 16:05:55 +00:00
|
|
|
(byte~) main::$16 reg byte a 202.0
|
|
|
|
(byte~) main::$17 reg byte a 202.0
|
|
|
|
(byte~) main::$18 reg byte a 202.0
|
2019-03-31 15:10:41 +00:00
|
|
|
(label) main::@1
|
2019-03-29 23:15:53 +00:00
|
|
|
(label) main::@2
|
2019-03-31 15:10:41 +00:00
|
|
|
(label) main::@3
|
|
|
|
(label) main::@4
|
|
|
|
(label) main::@5
|
2019-03-29 23:15:53 +00:00
|
|
|
(label) main::@6
|
2018-04-15 21:32:49 +00:00
|
|
|
(byte) main::j
|
|
|
|
(byte) main::j#1 reg byte x 16.5
|
|
|
|
(byte) main::j#2 reg byte x 22.0
|
|
|
|
(byte) main::rst
|
|
|
|
(byte) main::rst#1 reg byte x 57.714285714285715
|
|
|
|
|
|
|
|
reg byte x [ main::j#2 main::j#1 ]
|
2019-10-12 09:40:36 +00:00
|
|
|
zp[1]:2 [ gfx_init_chunky::y#6 gfx_init_chunky::y#1 ]
|
|
|
|
zp[2]:3 [ gfx_init_chunky::x#2 gfx_init_chunky::x#1 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
reg byte x [ gfx_init_chunky::gfxbCpuBank#4 gfx_init_chunky::gfxbCpuBank#7 gfx_init_chunky::gfxbCpuBank#8 gfx_init_chunky::gfxbCpuBank#2 ]
|
2019-10-12 09:40:36 +00:00
|
|
|
zp[2]:5 [ gfx_init_chunky::gfxb#4 gfx_init_chunky::gfxb#3 gfx_init_chunky::gfxb#5 gfx_init_chunky::gfxb#1 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
reg byte a [ dtvSetCpuBankSegment1::cpuBankIdx#3 dtvSetCpuBankSegment1::cpuBankIdx#1 ]
|
|
|
|
reg byte x [ main::rst#1 ]
|
2019-11-03 16:05:55 +00:00
|
|
|
reg byte a [ main::$16 ]
|
|
|
|
reg byte a [ main::$17 ]
|
|
|
|
reg byte a [ main::$18 ]
|
|
|
|
zp[2]:7 [ gfx_init_chunky::$7 ]
|
2018-04-15 21:32:49 +00:00
|
|
|
reg byte a [ gfx_init_chunky::c#0 ]
|
|
|
|
|
|
|
|
|
|
|
|
FINAL ASSEMBLER
|
2018-12-25 16:04:50 +00:00
|
|
|
Score: 19882
|
2018-04-15 21:32:49 +00:00
|
|
|
|
2019-07-08 14:43:09 +00:00
|
|
|
// File Comments
|
2019-02-17 23:12:29 +00:00
|
|
|
// C64DTV 8bpp charmode stretcher
|
2019-07-25 15:06:17 +00:00
|
|
|
// Upstart
|
2018-04-15 21:32:49 +00:00
|
|
|
.pc = $801 "Basic"
|
|
|
|
:BasicUpstart(main)
|
|
|
|
.pc = $80d "Program"
|
2019-07-08 14:43:09 +00:00
|
|
|
// Global Constants & labels
|
2019-02-17 23:12:29 +00:00
|
|
|
// Processor port data direction register
|
2018-04-15 21:32:49 +00:00
|
|
|
.label PROCPORT_DDR = 0
|
2019-02-17 23:12:29 +00:00
|
|
|
// Mask for PROCESSOR_PORT_DDR which allows only memory configuration to be written
|
2018-04-15 21:32:49 +00:00
|
|
|
.const PROCPORT_DDR_MEMORY_MASK = 7
|
2019-02-17 23:12:29 +00:00
|
|
|
// Processor Port Register controlling RAM/ROM configuration and the datasette
|
2018-04-15 21:32:49 +00:00
|
|
|
.label PROCPORT = 1
|
2019-02-17 23:12:29 +00:00
|
|
|
// RAM in $A000, $E000 I/O in $D000
|
2019-07-30 13:01:43 +00:00
|
|
|
.const PROCPORT_RAM_IO = 5
|
2018-04-15 21:32:49 +00:00
|
|
|
.label RASTER = $d012
|
|
|
|
.label BORDERCOL = $d020
|
|
|
|
.label VIC_CONTROL = $d011
|
|
|
|
.const VIC_ECM = $40
|
|
|
|
.const VIC_DEN = $10
|
|
|
|
.const VIC_RSEL = 8
|
|
|
|
.label VIC_CONTROL2 = $d016
|
|
|
|
.const VIC_MCM = $10
|
|
|
|
.const VIC_CSEL = 8
|
|
|
|
.label VIC_MEMORY = $d018
|
2019-02-17 23:12:29 +00:00
|
|
|
// CIA#2 Port A: Serial bus, RS-232, VIC memory bank
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CIA2_PORT_A = $dd00
|
2019-02-17 23:12:29 +00:00
|
|
|
// CIA #2 Port A data direction register.
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CIA2_PORT_A_DDR = $dd02
|
2019-02-17 23:12:29 +00:00
|
|
|
// Feature enables or disables the extra C64 DTV features
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_FEATURE = $d03f
|
|
|
|
.const DTV_FEATURE_ENABLE = 1
|
2019-02-17 23:12:29 +00:00
|
|
|
// Controls the graphics modes of the C64 DTV
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_CONTROL = $d03c
|
|
|
|
.const DTV_LINEAR = 1
|
|
|
|
.const DTV_HIGHCOLOR = 4
|
|
|
|
.const DTV_COLORRAM_OFF = $10
|
|
|
|
.const DTV_BADLINE_OFF = $20
|
|
|
|
.const DTV_CHUNKY = $40
|
2019-02-17 23:12:29 +00:00
|
|
|
// Defines colors for the 16 first colors ($00-$0f)
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_PALETTE = $d200
|
2019-02-17 23:12:29 +00:00
|
|
|
// Linear Graphics Plane B Counter Control
|
2018-04-15 21:32:49 +00:00
|
|
|
.label DTV_PLANEB_START_LO = $d049
|
|
|
|
.label DTV_PLANEB_START_MI = $d04a
|
|
|
|
.label DTV_PLANEB_START_HI = $d04b
|
|
|
|
.label DTV_PLANEB_STEP = $d04c
|
|
|
|
.label DTV_PLANEB_MODULO_LO = $d047
|
|
|
|
.label DTV_PLANEB_MODULO_HI = $d048
|
2019-02-17 23:12:29 +00:00
|
|
|
// Plane with all pixels
|
2018-04-15 21:32:49 +00:00
|
|
|
.label CHUNKY = $8000
|
2019-07-08 14:43:09 +00:00
|
|
|
// @begin
|
|
|
|
// [1] phi from @begin to @1 [phi:@begin->@1]
|
|
|
|
// @1
|
|
|
|
// [2] call main
|
|
|
|
// [3] phi from @1 to @end [phi:@1->@end]
|
|
|
|
// @end
|
|
|
|
// main
|
2018-04-15 21:32:49 +00:00
|
|
|
main: {
|
2019-07-08 14:43:09 +00:00
|
|
|
// asm
|
|
|
|
// asm { sei }
|
2018-04-15 21:32:49 +00:00
|
|
|
sei
|
2019-07-08 14:43:09 +00:00
|
|
|
// *PROCPORT_DDR = PROCPORT_DDR_MEMORY_MASK
|
2019-09-29 18:57:23 +00:00
|
|
|
// [5] *((const byte*) PROCPORT_DDR) ← (const byte) PROCPORT_DDR_MEMORY_MASK -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Disable normal interrupt (prevent keyboard reading glitches and allows to hide basic/kernal)
|
|
|
|
// Disable kernal & basic
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #PROCPORT_DDR_MEMORY_MASK
|
|
|
|
sta PROCPORT_DDR
|
2019-07-08 14:43:09 +00:00
|
|
|
// *PROCPORT = PROCPORT_RAM_IO
|
2019-09-29 18:57:23 +00:00
|
|
|
// [6] *((const byte*) PROCPORT) ← (const byte) PROCPORT_RAM_IO -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #PROCPORT_RAM_IO
|
|
|
|
sta PROCPORT
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky()
|
|
|
|
// [7] call gfx_init_chunky
|
|
|
|
// [38] phi from main to gfx_init_chunky [phi:main->gfx_init_chunky]
|
2018-04-15 21:32:49 +00:00
|
|
|
jsr gfx_init_chunky
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@6
|
|
|
|
// *DTV_FEATURE = DTV_FEATURE_ENABLE
|
2019-09-29 18:57:23 +00:00
|
|
|
// [8] *((const byte*) DTV_FEATURE) ← (const byte) DTV_FEATURE_ENABLE -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Enable DTV extended modes
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #DTV_FEATURE_ENABLE
|
|
|
|
sta DTV_FEATURE
|
2019-07-08 14:43:09 +00:00
|
|
|
// *DTV_CONTROL = DTV_HIGHCOLOR | DTV_LINEAR | DTV_COLORRAM_OFF | DTV_CHUNKY | DTV_BADLINE_OFF
|
2019-09-29 18:57:23 +00:00
|
|
|
// [9] *((const byte*) DTV_CONTROL) ← (const byte) DTV_HIGHCOLOR|(const byte) DTV_LINEAR|(const byte) DTV_COLORRAM_OFF|(const byte) DTV_CHUNKY|(const byte) DTV_BADLINE_OFF -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// 8BPP Pixel Cell Mode
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #DTV_HIGHCOLOR|DTV_LINEAR|DTV_COLORRAM_OFF|DTV_CHUNKY|DTV_BADLINE_OFF
|
|
|
|
sta DTV_CONTROL
|
2019-07-08 14:43:09 +00:00
|
|
|
// *VIC_CONTROL = VIC_DEN | VIC_ECM | VIC_RSEL | 3
|
2019-09-29 18:57:23 +00:00
|
|
|
// [10] *((const byte*) VIC_CONTROL) ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(byte) 3 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_DEN|VIC_ECM|VIC_RSEL|3
|
|
|
|
sta VIC_CONTROL
|
2019-07-08 14:43:09 +00:00
|
|
|
// *VIC_CONTROL2 = VIC_MCM | VIC_CSEL
|
2019-09-29 18:57:23 +00:00
|
|
|
// [11] *((const byte*) VIC_CONTROL2) ← (const byte) VIC_MCM|(const byte) VIC_CSEL -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_MCM|VIC_CSEL
|
|
|
|
sta VIC_CONTROL2
|
2019-07-08 14:43:09 +00:00
|
|
|
// *DTV_PLANEB_START_LO = < CHUNKY
|
2019-09-29 18:57:23 +00:00
|
|
|
// [12] *((const byte*) DTV_PLANEB_START_LO) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Plane B: CHUNKY
|
2019-05-30 20:29:04 +00:00
|
|
|
lda #0
|
2018-04-15 21:32:49 +00:00
|
|
|
sta DTV_PLANEB_START_LO
|
2019-07-08 14:43:09 +00:00
|
|
|
// *DTV_PLANEB_START_MI = > CHUNKY
|
2019-09-29 18:57:23 +00:00
|
|
|
// [13] *((const byte*) DTV_PLANEB_START_MI) ← >(const byte*) CHUNKY -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #>CHUNKY
|
|
|
|
sta DTV_PLANEB_START_MI
|
2019-07-08 14:43:09 +00:00
|
|
|
// *DTV_PLANEB_START_HI = 0
|
2019-09-29 18:57:23 +00:00
|
|
|
// [14] *((const byte*) DTV_PLANEB_START_HI) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta DTV_PLANEB_START_HI
|
2019-07-08 14:43:09 +00:00
|
|
|
// *DTV_PLANEB_STEP = 8
|
2019-09-29 18:57:23 +00:00
|
|
|
// [15] *((const byte*) DTV_PLANEB_STEP) ← (byte) 8 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #8
|
|
|
|
sta DTV_PLANEB_STEP
|
2019-07-08 14:43:09 +00:00
|
|
|
// *DTV_PLANEB_MODULO_LO = 0
|
2019-09-29 18:57:23 +00:00
|
|
|
// [16] *((const byte*) DTV_PLANEB_MODULO_LO) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta DTV_PLANEB_MODULO_LO
|
2019-07-08 14:43:09 +00:00
|
|
|
// *DTV_PLANEB_MODULO_HI = 0
|
2019-09-29 18:57:23 +00:00
|
|
|
// [17] *((const byte*) DTV_PLANEB_MODULO_HI) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
sta DTV_PLANEB_MODULO_HI
|
2019-07-08 14:43:09 +00:00
|
|
|
// *CIA2_PORT_A_DDR = %00000011
|
2019-09-29 18:57:23 +00:00
|
|
|
// [18] *((const byte*) CIA2_PORT_A_DDR) ← (byte) 3 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// VIC Graphics Bank
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #3
|
|
|
|
sta CIA2_PORT_A_DDR
|
2019-07-08 14:43:09 +00:00
|
|
|
// *CIA2_PORT_A = %00000011 ^ (byte)((word)CHUNKY/$4000)
|
2019-09-29 18:57:23 +00:00
|
|
|
// [19] *((const byte*) CIA2_PORT_A) ← (byte) 3^(byte)(word)(const byte*) CHUNKY/(word) $4000 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set VIC Bank bits to output - all others to input
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #3^CHUNKY/$4000
|
|
|
|
sta CIA2_PORT_A
|
2019-07-08 14:43:09 +00:00
|
|
|
// *VIC_MEMORY = (byte)((((word)CHUNKY)&$3fff)/$40) | ((>(((word)CHUNKY)&$3fff))/4)
|
2019-09-29 18:57:23 +00:00
|
|
|
// [20] *((const byte*) VIC_MEMORY) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set VIC Bank
|
|
|
|
// VIC memory
|
2019-05-30 20:29:04 +00:00
|
|
|
lda #0
|
2018-04-15 21:32:49 +00:00
|
|
|
sta VIC_MEMORY
|
2019-07-08 14:43:09 +00:00
|
|
|
// [21] phi from main::@6 to main::@1 [phi:main::@6->main::@1]
|
|
|
|
// [21] phi (byte) main::j#2 = (byte) 0 [phi:main::@6->main::@1#0] -- vbuxx=vbuc1
|
2019-05-30 20:29:04 +00:00
|
|
|
tax
|
2019-02-17 23:12:29 +00:00
|
|
|
// DTV Palette - Grey Tones
|
2019-07-08 14:43:09 +00:00
|
|
|
// [21] phi from main::@1 to main::@1 [phi:main::@1->main::@1]
|
|
|
|
// [21] phi (byte) main::j#2 = (byte) main::j#1 [phi:main::@1->main::@1#0] -- register_copy
|
|
|
|
// main::@1
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1:
|
2019-07-08 14:43:09 +00:00
|
|
|
// DTV_PALETTE[j] = j
|
2019-09-29 18:57:23 +00:00
|
|
|
// [22] *((const byte*) DTV_PALETTE + (byte) main::j#2) ← (byte) main::j#2 -- pbuc1_derefidx_vbuxx=vbuxx
|
2018-04-15 21:32:49 +00:00
|
|
|
txa
|
|
|
|
sta DTV_PALETTE,x
|
2019-07-08 14:43:09 +00:00
|
|
|
// for(byte j : 0..$f)
|
|
|
|
// [23] (byte) main::j#1 ← ++ (byte) main::j#2 -- vbuxx=_inc_vbuxx
|
2018-04-15 21:32:49 +00:00
|
|
|
inx
|
2019-07-08 14:43:09 +00:00
|
|
|
// [24] if((byte) main::j#1!=(byte) $10) goto main::@1 -- vbuxx_neq_vbuc1_then_la1
|
2018-04-15 21:32:49 +00:00
|
|
|
cpx #$10
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b1
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@2
|
2019-09-29 21:13:37 +00:00
|
|
|
__b2:
|
2019-07-08 14:43:09 +00:00
|
|
|
// asm
|
|
|
|
// asm { ldx#$ff rff: cpxRASTER bnerff stabilize: nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop cpxRASTER beqeat+0 eat: inx cpx#$08 bnestabilize }
|
2019-02-17 23:12:29 +00:00
|
|
|
// Stabilize Raster
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx #$ff
|
|
|
|
rff:
|
|
|
|
cpx RASTER
|
|
|
|
bne rff
|
|
|
|
stabilize:
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
cpx RASTER
|
|
|
|
beq eat+0
|
|
|
|
eat:
|
|
|
|
inx
|
|
|
|
cpx #8
|
|
|
|
bne stabilize
|
2019-07-08 14:43:09 +00:00
|
|
|
// *VIC_CONTROL = VIC_DEN | VIC_ECM | VIC_RSEL | 3
|
2019-09-29 18:57:23 +00:00
|
|
|
// [26] *((const byte*) VIC_CONTROL) ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL|(byte) 3 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #VIC_DEN|VIC_ECM|VIC_RSEL|3
|
|
|
|
sta VIC_CONTROL
|
2019-07-08 14:43:09 +00:00
|
|
|
// *BORDERCOL = 0
|
2019-09-29 18:57:23 +00:00
|
|
|
// [27] *((const byte*) BORDERCOL) ← (byte) 0 -- _deref_pbuc1=vbuc2
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
|
|
|
sta BORDERCOL
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@3
|
2019-09-29 21:13:37 +00:00
|
|
|
__b3:
|
2019-07-08 14:43:09 +00:00
|
|
|
// while(*RASTER!=rst)
|
2019-09-29 18:57:23 +00:00
|
|
|
// [28] if(*((const byte*) RASTER)!=(byte) $42) goto main::@3 -- _deref_pbuc1_neq_vbuc2_then_la1
|
2019-03-26 22:49:44 +00:00
|
|
|
lda #$42
|
|
|
|
cmp RASTER
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b3
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@4
|
|
|
|
// asm
|
|
|
|
// asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
|
2018-04-15 21:32:49 +00:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2019-07-08 14:43:09 +00:00
|
|
|
// main::@5
|
2019-09-29 21:13:37 +00:00
|
|
|
__b5:
|
2019-07-08 14:43:09 +00:00
|
|
|
// rst = *RASTER
|
2019-09-29 18:57:23 +00:00
|
|
|
// [30] (byte) main::rst#1 ← *((const byte*) RASTER) -- vbuxx=_deref_pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx RASTER
|
2019-07-08 14:43:09 +00:00
|
|
|
// rst&7
|
2019-11-03 16:05:55 +00:00
|
|
|
// [31] (byte~) main::$16 ← (byte) main::rst#1 & (byte) 7 -- vbuaa=vbuxx_band_vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
txa
|
|
|
|
and #7
|
2019-07-08 14:43:09 +00:00
|
|
|
// VIC_DEN | VIC_ECM | VIC_RSEL | (rst&7)
|
2019-11-03 16:05:55 +00:00
|
|
|
// [32] (byte~) main::$17 ← (const byte) VIC_DEN|(const byte) VIC_ECM|(const byte) VIC_RSEL | (byte~) main::$16 -- vbuaa=vbuc1_bor_vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
ora #VIC_DEN|VIC_ECM|VIC_RSEL
|
2019-07-08 14:43:09 +00:00
|
|
|
// *VIC_CONTROL = VIC_DEN | VIC_ECM | VIC_RSEL | (rst&7)
|
2019-11-03 16:05:55 +00:00
|
|
|
// [33] *((const byte*) VIC_CONTROL) ← (byte~) main::$17 -- _deref_pbuc1=vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
sta VIC_CONTROL
|
2019-07-08 14:43:09 +00:00
|
|
|
// rst*$10
|
2019-11-03 16:05:55 +00:00
|
|
|
// [34] (byte~) main::$18 ← (byte) main::rst#1 << (byte) 4 -- vbuaa=vbuxx_rol_4
|
2018-04-15 21:32:49 +00:00
|
|
|
txa
|
|
|
|
asl
|
|
|
|
asl
|
|
|
|
asl
|
|
|
|
asl
|
2019-07-08 14:43:09 +00:00
|
|
|
// *BORDERCOL = rst*$10
|
2019-11-03 16:05:55 +00:00
|
|
|
// [35] *((const byte*) BORDERCOL) ← (byte~) main::$18 -- _deref_pbuc1=vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
sta BORDERCOL
|
2019-07-08 14:43:09 +00:00
|
|
|
// asm
|
|
|
|
// asm { nop nop nop nop nop nop nop nop nop nop nop nop nop nop nop }
|
2018-04-15 21:32:49 +00:00
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
2019-07-08 14:43:09 +00:00
|
|
|
// while (rst!=$f2)
|
|
|
|
// [37] if((byte) main::rst#1!=(byte) $f2) goto main::@5 -- vbuxx_neq_vbuc1_then_la1
|
2018-04-15 21:32:49 +00:00
|
|
|
cpx #$f2
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b5
|
|
|
|
jmp __b2
|
2018-04-15 21:32:49 +00:00
|
|
|
}
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky
|
2019-02-17 23:12:29 +00:00
|
|
|
// Initialize Plane with 8bpp chunky
|
2018-04-15 21:32:49 +00:00
|
|
|
gfx_init_chunky: {
|
2019-11-03 16:05:55 +00:00
|
|
|
.label __7 = 7
|
2018-04-15 21:32:49 +00:00
|
|
|
.label gfxb = 5
|
|
|
|
.label x = 3
|
|
|
|
.label y = 2
|
2019-07-08 14:43:09 +00:00
|
|
|
// dtvSetCpuBankSegment1(gfxbCpuBank++)
|
|
|
|
// [39] call dtvSetCpuBankSegment1
|
|
|
|
// [58] phi from gfx_init_chunky to dtvSetCpuBankSegment1 [phi:gfx_init_chunky->dtvSetCpuBankSegment1]
|
2019-09-29 18:57:23 +00:00
|
|
|
// [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = (byte)(const byte*) CHUNKY/(word) $4000 [phi:gfx_init_chunky->dtvSetCpuBankSegment1#0] -- vbuaa=vbuc1
|
2019-05-30 20:29:04 +00:00
|
|
|
lda #CHUNKY/$4000
|
2018-04-15 21:32:49 +00:00
|
|
|
jsr dtvSetCpuBankSegment1
|
2019-07-08 14:43:09 +00:00
|
|
|
// [40] phi from gfx_init_chunky to gfx_init_chunky::@1 [phi:gfx_init_chunky->gfx_init_chunky::@1]
|
2019-09-29 18:57:23 +00:00
|
|
|
// [40] phi (byte) gfx_init_chunky::gfxbCpuBank#7 = ++(byte)(const byte*) CHUNKY/(word) $4000 [phi:gfx_init_chunky->gfx_init_chunky::@1#0] -- vbuxx=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
ldx #($ff&CHUNKY/$4000)+1
|
2019-07-08 14:43:09 +00:00
|
|
|
// [40] phi (byte) gfx_init_chunky::y#6 = (byte) 0 [phi:gfx_init_chunky->gfx_init_chunky::@1#1] -- vbuz1=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z y
|
2019-07-08 14:43:09 +00:00
|
|
|
// [40] phi (byte*) gfx_init_chunky::gfxb#5 = (byte*) 16384 [phi:gfx_init_chunky->gfx_init_chunky::@1#2] -- pbuz1=pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #<$4000
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z gfxb
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #>$4000
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z gfxb+1
|
2019-07-08 14:43:09 +00:00
|
|
|
// [40] phi from gfx_init_chunky::@5 to gfx_init_chunky::@1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1]
|
|
|
|
// [40] phi (byte) gfx_init_chunky::gfxbCpuBank#7 = (byte) gfx_init_chunky::gfxbCpuBank#8 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#0] -- register_copy
|
|
|
|
// [40] phi (byte) gfx_init_chunky::y#6 = (byte) gfx_init_chunky::y#1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#1] -- register_copy
|
|
|
|
// [40] phi (byte*) gfx_init_chunky::gfxb#5 = (byte*) gfx_init_chunky::gfxb#1 [phi:gfx_init_chunky::@5->gfx_init_chunky::@1#2] -- register_copy
|
|
|
|
// gfx_init_chunky::@1
|
2019-09-29 21:13:37 +00:00
|
|
|
__b1:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [41] phi from gfx_init_chunky::@1 to gfx_init_chunky::@2 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2]
|
|
|
|
// [41] phi (byte) gfx_init_chunky::gfxbCpuBank#4 = (byte) gfx_init_chunky::gfxbCpuBank#7 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#0] -- register_copy
|
|
|
|
// [41] phi (word) gfx_init_chunky::x#2 = (word) 0 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#1] -- vwuz1=vwuc1
|
2019-06-02 22:44:46 +00:00
|
|
|
lda #<0
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z x
|
|
|
|
sta.z x+1
|
2019-07-08 14:43:09 +00:00
|
|
|
// [41] phi (byte*) gfx_init_chunky::gfxb#3 = (byte*) gfx_init_chunky::gfxb#5 [phi:gfx_init_chunky::@1->gfx_init_chunky::@2#2] -- register_copy
|
|
|
|
// [41] phi from gfx_init_chunky::@3 to gfx_init_chunky::@2 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2]
|
|
|
|
// [41] phi (byte) gfx_init_chunky::gfxbCpuBank#4 = (byte) gfx_init_chunky::gfxbCpuBank#8 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#0] -- register_copy
|
|
|
|
// [41] phi (word) gfx_init_chunky::x#2 = (word) gfx_init_chunky::x#1 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#1] -- register_copy
|
|
|
|
// [41] phi (byte*) gfx_init_chunky::gfxb#3 = (byte*) gfx_init_chunky::gfxb#1 [phi:gfx_init_chunky::@3->gfx_init_chunky::@2#2] -- register_copy
|
|
|
|
// gfx_init_chunky::@2
|
2019-09-29 21:13:37 +00:00
|
|
|
__b2:
|
2019-07-08 14:43:09 +00:00
|
|
|
// if(gfxb==$8000)
|
|
|
|
// [42] if((byte*) gfx_init_chunky::gfxb#3!=(word) $8000) goto gfx_init_chunky::@3 -- pbuz1_neq_vwuc1_then_la1
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z gfxb+1
|
2018-04-15 21:32:49 +00:00
|
|
|
cmp #>$8000
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b3
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z gfxb
|
2018-04-15 21:32:49 +00:00
|
|
|
cmp #<$8000
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b3
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@4
|
|
|
|
// dtvSetCpuBankSegment1(gfxbCpuBank++)
|
|
|
|
// [43] (byte) dtvSetCpuBankSegment1::cpuBankIdx#1 ← (byte) gfx_init_chunky::gfxbCpuBank#4 -- vbuaa=vbuxx
|
2018-04-15 21:32:49 +00:00
|
|
|
txa
|
2019-07-08 14:43:09 +00:00
|
|
|
// [44] call dtvSetCpuBankSegment1
|
|
|
|
// [58] phi from gfx_init_chunky::@4 to dtvSetCpuBankSegment1 [phi:gfx_init_chunky::@4->dtvSetCpuBankSegment1]
|
|
|
|
// [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = (byte) dtvSetCpuBankSegment1::cpuBankIdx#1 [phi:gfx_init_chunky::@4->dtvSetCpuBankSegment1#0] -- register_copy
|
2018-04-15 21:32:49 +00:00
|
|
|
jsr dtvSetCpuBankSegment1
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@7
|
|
|
|
// dtvSetCpuBankSegment1(gfxbCpuBank++);
|
|
|
|
// [45] (byte) gfx_init_chunky::gfxbCpuBank#2 ← ++ (byte) gfx_init_chunky::gfxbCpuBank#4 -- vbuxx=_inc_vbuxx
|
2018-04-15 21:32:49 +00:00
|
|
|
inx
|
2019-07-08 14:43:09 +00:00
|
|
|
// [46] phi from gfx_init_chunky::@7 to gfx_init_chunky::@3 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3]
|
|
|
|
// [46] phi (byte) gfx_init_chunky::gfxbCpuBank#8 = (byte) gfx_init_chunky::gfxbCpuBank#2 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3#0] -- register_copy
|
|
|
|
// [46] phi (byte*) gfx_init_chunky::gfxb#4 = (byte*) 16384 [phi:gfx_init_chunky::@7->gfx_init_chunky::@3#1] -- pbuz1=pbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #<$4000
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z gfxb
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #>$4000
|
2019-08-07 19:00:19 +00:00
|
|
|
sta.z gfxb+1
|
2019-07-08 14:43:09 +00:00
|
|
|
// [46] phi from gfx_init_chunky::@2 to gfx_init_chunky::@3 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3]
|
|
|
|
// [46] phi (byte) gfx_init_chunky::gfxbCpuBank#8 = (byte) gfx_init_chunky::gfxbCpuBank#4 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3#0] -- register_copy
|
|
|
|
// [46] phi (byte*) gfx_init_chunky::gfxb#4 = (byte*) gfx_init_chunky::gfxb#3 [phi:gfx_init_chunky::@2->gfx_init_chunky::@3#1] -- register_copy
|
|
|
|
// gfx_init_chunky::@3
|
2019-09-29 21:13:37 +00:00
|
|
|
__b3:
|
2019-07-08 14:43:09 +00:00
|
|
|
// x+y
|
2019-11-03 16:05:55 +00:00
|
|
|
// [47] (word~) gfx_init_chunky::$7 ← (word) gfx_init_chunky::x#2 + (byte) gfx_init_chunky::y#6 -- vwuz1=vwuz2_plus_vbuz3
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z y
|
2018-04-15 21:32:49 +00:00
|
|
|
clc
|
2019-08-07 19:00:19 +00:00
|
|
|
adc.z x
|
2019-11-03 16:05:55 +00:00
|
|
|
sta.z __7
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #0
|
2019-08-07 19:00:19 +00:00
|
|
|
adc.z x+1
|
2019-11-03 16:05:55 +00:00
|
|
|
sta.z __7+1
|
2019-07-08 14:43:09 +00:00
|
|
|
// c = (byte)(x+y)
|
2019-11-03 16:05:55 +00:00
|
|
|
// [48] (byte) gfx_init_chunky::c#0 ← (byte)(word~) gfx_init_chunky::$7 -- vbuaa=_byte_vwuz1
|
|
|
|
lda.z __7
|
2019-07-08 14:43:09 +00:00
|
|
|
// *gfxb++ = c
|
|
|
|
// [49] *((byte*) gfx_init_chunky::gfxb#4) ← (byte) gfx_init_chunky::c#0 -- _deref_pbuz1=vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
ldy #0
|
|
|
|
sta (gfxb),y
|
2019-07-08 14:43:09 +00:00
|
|
|
// *gfxb++ = c;
|
|
|
|
// [50] (byte*) gfx_init_chunky::gfxb#1 ← ++ (byte*) gfx_init_chunky::gfxb#4 -- pbuz1=_inc_pbuz1
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z gfxb
|
2018-04-15 21:32:49 +00:00
|
|
|
bne !+
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z gfxb+1
|
2018-04-15 21:32:49 +00:00
|
|
|
!:
|
2019-07-08 14:43:09 +00:00
|
|
|
// for (word x : 0..319)
|
|
|
|
// [51] (word) gfx_init_chunky::x#1 ← ++ (word) gfx_init_chunky::x#2 -- vwuz1=_inc_vwuz1
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z x
|
2018-04-15 21:32:49 +00:00
|
|
|
bne !+
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z x+1
|
2018-04-15 21:32:49 +00:00
|
|
|
!:
|
2019-07-08 14:43:09 +00:00
|
|
|
// [52] if((word) gfx_init_chunky::x#1!=(word) $140) goto gfx_init_chunky::@2 -- vwuz1_neq_vwuc1_then_la1
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z x+1
|
2018-04-15 21:32:49 +00:00
|
|
|
cmp #>$140
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b2
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z x
|
2018-04-15 21:32:49 +00:00
|
|
|
cmp #<$140
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b2
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@5
|
|
|
|
// for(byte y : 0..50)
|
|
|
|
// [53] (byte) gfx_init_chunky::y#1 ← ++ (byte) gfx_init_chunky::y#6 -- vbuz1=_inc_vbuz1
|
2019-08-07 19:00:19 +00:00
|
|
|
inc.z y
|
2019-07-08 14:43:09 +00:00
|
|
|
// [54] if((byte) gfx_init_chunky::y#1!=(byte) $33) goto gfx_init_chunky::@1 -- vbuz1_neq_vbuc1_then_la1
|
2019-03-26 22:49:44 +00:00
|
|
|
lda #$33
|
2019-08-07 19:00:19 +00:00
|
|
|
cmp.z y
|
2019-09-29 21:13:37 +00:00
|
|
|
bne __b1
|
2019-07-08 14:43:09 +00:00
|
|
|
// [55] phi from gfx_init_chunky::@5 to gfx_init_chunky::@6 [phi:gfx_init_chunky::@5->gfx_init_chunky::@6]
|
|
|
|
// gfx_init_chunky::@6
|
|
|
|
// dtvSetCpuBankSegment1((byte)($4000/$4000))
|
|
|
|
// [56] call dtvSetCpuBankSegment1
|
|
|
|
// [58] phi from gfx_init_chunky::@6 to dtvSetCpuBankSegment1 [phi:gfx_init_chunky::@6->dtvSetCpuBankSegment1]
|
|
|
|
// [58] phi (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 = (byte)(number) $4000/(number) $4000 [phi:gfx_init_chunky::@6->dtvSetCpuBankSegment1#0] -- vbuaa=vbuc1
|
2018-04-15 21:32:49 +00:00
|
|
|
lda #$4000/$4000
|
|
|
|
jsr dtvSetCpuBankSegment1
|
2019-07-08 14:43:09 +00:00
|
|
|
// gfx_init_chunky::@return
|
|
|
|
// }
|
|
|
|
// [57] return
|
2018-04-15 21:32:49 +00:00
|
|
|
rts
|
|
|
|
}
|
2019-07-08 14:43:09 +00:00
|
|
|
// dtvSetCpuBankSegment1
|
2019-02-17 23:12:29 +00:00
|
|
|
// Set the memory pointed to by CPU BANK 1 SEGMENT ($4000-$7fff)
|
|
|
|
// This sets which actual memory is addressed when the CPU reads/writes to $4000-$7fff
|
|
|
|
// The actual memory addressed will be $4000*cpuSegmentIdx
|
2019-02-19 19:51:48 +00:00
|
|
|
// dtvSetCpuBankSegment1(byte register(A) cpuBankIdx)
|
2018-04-15 21:32:49 +00:00
|
|
|
dtvSetCpuBankSegment1: {
|
2019-02-17 23:12:29 +00:00
|
|
|
// Move CPU BANK 1 SEGMENT ($4000-$7fff)
|
2018-04-15 21:32:49 +00:00
|
|
|
.label cpuBank = $ff
|
2019-07-08 14:43:09 +00:00
|
|
|
// *cpuBank = cpuBankIdx
|
2019-09-29 20:36:00 +00:00
|
|
|
// [59] *((const byte*) dtvSetCpuBankSegment1::cpuBank) ← (byte) dtvSetCpuBankSegment1::cpuBankIdx#3 -- _deref_pbuc1=vbuaa
|
2018-04-15 21:32:49 +00:00
|
|
|
sta cpuBank
|
2019-07-08 14:43:09 +00:00
|
|
|
// asm
|
|
|
|
// asm { .byte$32,$dd lda$ff .byte$32,$00 }
|
2018-04-15 21:32:49 +00:00
|
|
|
.byte $32, $dd
|
2019-08-07 19:00:19 +00:00
|
|
|
lda.z $ff
|
2018-04-15 21:32:49 +00:00
|
|
|
.byte $32, $00
|
2019-07-08 14:43:09 +00:00
|
|
|
// dtvSetCpuBankSegment1::@return
|
|
|
|
// }
|
|
|
|
// [61] return
|
2018-04-15 21:32:49 +00:00
|
|
|
rts
|
|
|
|
}
|
2019-07-08 14:43:09 +00:00
|
|
|
// File Data
|
2018-04-15 21:32:49 +00:00
|
|
|
|