diff --git a/src/main/kc/lib/sine.c b/src/main/kc/lib/sine.c
index f88014847..5a9ea5cd8 100644
--- a/src/main/kc/lib/sine.c
+++ b/src/main/kc/lib/sine.c
@@ -80,7 +80,7 @@ signed int sin16s(unsigned long x) {
         x = PI_u4f28 - x;
     }
     // sinx = x - x^3/6 + x5/128;
-    unsigned int x1 = WORD1(x)<<3; // u[1.15]
+    unsigned int x1 = WORD1(x<<3); // u[1.15]
     unsigned int x2 = mulu16_sel(x1, x1, 0); // u[2.14] x^2
     unsigned int x3 = mulu16_sel(x2, x1, 1); // u[2.14] x^3
     unsigned int x3_6 = mulu16_sel(x3, $10000/6, 1);  // u[1.15] x^3/6;
diff --git a/src/test/ref/bitmap-plotter.asm b/src/test/ref/bitmap-plotter.asm
index 3baf912a6..68e79cfee 100644
--- a/src/test/ref/bitmap-plotter.asm
+++ b/src/test/ref/bitmap-plotter.asm
@@ -110,7 +110,7 @@ init_plot_tables: {
     and #$f8
     // plot_xlo[x] = x&$f8
     sta plot_xlo,x
-    // plot_xhi[x] = >BITMAP
+    // plot_xhi[x] = BYTE1(BITMAP)
     lda #>BITMAP
     sta plot_xhi,x
     // plot_bit[x] = bits
@@ -137,15 +137,15 @@ init_plot_tables: {
     // y&$7
     lda #7
     sax.z __9
-    // <yoffs
+    // BYTE0(yoffs)
     lda.z yoffs
-    // y&$7 | <yoffs
+    // y&$7 | BYTE0(yoffs)
     ora.z __9
-    // plot_ylo[y] = y&$7 | <yoffs
+    // plot_ylo[y] = y&$7 | BYTE0(yoffs)
     sta plot_ylo,x
-    // >yoffs
+    // BYTE1(yoffs)
     lda.z yoffs+1
-    // plot_yhi[y] = >yoffs
+    // plot_yhi[y] = BYTE1(yoffs)
     sta plot_yhi,x
     // if((y&$7)==7)
     lda #7
diff --git a/src/test/ref/bitmap-plotter.log b/src/test/ref/bitmap-plotter.log
index aba3500a2..0a61e8fcf 100644
--- a/src/test/ref/bitmap-plotter.log
+++ b/src/test/ref/bitmap-plotter.log
@@ -1480,9 +1480,9 @@ Missing ASM fragment Fragment not found pbuz1=pbuz2_setbyte0_vbuaa. Attempted va
 Warning! Unknown fragment for statement [57] plot::plotter_x#2 = plot::plotter_x#1 byte0= plot::$7
 Missing ASM fragment Fragment not found pbuz1=pbuz2_setbyte0_vbuaa. Attempted variations pbuz1=pbuz2_setbyte0_vbuaa 
 /Users/jespergravgaard/c64/kickc/src/test/kc/bitmap-plotter.c:56:5:
-Warning! Unknown fragment for statement [57] plot::plotter_x#2 = plot::plotter_x#1 byte0= plot::$7
-Missing ASM fragment Fragment not found pbuz1=pbuz2_setbyte0_vbuaa. Attempted variations pbuz1=pbuz2_setbyte0_vbuaa 
-/Users/jespergravgaard/c64/kickc/src/test/kc/bitmap-plotter.c:56:5:
+Warning! Unknown fragment for statement [36] init_plot_tables::$7 = init_plot_tables::$9 | init_plot_tables::$6
+Missing ASM fragment Fragment not found vbuz1=vbuz2_bor__byte0_pbuz3. Attempted variations vbuz1=vbuz2_bor__byte0_pbuz3 
+/Users/jespergravgaard/c64/kickc/src/test/kc/bitmap-plotter.c:76:23:
 Uplifting [init_plot_tables] best 9784 combination reg byte a [ init_plot_tables::$6 ] 
 Attempting to uplift remaining variables inzp[1]:15 [ init_plot_tables::$7 ]
 Warning! Unknown fragment for statement [57] plot::plotter_x#2 = plot::plotter_x#1 byte0= plot::$7
@@ -1752,13 +1752,13 @@ init_plot_tables: {
     // [34] init_plot_tables::$9 = init_plot_tables::y#2 & 7 -- vbuz1=vbuxx_band_vbuc1 
     lda #7
     sax.z __9
-    // [35] init_plot_tables::$6 = < init_plot_tables::yoffs#2 -- vbuaa=_lo_pbuz1 
+    // [35] init_plot_tables::$6 = < init_plot_tables::yoffs#2 -- vbuaa=_byte0_pbuz1 
     lda.z yoffs
     // [36] init_plot_tables::$7 = init_plot_tables::$9 | init_plot_tables::$6 -- vbuaa=vbuz1_bor_vbuaa 
     ora.z __9
     // [37] plot_ylo[init_plot_tables::y#2] = init_plot_tables::$7 -- pbuc1_derefidx_vbuxx=vbuaa 
     sta plot_ylo,x
-    // [38] init_plot_tables::$8 = > init_plot_tables::yoffs#2 -- vbuaa=_hi_pbuz1 
+    // [38] init_plot_tables::$8 = > init_plot_tables::yoffs#2 -- vbuaa=_byte1_pbuz1 
     lda.z yoffs+1
     // [39] plot_yhi[init_plot_tables::y#2] = init_plot_tables::$8 -- pbuc1_derefidx_vbuxx=vbuaa 
     sta plot_yhi,x
@@ -2226,7 +2226,7 @@ init_plot_tables: {
     // plot_xlo[x] = x&$f8
     // [24] plot_xlo[init_plot_tables::x#2] = init_plot_tables::$0 -- pbuc1_derefidx_vbuxx=vbuaa 
     sta plot_xlo,x
-    // plot_xhi[x] = >BITMAP
+    // plot_xhi[x] = BYTE1(BITMAP)
     // [25] plot_xhi[init_plot_tables::x#2] = >BITMAP -- pbuc1_derefidx_vbuxx=vbuc2 
     lda #>BITMAP
     sta plot_xhi,x
@@ -2274,19 +2274,19 @@ init_plot_tables: {
     // [34] init_plot_tables::$9 = init_plot_tables::y#2 & 7 -- vbuz1=vbuxx_band_vbuc1 
     lda #7
     sax.z __9
-    // <yoffs
-    // [35] init_plot_tables::$6 = < init_plot_tables::yoffs#2 -- vbuaa=_lo_pbuz1 
+    // BYTE0(yoffs)
+    // [35] init_plot_tables::$6 = < init_plot_tables::yoffs#2 -- vbuaa=_byte0_pbuz1 
     lda.z yoffs
-    // y&$7 | <yoffs
+    // y&$7 | BYTE0(yoffs)
     // [36] init_plot_tables::$7 = init_plot_tables::$9 | init_plot_tables::$6 -- vbuaa=vbuz1_bor_vbuaa 
     ora.z __9
-    // plot_ylo[y] = y&$7 | <yoffs
+    // plot_ylo[y] = y&$7 | BYTE0(yoffs)
     // [37] plot_ylo[init_plot_tables::y#2] = init_plot_tables::$7 -- pbuc1_derefidx_vbuxx=vbuaa 
     sta plot_ylo,x
-    // >yoffs
-    // [38] init_plot_tables::$8 = > init_plot_tables::yoffs#2 -- vbuaa=_hi_pbuz1 
+    // BYTE1(yoffs)
+    // [38] init_plot_tables::$8 = > init_plot_tables::yoffs#2 -- vbuaa=_byte1_pbuz1 
     lda.z yoffs+1
-    // plot_yhi[y] = >yoffs
+    // plot_yhi[y] = BYTE1(yoffs)
     // [39] plot_yhi[init_plot_tables::y#2] = init_plot_tables::$8 -- pbuc1_derefidx_vbuxx=vbuaa 
     sta plot_yhi,x
     // if((y&$7)==7)
diff --git a/src/test/ref/linegen.asm b/src/test/ref/linegen.asm
index c382e8f95..7cbd61bd5 100644
--- a/src/test/ref/linegen.asm
+++ b/src/test/ref/linegen.asm
@@ -298,12 +298,12 @@ lin16u_gen: {
     // }
     rts
   __b2:
-    // >val
+    // WORD1(val)
     lda.z val+2
     sta.z __6
     lda.z val+3
     sta.z __6+1
-    // *lintab = >val
+    // *lintab = WORD1(val)
     ldy #0
     lda.z __6
     sta (lintab),y
@@ -374,10 +374,10 @@ print_str: {
 // print_uint(word zp(9) w)
 print_uint: {
     .label w = 9
-    // print_uchar(>w)
+    // print_uchar(BYTE1(w))
     ldx.z w+1
     jsr print_uchar
-    // print_uchar(<w)
+    // print_uchar(BYTE0(w))
     ldx.z w
     jsr print_uchar
     // }
@@ -447,11 +447,11 @@ divr16u: {
     // rem = rem << 1
     asl.z rem
     rol.z rem+1
-    // >dividend
+    // BYTE1(dividend)
     lda.z dividend+1
-    // >dividend & $80
+    // BYTE1(dividend) & $80
     and #$80
-    // if( (>dividend & $80) != 0 )
+    // if( (BYTE1(dividend) & $80) != 0 )
     cmp #0
     beq __b2
     // rem = rem | 1
diff --git a/src/test/ref/linegen.cfg b/src/test/ref/linegen.cfg
index b8bdd0031..fd9b81210 100644
--- a/src/test/ref/linegen.cfg
+++ b/src/test/ref/linegen.cfg
@@ -148,7 +148,7 @@ lin16u_gen::@return: scope:[lin16u_gen]  from lin16u_gen::@1
   [72] return 
   to:@return
 lin16u_gen::@2: scope:[lin16u_gen]  from lin16u_gen::@1
-  [73] lin16u_gen::$6 = > lin16u_gen::val#2
+  [73] lin16u_gen::$6 = _word1_ lin16u_gen::val#2
   [74] *lin16u_gen::lintab#4 = lin16u_gen::$6
   [75] lin16u_gen::val#1 = lin16u_gen::val#2 + lin16u_gen::step#0
   [76] lin16u_gen::lintab#3 = lin16u_gen::lintab#4 + SIZEOF_WORD
diff --git a/src/test/ref/linegen.log b/src/test/ref/linegen.log
index f9d47bc89..499b80370 100644
--- a/src/test/ref/linegen.log
+++ b/src/test/ref/linegen.log
@@ -598,7 +598,7 @@ lin16u_gen::@2: scope:[lin16u_gen]  from lin16u_gen::@1
   lin16u_gen::step#1 = phi( lin16u_gen::@1/lin16u_gen::step#2 )
   lin16u_gen::lintab#4 = phi( lin16u_gen::@1/lin16u_gen::lintab#5 )
   lin16u_gen::val#2 = phi( lin16u_gen::@1/lin16u_gen::val#3 )
-  lin16u_gen::$6 = > lin16u_gen::val#2
+  lin16u_gen::$6 = _word1_ lin16u_gen::val#2
   *lin16u_gen::lintab#4 = lin16u_gen::$6
   lin16u_gen::$7 = lin16u_gen::val#2 + lin16u_gen::step#1
   lin16u_gen::val#1 = lin16u_gen::$7
@@ -1919,7 +1919,7 @@ lin16u_gen::@return: scope:[lin16u_gen]  from lin16u_gen::@1
   [72] return 
   to:@return
 lin16u_gen::@2: scope:[lin16u_gen]  from lin16u_gen::@1
-  [73] lin16u_gen::$6 = > lin16u_gen::val#2
+  [73] lin16u_gen::$6 = _word1_ lin16u_gen::val#2
   [74] *lin16u_gen::lintab#4 = lin16u_gen::$6
   [75] lin16u_gen::val#1 = lin16u_gen::val#2 + lin16u_gen::step#0
   [76] lin16u_gen::lintab#3 = lin16u_gen::lintab#4 + SIZEOF_WORD
@@ -2294,7 +2294,7 @@ Statement [67] lin16u_gen::stepf#0 = divr16u::return#3 [ lin16u_gen::min#3 lin16
 Statement [68] lin16u_gen::step#0 = lin16u_gen::stepi#0 dw= lin16u_gen::stepf#0 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::step#0 ] ( lin16u_gen:1 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::step#0 ] { }  lin16u_gen:3 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::step#0 ] { }  lin16u_gen:5 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::step#0 ] { }  ) always clobbers reg byte a 
 Statement [69] lin16u_gen::val#0 = lin16u_gen::min#3 dw= 0 [ lin16u_gen::lintab#6 lin16u_gen::step#0 lin16u_gen::val#0 ] ( lin16u_gen:1 [ lin16u_gen::lintab#6 lin16u_gen::step#0 lin16u_gen::val#0 ] { }  lin16u_gen:3 [ lin16u_gen::lintab#6 lin16u_gen::step#0 lin16u_gen::val#0 ] { }  lin16u_gen:5 [ lin16u_gen::lintab#6 lin16u_gen::step#0 lin16u_gen::val#0 ] { }  ) always clobbers reg byte a 
 Statement [71] if(lin16u_gen::i#2<$14) goto lin16u_gen::@2 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] ( lin16u_gen:1 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { }  lin16u_gen:3 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { }  lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { }  ) always clobbers reg byte a 
-Statement [73] lin16u_gen::$6 = > lin16u_gen::val#2 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 lin16u_gen::$6 ] ( lin16u_gen:1 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 lin16u_gen::$6 ] { }  lin16u_gen:3 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 lin16u_gen::$6 ] { }  lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 lin16u_gen::$6 ] { }  ) always clobbers reg byte a 
+Statement [73] lin16u_gen::$6 = _word1_ lin16u_gen::val#2 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 lin16u_gen::$6 ] ( lin16u_gen:1 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 lin16u_gen::$6 ] { }  lin16u_gen:3 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 lin16u_gen::$6 ] { }  lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 lin16u_gen::$6 ] { }  ) always clobbers reg byte a 
 Statement [74] *lin16u_gen::lintab#4 = lin16u_gen::$6 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] ( lin16u_gen:1 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { }  lin16u_gen:3 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { }  lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { }  ) always clobbers reg byte a reg byte y 
 Statement [75] lin16u_gen::val#1 = lin16u_gen::val#2 + lin16u_gen::step#0 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::lintab#4 lin16u_gen::val#1 ] ( lin16u_gen:1 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::lintab#4 lin16u_gen::val#1 ] { }  lin16u_gen:3 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::lintab#4 lin16u_gen::val#1 ] { }  lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::lintab#4 lin16u_gen::val#1 ] { }  ) always clobbers reg byte a 
 Statement [76] lin16u_gen::lintab#3 = lin16u_gen::lintab#4 + SIZEOF_WORD [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#1 lin16u_gen::lintab#3 ] ( lin16u_gen:1 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#1 lin16u_gen::lintab#3 ] { }  lin16u_gen:3 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#1 lin16u_gen::lintab#3 ] { }  lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#1 lin16u_gen::lintab#3 ] { }  ) always clobbers reg byte a 
@@ -2331,7 +2331,7 @@ Statement [67] lin16u_gen::stepf#0 = divr16u::return#3 [ lin16u_gen::min#3 lin16
 Statement [68] lin16u_gen::step#0 = lin16u_gen::stepi#0 dw= lin16u_gen::stepf#0 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::step#0 ] ( lin16u_gen:1 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::step#0 ] { }  lin16u_gen:3 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::step#0 ] { }  lin16u_gen:5 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::step#0 ] { }  ) always clobbers reg byte a 
 Statement [69] lin16u_gen::val#0 = lin16u_gen::min#3 dw= 0 [ lin16u_gen::lintab#6 lin16u_gen::step#0 lin16u_gen::val#0 ] ( lin16u_gen:1 [ lin16u_gen::lintab#6 lin16u_gen::step#0 lin16u_gen::val#0 ] { }  lin16u_gen:3 [ lin16u_gen::lintab#6 lin16u_gen::step#0 lin16u_gen::val#0 ] { }  lin16u_gen:5 [ lin16u_gen::lintab#6 lin16u_gen::step#0 lin16u_gen::val#0 ] { }  ) always clobbers reg byte a 
 Statement [71] if(lin16u_gen::i#2<$14) goto lin16u_gen::@2 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] ( lin16u_gen:1 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { }  lin16u_gen:3 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { }  lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { }  ) always clobbers reg byte a 
-Statement [73] lin16u_gen::$6 = > lin16u_gen::val#2 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 lin16u_gen::$6 ] ( lin16u_gen:1 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 lin16u_gen::$6 ] { }  lin16u_gen:3 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 lin16u_gen::$6 ] { }  lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 lin16u_gen::$6 ] { }  ) always clobbers reg byte a 
+Statement [73] lin16u_gen::$6 = _word1_ lin16u_gen::val#2 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 lin16u_gen::$6 ] ( lin16u_gen:1 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 lin16u_gen::$6 ] { }  lin16u_gen:3 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 lin16u_gen::$6 ] { }  lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 lin16u_gen::$6 ] { }  ) always clobbers reg byte a 
 Statement [74] *lin16u_gen::lintab#4 = lin16u_gen::$6 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] ( lin16u_gen:1 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { }  lin16u_gen:3 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { }  lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { }  ) always clobbers reg byte a reg byte y 
 Statement [75] lin16u_gen::val#1 = lin16u_gen::val#2 + lin16u_gen::step#0 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::lintab#4 lin16u_gen::val#1 ] ( lin16u_gen:1 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::lintab#4 lin16u_gen::val#1 ] { }  lin16u_gen:3 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::lintab#4 lin16u_gen::val#1 ] { }  lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::lintab#4 lin16u_gen::val#1 ] { }  ) always clobbers reg byte a 
 Statement [76] lin16u_gen::lintab#3 = lin16u_gen::lintab#4 + SIZEOF_WORD [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#1 lin16u_gen::lintab#3 ] ( lin16u_gen:1 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#1 lin16u_gen::lintab#3 ] { }  lin16u_gen:3 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#1 lin16u_gen::lintab#3 ] { }  lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#1 lin16u_gen::lintab#3 ] { }  ) always clobbers reg byte a 
@@ -2997,7 +2997,7 @@ lin16u_gen: {
     rts
     // lin16u_gen::@2
   __b2:
-    // [73] lin16u_gen::$6 = > lin16u_gen::val#2 -- vwuz1=_hi_vduz2 
+    // [73] lin16u_gen::$6 = _word1_ lin16u_gen::val#2 -- vwuz1=_word1_vduz2 
     lda.z val+2
     sta.z __6
     lda.z val+3
@@ -3105,7 +3105,7 @@ print_str: {
 // print_uint(word zp(9) w)
 print_uint: {
     .label w = 9
-    // [89] print_uchar::b#0 = > print_uint::w#10 -- vbuxx=_hi_vwuz1 
+    // [89] print_uchar::b#0 = > print_uint::w#10 -- vbuxx=_byte1_vwuz1 
     ldx.z w+1
     // [90] call print_uchar 
     // [99] phi from print_uint to print_uchar [phi:print_uint->print_uchar]
@@ -3116,7 +3116,7 @@ print_uint: {
     jmp __b1
     // print_uint::@1
   __b1:
-    // [91] print_uchar::b#1 = < print_uint::w#10 -- vbuxx=_lo_vwuz1 
+    // [91] print_uchar::b#1 = < print_uint::w#10 -- vbuxx=_byte0_vwuz1 
     ldx.z w
     // [92] call print_uchar 
     // [99] phi from print_uint::@1 to print_uchar [phi:print_uint::@1->print_uchar]
@@ -3238,7 +3238,7 @@ divr16u: {
     // [109] divr16u::rem#0 = divr16u::rem#5 << 1 -- vwuz1=vwuz1_rol_1 
     asl.z rem
     rol.z rem+1
-    // [110] divr16u::$1 = > divr16u::dividend#3 -- vbuaa=_hi_vwuz1 
+    // [110] divr16u::$1 = > divr16u::dividend#3 -- vbuaa=_byte1_vwuz1 
     lda.z dividend+1
     // [111] divr16u::$2 = divr16u::$1 & $80 -- vbuaa=vbuaa_band_vbuc1 
     and #$80
@@ -4206,13 +4206,13 @@ lin16u_gen: {
     rts
     // lin16u_gen::@2
   __b2:
-    // >val
-    // [73] lin16u_gen::$6 = > lin16u_gen::val#2 -- vwuz1=_hi_vduz2 
+    // WORD1(val)
+    // [73] lin16u_gen::$6 = _word1_ lin16u_gen::val#2 -- vwuz1=_word1_vduz2 
     lda.z val+2
     sta.z __6
     lda.z val+3
     sta.z __6+1
-    // *lintab = >val
+    // *lintab = WORD1(val)
     // [74] *lin16u_gen::lintab#4 = lin16u_gen::$6 -- _deref_pwuz1=vwuz2 
     ldy #0
     lda.z __6
@@ -4313,8 +4313,8 @@ print_str: {
 // print_uint(word zp(9) w)
 print_uint: {
     .label w = 9
-    // print_uchar(>w)
-    // [89] print_uchar::b#0 = > print_uint::w#10 -- vbuxx=_hi_vwuz1 
+    // print_uchar(BYTE1(w))
+    // [89] print_uchar::b#0 = > print_uint::w#10 -- vbuxx=_byte1_vwuz1 
     ldx.z w+1
     // [90] call print_uchar 
     // [99] phi from print_uint to print_uchar [phi:print_uint->print_uchar]
@@ -4322,8 +4322,8 @@ print_uint: {
     // [99] phi print_uchar::b#3 = print_uchar::b#0 [phi:print_uint->print_uchar#1] -- register_copy 
     jsr print_uchar
     // print_uint::@1
-    // print_uchar(<w)
-    // [91] print_uchar::b#1 = < print_uint::w#10 -- vbuxx=_lo_vwuz1 
+    // print_uchar(BYTE0(w))
+    // [91] print_uchar::b#1 = < print_uint::w#10 -- vbuxx=_byte0_vwuz1 
     ldx.z w
     // [92] call print_uchar 
     // [99] phi from print_uint::@1 to print_uchar [phi:print_uint::@1->print_uchar]
@@ -4436,13 +4436,13 @@ divr16u: {
     // [109] divr16u::rem#0 = divr16u::rem#5 << 1 -- vwuz1=vwuz1_rol_1 
     asl.z rem
     rol.z rem+1
-    // >dividend
-    // [110] divr16u::$1 = > divr16u::dividend#3 -- vbuaa=_hi_vwuz1 
+    // BYTE1(dividend)
+    // [110] divr16u::$1 = > divr16u::dividend#3 -- vbuaa=_byte1_vwuz1 
     lda.z dividend+1
-    // >dividend & $80
+    // BYTE1(dividend) & $80
     // [111] divr16u::$2 = divr16u::$1 & $80 -- vbuaa=vbuaa_band_vbuc1 
     and #$80
-    // if( (>dividend & $80) != 0 )
+    // if( (BYTE1(dividend) & $80) != 0 )
     // [112] if(divr16u::$2==0) goto divr16u::@2 -- vbuaa_eq_0_then_la1 
     cmp #0
     beq __b2
diff --git a/src/test/ref/loophead-problem-3.asm b/src/test/ref/loophead-problem-3.asm
index 677f89589..b8d3769f3 100644
--- a/src/test/ref/loophead-problem-3.asm
+++ b/src/test/ref/loophead-problem-3.asm
@@ -18,18 +18,18 @@ main: {
     jsr mul16u
     // mul16u(4,123)
     // dword result = mul16u(4,123)
-    // word kaputt = <result
+    // word kaputt = WORD0(result)
     lda.z result
     sta.z kaputt
     lda.z result+1
     sta.z kaputt+1
-    // <kaputt
+    // BYTE0(kaputt)
     lda.z kaputt
-    // *BORDER_COLOR = <kaputt
+    // *BORDER_COLOR = BYTE0(kaputt)
     sta BORDER_COLOR
-    // >kaputt
+    // BYTE1(kaputt)
     lda.z kaputt+1
-    // *BG_COLOR = >kaputt
+    // *BG_COLOR = BYTE1(kaputt)
     sta BG_COLOR
     // }
     rts
diff --git a/src/test/ref/loophead-problem-3.cfg b/src/test/ref/loophead-problem-3.cfg
index be240172e..fda975352 100644
--- a/src/test/ref/loophead-problem-3.cfg
+++ b/src/test/ref/loophead-problem-3.cfg
@@ -7,7 +7,7 @@ main: scope:[main]  from
   to:main::@1
 main::@1: scope:[main]  from main
   [3] main::result#0 = mul16u::return#2
-  [4] main::kaputt#0 = < main::result#0
+  [4] main::kaputt#0 = _word0_ main::result#0
   [5] main::$2 = < main::kaputt#0
   [6] *BORDER_COLOR = main::$2
   [7] main::$3 = > main::kaputt#0
diff --git a/src/test/ref/loophead-problem-3.log b/src/test/ref/loophead-problem-3.log
index 2234ea185..f0906c935 100644
--- a/src/test/ref/loophead-problem-3.log
+++ b/src/test/ref/loophead-problem-3.log
@@ -62,7 +62,7 @@ main::@1: scope:[main]  from main
   mul16u::return#4 = phi( main/mul16u::return#2 )
   main::$0 = mul16u::return#4
   main::result#0 = main::$0
-  main::$1 = < main::result#0
+  main::$1 = _word0_ main::result#0
   main::kaputt#0 = main::$1
   main::$2 = < main::kaputt#0
   *BORDER_COLOR = main::$2
@@ -238,7 +238,7 @@ main: scope:[main]  from
   to:main::@1
 main::@1: scope:[main]  from main
   [3] main::result#0 = mul16u::return#2
-  [4] main::kaputt#0 = < main::result#0
+  [4] main::kaputt#0 = _word0_ main::result#0
   [5] main::$2 = < main::kaputt#0
   [6] *BORDER_COLOR = main::$2
   [7] main::$3 = > main::kaputt#0
@@ -331,7 +331,7 @@ Allocated zp[1]:24 [ mul16u::$1 ]
 REGISTER UPLIFT POTENTIAL REGISTERS
 Statement [2] mul16u::return#2 = mul16u::res#2 [ mul16u::return#2 ] (  [ mul16u::return#2 ] { { mul16u::return#2 = mul16u::res#2 } }  ) always clobbers reg byte a 
 Statement [3] main::result#0 = mul16u::return#2 [ main::result#0 ] (  [ main::result#0 ] { }  ) always clobbers reg byte a 
-Statement [4] main::kaputt#0 = < main::result#0 [ main::kaputt#0 ] (  [ main::kaputt#0 ] { }  ) always clobbers reg byte a 
+Statement [4] main::kaputt#0 = _word0_ main::result#0 [ main::kaputt#0 ] (  [ main::kaputt#0 ] { }  ) always clobbers reg byte a 
 Statement [12] if(mul16u::a#2!=0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( mul16u:1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] { { mul16u::return#2 = mul16u::res#2 } }  ) always clobbers reg byte a 
 Statement [14] mul16u::$1 = mul16u::a#2 & 1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ( mul16u:1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] { { mul16u::return#2 = mul16u::res#2 } }  ) always clobbers reg byte a 
 Statement [16] mul16u::res#1 = mul16u::res#2 + mul16u::mb#2 [ mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ( mul16u:1 [ mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] { { mul16u::return#2 = mul16u::res#2 } }  ) always clobbers reg byte a 
@@ -396,16 +396,16 @@ main: {
     // main::@1
   __b1:
     // [3] main::result#0 = mul16u::return#2
-    // [4] main::kaputt#0 = < main::result#0 -- vwuz1=_lo_vduz2 
+    // [4] main::kaputt#0 = _word0_ main::result#0 -- vwuz1=_word0_vduz2 
     lda.z result
     sta.z kaputt
     lda.z result+1
     sta.z kaputt+1
-    // [5] main::$2 = < main::kaputt#0 -- vbuaa=_lo_vwuz1 
+    // [5] main::$2 = < main::kaputt#0 -- vbuaa=_byte0_vwuz1 
     lda.z kaputt
     // [6] *BORDER_COLOR = main::$2 -- _deref_pbuc1=vbuaa 
     sta BORDER_COLOR
-    // [7] main::$3 = > main::kaputt#0 -- vbuaa=_hi_vwuz1 
+    // [7] main::$3 = > main::kaputt#0 -- vbuaa=_byte1_vwuz1 
     lda.z kaputt+1
     // [8] *BG_COLOR = main::$3 -- _deref_pbuc1=vbuaa 
     sta BG_COLOR
@@ -600,22 +600,22 @@ main: {
     // main::@1
     // dword result = mul16u(4,123)
     // [3] main::result#0 = mul16u::return#2
-    // word kaputt = <result
-    // [4] main::kaputt#0 = < main::result#0 -- vwuz1=_lo_vduz2 
+    // word kaputt = WORD0(result)
+    // [4] main::kaputt#0 = _word0_ main::result#0 -- vwuz1=_word0_vduz2 
     lda.z result
     sta.z kaputt
     lda.z result+1
     sta.z kaputt+1
-    // <kaputt
-    // [5] main::$2 = < main::kaputt#0 -- vbuaa=_lo_vwuz1 
+    // BYTE0(kaputt)
+    // [5] main::$2 = < main::kaputt#0 -- vbuaa=_byte0_vwuz1 
     lda.z kaputt
-    // *BORDER_COLOR = <kaputt
+    // *BORDER_COLOR = BYTE0(kaputt)
     // [6] *BORDER_COLOR = main::$2 -- _deref_pbuc1=vbuaa 
     sta BORDER_COLOR
-    // >kaputt
-    // [7] main::$3 = > main::kaputt#0 -- vbuaa=_hi_vwuz1 
+    // BYTE1(kaputt)
+    // [7] main::$3 = > main::kaputt#0 -- vbuaa=_byte1_vwuz1 
     lda.z kaputt+1
-    // *BG_COLOR = >kaputt
+    // *BG_COLOR = BYTE1(kaputt)
     // [8] *BG_COLOR = main::$3 -- _deref_pbuc1=vbuaa 
     sta BG_COLOR
     // main::@return
diff --git a/src/test/ref/precedence-1.asm b/src/test/ref/precedence-1.asm
new file mode 100644
index 000000000..4c71ea2be
--- /dev/null
+++ b/src/test/ref/precedence-1.asm
@@ -0,0 +1,18 @@
+// Tests ASM constant operator precedence
+  // Commodore 64 PRG executable file
+.file [name="precedence-1.prg", type="prg", segments="Program"]
+.segmentdef Program [segments="Basic, Code, Data"]
+.segmentdef Basic [start=$0801]
+.segmentdef Code [start=$80d]
+.segmentdef Data [startAfter="Code"]
+.segment Basic
+:BasicUpstart(main)
+.segment Code
+main: {
+    .label SCREEN = $400
+    // SCREEN[0] = 1+2*3*4+5*6|7
+    lda #1+2*3*4+5*6|7
+    sta SCREEN
+    // }
+    rts
+}
diff --git a/src/test/ref/precedence-1.cfg b/src/test/ref/precedence-1.cfg
new file mode 100644
index 000000000..b5d359590
--- /dev/null
+++ b/src/test/ref/precedence-1.cfg
@@ -0,0 +1,8 @@
+
+void main()
+main: scope:[main]  from
+  [0] *main::SCREEN = 1+2*3*4+5*6|7
+  to:main::@return
+main::@return: scope:[main]  from main
+  [1] return 
+  to:@return
diff --git a/src/test/ref/precedence-1.log b/src/test/ref/precedence-1.log
new file mode 100644
index 000000000..071509f1f
--- /dev/null
+++ b/src/test/ref/precedence-1.log
@@ -0,0 +1,156 @@
+
+CONTROL FLOW GRAPH SSA
+
+void main()
+main: scope:[main]  from __start
+  main::SCREEN[0] = 1+2*3*4+5*6|7
+  to:main::@return
+main::@return: scope:[main]  from main
+  return 
+  to:@return
+
+void __start()
+__start: scope:[__start]  from
+  call main 
+  to:__start::@1
+__start::@1: scope:[__start]  from __start
+  to:__start::@return
+__start::@return: scope:[__start]  from __start::@1
+  return 
+  to:@return
+
+SYMBOL TABLE SSA
+void __start()
+void main()
+constant byte* const main::SCREEN = (byte*)$400
+
+Adding number conversion cast (unumber) 1+2*3*4+5*6|7 in main::SCREEN[0] = 1+2*3*4+5*6|7
+Adding number conversion cast (unumber) 0 in main::SCREEN[0] = ((unumber)) 1+2*3*4+5*6|7
+Successful SSA optimization PassNAddNumberTypeConversions
+Inlining cast main::SCREEN[(unumber)0] = (unumber)1+2*3*4+5*6|7
+Successful SSA optimization Pass2InlineCast
+Simplifying constant pointer cast (byte*) 1024
+Simplifying constant integer cast 0
+Successful SSA optimization PassNCastSimplification
+Finalized unsigned number type (byte) 0
+Successful SSA optimization PassNFinalizeNumberTypeConversions
+Constant right-side identified [0] main::SCREEN[0] = (unumber)1+2*3*4+5*6|7
+Successful SSA optimization Pass2ConstantRValueConsolidation
+Simplifying expression containing zero main::SCREEN in [0] main::SCREEN[0] = (unumber)1+2*3*4+5*6|7
+Successful SSA optimization PassNSimplifyExpressionWithZero
+Removing unused procedure __start
+Removing unused procedure block __start
+Removing unused procedure block __start::@1
+Removing unused procedure block __start::@return
+Successful SSA optimization PassNEliminateEmptyStart
+Finalized unsigned number type (byte) 1
+Finalized unsigned number type (byte) 2
+Finalized unsigned number type (byte) 3
+Finalized unsigned number type (byte) 4
+Finalized unsigned number type (byte) 5
+Finalized unsigned number type (byte) 6
+Finalized unsigned number type (byte) 7
+Successful SSA optimization PassNFinalizeNumberTypeConversions
+Simplifying constant integer cast 1+2*3*4+5*6|7
+Successful SSA optimization PassNCastSimplification
+CALL GRAPH
+
+Created 0 initial phi equivalence classes
+Coalesced down to 0 phi equivalence classes
+
+FINAL CONTROL FLOW GRAPH
+
+void main()
+main: scope:[main]  from
+  [0] *main::SCREEN = 1+2*3*4+5*6|7
+  to:main::@return
+main::@return: scope:[main]  from main
+  [1] return 
+  to:@return
+
+
+VARIABLE REGISTER WEIGHTS
+void main()
+
+Initial phi equivalence classes
+Complete equivalence classes
+REGISTER UPLIFT POTENTIAL REGISTERS
+Statement [0] *main::SCREEN = 1+2*3*4+5*6|7 [ ] (  [ ] { }  ) always clobbers reg byte a 
+
+REGISTER UPLIFT SCOPES
+Uplift Scope [main] 
+Uplift Scope [] 
+
+Uplifting [main] best 15 combination 
+Uplifting [] best 15 combination 
+
+ASSEMBLER BEFORE OPTIMIZATION
+  // File Comments
+// Tests ASM constant operator precedence
+  // Upstart
+  // Commodore 64 PRG executable file
+.file [name="precedence-1.prg", type="prg", segments="Program"]
+.segmentdef Program [segments="Basic, Code, Data"]
+.segmentdef Basic [start=$0801]
+.segmentdef Code [start=$80d]
+.segmentdef Data [startAfter="Code"]
+.segment Basic
+:BasicUpstart(main)
+  // Global Constants & labels
+.segment Code
+  // main
+main: {
+    .label SCREEN = $400
+    // [0] *main::SCREEN = 1+2*3*4+5*6|7 -- _deref_pbuc1=vbuc2 
+    lda #1+2*3*4+5*6|7
+    sta SCREEN
+    jmp __breturn
+    // main::@return
+  __breturn:
+    // [1] return 
+    rts
+}
+  // File Data
+
+ASSEMBLER OPTIMIZATIONS
+Removing instruction jmp __breturn
+Succesful ASM optimization Pass5NextJumpElimination
+Removing instruction __breturn:
+Succesful ASM optimization Pass5UnusedLabelElimination
+
+FINAL SYMBOL TABLE
+void main()
+constant byte* const main::SCREEN = (byte*) 1024
+
+
+
+FINAL ASSEMBLER
+Score: 12
+
+  // File Comments
+// Tests ASM constant operator precedence
+  // Upstart
+  // Commodore 64 PRG executable file
+.file [name="precedence-1.prg", type="prg", segments="Program"]
+.segmentdef Program [segments="Basic, Code, Data"]
+.segmentdef Basic [start=$0801]
+.segmentdef Code [start=$80d]
+.segmentdef Data [startAfter="Code"]
+.segment Basic
+:BasicUpstart(main)
+  // Global Constants & labels
+.segment Code
+  // main
+main: {
+    .label SCREEN = $400
+    // SCREEN[0] = 1+2*3*4+5*6|7
+    // [0] *main::SCREEN = 1+2*3*4+5*6|7 -- _deref_pbuc1=vbuc2 
+    lda #1+2*3*4+5*6|7
+    sta SCREEN
+    // main::@return
+    // }
+    // [1] return 
+    rts
+}
+  // File Data
+
diff --git a/src/test/ref/precedence-1.sym b/src/test/ref/precedence-1.sym
new file mode 100644
index 000000000..0590bd536
--- /dev/null
+++ b/src/test/ref/precedence-1.sym
@@ -0,0 +1,3 @@
+void main()
+constant byte* const main::SCREEN = (byte*) 1024
+
diff --git a/src/test/ref/primes-1000-2.asm b/src/test/ref/primes-1000-2.asm
index 864b2a68d..d50d3f70e 100644
--- a/src/test/ref/primes-1000-2.asm
+++ b/src/test/ref/primes-1000-2.asm
@@ -203,12 +203,12 @@ mul8u: {
 div16u8u: {
     .label dividend = 5
     .label divisor = 9
-    // divr8u(>dividend, divisor, 0)
+    // divr8u(BYTE1(dividend), divisor, 0)
     lda.z dividend+1
     sta.z divr8u.dividend
     ldy #0
     jsr divr8u
-    // divr8u(<dividend, divisor, rem8u)
+    // divr8u(BYTE0(dividend), divisor, rem8u)
     lda.z dividend
     sta.z divr8u.dividend
     jsr divr8u
@@ -321,9 +321,8 @@ utoa: {
     cmp #max_digits-1
     bcc __b2
     // *buffer++ = DIGITS[(char)value]
-    lda.z value
-    tay
-    lda DIGITS,y
+    ldx.z value
+    lda DIGITS,x
     ldy #0
     sta (buffer),y
     // *buffer++ = DIGITS[(char)value];
diff --git a/src/test/ref/primes-1000-2.log b/src/test/ref/primes-1000-2.log
index ea53e6426..3582dd8b7 100644
--- a/src/test/ref/primes-1000-2.log
+++ b/src/test/ref/primes-1000-2.log
@@ -2284,7 +2284,6 @@ Removing always clobbered register reg byte a as potential for zp[1]:16 [ divr8u
 Removing always clobbered register reg byte a as potential for zp[1]:17 [ divr8u::quotient#3 divr8u::return#0 divr8u::quotient#1 divr8u::quotient#2 ]
 Removing always clobbered register reg byte a as potential for zp[1]:18 [ divr8u::i#2 divr8u::i#1 ]
 Statement [72] divr8u::rem#2 = divr8u::rem#6 - divr8u::divisor#6 [ divr8u::divisor#6 divr8u::i#2 divr8u::dividend#0 divr8u::quotient#2 divr8u::rem#2 ] ( div16u8u:18::divr8u:46 [ prime_idx#17 print_char_cursor#34 test_last#19 test_idx#7 potential#10 div16u8u::dividend#0 div16u8u::divisor#0 divr8u::divisor#6 divr8u::i#2 divr8u::dividend#0 divr8u::quotient#2 divr8u::rem#2 ] { { potential#10 = div16u8u::dividend#0 } { divr8u::dividend#1 = divr8u::dividend#5 } { divr8u::divisor#0 = divr8u::divisor#6 div16u8u::divisor#0 } }  div16u8u:18::divr8u:50 [ prime_idx#17 print_char_cursor#34 test_last#19 test_idx#7 potential#10 divr8u::divisor#6 divr8u::i#2 divr8u::dividend#0 divr8u::quotient#2 divr8u::rem#2 ] { { potential#10 = div16u8u::dividend#0 } { divr8u::rem#10 = divr8u::rem#4 rem8u#0 } { divr8u::dividend#2 = divr8u::dividend#5 } { divr8u::divisor#1 = divr8u::divisor#6 div16u8u::divisor#0 } }  ) always clobbers reg byte a 
-Statement [81] utoa::$11 = (byte)utoa::value#2 [ utoa::buffer#11 utoa::$11 ] ( print_uint_decimal:29::utoa:53 [ test_last#19 potential#11 prime_idx#1 print_char_cursor#34 utoa::buffer#11 utoa::$11 ] { { potential#11 = print_uint_decimal::w#0 utoa::value#0 } }  ) always clobbers reg byte a 
 Statement [82] *utoa::buffer#11 = DIGITS[utoa::$11] [ utoa::buffer#11 ] ( print_uint_decimal:29::utoa:53 [ test_last#19 potential#11 prime_idx#1 print_char_cursor#34 utoa::buffer#11 ] { { potential#11 = print_uint_decimal::w#0 utoa::value#0 } }  ) always clobbers reg byte a reg byte y 
 Statement [83] utoa::buffer#4 = ++ utoa::buffer#11 [ utoa::buffer#4 ] ( print_uint_decimal:29::utoa:53 [ test_last#19 potential#11 prime_idx#1 print_char_cursor#34 utoa::buffer#4 ] { { potential#11 = print_uint_decimal::w#0 utoa::value#0 } }  ) always clobbers reg byte a 
 Statement [84] *utoa::buffer#4 = 0 [ ] ( print_uint_decimal:29::utoa:53 [ test_last#19 potential#11 prime_idx#1 print_char_cursor#34 ] { { potential#11 = print_uint_decimal::w#0 utoa::value#0 } }  ) always clobbers reg byte a reg byte y 
@@ -2331,7 +2330,6 @@ Statement [64] divr8u::$1 = divr8u::dividend#3 & $80 [ divr8u::divisor#6 divr8u:
 Removing always clobbered register reg byte a as potential for zp[1]:15 [ divr8u::rem#5 divr8u::rem#10 divr8u::rem#4 divr8u::rem#11 divr8u::rem#6 divr8u::rem#0 divr8u::rem#1 divr8u::rem#2 ]
 Statement [66] divr8u::rem#1 = divr8u::rem#0 | 1 [ divr8u::divisor#6 divr8u::dividend#3 divr8u::quotient#3 divr8u::i#2 divr8u::rem#1 ] ( div16u8u:18::divr8u:46 [ prime_idx#17 print_char_cursor#34 test_last#19 test_idx#7 potential#10 div16u8u::dividend#0 div16u8u::divisor#0 divr8u::divisor#6 divr8u::dividend#3 divr8u::quotient#3 divr8u::i#2 divr8u::rem#1 ] { { potential#10 = div16u8u::dividend#0 } { divr8u::dividend#1 = divr8u::dividend#5 } { divr8u::divisor#0 = divr8u::divisor#6 div16u8u::divisor#0 } }  div16u8u:18::divr8u:50 [ prime_idx#17 print_char_cursor#34 test_last#19 test_idx#7 potential#10 divr8u::divisor#6 divr8u::dividend#3 divr8u::quotient#3 divr8u::i#2 divr8u::rem#1 ] { { potential#10 = div16u8u::dividend#0 } { divr8u::rem#10 = divr8u::rem#4 rem8u#0 } { divr8u::dividend#2 = divr8u::dividend#5 } { divr8u::divisor#1 = divr8u::divisor#6 div16u8u::divisor#0 } }  ) always clobbers reg byte a 
 Statement [72] divr8u::rem#2 = divr8u::rem#6 - divr8u::divisor#6 [ divr8u::divisor#6 divr8u::i#2 divr8u::dividend#0 divr8u::quotient#2 divr8u::rem#2 ] ( div16u8u:18::divr8u:46 [ prime_idx#17 print_char_cursor#34 test_last#19 test_idx#7 potential#10 div16u8u::dividend#0 div16u8u::divisor#0 divr8u::divisor#6 divr8u::i#2 divr8u::dividend#0 divr8u::quotient#2 divr8u::rem#2 ] { { potential#10 = div16u8u::dividend#0 } { divr8u::dividend#1 = divr8u::dividend#5 } { divr8u::divisor#0 = divr8u::divisor#6 div16u8u::divisor#0 } }  div16u8u:18::divr8u:50 [ prime_idx#17 print_char_cursor#34 test_last#19 test_idx#7 potential#10 divr8u::divisor#6 divr8u::i#2 divr8u::dividend#0 divr8u::quotient#2 divr8u::rem#2 ] { { potential#10 = div16u8u::dividend#0 } { divr8u::rem#10 = divr8u::rem#4 rem8u#0 } { divr8u::dividend#2 = divr8u::dividend#5 } { divr8u::divisor#1 = divr8u::divisor#6 div16u8u::divisor#0 } }  ) always clobbers reg byte a 
-Statement [81] utoa::$11 = (byte)utoa::value#2 [ utoa::buffer#11 utoa::$11 ] ( print_uint_decimal:29::utoa:53 [ test_last#19 potential#11 prime_idx#1 print_char_cursor#34 utoa::buffer#11 utoa::$11 ] { { potential#11 = print_uint_decimal::w#0 utoa::value#0 } }  ) always clobbers reg byte a 
 Statement [82] *utoa::buffer#11 = DIGITS[utoa::$11] [ utoa::buffer#11 ] ( print_uint_decimal:29::utoa:53 [ test_last#19 potential#11 prime_idx#1 print_char_cursor#34 utoa::buffer#11 ] { { potential#11 = print_uint_decimal::w#0 utoa::value#0 } }  ) always clobbers reg byte a reg byte y 
 Statement [83] utoa::buffer#4 = ++ utoa::buffer#11 [ utoa::buffer#4 ] ( print_uint_decimal:29::utoa:53 [ test_last#19 potential#11 prime_idx#1 print_char_cursor#34 utoa::buffer#4 ] { { potential#11 = print_uint_decimal::w#0 utoa::value#0 } }  ) always clobbers reg byte a 
 Statement [84] *utoa::buffer#4 = 0 [ ] ( print_uint_decimal:29::utoa:53 [ test_last#19 potential#11 prime_idx#1 print_char_cursor#34 ] { { potential#11 = print_uint_decimal::w#0 utoa::value#0 } }  ) always clobbers reg byte a reg byte y 
@@ -2373,7 +2371,6 @@ Statement [58] *print_char_cursor#1 = print_char::ch#2 [ print_char_cursor#1 ] (
 Statement [64] divr8u::$1 = divr8u::dividend#3 & $80 [ divr8u::divisor#6 divr8u::dividend#3 divr8u::quotient#3 divr8u::i#2 divr8u::rem#0 divr8u::$1 ] ( div16u8u:18::divr8u:46 [ prime_idx#17 print_char_cursor#34 test_last#19 test_idx#7 potential#10 div16u8u::dividend#0 div16u8u::divisor#0 divr8u::divisor#6 divr8u::dividend#3 divr8u::quotient#3 divr8u::i#2 divr8u::rem#0 divr8u::$1 ] { { potential#10 = div16u8u::dividend#0 } { divr8u::dividend#1 = divr8u::dividend#5 } { divr8u::divisor#0 = divr8u::divisor#6 div16u8u::divisor#0 } }  div16u8u:18::divr8u:50 [ prime_idx#17 print_char_cursor#34 test_last#19 test_idx#7 potential#10 divr8u::divisor#6 divr8u::dividend#3 divr8u::quotient#3 divr8u::i#2 divr8u::rem#0 divr8u::$1 ] { { potential#10 = div16u8u::dividend#0 } { divr8u::rem#10 = divr8u::rem#4 rem8u#0 } { divr8u::dividend#2 = divr8u::dividend#5 } { divr8u::divisor#1 = divr8u::divisor#6 div16u8u::divisor#0 } }  ) always clobbers reg byte a 
 Statement [66] divr8u::rem#1 = divr8u::rem#0 | 1 [ divr8u::divisor#6 divr8u::dividend#3 divr8u::quotient#3 divr8u::i#2 divr8u::rem#1 ] ( div16u8u:18::divr8u:46 [ prime_idx#17 print_char_cursor#34 test_last#19 test_idx#7 potential#10 div16u8u::dividend#0 div16u8u::divisor#0 divr8u::divisor#6 divr8u::dividend#3 divr8u::quotient#3 divr8u::i#2 divr8u::rem#1 ] { { potential#10 = div16u8u::dividend#0 } { divr8u::dividend#1 = divr8u::dividend#5 } { divr8u::divisor#0 = divr8u::divisor#6 div16u8u::divisor#0 } }  div16u8u:18::divr8u:50 [ prime_idx#17 print_char_cursor#34 test_last#19 test_idx#7 potential#10 divr8u::divisor#6 divr8u::dividend#3 divr8u::quotient#3 divr8u::i#2 divr8u::rem#1 ] { { potential#10 = div16u8u::dividend#0 } { divr8u::rem#10 = divr8u::rem#4 rem8u#0 } { divr8u::dividend#2 = divr8u::dividend#5 } { divr8u::divisor#1 = divr8u::divisor#6 div16u8u::divisor#0 } }  ) always clobbers reg byte a 
 Statement [72] divr8u::rem#2 = divr8u::rem#6 - divr8u::divisor#6 [ divr8u::divisor#6 divr8u::i#2 divr8u::dividend#0 divr8u::quotient#2 divr8u::rem#2 ] ( div16u8u:18::divr8u:46 [ prime_idx#17 print_char_cursor#34 test_last#19 test_idx#7 potential#10 div16u8u::dividend#0 div16u8u::divisor#0 divr8u::divisor#6 divr8u::i#2 divr8u::dividend#0 divr8u::quotient#2 divr8u::rem#2 ] { { potential#10 = div16u8u::dividend#0 } { divr8u::dividend#1 = divr8u::dividend#5 } { divr8u::divisor#0 = divr8u::divisor#6 div16u8u::divisor#0 } }  div16u8u:18::divr8u:50 [ prime_idx#17 print_char_cursor#34 test_last#19 test_idx#7 potential#10 divr8u::divisor#6 divr8u::i#2 divr8u::dividend#0 divr8u::quotient#2 divr8u::rem#2 ] { { potential#10 = div16u8u::dividend#0 } { divr8u::rem#10 = divr8u::rem#4 rem8u#0 } { divr8u::dividend#2 = divr8u::dividend#5 } { divr8u::divisor#1 = divr8u::divisor#6 div16u8u::divisor#0 } }  ) always clobbers reg byte a 
-Statement [81] utoa::$11 = (byte)utoa::value#2 [ utoa::buffer#11 utoa::$11 ] ( print_uint_decimal:29::utoa:53 [ test_last#19 potential#11 prime_idx#1 print_char_cursor#34 utoa::buffer#11 utoa::$11 ] { { potential#11 = print_uint_decimal::w#0 utoa::value#0 } }  ) always clobbers reg byte a 
 Statement [82] *utoa::buffer#11 = DIGITS[utoa::$11] [ utoa::buffer#11 ] ( print_uint_decimal:29::utoa:53 [ test_last#19 potential#11 prime_idx#1 print_char_cursor#34 utoa::buffer#11 ] { { potential#11 = print_uint_decimal::w#0 utoa::value#0 } }  ) always clobbers reg byte a reg byte y 
 Statement [83] utoa::buffer#4 = ++ utoa::buffer#11 [ utoa::buffer#4 ] ( print_uint_decimal:29::utoa:53 [ test_last#19 potential#11 prime_idx#1 print_char_cursor#34 utoa::buffer#4 ] { { potential#11 = print_uint_decimal::w#0 utoa::value#0 } }  ) always clobbers reg byte a 
 Statement [84] *utoa::buffer#4 = 0 [ ] ( print_uint_decimal:29::utoa:53 [ test_last#19 potential#11 prime_idx#1 print_char_cursor#34 ] { { potential#11 = print_uint_decimal::w#0 utoa::value#0 } }  ) always clobbers reg byte a reg byte y 
@@ -2449,29 +2446,29 @@ Uplift Scope [RADIX]
 Uplifting [utoa_append] best 201828 combination zp[2]:29 [ utoa_append::value#2 utoa_append::value#0 utoa_append::value#1 ] reg byte x [ utoa_append::digit#2 utoa_append::digit#1 ] zp[2]:60 [ utoa_append::sub#0 ] zp[2]:62 [ utoa_append::return#0 ] zp[2]:58 [ utoa_append::buffer#0 ] 
 Uplifting [divr8u] best 182819 combination reg byte y [ divr8u::rem#5 divr8u::rem#10 divr8u::rem#4 divr8u::rem#11 divr8u::rem#6 divr8u::rem#0 divr8u::rem#1 divr8u::rem#2 ] zp[1]:17 [ divr8u::quotient#3 divr8u::return#0 divr8u::quotient#1 divr8u::quotient#2 ] reg byte a [ divr8u::$1 ] reg byte x [ divr8u::i#2 divr8u::i#1 ] zp[1]:16 [ divr8u::dividend#3 divr8u::dividend#5 divr8u::dividend#1 divr8u::dividend#2 divr8u::dividend#0 ] zp[1]:14 [ divr8u::divisor#6 divr8u::divisor#0 divr8u::divisor#1 ] 
 Limited combination testing to 100 combinations of 972 possible.
-Uplifting [utoa] best 181715 combination zp[2]:23 [ utoa::buffer#11 utoa::buffer#14 utoa::buffer#5 ] zp[2]:20 [ utoa::value#2 utoa::value#6 utoa::value#0 utoa::value#1 ] zp[1]:19 [ utoa::digit#2 utoa::digit#1 ] reg byte a [ utoa::$10 ] reg byte x [ utoa::started#2 utoa::started#4 ] zp[2]:56 [ utoa::digit_value#0 ] reg byte a [ utoa::$11 ] zp[2]:53 [ utoa::buffer#4 ] 
-Uplifting [print_char] best 181409 combination reg byte a [ print_char::ch#2 print_char::ch#0 ] 
-Uplifting [] best 181303 combination zp[2]:27 [ print_char_cursor#1 print_char_cursor#34 print_char_cursor#17 ] reg byte y [ rem8u#0 ] zp[2]:6 [ potential#10 potential#1 potential#15 potential#11 potential#2 ] zp[1]:5 [ test_idx#7 test_idx#10 test_idx#1 ] zp[1]:2 [ test_last#13 test_last#19 test_last#1 ] zp[2]:3 [ prime_idx#17 prime_idx#1 ] 
-Uplifting [print_str] best 181303 combination zp[2]:25 [ print_str::str#2 print_str::str#0 ] 
-Uplifting [mul8u] best 180740 combination zp[2]:9 [ mul8u::res#2 mul8u::res#6 mul8u::res#1 ] zp[2]:11 [ mul8u::mb#2 mul8u::mb#0 mul8u::mb#1 ] reg byte a [ mul8u::$1 ] reg byte x [ mul8u::a#2 mul8u::a#1 mul8u::a#0 ] zp[2]:35 [ mul8u::return#2 ] reg byte a [ mul8u::b#0 ] 
-Uplifting [div16u8u] best 180740 combination zp[2]:40 [ div16u8u::dividend#0 ] zp[1]:42 [ div16u8u::divisor#0 ] 
-Uplifting [main] best 180230 combination reg byte x [ main::$13 ] zp[2]:37 [ main::$0 ] zp[2]:43 [ main::$14 ] zp[2]:45 [ main::$15 ] reg byte a [ main::p#0 ] reg byte a [ main::$12 ] 
-Uplifting [print_uint_decimal] best 180230 combination zp[2]:47 [ print_uint_decimal::w#0 ] 
-Uplifting [RADIX] best 180230 combination 
+Uplifting [utoa] best 181713 combination zp[2]:23 [ utoa::buffer#11 utoa::buffer#14 utoa::buffer#5 ] zp[2]:20 [ utoa::value#2 utoa::value#6 utoa::value#0 utoa::value#1 ] zp[1]:19 [ utoa::digit#2 utoa::digit#1 ] reg byte a [ utoa::$10 ] reg byte x [ utoa::started#2 utoa::started#4 ] zp[2]:56 [ utoa::digit_value#0 ] reg byte x [ utoa::$11 ] zp[2]:53 [ utoa::buffer#4 ] 
+Uplifting [print_char] best 181407 combination reg byte a [ print_char::ch#2 print_char::ch#0 ] 
+Uplifting [] best 181301 combination zp[2]:27 [ print_char_cursor#1 print_char_cursor#34 print_char_cursor#17 ] reg byte y [ rem8u#0 ] zp[2]:6 [ potential#10 potential#1 potential#15 potential#11 potential#2 ] zp[1]:5 [ test_idx#7 test_idx#10 test_idx#1 ] zp[1]:2 [ test_last#13 test_last#19 test_last#1 ] zp[2]:3 [ prime_idx#17 prime_idx#1 ] 
+Uplifting [print_str] best 181301 combination zp[2]:25 [ print_str::str#2 print_str::str#0 ] 
+Uplifting [mul8u] best 180738 combination zp[2]:9 [ mul8u::res#2 mul8u::res#6 mul8u::res#1 ] zp[2]:11 [ mul8u::mb#2 mul8u::mb#0 mul8u::mb#1 ] reg byte a [ mul8u::$1 ] reg byte x [ mul8u::a#2 mul8u::a#1 mul8u::a#0 ] zp[2]:35 [ mul8u::return#2 ] reg byte a [ mul8u::b#0 ] 
+Uplifting [div16u8u] best 180738 combination zp[2]:40 [ div16u8u::dividend#0 ] zp[1]:42 [ div16u8u::divisor#0 ] 
+Uplifting [main] best 180228 combination reg byte x [ main::$13 ] zp[2]:37 [ main::$0 ] zp[2]:43 [ main::$14 ] zp[2]:45 [ main::$15 ] reg byte a [ main::p#0 ] reg byte a [ main::$12 ] 
+Uplifting [print_uint_decimal] best 180228 combination zp[2]:47 [ print_uint_decimal::w#0 ] 
+Uplifting [RADIX] best 180228 combination 
 Attempting to uplift remaining variables inzp[1]:17 [ divr8u::quotient#3 divr8u::return#0 divr8u::quotient#1 divr8u::quotient#2 ]
-Uplifting [divr8u] best 180230 combination zp[1]:17 [ divr8u::quotient#3 divr8u::return#0 divr8u::quotient#1 divr8u::quotient#2 ] 
+Uplifting [divr8u] best 180228 combination zp[1]:17 [ divr8u::quotient#3 divr8u::return#0 divr8u::quotient#1 divr8u::quotient#2 ] 
 Attempting to uplift remaining variables inzp[1]:16 [ divr8u::dividend#3 divr8u::dividend#5 divr8u::dividend#1 divr8u::dividend#2 divr8u::dividend#0 ]
-Uplifting [divr8u] best 180230 combination zp[1]:16 [ divr8u::dividend#3 divr8u::dividend#5 divr8u::dividend#1 divr8u::dividend#2 divr8u::dividend#0 ] 
+Uplifting [divr8u] best 180228 combination zp[1]:16 [ divr8u::dividend#3 divr8u::dividend#5 divr8u::dividend#1 divr8u::dividend#2 divr8u::dividend#0 ] 
 Attempting to uplift remaining variables inzp[1]:14 [ divr8u::divisor#6 divr8u::divisor#0 divr8u::divisor#1 ]
-Uplifting [divr8u] best 180230 combination zp[1]:14 [ divr8u::divisor#6 divr8u::divisor#0 divr8u::divisor#1 ] 
+Uplifting [divr8u] best 180228 combination zp[1]:14 [ divr8u::divisor#6 divr8u::divisor#0 divr8u::divisor#1 ] 
 Attempting to uplift remaining variables inzp[1]:19 [ utoa::digit#2 utoa::digit#1 ]
-Uplifting [utoa] best 180230 combination zp[1]:19 [ utoa::digit#2 utoa::digit#1 ] 
+Uplifting [utoa] best 180228 combination zp[1]:19 [ utoa::digit#2 utoa::digit#1 ] 
 Attempting to uplift remaining variables inzp[1]:42 [ div16u8u::divisor#0 ]
-Uplifting [div16u8u] best 180230 combination zp[1]:42 [ div16u8u::divisor#0 ] 
+Uplifting [div16u8u] best 180228 combination zp[1]:42 [ div16u8u::divisor#0 ] 
 Attempting to uplift remaining variables inzp[1]:5 [ test_idx#7 test_idx#10 test_idx#1 ]
-Uplifting [] best 180230 combination zp[1]:5 [ test_idx#7 test_idx#10 test_idx#1 ] 
+Uplifting [] best 180228 combination zp[1]:5 [ test_idx#7 test_idx#10 test_idx#1 ] 
 Attempting to uplift remaining variables inzp[1]:2 [ test_last#13 test_last#19 test_last#1 ]
-Uplifting [] best 180230 combination zp[1]:2 [ test_last#13 test_last#19 test_last#1 ] 
+Uplifting [] best 180228 combination zp[1]:2 [ test_last#13 test_last#19 test_last#1 ] 
 Coalescing zero page register [ zp[1]:14 [ divr8u::divisor#6 divr8u::divisor#0 divr8u::divisor#1 ] ] with [ zp[1]:42 [ div16u8u::divisor#0 ] ] - score: 2
 Coalescing zero page register [ zp[2]:6 [ potential#10 potential#1 potential#15 potential#11 potential#2 ] ] with [ zp[2]:40 [ div16u8u::dividend#0 ] ] - score: 1
 Coalescing zero page register [ zp[2]:6 [ potential#10 potential#1 potential#15 potential#11 potential#2 div16u8u::dividend#0 ] ] with [ zp[2]:47 [ print_uint_decimal::w#0 ] ] - score: 1
@@ -2816,7 +2813,7 @@ mul8u: {
 div16u8u: {
     .label dividend = 5
     .label divisor = 9
-    // [44] divr8u::dividend#1 = > div16u8u::dividend#0 -- vbuz1=_hi_vwuz2 
+    // [44] divr8u::dividend#1 = > div16u8u::dividend#0 -- vbuz1=_byte1_vwuz2 
     lda.z dividend+1
     sta.z divr8u.dividend
     // [45] divr8u::divisor#0 = div16u8u::divisor#0
@@ -2831,7 +2828,7 @@ div16u8u: {
     jmp __b1
     // div16u8u::@1
   __b1:
-    // [47] divr8u::dividend#2 = < div16u8u::dividend#0 -- vbuz1=_lo_vwuz2 
+    // [47] divr8u::dividend#2 = < div16u8u::dividend#0 -- vbuz1=_byte0_vwuz2 
     lda.z dividend
     sta.z divr8u.dividend
     // [48] divr8u::divisor#1 = div16u8u::divisor#0
@@ -3026,11 +3023,10 @@ utoa: {
     jmp __b3
     // utoa::@3
   __b3:
-    // [81] utoa::$11 = (byte)utoa::value#2 -- vbuaa=_byte_vwuz1 
-    lda.z value
-    // [82] *utoa::buffer#11 = DIGITS[utoa::$11] -- _deref_pbuz1=pbuc1_derefidx_vbuaa 
-    tay
-    lda DIGITS,y
+    // [81] utoa::$11 = (byte)utoa::value#2 -- vbuxx=_byte_vwuz1 
+    ldx.z value
+    // [82] *utoa::buffer#11 = DIGITS[utoa::$11] -- _deref_pbuz1=pbuc1_derefidx_vbuxx 
+    lda DIGITS,x
     ldy #0
     sta (buffer),y
     // [83] utoa::buffer#4 = ++ utoa::buffer#11 -- pbuz1=_inc_pbuz1 
@@ -3486,7 +3482,7 @@ byte test_last#13 test_last zp[1]:2 4.888888888888889
 byte test_last#19 test_last zp[1]:2 6.380952380952381
 void utoa(word utoa::value , byte* utoa::buffer , byte utoa::radix)
 byte~ utoa::$10 reg byte a 200002.0
-byte~ utoa::$11 reg byte a 2002.0
+byte~ utoa::$11 reg byte x 2002.0
 byte* utoa::buffer
 byte* utoa::buffer#11 buffer zp[2]:13 28714.714285714286
 byte* utoa::buffer#14 buffer zp[2]:13 150001.5
@@ -3548,13 +3544,13 @@ zp[2]:17 [ main::$14 main::$15 utoa::value#2 utoa::value#6 utoa::value#0 utoa::v
 reg byte a [ mul8u::$1 ]
 reg byte a [ divr8u::$1 ]
 reg byte y [ rem8u#0 ]
-reg byte a [ utoa::$11 ]
+reg byte x [ utoa::$11 ]
 reg byte a [ utoa::$10 ]
 zp[2]:19 [ utoa::digit_value#0 utoa_append::sub#0 ]
 
 
 FINAL ASSEMBLER
-Score: 139372
+Score: 139370
 
   // File Comments
 // Calculates the 1000 first primes
@@ -3858,8 +3854,8 @@ mul8u: {
 div16u8u: {
     .label dividend = 5
     .label divisor = 9
-    // divr8u(>dividend, divisor, 0)
-    // [44] divr8u::dividend#1 = > div16u8u::dividend#0 -- vbuz1=_hi_vwuz2 
+    // divr8u(BYTE1(dividend), divisor, 0)
+    // [44] divr8u::dividend#1 = > div16u8u::dividend#0 -- vbuz1=_byte1_vwuz2 
     lda.z dividend+1
     sta.z divr8u.dividend
     // [45] divr8u::divisor#0 = div16u8u::divisor#0
@@ -3871,8 +3867,8 @@ div16u8u: {
     ldy #0
     jsr divr8u
     // div16u8u::@1
-    // divr8u(<dividend, divisor, rem8u)
-    // [47] divr8u::dividend#2 = < div16u8u::dividend#0 -- vbuz1=_lo_vwuz2 
+    // divr8u(BYTE0(dividend), divisor, rem8u)
+    // [47] divr8u::dividend#2 = < div16u8u::dividend#0 -- vbuz1=_byte0_vwuz2 
     lda.z dividend
     sta.z divr8u.dividend
     // [48] divr8u::divisor#1 = div16u8u::divisor#0
@@ -4054,11 +4050,10 @@ utoa: {
     bcc __b2
     // utoa::@3
     // *buffer++ = DIGITS[(char)value]
-    // [81] utoa::$11 = (byte)utoa::value#2 -- vbuaa=_byte_vwuz1 
-    lda.z value
-    // [82] *utoa::buffer#11 = DIGITS[utoa::$11] -- _deref_pbuz1=pbuc1_derefidx_vbuaa 
-    tay
-    lda DIGITS,y
+    // [81] utoa::$11 = (byte)utoa::value#2 -- vbuxx=_byte_vwuz1 
+    ldx.z value
+    // [82] *utoa::buffer#11 = DIGITS[utoa::$11] -- _deref_pbuz1=pbuc1_derefidx_vbuxx 
+    lda DIGITS,x
     ldy #0
     sta (buffer),y
     // *buffer++ = DIGITS[(char)value];
diff --git a/src/test/ref/primes-1000-2.sym b/src/test/ref/primes-1000-2.sym
index 9d4528a63..42ab2eb5f 100644
--- a/src/test/ref/primes-1000-2.sym
+++ b/src/test/ref/primes-1000-2.sym
@@ -111,7 +111,7 @@ byte test_last#13 test_last zp[1]:2 4.888888888888889
 byte test_last#19 test_last zp[1]:2 6.380952380952381
 void utoa(word utoa::value , byte* utoa::buffer , byte utoa::radix)
 byte~ utoa::$10 reg byte a 200002.0
-byte~ utoa::$11 reg byte a 2002.0
+byte~ utoa::$11 reg byte x 2002.0
 byte* utoa::buffer
 byte* utoa::buffer#11 buffer zp[2]:13 28714.714285714286
 byte* utoa::buffer#14 buffer zp[2]:13 150001.5
@@ -173,6 +173,6 @@ zp[2]:17 [ main::$14 main::$15 utoa::value#2 utoa::value#6 utoa::value#0 utoa::v
 reg byte a [ mul8u::$1 ]
 reg byte a [ divr8u::$1 ]
 reg byte y [ rem8u#0 ]
-reg byte a [ utoa::$11 ]
+reg byte x [ utoa::$11 ]
 reg byte a [ utoa::$10 ]
 zp[2]:19 [ utoa::digit_value#0 utoa_append::sub#0 ]
diff --git a/src/test/ref/sinusgen16.asm b/src/test/ref/sinusgen16.asm
index 40e6ad93c..d2945dd10 100644
--- a/src/test/ref/sinusgen16.asm
+++ b/src/test/ref/sinusgen16.asm
@@ -250,7 +250,7 @@ div32u16u: {
     .label return = $1a
     .label quotient_hi = $24
     .label quotient_lo = $14
-    // divr16u(>dividend, divisor, 0)
+    // divr16u(WORD1(dividend), divisor, 0)
     lda #<PI2_u4f28>>$10
     sta.z divr16u.dividend
     lda #>PI2_u4f28>>$10
@@ -259,20 +259,20 @@ div32u16u: {
     sta.z divr16u.rem
     sta.z divr16u.rem+1
     jsr divr16u
-    // divr16u(>dividend, divisor, 0)
-    // unsigned int quotient_hi = divr16u(>dividend, divisor, 0)
+    // divr16u(WORD1(dividend), divisor, 0)
+    // unsigned int quotient_hi = divr16u(WORD1(dividend), divisor, 0)
     lda.z divr16u.return
     sta.z quotient_hi
     lda.z divr16u.return+1
     sta.z quotient_hi+1
-    // divr16u(<dividend, divisor, rem16u)
+    // divr16u(WORD0(dividend), divisor, rem16u)
     lda #<PI2_u4f28&$ffff
     sta.z divr16u.dividend
     lda #>PI2_u4f28&$ffff
     sta.z divr16u.dividend+1
     jsr divr16u
-    // divr16u(<dividend, divisor, rem16u)
-    // unsigned int quotient_lo = divr16u(<dividend, divisor, rem16u)
+    // divr16u(WORD0(dividend), divisor, rem16u)
+    // unsigned int quotient_lo = divr16u(WORD0(dividend), divisor, rem16u)
     // unsigned long quotient = { quotient_hi, quotient_lo}
     lda.z quotient_hi
     sta.z return+2
@@ -391,7 +391,7 @@ sin16s: {
     rol.z __4+1
     rol.z __4+2
     rol.z __4+3
-    // unsigned int x1 = >x<<3
+    // unsigned int x1 = WORD1(x<<3)
     lda.z __4+2
     sta.z x1
     lda.z __4+3
@@ -548,10 +548,10 @@ print_char: {
 // print_uint(word zp($a) w)
 print_uint: {
     .label w = $a
-    // print_uchar(>w)
+    // print_uchar(BYTE1(w))
     ldx.z w+1
     jsr print_uchar
-    // print_uchar(<w)
+    // print_uchar(BYTE0(w))
     ldx.z w
     jsr print_uchar
     // }
@@ -575,11 +575,11 @@ divr16u: {
     // rem = rem << 1
     asl.z rem
     rol.z rem+1
-    // >dividend
+    // BYTE1(dividend)
     lda.z dividend+1
-    // >dividend & $80
+    // BYTE1(dividend) & $80
     and #$80
-    // if( (>dividend & $80) != 0 )
+    // if( (BYTE1(dividend) & $80) != 0 )
     cmp #0
     beq __b2
     // rem = rem | 1
@@ -651,7 +651,7 @@ mulu16_sel: {
     dex
     bne !-
   !e:
-    // >mul16u(v1, v2)<<select
+    // WORD1(mul16u(v1, v2)<<select)
     lda.z __1+2
     sta.z return
     lda.z __1+3
diff --git a/src/test/ref/sinusgen16.cfg b/src/test/ref/sinusgen16.cfg
index df647466d..f2e971ed1 100644
--- a/src/test/ref/sinusgen16.cfg
+++ b/src/test/ref/sinusgen16.cfg
@@ -160,7 +160,7 @@ sin16s::@5: scope:[sin16s]  from sin16s::@1
 sin16s::@2: scope:[sin16s]  from sin16s::@1 sin16s::@5
   [67] sin16s::x#6 = phi( sin16s::@1/sin16s::x#4, sin16s::@5/sin16s::x#2 )
   [68] sin16s::$4 = sin16s::x#6 << 3
-  [69] sin16s::x1#0 = > sin16s::$4
+  [69] sin16s::x1#0 = _word1_ sin16s::$4
   [70] mulu16_sel::v1#0 = sin16s::x1#0
   [71] mulu16_sel::v2#0 = sin16s::x1#0
   [72] call mulu16_sel 
@@ -255,7 +255,7 @@ print_uint::@return: scope:[print_uint]  from print_uint::@1
 
 word divr16u(word divr16u::dividend , word divr16u::divisor , word divr16u::rem)
 divr16u: scope:[divr16u]  from div32u16u div32u16u::@1
-  [117] divr16u::dividend#5 = phi( div32u16u/>PI2_u4f28, div32u16u::@1/<PI2_u4f28 )
+  [117] divr16u::dividend#5 = phi( div32u16u/_word1_PI2_u4f28, div32u16u::@1/_word0_PI2_u4f28 )
   [117] divr16u::rem#10 = phi( div32u16u/0, div32u16u::@1/divr16u::rem#4 )
   to:divr16u::@1
 divr16u::@1: scope:[divr16u]  from divr16u divr16u::@3
@@ -307,7 +307,7 @@ mulu16_sel: scope:[mulu16_sel]  from sin16s::@10 sin16s::@2 sin16s::@7 sin16s::@
 mulu16_sel::@1: scope:[mulu16_sel]  from mulu16_sel
   [140] mulu16_sel::$0 = mul16u::return#0
   [141] mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5
-  [142] mulu16_sel::return#12 = > mulu16_sel::$1
+  [142] mulu16_sel::return#12 = _word1_ mulu16_sel::$1
   to:mulu16_sel::@return
 mulu16_sel::@return: scope:[mulu16_sel]  from mulu16_sel::@1
   [143] return 
diff --git a/src/test/ref/sinusgen16.log b/src/test/ref/sinusgen16.log
index f299b5c7c..0eb2e39d1 100644
--- a/src/test/ref/sinusgen16.log
+++ b/src/test/ref/sinusgen16.log
@@ -90,7 +90,7 @@ sin16s::@2: scope:[sin16s]  from sin16s::@1 sin16s::@5
   sin16s::isUpper#7 = phi( sin16s::@1/sin16s::isUpper#8, sin16s::@5/sin16s::isUpper#9 )
   sin16s::x#6 = phi( sin16s::@1/sin16s::x#4, sin16s::@5/sin16s::x#2 )
   sin16s::$4 = sin16s::x#6 << 3
-  sin16s::$5 = > sin16s::$4
+  sin16s::$5 = _word1_ sin16s::$4
   sin16s::x1#0 = sin16s::$5
   mulu16_sel::v1#0 = sin16s::x1#0
   mulu16_sel::v2#0 = sin16s::x1#0
@@ -201,7 +201,7 @@ mulu16_sel::@1: scope:[mulu16_sel]  from mulu16_sel
   mul16u::return#3 = phi( mulu16_sel/mul16u::return#0 )
   mulu16_sel::$0 = mul16u::return#3
   mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5
-  mulu16_sel::$2 = > mulu16_sel::$1
+  mulu16_sel::$2 = _word1_ mulu16_sel::$1
   mulu16_sel::return#5 = mulu16_sel::$2
   to:mulu16_sel::@return
 mulu16_sel::@return: scope:[mulu16_sel]  from mulu16_sel::@1
@@ -294,7 +294,7 @@ div32u16u: scope:[div32u16u]  from sin16s_gen
   rem16u#24 = phi( sin16s_gen/rem16u#22 )
   div32u16u::divisor#1 = phi( sin16s_gen/div32u16u::divisor#0 )
   div32u16u::dividend#1 = phi( sin16s_gen/div32u16u::dividend#0 )
-  div32u16u::$0 = > div32u16u::dividend#1
+  div32u16u::$0 = _word1_ div32u16u::dividend#1
   divr16u::dividend#1 = div32u16u::$0
   divr16u::divisor#0 = div32u16u::divisor#1
   divr16u::rem#3 = 0
@@ -309,7 +309,7 @@ div32u16u::@1: scope:[div32u16u]  from div32u16u
   div32u16u::$1 = divr16u::return#5
   rem16u#4 = rem16u#15
   div32u16u::quotient_hi#0 = div32u16u::$1
-  div32u16u::$2 = < div32u16u::dividend#2
+  div32u16u::$2 = _word0_ div32u16u::dividend#2
   divr16u::dividend#2 = div32u16u::$2
   divr16u::divisor#1 = div32u16u::divisor#2
   divr16u::rem#4 = rem16u#4
@@ -1656,13 +1656,13 @@ Simplifying constant integer cast $10
 Successful SSA optimization PassNCastSimplification
 Finalized unsigned number type (byte) $10
 Successful SSA optimization PassNFinalizeNumberTypeConversions
-Constant right-side identified [81] divr16u::dividend#1 = > div32u16u::dividend#0
-Constant right-side identified [85] divr16u::dividend#2 = < div32u16u::dividend#0
+Constant right-side identified [81] divr16u::dividend#1 = _word1_ div32u16u::dividend#0
+Constant right-side identified [85] divr16u::dividend#2 = _word0_ div32u16u::dividend#0
 Constant right-side identified [136] memset::end#0 = memset::$4 + memset::num#0
 Constant right-side identified [145] main::$2 = main::sintab1 + main::$9
 Successful SSA optimization Pass2ConstantRValueConsolidation
-Constant divr16u::dividend#1 = >div32u16u::dividend#0
-Constant divr16u::dividend#2 = <div32u16u::dividend#0
+Constant divr16u::dividend#1 = _word1_div32u16u::dividend#0
+Constant divr16u::dividend#2 = _word0_div32u16u::dividend#0
 Constant memset::end#0 = memset::$4+memset::num#0
 Constant main::$2 = main::sintab1+main::$9
 Successful SSA optimization Pass2ConstantIdentification
@@ -1710,8 +1710,8 @@ Constant inlined mulu16_sel::select#1 = 1
 Constant inlined divr16u::divisor#1 = main::wavelength
 Constant inlined divr16u::divisor#0 = main::wavelength
 Constant inlined sin16s_gen::i#0 = 0
-Constant inlined divr16u::dividend#1 = >PI2_u4f28
-Constant inlined divr16u::dividend#2 = <PI2_u4f28
+Constant inlined divr16u::dividend#1 = _word1_PI2_u4f28
+Constant inlined divr16u::dividend#2 = _word0_PI2_u4f28
 Constant inlined sin16s_gen::sintab#1 = main::sintab1
 Constant inlined print_char::ch#2 = ' '
 Constant inlined main::$2 = main::sintab1+main::wavelength*SIZEOF_SIGNED_WORD
@@ -2031,7 +2031,7 @@ sin16s::@5: scope:[sin16s]  from sin16s::@1
 sin16s::@2: scope:[sin16s]  from sin16s::@1 sin16s::@5
   [67] sin16s::x#6 = phi( sin16s::@1/sin16s::x#4, sin16s::@5/sin16s::x#2 )
   [68] sin16s::$4 = sin16s::x#6 << 3
-  [69] sin16s::x1#0 = > sin16s::$4
+  [69] sin16s::x1#0 = _word1_ sin16s::$4
   [70] mulu16_sel::v1#0 = sin16s::x1#0
   [71] mulu16_sel::v2#0 = sin16s::x1#0
   [72] call mulu16_sel 
@@ -2126,7 +2126,7 @@ print_uint::@return: scope:[print_uint]  from print_uint::@1
 
 word divr16u(word divr16u::dividend , word divr16u::divisor , word divr16u::rem)
 divr16u: scope:[divr16u]  from div32u16u div32u16u::@1
-  [117] divr16u::dividend#5 = phi( div32u16u/>PI2_u4f28, div32u16u::@1/<PI2_u4f28 )
+  [117] divr16u::dividend#5 = phi( div32u16u/_word1_PI2_u4f28, div32u16u::@1/_word0_PI2_u4f28 )
   [117] divr16u::rem#10 = phi( div32u16u/0, div32u16u::@1/divr16u::rem#4 )
   to:divr16u::@1
 divr16u::@1: scope:[divr16u]  from divr16u divr16u::@3
@@ -2178,7 +2178,7 @@ mulu16_sel: scope:[mulu16_sel]  from sin16s::@10 sin16s::@2 sin16s::@7 sin16s::@
 mulu16_sel::@1: scope:[mulu16_sel]  from mulu16_sel
   [140] mulu16_sel::$0 = mul16u::return#0
   [141] mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5
-  [142] mulu16_sel::return#12 = > mulu16_sel::$1
+  [142] mulu16_sel::return#12 = _word1_ mulu16_sel::$1
   to:mulu16_sel::@return
 mulu16_sel::@return: scope:[mulu16_sel]  from mulu16_sel::@1
   [143] return 
@@ -2625,7 +2625,7 @@ Statement [65] if(sin16s::x#4<PI_HALF_u4f28) goto sin16s::@2 [ sin16s::x#4 sin16
 Removing always clobbered register reg byte a as potential for zp[1]:16 [ sin16s::isUpper#2 ]
 Statement [66] sin16s::x#2 = PI_u4f28 - sin16s::x#4 [ sin16s::isUpper#2 sin16s::x#2 ] ( sin16s_gen:1::sin16s:25 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x#2 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
 Statement [68] sin16s::$4 = sin16s::x#6 << 3 [ sin16s::isUpper#2 sin16s::$4 ] ( sin16s_gen:1::sin16s:25 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::$4 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
-Statement [69] sin16s::x1#0 = > sin16s::$4 [ sin16s::isUpper#2 sin16s::x1#0 ] ( sin16s_gen:1::sin16s:25 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
+Statement [69] sin16s::x1#0 = _word1_ sin16s::$4 [ sin16s::isUpper#2 sin16s::x1#0 ] ( sin16s_gen:1::sin16s:25 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [70] mulu16_sel::v1#0 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 ] ( sin16s_gen:1::sin16s:25 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [71] mulu16_sel::v2#0 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 mulu16_sel::v2#0 ] ( sin16s_gen:1::sin16s:25 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 mulu16_sel::v2#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [73] mulu16_sel::return#0 = mulu16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#0 ] ( sin16s_gen:1::sin16s:25 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
@@ -2665,7 +2665,7 @@ Statement [137] mul16u::b#0 = mulu16_sel::v2#5 [ mulu16_sel::select#5 mul16u::a#
 Statement [139] mul16u::return#0 = mul16u::res#2 [ mulu16_sel::select#5 mul16u::return#0 ] ( sin16s_gen:1::sin16s:25::mulu16_sel:72 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 mul16u::a#0 mul16u::b#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:77 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 mul16u::a#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 mul16u::b#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:81 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 mul16u::a#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mulu16_sel::v2#5 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:87 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 mul16u::a#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 mul16u::b#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 mul16u::a#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 mul16u::b#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
 Statement [140] mulu16_sel::$0 = mul16u::return#0 [ mulu16_sel::select#5 mulu16_sel::$0 ] ( sin16s_gen:1::sin16s:25::mulu16_sel:72 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:77 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:81 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:87 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [141] mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5 [ mulu16_sel::$1 ] ( sin16s_gen:1::sin16s:25::mulu16_sel:72 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:77 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:81 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:87 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
-Statement [142] mulu16_sel::return#12 = > mulu16_sel::$1 [ mulu16_sel::return#12 ] ( sin16s_gen:1::sin16s:25::mulu16_sel:72 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:77 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:81 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:87 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
+Statement [142] mulu16_sel::return#12 = _word1_ mulu16_sel::$1 [ mulu16_sel::return#12 ] ( sin16s_gen:1::sin16s:25::mulu16_sel:72 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:77 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:81 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:87 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [145] print_uchar::$0 = print_uchar::b#2 >> 4 [ print_char_cursor#12 print_uchar::b#2 print_uchar::$0 ] ( print_sint:13::print_uint:47::print_uchar:113 [ main::st1#2 print_uint::w#0 print_char_cursor#12 print_uchar::b#2 print_uchar::$0 ] { { print_sint::w#1 = main::sw#0 } { print_uchar::b#0 = print_uchar::b#2 } { print_char::ch#3 = print_char::ch#5 } { print_char_cursor#12 = print_char_cursor#36 } }  print_sint:13::print_uint:47::print_uchar:115 [ main::st1#2 print_char_cursor#12 print_uchar::b#2 print_uchar::$0 ] { { print_sint::w#1 = main::sw#0 } { print_uchar::b#1 = print_uchar::b#2 } { print_char::ch#3 = print_char::ch#5 } { print_char_cursor#12 = print_char_cursor#36 } }  ) always clobbers reg byte a 
 Removing always clobbered register reg byte a as potential for zp[1]:40 [ print_uchar::b#2 print_uchar::b#0 print_uchar::b#1 ]
 Statement [148] print_uchar::$2 = print_uchar::b#2 & $f [ print_char_cursor#12 print_uchar::$2 ] ( print_sint:13::print_uint:47::print_uchar:113 [ main::st1#2 print_uint::w#0 print_char_cursor#12 print_uchar::$2 ] { { print_sint::w#1 = main::sw#0 } { print_uchar::b#0 = print_uchar::b#2 } { print_char::ch#4 = print_char::ch#5 } { print_char_cursor#12 = print_char_cursor#36 } }  print_sint:13::print_uint:47::print_uchar:115 [ main::st1#2 print_char_cursor#12 print_uchar::$2 ] { { print_sint::w#1 = main::sw#0 } { print_uchar::b#1 = print_uchar::b#2 } { print_char::ch#4 = print_char::ch#5 } { print_char_cursor#12 = print_char_cursor#36 } }  ) always clobbers reg byte a 
@@ -2703,7 +2703,7 @@ Statement [63] sin16s::x#1 = sin16s::x#0 - PI_u4f28 [ sin16s::x#1 ] ( sin16s_gen
 Statement [65] if(sin16s::x#4<PI_HALF_u4f28) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#2 ] ( sin16s_gen:1::sin16s:25 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::x#4 sin16s::isUpper#2 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
 Statement [66] sin16s::x#2 = PI_u4f28 - sin16s::x#4 [ sin16s::isUpper#2 sin16s::x#2 ] ( sin16s_gen:1::sin16s:25 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x#2 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
 Statement [68] sin16s::$4 = sin16s::x#6 << 3 [ sin16s::isUpper#2 sin16s::$4 ] ( sin16s_gen:1::sin16s:25 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::$4 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
-Statement [69] sin16s::x1#0 = > sin16s::$4 [ sin16s::isUpper#2 sin16s::x1#0 ] ( sin16s_gen:1::sin16s:25 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
+Statement [69] sin16s::x1#0 = _word1_ sin16s::$4 [ sin16s::isUpper#2 sin16s::x1#0 ] ( sin16s_gen:1::sin16s:25 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [70] mulu16_sel::v1#0 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 ] ( sin16s_gen:1::sin16s:25 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [71] mulu16_sel::v2#0 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 mulu16_sel::v2#0 ] ( sin16s_gen:1::sin16s:25 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 mulu16_sel::v2#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [73] mulu16_sel::return#0 = mulu16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#0 ] ( sin16s_gen:1::sin16s:25 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
@@ -2740,7 +2740,7 @@ Statement [137] mul16u::b#0 = mulu16_sel::v2#5 [ mulu16_sel::select#5 mul16u::a#
 Statement [139] mul16u::return#0 = mul16u::res#2 [ mulu16_sel::select#5 mul16u::return#0 ] ( sin16s_gen:1::sin16s:25::mulu16_sel:72 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 mul16u::a#0 mul16u::b#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:77 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 mul16u::a#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 mul16u::b#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:81 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 mul16u::a#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mulu16_sel::v2#5 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:87 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 mul16u::a#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 mul16u::b#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 mul16u::a#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 mul16u::b#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
 Statement [140] mulu16_sel::$0 = mul16u::return#0 [ mulu16_sel::select#5 mulu16_sel::$0 ] ( sin16s_gen:1::sin16s:25::mulu16_sel:72 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:77 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:81 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:87 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [141] mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5 [ mulu16_sel::$1 ] ( sin16s_gen:1::sin16s:25::mulu16_sel:72 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:77 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:81 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:87 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
-Statement [142] mulu16_sel::return#12 = > mulu16_sel::$1 [ mulu16_sel::return#12 ] ( sin16s_gen:1::sin16s:25::mulu16_sel:72 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:77 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:81 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:87 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
+Statement [142] mulu16_sel::return#12 = _word1_ mulu16_sel::$1 [ mulu16_sel::return#12 ] ( sin16s_gen:1::sin16s:25::mulu16_sel:72 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:77 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:81 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:87 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen:1::sin16s:25::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [145] print_uchar::$0 = print_uchar::b#2 >> 4 [ print_char_cursor#12 print_uchar::b#2 print_uchar::$0 ] ( print_sint:13::print_uint:47::print_uchar:113 [ main::st1#2 print_uint::w#0 print_char_cursor#12 print_uchar::b#2 print_uchar::$0 ] { { print_sint::w#1 = main::sw#0 } { print_uchar::b#0 = print_uchar::b#2 } { print_char::ch#3 = print_char::ch#5 } { print_char_cursor#12 = print_char_cursor#36 } }  print_sint:13::print_uint:47::print_uchar:115 [ main::st1#2 print_char_cursor#12 print_uchar::b#2 print_uchar::$0 ] { { print_sint::w#1 = main::sw#0 } { print_uchar::b#1 = print_uchar::b#2 } { print_char::ch#3 = print_char::ch#5 } { print_char_cursor#12 = print_char_cursor#36 } }  ) always clobbers reg byte a 
 Statement [148] print_uchar::$2 = print_uchar::b#2 & $f [ print_char_cursor#12 print_uchar::$2 ] ( print_sint:13::print_uint:47::print_uchar:113 [ main::st1#2 print_uint::w#0 print_char_cursor#12 print_uchar::$2 ] { { print_sint::w#1 = main::sw#0 } { print_uchar::b#0 = print_uchar::b#2 } { print_char::ch#4 = print_char::ch#5 } { print_char_cursor#12 = print_char_cursor#36 } }  print_sint:13::print_uint:47::print_uchar:115 [ main::st1#2 print_char_cursor#12 print_uchar::$2 ] { { print_sint::w#1 = main::sw#0 } { print_uchar::b#1 = print_uchar::b#2 } { print_char::ch#4 = print_char::ch#5 } { print_char_cursor#12 = print_char_cursor#36 } }  ) always clobbers reg byte a 
 Statement [152] mul16u::mb#0 = (dword)mul16u::b#0 [ mul16u::a#0 mul16u::mb#0 ] ( sin16s_gen:1::sin16s:25::mulu16_sel:72::mul16u:138 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#0 mul16u::mb#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 mul16u::a#0 mul16u::b#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:77::mul16u:138 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#0 mul16u::mb#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 mul16u::a#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 mul16u::b#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:81::mul16u:138 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::a#0 mul16u::mb#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 mul16u::a#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mulu16_sel::v2#5 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:87::mul16u:138 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#0 mul16u::mb#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 mul16u::a#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 mul16u::b#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:1::sin16s:25::mulu16_sel:92::mul16u:138 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#0 mul16u::mb#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 mul16u::a#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 mul16u::b#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
@@ -3292,7 +3292,7 @@ div32u16u: {
     // [53] call divr16u 
     // [117] phi from div32u16u to divr16u [phi:div32u16u->divr16u]
   divr16u_from_div32u16u:
-    // [117] phi divr16u::dividend#5 = >PI2_u4f28 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1 
+    // [117] phi divr16u::dividend#5 = _word1_PI2_u4f28 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1 
     lda #<PI2_u4f28>>$10
     sta.z divr16u.dividend
     lda #>PI2_u4f28>>$10
@@ -3316,7 +3316,7 @@ div32u16u: {
     // [57] call divr16u 
     // [117] phi from div32u16u::@1 to divr16u [phi:div32u16u::@1->divr16u]
   divr16u_from___b1:
-    // [117] phi divr16u::dividend#5 = <PI2_u4f28 [phi:div32u16u::@1->divr16u#0] -- vwuz1=vwuc1 
+    // [117] phi divr16u::dividend#5 = _word0_PI2_u4f28 [phi:div32u16u::@1->divr16u#0] -- vwuz1=vwuc1 
     lda #<PI2_u4f28&$ffff
     sta.z divr16u.dividend
     lda #>PI2_u4f28&$ffff
@@ -3471,7 +3471,7 @@ sin16s: {
     rol.z __4+1
     rol.z __4+2
     rol.z __4+3
-    // [69] sin16s::x1#0 = > sin16s::$4 -- vwuz1=_hi_vduz2 
+    // [69] sin16s::x1#0 = _word1_ sin16s::$4 -- vwuz1=_word1_vduz2 
     lda.z __4+2
     sta.z x1
     lda.z __4+3
@@ -3711,7 +3711,7 @@ print_char: {
 // print_uint(word zp($a) w)
 print_uint: {
     .label w = $a
-    // [112] print_uchar::b#0 = > print_uint::w#0 -- vbuxx=_hi_vwuz1 
+    // [112] print_uchar::b#0 = > print_uint::w#0 -- vbuxx=_byte1_vwuz1 
     ldx.z w+1
     // [113] call print_uchar 
     // [144] phi from print_uint to print_uchar [phi:print_uint->print_uchar]
@@ -3721,7 +3721,7 @@ print_uint: {
     jmp __b1
     // print_uint::@1
   __b1:
-    // [114] print_uchar::b#1 = < print_uint::w#0 -- vbuxx=_lo_vwuz1 
+    // [114] print_uchar::b#1 = < print_uint::w#0 -- vbuxx=_byte0_vwuz1 
     ldx.z w
     // [115] call print_uchar 
     // [144] phi from print_uint::@1 to print_uchar [phi:print_uint::@1->print_uchar]
@@ -3769,7 +3769,7 @@ divr16u: {
     // [119] divr16u::rem#0 = divr16u::rem#5 << 1 -- vwuz1=vwuz1_rol_1 
     asl.z rem
     rol.z rem+1
-    // [120] divr16u::$1 = > divr16u::dividend#3 -- vbuaa=_hi_vwuz1 
+    // [120] divr16u::$1 = > divr16u::dividend#3 -- vbuaa=_byte1_vwuz1 
     lda.z dividend+1
     // [121] divr16u::$2 = divr16u::$1 & $80 -- vbuaa=vbuaa_band_vbuc1 
     and #$80
@@ -3879,7 +3879,7 @@ mulu16_sel: {
     dex
     bne !-
   !e:
-    // [142] mulu16_sel::return#12 = > mulu16_sel::$1 -- vwuz1=_hi_vduz2 
+    // [142] mulu16_sel::return#12 = _word1_ mulu16_sel::$1 -- vwuz1=_word1_vduz2 
     lda.z __1+2
     sta.z return
     lda.z __1+3
@@ -4807,10 +4807,10 @@ div32u16u: {
     .label return = $1a
     .label quotient_hi = $24
     .label quotient_lo = $14
-    // divr16u(>dividend, divisor, 0)
+    // divr16u(WORD1(dividend), divisor, 0)
     // [53] call divr16u 
     // [117] phi from div32u16u to divr16u [phi:div32u16u->divr16u]
-    // [117] phi divr16u::dividend#5 = >PI2_u4f28 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1 
+    // [117] phi divr16u::dividend#5 = _word1_PI2_u4f28 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1 
     lda #<PI2_u4f28>>$10
     sta.z divr16u.dividend
     lda #>PI2_u4f28>>$10
@@ -4820,30 +4820,30 @@ div32u16u: {
     sta.z divr16u.rem
     sta.z divr16u.rem+1
     jsr divr16u
-    // divr16u(>dividend, divisor, 0)
+    // divr16u(WORD1(dividend), divisor, 0)
     // [54] divr16u::return#2 = divr16u::return#0
     // div32u16u::@1
-    // unsigned int quotient_hi = divr16u(>dividend, divisor, 0)
+    // unsigned int quotient_hi = divr16u(WORD1(dividend), divisor, 0)
     // [55] div32u16u::quotient_hi#0 = divr16u::return#2 -- vwuz1=vwuz2 
     lda.z divr16u.return
     sta.z quotient_hi
     lda.z divr16u.return+1
     sta.z quotient_hi+1
-    // divr16u(<dividend, divisor, rem16u)
+    // divr16u(WORD0(dividend), divisor, rem16u)
     // [56] divr16u::rem#4 = rem16u#14
     // [57] call divr16u 
     // [117] phi from div32u16u::@1 to divr16u [phi:div32u16u::@1->divr16u]
-    // [117] phi divr16u::dividend#5 = <PI2_u4f28 [phi:div32u16u::@1->divr16u#0] -- vwuz1=vwuc1 
+    // [117] phi divr16u::dividend#5 = _word0_PI2_u4f28 [phi:div32u16u::@1->divr16u#0] -- vwuz1=vwuc1 
     lda #<PI2_u4f28&$ffff
     sta.z divr16u.dividend
     lda #>PI2_u4f28&$ffff
     sta.z divr16u.dividend+1
     // [117] phi divr16u::rem#10 = divr16u::rem#4 [phi:div32u16u::@1->divr16u#1] -- register_copy 
     jsr divr16u
-    // divr16u(<dividend, divisor, rem16u)
+    // divr16u(WORD0(dividend), divisor, rem16u)
     // [58] divr16u::return#3 = divr16u::return#0
     // div32u16u::@2
-    // unsigned int quotient_lo = divr16u(<dividend, divisor, rem16u)
+    // unsigned int quotient_lo = divr16u(WORD0(dividend), divisor, rem16u)
     // [59] div32u16u::quotient_lo#0 = divr16u::return#3
     // unsigned long quotient = { quotient_hi, quotient_lo}
     // [60] div32u16u::return#1 = div32u16u::quotient_hi#0 dw= div32u16u::quotient_lo#0 -- vduz1=vwuz2_dword_vwuz3 
@@ -4984,8 +4984,8 @@ sin16s: {
     rol.z __4+1
     rol.z __4+2
     rol.z __4+3
-    // unsigned int x1 = >x<<3
-    // [69] sin16s::x1#0 = > sin16s::$4 -- vwuz1=_hi_vduz2 
+    // unsigned int x1 = WORD1(x<<3)
+    // [69] sin16s::x1#0 = _word1_ sin16s::$4 -- vwuz1=_word1_vduz2 
     lda.z __4+2
     sta.z x1
     lda.z __4+3
@@ -5222,16 +5222,16 @@ print_char: {
 // print_uint(word zp($a) w)
 print_uint: {
     .label w = $a
-    // print_uchar(>w)
-    // [112] print_uchar::b#0 = > print_uint::w#0 -- vbuxx=_hi_vwuz1 
+    // print_uchar(BYTE1(w))
+    // [112] print_uchar::b#0 = > print_uint::w#0 -- vbuxx=_byte1_vwuz1 
     ldx.z w+1
     // [113] call print_uchar 
     // [144] phi from print_uint to print_uchar [phi:print_uint->print_uchar]
     // [144] phi print_uchar::b#2 = print_uchar::b#0 [phi:print_uint->print_uchar#0] -- register_copy 
     jsr print_uchar
     // print_uint::@1
-    // print_uchar(<w)
-    // [114] print_uchar::b#1 = < print_uint::w#0 -- vbuxx=_lo_vwuz1 
+    // print_uchar(BYTE0(w))
+    // [114] print_uchar::b#1 = < print_uint::w#0 -- vbuxx=_byte0_vwuz1 
     ldx.z w
     // [115] call print_uchar 
     // [144] phi from print_uint::@1 to print_uchar [phi:print_uint::@1->print_uchar]
@@ -5273,13 +5273,13 @@ divr16u: {
     // [119] divr16u::rem#0 = divr16u::rem#5 << 1 -- vwuz1=vwuz1_rol_1 
     asl.z rem
     rol.z rem+1
-    // >dividend
-    // [120] divr16u::$1 = > divr16u::dividend#3 -- vbuaa=_hi_vwuz1 
+    // BYTE1(dividend)
+    // [120] divr16u::$1 = > divr16u::dividend#3 -- vbuaa=_byte1_vwuz1 
     lda.z dividend+1
-    // >dividend & $80
+    // BYTE1(dividend) & $80
     // [121] divr16u::$2 = divr16u::$1 & $80 -- vbuaa=vbuaa_band_vbuc1 
     and #$80
-    // if( (>dividend & $80) != 0 )
+    // if( (BYTE1(dividend) & $80) != 0 )
     // [122] if(divr16u::$2==0) goto divr16u::@2 -- vbuaa_eq_0_then_la1 
     cmp #0
     beq __b2
@@ -5381,8 +5381,8 @@ mulu16_sel: {
     dex
     bne !-
   !e:
-    // >mul16u(v1, v2)<<select
-    // [142] mulu16_sel::return#12 = > mulu16_sel::$1 -- vwuz1=_hi_vduz2 
+    // WORD1(mul16u(v1, v2)<<select)
+    // [142] mulu16_sel::return#12 = _word1_ mulu16_sel::$1 -- vwuz1=_word1_vduz2 
     lda.z __1+2
     sta.z return
     lda.z __1+3