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@ -1654,6 +1654,8 @@ Inlining constant with var siblings (const word) divr16u::divisor#1
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Constant inlined divr16u::divisor#1 = (byte) $14-(byte) 1
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Constant inlined divr16u::divisor#0 = (byte) $14-(byte) 1
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Successful SSA optimization Pass2ConstantInlining
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Identical Phi Values (word) divr16u::divisor#6 (byte) $14-(byte) 1
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Successful SSA optimization Pass2IdenticalPhiElimination
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Added new block during phi lifting divr16u::@7(between divr16u::@3 and divr16u::@1)
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Added new block during phi lifting divr16u::@8(between divr16u::@1 and divr16u::@2)
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Added new block during phi lifting divr16u::@9(between divr16u::@2 and divr16u::@3)
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@ -1695,7 +1697,7 @@ Calls in [print_str] to print_char:119
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Calls in [print_cls] to memset:124
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Calls in [lin16u_gen] to divr16u:140 divr16u:145
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Created 29 initial phi equivalence classes
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Created 28 initial phi equivalence classes
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Coalesced [19] print_char_cursor#99 ← print_char_cursor#11
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Coalesced (already) [23] print_char_cursor#92 ← print_char_cursor#11
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Not coalescing [32] print_char_cursor#98 ← print_line_cursor#1
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@ -1748,7 +1750,7 @@ Coalesced [189] divr16u::i#7 ← divr16u::i#1
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Coalesced [190] divr16u::rem#17 ← divr16u::rem#6
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Coalesced [191] divr16u::return#7 ← divr16u::quotient#1
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Coalesced [192] divr16u::rem#15 ← divr16u::rem#0
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Coalesced down to 18 phi equivalence classes
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Coalesced down to 17 phi equivalence classes
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Culled Empty Block (label) @1
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Culled Empty Block (label) @2
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Culled Empty Block (label) @4
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@ -2080,7 +2082,6 @@ lin16u_gen::@2: scope:[lin16u_gen] from lin16u_gen::@1
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(word()) divr16u((word) divr16u::dividend , (word) divr16u::divisor , (word) divr16u::rem)
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divr16u: scope:[divr16u] from lin16u_gen lin16u_gen::@3
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[123] (word) divr16u::divisor#6 ← phi( lin16u_gen/(byte) $14-(byte) 1 lin16u_gen::@3/(byte) $14-(byte) 1 )
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[123] (word) divr16u::dividend#5 ← phi( lin16u_gen/(word) divr16u::dividend#1 lin16u_gen::@3/(byte) 0 )
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[123] (word) divr16u::rem#10 ← phi( lin16u_gen/(byte) 0 lin16u_gen::@3/(word) divr16u::rem#4 )
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to:divr16u::@1
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@ -2101,11 +2102,11 @@ divr16u::@2: scope:[divr16u] from divr16u::@1 divr16u::@4
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[130] (word) divr16u::rem#6 ← phi( divr16u::@1/(word) divr16u::rem#0 divr16u::@4/(word) divr16u::rem#1 )
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[131] (word) divr16u::dividend#0 ← (word) divr16u::dividend#3 << (byte) 1
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[132] (word) divr16u::quotient#1 ← (word) divr16u::quotient#3 << (byte) 1
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[133] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3
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[133] if((word) divr16u::rem#6<(byte) $14-(byte) 1) goto divr16u::@3
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to:divr16u::@5
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divr16u::@5: scope:[divr16u] from divr16u::@2
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[134] (word) divr16u::quotient#2 ← ++ (word) divr16u::quotient#1
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[135] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6
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[135] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (byte) $14-(byte) 1
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to:divr16u::@3
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divr16u::@3: scope:[divr16u] from divr16u::@2 divr16u::@5
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[136] (word) divr16u::return#0 ← phi( divr16u::@2/(word) divr16u::quotient#1 divr16u::@5/(word) divr16u::quotient#2 )
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@ -2131,7 +2132,6 @@ VARIABLE REGISTER WEIGHTS
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(word) divr16u::dividend#3 4429.142857142857
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(word) divr16u::dividend#5 1102.0
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(word) divr16u::divisor
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(word) divr16u::divisor#6 1250.125
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(byte) divr16u::i
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(byte) divr16u::i#1 15001.5
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(byte) divr16u::i#2 1538.6153846153845
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@ -2251,7 +2251,6 @@ Initial phi equivalence classes
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[ lin16u_gen::i#2 lin16u_gen::i#1 ]
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[ lin16u_gen::val#2 lin16u_gen::val#1 lin16u_gen::val#0 ]
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[ lin16u_gen::lintab#4 lin16u_gen::lintab#3 lin16u_gen::lintab#6 ]
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[ divr16u::divisor#6 ]
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[ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ]
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[ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#1 divr16u::dividend#0 ]
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[ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ]
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@ -2285,7 +2284,6 @@ Complete equivalence classes
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[ lin16u_gen::i#2 lin16u_gen::i#1 ]
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[ lin16u_gen::val#2 lin16u_gen::val#1 lin16u_gen::val#0 ]
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[ lin16u_gen::lintab#4 lin16u_gen::lintab#3 lin16u_gen::lintab#6 ]
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[ divr16u::divisor#6 ]
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[ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ]
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[ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#1 divr16u::dividend#0 ]
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[ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ]
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@ -2318,26 +2316,25 @@ Allocated zp[2]:17 [ lin16u_gen::min#3 ]
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Allocated zp[2]:19 [ lin16u_gen::i#2 lin16u_gen::i#1 ]
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Allocated zp[4]:21 [ lin16u_gen::val#2 lin16u_gen::val#1 lin16u_gen::val#0 ]
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Allocated zp[2]:25 [ lin16u_gen::lintab#4 lin16u_gen::lintab#3 lin16u_gen::lintab#6 ]
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Allocated zp[2]:27 [ divr16u::divisor#6 ]
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Allocated zp[2]:29 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ]
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Allocated zp[2]:31 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#1 divr16u::dividend#0 ]
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Allocated zp[2]:33 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ]
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Allocated zp[1]:35 [ divr16u::i#2 divr16u::i#1 ]
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Allocated zp[1]:36 [ main::$27 ]
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Allocated zp[1]:37 [ main::$28 ]
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Allocated zp[1]:38 [ main::$29 ]
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Allocated zp[1]:39 [ print_uchar::$0 ]
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Allocated zp[1]:40 [ print_uchar::$2 ]
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Allocated zp[2]:41 [ lin16u_gen::ampl#0 ]
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Allocated zp[2]:43 [ divr16u::return#2 ]
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Allocated zp[2]:45 [ lin16u_gen::stepi#0 ]
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Allocated zp[2]:47 [ divr16u::return#3 ]
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Allocated zp[2]:49 [ lin16u_gen::stepf#0 ]
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Allocated zp[4]:51 [ lin16u_gen::step#0 ]
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Allocated zp[2]:55 [ lin16u_gen::$6 ]
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Allocated zp[1]:57 [ divr16u::$1 ]
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Allocated zp[1]:58 [ divr16u::$2 ]
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Allocated zp[2]:59 [ rem16u#1 ]
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Allocated zp[2]:27 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ]
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Allocated zp[2]:29 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#1 divr16u::dividend#0 ]
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Allocated zp[2]:31 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ]
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Allocated zp[1]:33 [ divr16u::i#2 divr16u::i#1 ]
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Allocated zp[1]:34 [ main::$27 ]
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Allocated zp[1]:35 [ main::$28 ]
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Allocated zp[1]:36 [ main::$29 ]
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Allocated zp[1]:37 [ print_uchar::$0 ]
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Allocated zp[1]:38 [ print_uchar::$2 ]
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Allocated zp[2]:39 [ lin16u_gen::ampl#0 ]
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Allocated zp[2]:41 [ divr16u::return#2 ]
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Allocated zp[2]:43 [ lin16u_gen::stepi#0 ]
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Allocated zp[2]:45 [ divr16u::return#3 ]
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Allocated zp[2]:47 [ lin16u_gen::stepf#0 ]
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Allocated zp[4]:49 [ lin16u_gen::step#0 ]
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Allocated zp[2]:53 [ lin16u_gen::$6 ]
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Allocated zp[1]:55 [ divr16u::$1 ]
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Allocated zp[1]:56 [ divr16u::$2 ]
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Allocated zp[2]:57 [ rem16u#1 ]
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INITIAL ASM
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Target platform is c64basic / MOS6502X
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@ -2351,7 +2348,7 @@ Target platform is c64basic / MOS6502X
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// Global Constants & labels
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.const SIZEOF_WORD = 2
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// Remainder after unsigned 16-bit division
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.label rem16u = $3b
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.label rem16u = $39
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.label print_char_cursor = 9
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.label print_line_cursor = 3
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// @begin
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@ -2372,9 +2369,9 @@ __bend_from___b1:
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__bend:
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// main
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main: {
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.label __27 = $24
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.label __28 = $25
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.label __29 = $26
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.label __27 = $22
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.label __28 = $23
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.label __29 = $24
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.label i = 2
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// [5] call lin16u_gen
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// [103] phi from main to lin16u_gen [phi:main->lin16u_gen]
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@ -2885,8 +2882,8 @@ print_uint: {
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// Print a char as HEX
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// print_uchar(byte zp(7) b)
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print_uchar: {
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.label __0 = $27
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.label __2 = $28
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.label __0 = $25
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.label __2 = $26
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.label b = 7
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// [76] (byte~) print_uchar::$0 ← (byte) print_uchar::b#3 >> (byte) 4 -- vbuz1=vbuz2_ror_4
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lda.z b
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@ -3059,11 +3056,11 @@ memset: {
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// length - the number of points in a total sinus wavelength (the size of the table)
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// lin16u_gen(word zp($11) min, word zp($f) max, word* zp($19) lintab)
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lin16u_gen: {
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.label __6 = $37
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.label ampl = $29
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.label stepi = $2d
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.label stepf = $31
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.label step = $33
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.label __6 = $35
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.label ampl = $27
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.label stepi = $2b
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.label stepf = $2f
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.label step = $31
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.label val = $15
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.label lintab = $19
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.label i = $13
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@ -3085,13 +3082,8 @@ lin16u_gen: {
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// [106] call divr16u
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// [123] phi from lin16u_gen to divr16u [phi:lin16u_gen->divr16u]
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divr16u_from_lin16u_gen:
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// [123] phi (word) divr16u::divisor#6 = (byte) $14-(byte) 1 [phi:lin16u_gen->divr16u#0] -- vwuz1=vbuc1
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lda #<$14-1
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sta.z divr16u.divisor
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lda #>$14-1
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sta.z divr16u.divisor+1
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// [123] phi (word) divr16u::dividend#5 = (word) divr16u::dividend#1 [phi:lin16u_gen->divr16u#1] -- register_copy
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// [123] phi (word) divr16u::rem#10 = (byte) 0 [phi:lin16u_gen->divr16u#2] -- vwuz1=vbuc1
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// [123] phi (word) divr16u::dividend#5 = (word) divr16u::dividend#1 [phi:lin16u_gen->divr16u#0] -- register_copy
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// [123] phi (word) divr16u::rem#10 = (byte) 0 [phi:lin16u_gen->divr16u#1] -- vwuz1=vbuc1
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lda #<0
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sta.z divr16u.rem
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lda #>0
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@ -3118,17 +3110,12 @@ lin16u_gen: {
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// [110] call divr16u
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// [123] phi from lin16u_gen::@3 to divr16u [phi:lin16u_gen::@3->divr16u]
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divr16u_from___b3:
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// [123] phi (word) divr16u::divisor#6 = (byte) $14-(byte) 1 [phi:lin16u_gen::@3->divr16u#0] -- vwuz1=vbuc1
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lda #<$14-1
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sta.z divr16u.divisor
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lda #>$14-1
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sta.z divr16u.divisor+1
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// [123] phi (word) divr16u::dividend#5 = (byte) 0 [phi:lin16u_gen::@3->divr16u#1] -- vwuz1=vbuc1
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// [123] phi (word) divr16u::dividend#5 = (byte) 0 [phi:lin16u_gen::@3->divr16u#0] -- vwuz1=vbuc1
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lda #<0
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sta.z divr16u.dividend
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lda #>0
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sta.z divr16u.dividend+1
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// [123] phi (word) divr16u::rem#10 = (word) divr16u::rem#4 [phi:lin16u_gen::@3->divr16u#2] -- register_copy
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// [123] phi (word) divr16u::rem#10 = (word) divr16u::rem#4 [phi:lin16u_gen::@3->divr16u#1] -- register_copy
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jsr divr16u
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// [111] (word) divr16u::return#3 ← (word) divr16u::return#0 -- vwuz1=vwuz2
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lda.z divr16u.return
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@ -3240,18 +3227,17 @@ lin16u_gen: {
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// Returns the quotient dividend/divisor.
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// The final remainder will be set into the global variable rem16u
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// Implemented using simple binary division
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// divr16u(word zp($1f) dividend, word zp($1b) divisor, word zp($1d) rem)
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// divr16u(word zp($1d) dividend, word zp($1b) rem)
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divr16u: {
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.label __1 = $39
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.label __2 = $3a
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.label rem = $1d
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.label dividend = $1f
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.label quotient = $21
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.label i = $23
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.label return = $21
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.label return_1 = $2b
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.label return_2 = $2f
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.label divisor = $1b
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.label __1 = $37
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.label __2 = $38
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.label rem = $1b
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.label dividend = $1d
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.label quotient = $1f
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.label i = $21
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.label return = $1f
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.label return_1 = $29
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.label return_2 = $2d
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// [124] phi from divr16u to divr16u::@1 [phi:divr16u->divr16u::@1]
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__b1_from_divr16u:
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// [124] phi (byte) divr16u::i#2 = (byte) 0 [phi:divr16u->divr16u::@1#0] -- vbuz1=vbuc1
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@ -3308,13 +3294,13 @@ divr16u: {
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// [132] (word) divr16u::quotient#1 ← (word) divr16u::quotient#3 << (byte) 1 -- vwuz1=vwuz1_rol_1
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asl.z quotient
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rol.z quotient+1
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// [133] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 -- vwuz1_lt_vwuz2_then_la1
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// [133] if((word) divr16u::rem#6<(byte) $14-(byte) 1) goto divr16u::@3 -- vwuz1_lt_vbuc1_then_la1
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lda.z rem+1
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cmp.z divisor+1
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cmp #>$14-1
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bcc __b3_from___b2
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bne !+
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lda.z rem
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cmp.z divisor
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cmp #<$14-1
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bcc __b3_from___b2
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!:
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jmp __b5
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@ -3325,13 +3311,13 @@ divr16u: {
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bne !+
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inc.z quotient+1
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!:
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// [135] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 -- vwuz1=vwuz1_minus_vwuz2
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// [135] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (byte) $14-(byte) 1 -- vwuz1=vwuz1_minus_vwuc1
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lda.z rem
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sec
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sbc.z divisor
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sbc #<$14-1
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sta.z rem
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lda.z rem+1
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sbc.z divisor+1
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sbc #>$14-1
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sta.z rem+1
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// [136] phi from divr16u::@2 divr16u::@5 to divr16u::@3 [phi:divr16u::@2/divr16u::@5->divr16u::@3]
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__b3_from___b2:
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@ -3400,10 +3386,10 @@ Statement [118] (word~) lin16u_gen::$6 ← > (dword) lin16u_gen::val#2 [ lin16u_
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Statement [119] *((word*) lin16u_gen::lintab#4) ← (word~) lin16u_gen::$6 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] ( main:2::lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { } main:2::lin16u_gen:7 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { } main:2::lin16u_gen:9 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { } ) always clobbers reg byte a reg byte y
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Statement [120] (dword) lin16u_gen::val#1 ← (dword) lin16u_gen::val#2 + (dword) lin16u_gen::step#0 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::lintab#4 lin16u_gen::val#1 ] ( main:2::lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::lintab#4 lin16u_gen::val#1 ] { } main:2::lin16u_gen:7 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::lintab#4 lin16u_gen::val#1 ] { } main:2::lin16u_gen:9 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::lintab#4 lin16u_gen::val#1 ] { } ) always clobbers reg byte a
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Statement [121] (word*) lin16u_gen::lintab#3 ← (word*) lin16u_gen::lintab#4 + (const byte) SIZEOF_WORD [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#1 lin16u_gen::lintab#3 ] ( main:2::lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#1 lin16u_gen::lintab#3 ] { } main:2::lin16u_gen:7 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#1 lin16u_gen::lintab#3 ] { } main:2::lin16u_gen:9 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#1 lin16u_gen::lintab#3 ] { } ) always clobbers reg byte a
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Statement [129] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::lin16u_gen:5::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:7::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:9::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:5::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:7::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:9::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } ) always clobbers reg byte a
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Removing always clobbered register reg byte a as potential for zp[1]:35 [ divr16u::i#2 divr16u::i#1 ]
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Statement [133] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::lin16u_gen:5::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:7::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:9::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:5::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:7::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:9::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } ) always clobbers reg byte a
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Statement [135] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::lin16u_gen:5::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:7::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:9::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:5::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:7::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:9::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } ) always clobbers reg byte a
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Statement [129] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte) 1 [ divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::lin16u_gen:5::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:7::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:9::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:5::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:7::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:9::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } ) always clobbers reg byte a
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Removing always clobbered register reg byte a as potential for zp[1]:33 [ divr16u::i#2 divr16u::i#1 ]
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Statement [133] if((word) divr16u::rem#6<(byte) $14-(byte) 1) goto divr16u::@3 [ divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::lin16u_gen:5::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:7::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:9::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:5::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:7::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:9::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } ) always clobbers reg byte a
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Statement [135] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (byte) $14-(byte) 1 [ divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::lin16u_gen:5::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:7::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:9::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:5::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:7::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:9::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } ) always clobbers reg byte a
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Statement [139] (word) rem16u#1 ← (word) divr16u::rem#11 [ divr16u::return#0 rem16u#1 ] ( main:2::lin16u_gen:5::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::return#0 rem16u#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:7::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::return#0 rem16u#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:9::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::return#0 rem16u#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:5::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::return#0 rem16u#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:7::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::return#0 rem16u#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:9::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::return#0 rem16u#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } ) always clobbers reg byte a
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Statement [28] (byte*) print_char_cursor#98 ← (byte*) print_line_cursor#1 [ print_char_cursor#98 print_line_cursor#1 ] ( main:2 [ print_char_cursor#98 print_line_cursor#1 ] { { print_char_cursor#87 = print_char_cursor#98 } } ) always clobbers reg byte a
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Statement [44] (byte*) print_char_cursor#102 ← (byte*) print_line_cursor#1 [ main::i#10 print_line_cursor#1 print_uchar::b#2 print_char_cursor#102 ] ( main:2 [ main::i#10 print_line_cursor#1 print_uchar::b#2 print_char_cursor#102 ] { { print_uchar::b#2 = print_uchar::b#3 main::i#10 } { print_char_cursor#102 = print_char_cursor#82 } } ) always clobbers reg byte a
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@ -3436,9 +3422,9 @@ Statement [118] (word~) lin16u_gen::$6 ← > (dword) lin16u_gen::val#2 [ lin16u_
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Statement [119] *((word*) lin16u_gen::lintab#4) ← (word~) lin16u_gen::$6 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] ( main:2::lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { } main:2::lin16u_gen:7 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { } main:2::lin16u_gen:9 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#2 lin16u_gen::lintab#4 ] { } ) always clobbers reg byte a reg byte y
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Statement [120] (dword) lin16u_gen::val#1 ← (dword) lin16u_gen::val#2 + (dword) lin16u_gen::step#0 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::lintab#4 lin16u_gen::val#1 ] ( main:2::lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::lintab#4 lin16u_gen::val#1 ] { } main:2::lin16u_gen:7 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::lintab#4 lin16u_gen::val#1 ] { } main:2::lin16u_gen:9 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::lintab#4 lin16u_gen::val#1 ] { } ) always clobbers reg byte a
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Statement [121] (word*) lin16u_gen::lintab#3 ← (word*) lin16u_gen::lintab#4 + (const byte) SIZEOF_WORD [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#1 lin16u_gen::lintab#3 ] ( main:2::lin16u_gen:5 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#1 lin16u_gen::lintab#3 ] { } main:2::lin16u_gen:7 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#1 lin16u_gen::lintab#3 ] { } main:2::lin16u_gen:9 [ lin16u_gen::step#0 lin16u_gen::i#2 lin16u_gen::val#1 lin16u_gen::lintab#3 ] { } ) always clobbers reg byte a
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Statement [129] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::lin16u_gen:5::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:7::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:9::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:5::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:7::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:9::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } ) always clobbers reg byte a
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Statement [133] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::lin16u_gen:5::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:7::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:9::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:5::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:7::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:9::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } ) always clobbers reg byte a
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Statement [135] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::lin16u_gen:5::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:7::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:9::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:5::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:7::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:9::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } ) always clobbers reg byte a
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Statement [129] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte) 1 [ divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::lin16u_gen:5::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:7::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:9::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:5::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:7::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:9::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } ) always clobbers reg byte a
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Statement [133] if((word) divr16u::rem#6<(byte) $14-(byte) 1) goto divr16u::@3 [ divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::lin16u_gen:5::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:7::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:9::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:5::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:7::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:9::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } ) always clobbers reg byte a
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Statement [135] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (byte) $14-(byte) 1 [ divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::lin16u_gen:5::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:7::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:9::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:5::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:7::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:9::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } ) always clobbers reg byte a
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Statement [139] (word) rem16u#1 ← (word) divr16u::rem#11 [ divr16u::return#0 rem16u#1 ] ( main:2::lin16u_gen:5::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::return#0 rem16u#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:7::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::return#0 rem16u#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:9::divr16u:106 [ lin16u_gen::min#3 lin16u_gen::lintab#6 divr16u::return#0 rem16u#1 ] { { divr16u::dividend#1 = divr16u::dividend#5 lin16u_gen::ampl#0 } { divr16u::return#0 = divr16u::return#2 } } main:2::lin16u_gen:5::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::return#0 rem16u#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:7::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::return#0 rem16u#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } main:2::lin16u_gen:9::divr16u:110 [ lin16u_gen::min#3 lin16u_gen::lintab#6 lin16u_gen::stepi#0 divr16u::return#0 rem16u#1 ] { { divr16u::rem#10 = divr16u::rem#4 rem16u#1 } { divr16u::return#0 = divr16u::return#3 } } ) always clobbers reg byte a
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Potential registers zp[1]:2 [ main::i#10 main::i#1 ] : zp[1]:2 , reg byte x ,
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Potential registers zp[2]:3 [ print_line_cursor#11 print_line_cursor#21 print_line_cursor#1 ] : zp[2]:3 ,
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@ -3453,65 +3439,63 @@ Potential registers zp[2]:17 [ lin16u_gen::min#3 ] : zp[2]:17 ,
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Potential registers zp[2]:19 [ lin16u_gen::i#2 lin16u_gen::i#1 ] : zp[2]:19 ,
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Potential registers zp[4]:21 [ lin16u_gen::val#2 lin16u_gen::val#1 lin16u_gen::val#0 ] : zp[4]:21 ,
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Potential registers zp[2]:25 [ lin16u_gen::lintab#4 lin16u_gen::lintab#3 lin16u_gen::lintab#6 ] : zp[2]:25 ,
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Potential registers zp[2]:27 [ divr16u::divisor#6 ] : zp[2]:27 ,
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Potential registers zp[2]:29 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] : zp[2]:29 ,
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Potential registers zp[2]:31 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#1 divr16u::dividend#0 ] : zp[2]:31 ,
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Potential registers zp[2]:33 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] : zp[2]:33 ,
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Potential registers zp[1]:35 [ divr16u::i#2 divr16u::i#1 ] : zp[1]:35 , reg byte x , reg byte y ,
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Potential registers zp[1]:36 [ main::$27 ] : zp[1]:36 , reg byte a , reg byte x , reg byte y ,
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Potential registers zp[1]:37 [ main::$28 ] : zp[1]:37 , reg byte a , reg byte x , reg byte y ,
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Potential registers zp[1]:38 [ main::$29 ] : zp[1]:38 , reg byte a , reg byte x , reg byte y ,
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Potential registers zp[1]:39 [ print_uchar::$0 ] : zp[1]:39 , reg byte a , reg byte x , reg byte y ,
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Potential registers zp[1]:40 [ print_uchar::$2 ] : zp[1]:40 , reg byte a , reg byte x , reg byte y ,
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Potential registers zp[2]:41 [ lin16u_gen::ampl#0 ] : zp[2]:41 ,
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Potential registers zp[2]:43 [ divr16u::return#2 ] : zp[2]:43 ,
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Potential registers zp[2]:45 [ lin16u_gen::stepi#0 ] : zp[2]:45 ,
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Potential registers zp[2]:47 [ divr16u::return#3 ] : zp[2]:47 ,
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Potential registers zp[2]:49 [ lin16u_gen::stepf#0 ] : zp[2]:49 ,
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Potential registers zp[4]:51 [ lin16u_gen::step#0 ] : zp[4]:51 ,
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Potential registers zp[2]:55 [ lin16u_gen::$6 ] : zp[2]:55 ,
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Potential registers zp[1]:57 [ divr16u::$1 ] : zp[1]:57 , reg byte a , reg byte x , reg byte y ,
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Potential registers zp[1]:58 [ divr16u::$2 ] : zp[1]:58 , reg byte a , reg byte x , reg byte y ,
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Potential registers zp[2]:59 [ rem16u#1 ] : zp[2]:59 ,
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Potential registers zp[2]:27 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] : zp[2]:27 ,
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Potential registers zp[2]:29 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#1 divr16u::dividend#0 ] : zp[2]:29 ,
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Potential registers zp[2]:31 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] : zp[2]:31 ,
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Potential registers zp[1]:33 [ divr16u::i#2 divr16u::i#1 ] : zp[1]:33 , reg byte x , reg byte y ,
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Potential registers zp[1]:34 [ main::$27 ] : zp[1]:34 , reg byte a , reg byte x , reg byte y ,
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Potential registers zp[1]:35 [ main::$28 ] : zp[1]:35 , reg byte a , reg byte x , reg byte y ,
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Potential registers zp[1]:36 [ main::$29 ] : zp[1]:36 , reg byte a , reg byte x , reg byte y ,
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Potential registers zp[1]:37 [ print_uchar::$0 ] : zp[1]:37 , reg byte a , reg byte x , reg byte y ,
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Potential registers zp[1]:38 [ print_uchar::$2 ] : zp[1]:38 , reg byte a , reg byte x , reg byte y ,
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Potential registers zp[2]:39 [ lin16u_gen::ampl#0 ] : zp[2]:39 ,
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Potential registers zp[2]:41 [ divr16u::return#2 ] : zp[2]:41 ,
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Potential registers zp[2]:43 [ lin16u_gen::stepi#0 ] : zp[2]:43 ,
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Potential registers zp[2]:45 [ divr16u::return#3 ] : zp[2]:45 ,
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Potential registers zp[2]:47 [ lin16u_gen::stepf#0 ] : zp[2]:47 ,
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Potential registers zp[4]:49 [ lin16u_gen::step#0 ] : zp[4]:49 ,
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Potential registers zp[2]:53 [ lin16u_gen::$6 ] : zp[2]:53 ,
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Potential registers zp[1]:55 [ divr16u::$1 ] : zp[1]:55 , reg byte a , reg byte x , reg byte y ,
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Potential registers zp[1]:56 [ divr16u::$2 ] : zp[1]:56 , reg byte a , reg byte x , reg byte y ,
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Potential registers zp[2]:57 [ rem16u#1 ] : zp[2]:57 ,
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REGISTER UPLIFT SCOPES
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Uplift Scope [print_char] 1,360,010: zp[1]:8 [ print_char::ch#3 print_char::ch#0 print_char::ch#1 print_char::ch#2 ]
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Uplift Scope [] 1,105,841.04: zp[2]:9 [ print_char_cursor#87 print_char_cursor#50 print_char_cursor#82 print_char_cursor#102 print_char_cursor#2 print_char_cursor#11 print_char_cursor#98 ] 209,621.67: zp[2]:3 [ print_line_cursor#11 print_line_cursor#21 print_line_cursor#1 ] 220.4: zp[2]:59 [ rem16u#1 ]
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Uplift Scope [] 1,105,841.04: zp[2]:9 [ print_char_cursor#87 print_char_cursor#50 print_char_cursor#82 print_char_cursor#102 print_char_cursor#2 print_char_cursor#11 print_char_cursor#98 ] 209,621.67: zp[2]:3 [ print_line_cursor#11 print_line_cursor#21 print_line_cursor#1 ] 220.4: zp[2]:57 [ rem16u#1 ]
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Uplift Scope [print_str] 301,254.25: zp[2]:11 [ print_str::str#10 print_str::str#13 print_str::str#0 ]
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Uplift Scope [divr16u] 90,147.42: zp[2]:29 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] 31,817.75: zp[2]:33 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] 20,002: zp[1]:57 [ divr16u::$1 ] 20,002: zp[1]:58 [ divr16u::$2 ] 16,540.12: zp[1]:35 [ divr16u::i#2 divr16u::i#1 ] 8,233.39: zp[2]:31 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#1 divr16u::dividend#0 ] 1,250.12: zp[2]:27 [ divr16u::divisor#6 ] 202: zp[2]:43 [ divr16u::return#2 ] 202: zp[2]:47 [ divr16u::return#3 ]
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Uplift Scope [print_uchar] 20,002: zp[1]:39 [ print_uchar::$0 ] 20,002: zp[1]:40 [ print_uchar::$2 ] 9,631.25: zp[1]:7 [ print_uchar::b#3 print_uchar::b#2 print_uchar::b#0 print_uchar::b#1 ]
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Uplift Scope [divr16u] 90,147.42: zp[2]:27 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] 31,817.75: zp[2]:31 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] 20,002: zp[1]:55 [ divr16u::$1 ] 20,002: zp[1]:56 [ divr16u::$2 ] 16,540.12: zp[1]:33 [ divr16u::i#2 divr16u::i#1 ] 8,233.39: zp[2]:29 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#1 divr16u::dividend#0 ] 202: zp[2]:41 [ divr16u::return#2 ] 202: zp[2]:45 [ divr16u::return#3 ]
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Uplift Scope [print_uchar] 20,002: zp[1]:37 [ print_uchar::$0 ] 20,002: zp[1]:38 [ print_uchar::$2 ] 9,631.25: zp[1]:7 [ print_uchar::b#3 print_uchar::b#2 print_uchar::b#0 print_uchar::b#1 ]
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Uplift Scope [memset] 33,336.67: zp[2]:13 [ memset::dst#2 memset::dst#1 ]
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Uplift Scope [lin16u_gen] 2,502.5: zp[2]:19 [ lin16u_gen::i#2 lin16u_gen::i#1 ] 2,002: zp[2]:55 [ lin16u_gen::$6 ] 1,645.33: zp[4]:21 [ lin16u_gen::val#2 lin16u_gen::val#1 lin16u_gen::val#0 ] 1,630.22: zp[2]:25 [ lin16u_gen::lintab#4 lin16u_gen::lintab#3 lin16u_gen::lintab#6 ] 202: zp[2]:41 [ lin16u_gen::ampl#0 ] 202: zp[2]:49 [ lin16u_gen::stepf#0 ] 122.44: zp[4]:51 [ lin16u_gen::step#0 ] 101: zp[2]:15 [ lin16u_gen::max#3 ] 40.4: zp[2]:45 [ lin16u_gen::stepi#0 ] 18.36: zp[2]:17 [ lin16u_gen::min#3 ]
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Uplift Scope [lin16u_gen] 2,502.5: zp[2]:19 [ lin16u_gen::i#2 lin16u_gen::i#1 ] 2,002: zp[2]:53 [ lin16u_gen::$6 ] 1,645.33: zp[4]:21 [ lin16u_gen::val#2 lin16u_gen::val#1 lin16u_gen::val#0 ] 1,630.22: zp[2]:25 [ lin16u_gen::lintab#4 lin16u_gen::lintab#3 lin16u_gen::lintab#6 ] 202: zp[2]:39 [ lin16u_gen::ampl#0 ] 202: zp[2]:47 [ lin16u_gen::stepf#0 ] 122.44: zp[4]:49 [ lin16u_gen::step#0 ] 101: zp[2]:15 [ lin16u_gen::max#3 ] 40.4: zp[2]:43 [ lin16u_gen::stepi#0 ] 18.36: zp[2]:17 [ lin16u_gen::min#3 ]
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Uplift Scope [print_uint] 1,374.33: zp[2]:5 [ print_uint::w#10 print_uint::w#3 print_uint::w#4 print_uint::w#5 ]
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Uplift Scope [main] 234.14: zp[1]:2 [ main::i#10 main::i#1 ] 202: zp[1]:36 [ main::$27 ] 202: zp[1]:37 [ main::$28 ] 202: zp[1]:38 [ main::$29 ]
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Uplift Scope [main] 234.14: zp[1]:2 [ main::i#10 main::i#1 ] 202: zp[1]:34 [ main::$27 ] 202: zp[1]:35 [ main::$28 ] 202: zp[1]:36 [ main::$29 ]
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Uplift Scope [RADIX]
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Uplift Scope [print_ln]
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Uplift Scope [print_cls]
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Uplifting [print_char] best 14194 combination reg byte a [ print_char::ch#3 print_char::ch#0 print_char::ch#1 print_char::ch#2 ]
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Uplifting [] best 14194 combination zp[2]:9 [ print_char_cursor#87 print_char_cursor#50 print_char_cursor#82 print_char_cursor#102 print_char_cursor#2 print_char_cursor#11 print_char_cursor#98 ] zp[2]:3 [ print_line_cursor#11 print_line_cursor#21 print_line_cursor#1 ] zp[2]:59 [ rem16u#1 ]
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Uplifting [print_str] best 14194 combination zp[2]:11 [ print_str::str#10 print_str::str#13 print_str::str#0 ]
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Uplifting [divr16u] best 13984 combination zp[2]:29 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] zp[2]:33 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] reg byte a [ divr16u::$1 ] reg byte a [ divr16u::$2 ] reg byte x [ divr16u::i#2 divr16u::i#1 ] zp[2]:31 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#1 divr16u::dividend#0 ] zp[2]:27 [ divr16u::divisor#6 ] zp[2]:43 [ divr16u::return#2 ] zp[2]:47 [ divr16u::return#3 ]
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Uplifting [print_uchar] best 13936 combination reg byte a [ print_uchar::$0 ] reg byte x [ print_uchar::$2 ] reg byte x [ print_uchar::b#3 print_uchar::b#2 print_uchar::b#0 print_uchar::b#1 ]
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Uplifting [memset] best 13936 combination zp[2]:13 [ memset::dst#2 memset::dst#1 ]
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Uplifting [lin16u_gen] best 13936 combination zp[2]:19 [ lin16u_gen::i#2 lin16u_gen::i#1 ] zp[2]:55 [ lin16u_gen::$6 ] zp[4]:21 [ lin16u_gen::val#2 lin16u_gen::val#1 lin16u_gen::val#0 ] zp[2]:25 [ lin16u_gen::lintab#4 lin16u_gen::lintab#3 lin16u_gen::lintab#6 ] zp[2]:41 [ lin16u_gen::ampl#0 ] zp[2]:49 [ lin16u_gen::stepf#0 ] zp[4]:51 [ lin16u_gen::step#0 ] zp[2]:15 [ lin16u_gen::max#3 ] zp[2]:45 [ lin16u_gen::stepi#0 ] zp[2]:17 [ lin16u_gen::min#3 ]
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Uplifting [print_uint] best 13936 combination zp[2]:5 [ print_uint::w#10 print_uint::w#3 print_uint::w#4 print_uint::w#5 ]
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Uplifting [main] best 13816 combination zp[1]:2 [ main::i#10 main::i#1 ] reg byte a [ main::$27 ] reg byte a [ main::$28 ] reg byte a [ main::$29 ]
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Uplifting [print_char] best 14134 combination reg byte a [ print_char::ch#3 print_char::ch#0 print_char::ch#1 print_char::ch#2 ]
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Uplifting [] best 14134 combination zp[2]:9 [ print_char_cursor#87 print_char_cursor#50 print_char_cursor#82 print_char_cursor#102 print_char_cursor#2 print_char_cursor#11 print_char_cursor#98 ] zp[2]:3 [ print_line_cursor#11 print_line_cursor#21 print_line_cursor#1 ] zp[2]:57 [ rem16u#1 ]
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Uplifting [print_str] best 14134 combination zp[2]:11 [ print_str::str#10 print_str::str#13 print_str::str#0 ]
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Uplifting [divr16u] best 13924 combination zp[2]:27 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] zp[2]:31 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] reg byte a [ divr16u::$1 ] reg byte a [ divr16u::$2 ] reg byte x [ divr16u::i#2 divr16u::i#1 ] zp[2]:29 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#1 divr16u::dividend#0 ] zp[2]:41 [ divr16u::return#2 ] zp[2]:45 [ divr16u::return#3 ]
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Uplifting [print_uchar] best 13876 combination reg byte a [ print_uchar::$0 ] reg byte x [ print_uchar::$2 ] reg byte x [ print_uchar::b#3 print_uchar::b#2 print_uchar::b#0 print_uchar::b#1 ]
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Uplifting [memset] best 13876 combination zp[2]:13 [ memset::dst#2 memset::dst#1 ]
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Uplifting [lin16u_gen] best 13876 combination zp[2]:19 [ lin16u_gen::i#2 lin16u_gen::i#1 ] zp[2]:53 [ lin16u_gen::$6 ] zp[4]:21 [ lin16u_gen::val#2 lin16u_gen::val#1 lin16u_gen::val#0 ] zp[2]:25 [ lin16u_gen::lintab#4 lin16u_gen::lintab#3 lin16u_gen::lintab#6 ] zp[2]:39 [ lin16u_gen::ampl#0 ] zp[2]:47 [ lin16u_gen::stepf#0 ] zp[4]:49 [ lin16u_gen::step#0 ] zp[2]:15 [ lin16u_gen::max#3 ] zp[2]:43 [ lin16u_gen::stepi#0 ] zp[2]:17 [ lin16u_gen::min#3 ]
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Uplifting [print_uint] best 13876 combination zp[2]:5 [ print_uint::w#10 print_uint::w#3 print_uint::w#4 print_uint::w#5 ]
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Uplifting [main] best 13756 combination zp[1]:2 [ main::i#10 main::i#1 ] reg byte a [ main::$27 ] reg byte a [ main::$28 ] reg byte a [ main::$29 ]
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Limited combination testing to 100 combinations of 128 possible.
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Uplifting [RADIX] best 13816 combination
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Uplifting [print_ln] best 13816 combination
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Uplifting [print_cls] best 13816 combination
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Uplifting [RADIX] best 13756 combination
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Uplifting [print_ln] best 13756 combination
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Uplifting [print_cls] best 13756 combination
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Attempting to uplift remaining variables inzp[1]:2 [ main::i#10 main::i#1 ]
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Uplifting [main] best 13816 combination zp[1]:2 [ main::i#10 main::i#1 ]
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Coalescing zero page register [ zp[2]:29 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] ] with [ zp[2]:59 [ rem16u#1 ] ] - score: 2
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Coalescing zero page register [ zp[2]:15 [ lin16u_gen::max#3 ] ] with [ zp[2]:41 [ lin16u_gen::ampl#0 ] ] - score: 1
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Coalescing zero page register [ zp[2]:33 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] ] with [ zp[2]:43 [ divr16u::return#2 ] ] - score: 1
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Coalescing zero page register [ zp[2]:33 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 ] ] with [ zp[2]:47 [ divr16u::return#3 ] ] - score: 1
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Coalescing zero page register [ zp[2]:15 [ lin16u_gen::max#3 lin16u_gen::ampl#0 ] ] with [ zp[2]:31 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#1 divr16u::dividend#0 ] ] - score: 1
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Coalescing zero page register [ zp[2]:33 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 ] ] with [ zp[2]:49 [ lin16u_gen::stepf#0 ] ] - score: 1
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Uplifting [main] best 13756 combination zp[1]:2 [ main::i#10 main::i#1 ]
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Coalescing zero page register [ zp[2]:27 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] ] with [ zp[2]:57 [ rem16u#1 ] ] - score: 2
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Coalescing zero page register [ zp[2]:15 [ lin16u_gen::max#3 ] ] with [ zp[2]:39 [ lin16u_gen::ampl#0 ] ] - score: 1
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Coalescing zero page register [ zp[2]:31 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] ] with [ zp[2]:41 [ divr16u::return#2 ] ] - score: 1
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Coalescing zero page register [ zp[2]:31 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 ] ] with [ zp[2]:45 [ divr16u::return#3 ] ] - score: 1
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Coalescing zero page register [ zp[2]:15 [ lin16u_gen::max#3 lin16u_gen::ampl#0 ] ] with [ zp[2]:29 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#1 divr16u::dividend#0 ] ] - score: 1
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Coalescing zero page register [ zp[2]:31 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 ] ] with [ zp[2]:47 [ lin16u_gen::stepf#0 ] ] - score: 1
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Coalescing zero page register [ zp[2]:11 [ print_str::str#10 print_str::str#13 print_str::str#0 ] ] with [ zp[2]:5 [ print_uint::w#10 print_uint::w#3 print_uint::w#4 print_uint::w#5 ] ]
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Coalescing zero page register [ zp[2]:15 [ lin16u_gen::max#3 lin16u_gen::ampl#0 divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#1 divr16u::dividend#0 ] ] with [ zp[2]:13 [ memset::dst#2 memset::dst#1 ] ]
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Coalescing zero page register [ zp[2]:55 [ lin16u_gen::$6 ] ] with [ zp[2]:27 [ divr16u::divisor#6 ] ]
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Coalescing zero page register [ zp[2]:15 [ lin16u_gen::max#3 lin16u_gen::ampl#0 divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#1 divr16u::dividend#0 memset::dst#2 memset::dst#1 ] ] with [ zp[2]:11 [ print_str::str#10 print_str::str#13 print_str::str#0 print_uint::w#10 print_uint::w#3 print_uint::w#4 print_uint::w#5 ] ]
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Allocated (was zp[2]:9) zp[2]:5 [ print_char_cursor#87 print_char_cursor#50 print_char_cursor#82 print_char_cursor#102 print_char_cursor#2 print_char_cursor#11 print_char_cursor#98 ]
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Allocated (was zp[2]:15) zp[2]:7 [ lin16u_gen::max#3 lin16u_gen::ampl#0 divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#1 divr16u::dividend#0 memset::dst#2 memset::dst#1 print_str::str#10 print_str::str#13 print_str::str#0 print_uint::w#10 print_uint::w#3 print_uint::w#4 print_uint::w#5 ]
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@ -3519,11 +3503,11 @@ Allocated (was zp[2]:17) zp[2]:9 [ lin16u_gen::min#3 ]
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Allocated (was zp[2]:19) zp[2]:11 [ lin16u_gen::i#2 lin16u_gen::i#1 ]
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Allocated (was zp[4]:21) zp[4]:13 [ lin16u_gen::val#2 lin16u_gen::val#1 lin16u_gen::val#0 ]
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Allocated (was zp[2]:25) zp[2]:17 [ lin16u_gen::lintab#4 lin16u_gen::lintab#3 lin16u_gen::lintab#6 ]
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Allocated (was zp[2]:29) zp[2]:19 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 rem16u#1 ]
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Allocated (was zp[2]:33) zp[2]:21 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 lin16u_gen::stepf#0 ]
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Allocated (was zp[2]:45) zp[2]:23 [ lin16u_gen::stepi#0 ]
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Allocated (was zp[4]:51) zp[4]:25 [ lin16u_gen::step#0 ]
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Allocated (was zp[2]:55) zp[2]:29 [ lin16u_gen::$6 divr16u::divisor#6 ]
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Allocated (was zp[2]:27) zp[2]:19 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 rem16u#1 ]
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Allocated (was zp[2]:31) zp[2]:21 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 lin16u_gen::stepf#0 ]
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Allocated (was zp[2]:43) zp[2]:23 [ lin16u_gen::stepi#0 ]
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Allocated (was zp[4]:49) zp[4]:25 [ lin16u_gen::step#0 ]
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Allocated (was zp[2]:53) zp[2]:29 [ lin16u_gen::$6 ]
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ASSEMBLER BEFORE OPTIMIZATION
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// File Comments
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@ -4246,13 +4230,8 @@ lin16u_gen: {
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// [106] call divr16u
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// [123] phi from lin16u_gen to divr16u [phi:lin16u_gen->divr16u]
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divr16u_from_lin16u_gen:
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// [123] phi (word) divr16u::divisor#6 = (byte) $14-(byte) 1 [phi:lin16u_gen->divr16u#0] -- vwuz1=vbuc1
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lda #<$14-1
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sta.z divr16u.divisor
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lda #>$14-1
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sta.z divr16u.divisor+1
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// [123] phi (word) divr16u::dividend#5 = (word) divr16u::dividend#1 [phi:lin16u_gen->divr16u#1] -- register_copy
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// [123] phi (word) divr16u::rem#10 = (byte) 0 [phi:lin16u_gen->divr16u#2] -- vwuz1=vbuc1
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// [123] phi (word) divr16u::dividend#5 = (word) divr16u::dividend#1 [phi:lin16u_gen->divr16u#0] -- register_copy
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// [123] phi (word) divr16u::rem#10 = (byte) 0 [phi:lin16u_gen->divr16u#1] -- vwuz1=vbuc1
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lda #<0
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sta.z divr16u.rem
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lda #>0
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@ -4271,17 +4250,12 @@ lin16u_gen: {
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// [110] call divr16u
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// [123] phi from lin16u_gen::@3 to divr16u [phi:lin16u_gen::@3->divr16u]
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divr16u_from___b3:
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// [123] phi (word) divr16u::divisor#6 = (byte) $14-(byte) 1 [phi:lin16u_gen::@3->divr16u#0] -- vwuz1=vbuc1
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lda #<$14-1
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sta.z divr16u.divisor
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lda #>$14-1
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sta.z divr16u.divisor+1
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// [123] phi (word) divr16u::dividend#5 = (byte) 0 [phi:lin16u_gen::@3->divr16u#1] -- vwuz1=vbuc1
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// [123] phi (word) divr16u::dividend#5 = (byte) 0 [phi:lin16u_gen::@3->divr16u#0] -- vwuz1=vbuc1
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lda #<0
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sta.z divr16u.dividend
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lda #>0
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sta.z divr16u.dividend+1
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// [123] phi (word) divr16u::rem#10 = (word) divr16u::rem#4 [phi:lin16u_gen::@3->divr16u#2] -- register_copy
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// [123] phi (word) divr16u::rem#10 = (word) divr16u::rem#4 [phi:lin16u_gen::@3->divr16u#1] -- register_copy
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jsr divr16u
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// [111] (word) divr16u::return#3 ← (word) divr16u::return#0
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jmp __b4
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@ -4385,13 +4359,12 @@ lin16u_gen: {
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// Returns the quotient dividend/divisor.
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// The final remainder will be set into the global variable rem16u
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// Implemented using simple binary division
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// divr16u(word zp(7) dividend, word zp($1d) divisor, word zp($13) rem)
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// divr16u(word zp(7) dividend, word zp($13) rem)
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divr16u: {
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.label rem = $13
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.label dividend = 7
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.label quotient = $15
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.label return = $15
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.label divisor = $1d
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// [124] phi from divr16u to divr16u::@1 [phi:divr16u->divr16u::@1]
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__b1_from_divr16u:
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// [124] phi (byte) divr16u::i#2 = (byte) 0 [phi:divr16u->divr16u::@1#0] -- vbuxx=vbuc1
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@ -4443,13 +4416,13 @@ divr16u: {
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// [132] (word) divr16u::quotient#1 ← (word) divr16u::quotient#3 << (byte) 1 -- vwuz1=vwuz1_rol_1
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asl.z quotient
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rol.z quotient+1
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// [133] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 -- vwuz1_lt_vwuz2_then_la1
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// [133] if((word) divr16u::rem#6<(byte) $14-(byte) 1) goto divr16u::@3 -- vwuz1_lt_vbuc1_then_la1
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lda.z rem+1
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cmp.z divisor+1
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cmp #>$14-1
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bcc __b3_from___b2
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bne !+
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lda.z rem
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cmp.z divisor
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cmp #<$14-1
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bcc __b3_from___b2
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!:
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jmp __b5
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@ -4460,13 +4433,13 @@ divr16u: {
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bne !+
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inc.z quotient+1
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!:
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// [135] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 -- vwuz1=vwuz1_minus_vwuz2
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// [135] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (byte) $14-(byte) 1 -- vwuz1=vwuz1_minus_vwuc1
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lda.z rem
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sec
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sbc.z divisor
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sbc #<$14-1
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sta.z rem
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lda.z rem+1
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sbc.z divisor+1
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sbc #>$14-1
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sta.z rem+1
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// [136] phi from divr16u::@2 divr16u::@5 to divr16u::@3 [phi:divr16u::@2/divr16u::@5->divr16u::@3]
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__b3_from___b2:
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@ -4718,7 +4691,6 @@ FINAL SYMBOL TABLE
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(word) divr16u::dividend#3 dividend zp[2]:7 4429.142857142857
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(word) divr16u::dividend#5 dividend zp[2]:7 1102.0
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(word) divr16u::divisor
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(word) divr16u::divisor#6 divisor zp[2]:29 1250.125
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(byte) divr16u::i
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(byte) divr16u::i#1 reg byte x 15001.5
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(byte) divr16u::i#2 reg byte x 1538.6153846153845
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@ -4902,13 +4874,13 @@ reg byte a [ print_uchar::$0 ]
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reg byte x [ print_uchar::$2 ]
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zp[2]:23 [ lin16u_gen::stepi#0 ]
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zp[4]:25 [ lin16u_gen::step#0 ]
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zp[2]:29 [ lin16u_gen::$6 divr16u::divisor#6 ]
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zp[2]:29 [ lin16u_gen::$6 ]
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reg byte a [ divr16u::$1 ]
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reg byte a [ divr16u::$2 ]
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FINAL ASSEMBLER
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Score: 11879
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Score: 11819
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// File Comments
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|
|
// Linear table generator
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@ -5538,13 +5510,8 @@ lin16u_gen: {
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// [105] (word) divr16u::dividend#1 ← (word) lin16u_gen::ampl#0
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// [106] call divr16u
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// [123] phi from lin16u_gen to divr16u [phi:lin16u_gen->divr16u]
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// [123] phi (word) divr16u::divisor#6 = (byte) $14-(byte) 1 [phi:lin16u_gen->divr16u#0] -- vwuz1=vbuc1
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lda #<$14-1
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sta.z divr16u.divisor
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lda #>$14-1
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sta.z divr16u.divisor+1
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// [123] phi (word) divr16u::dividend#5 = (word) divr16u::dividend#1 [phi:lin16u_gen->divr16u#1] -- register_copy
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// [123] phi (word) divr16u::rem#10 = (byte) 0 [phi:lin16u_gen->divr16u#2] -- vwuz1=vbuc1
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// [123] phi (word) divr16u::dividend#5 = (word) divr16u::dividend#1 [phi:lin16u_gen->divr16u#0] -- register_copy
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// [123] phi (word) divr16u::rem#10 = (byte) 0 [phi:lin16u_gen->divr16u#1] -- vwuz1=vbuc1
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lda #<0
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sta.z divr16u.rem
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sta.z divr16u.rem+1
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@ -5562,16 +5529,11 @@ lin16u_gen: {
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// [109] (word) divr16u::rem#4 ← (word) rem16u#1
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// [110] call divr16u
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// [123] phi from lin16u_gen::@3 to divr16u [phi:lin16u_gen::@3->divr16u]
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// [123] phi (word) divr16u::divisor#6 = (byte) $14-(byte) 1 [phi:lin16u_gen::@3->divr16u#0] -- vwuz1=vbuc1
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lda #<$14-1
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sta.z divr16u.divisor
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lda #>$14-1
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sta.z divr16u.divisor+1
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// [123] phi (word) divr16u::dividend#5 = (byte) 0 [phi:lin16u_gen::@3->divr16u#1] -- vwuz1=vbuc1
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// [123] phi (word) divr16u::dividend#5 = (byte) 0 [phi:lin16u_gen::@3->divr16u#0] -- vwuz1=vbuc1
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lda #<0
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sta.z divr16u.dividend
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sta.z divr16u.dividend+1
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// [123] phi (word) divr16u::rem#10 = (word) divr16u::rem#4 [phi:lin16u_gen::@3->divr16u#2] -- register_copy
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// [123] phi (word) divr16u::rem#10 = (word) divr16u::rem#4 [phi:lin16u_gen::@3->divr16u#1] -- register_copy
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jsr divr16u
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// divr16u(0, length-1, rem16u)
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// [111] (word) divr16u::return#3 ← (word) divr16u::return#0
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@ -5677,13 +5639,12 @@ lin16u_gen: {
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// Returns the quotient dividend/divisor.
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|
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|
|
// The final remainder will be set into the global variable rem16u
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|
|
|
|
// Implemented using simple binary division
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|
|
|
|
// divr16u(word zp(7) dividend, word zp($1d) divisor, word zp($13) rem)
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|
|
// divr16u(word zp(7) dividend, word zp($13) rem)
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|
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divr16u: {
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|
|
|
.label rem = $13
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|
|
.label dividend = 7
|
|
|
|
|
.label quotient = $15
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|
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|
|
.label return = $15
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|
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|
|
.label divisor = $1d
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|
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|
|
// [124] phi from divr16u to divr16u::@1 [phi:divr16u->divr16u::@1]
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// [124] phi (byte) divr16u::i#2 = (byte) 0 [phi:divr16u->divr16u::@1#0] -- vbuxx=vbuc1
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|
|
ldx #0
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|
@ -5733,13 +5694,13 @@ divr16u: {
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asl.z quotient
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rol.z quotient+1
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// if(rem>=divisor)
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// [133] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 -- vwuz1_lt_vwuz2_then_la1
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// [133] if((word) divr16u::rem#6<(byte) $14-(byte) 1) goto divr16u::@3 -- vwuz1_lt_vbuc1_then_la1
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|
lda.z rem+1
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|
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|
cmp.z divisor+1
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|
|
|
|
cmp #>$14-1
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|
|
bcc __b3
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|
|
bne !+
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|
lda.z rem
|
|
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|
|
cmp.z divisor
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|
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|
|
cmp #<$14-1
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|
|
bcc __b3
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|
|
|
|
!:
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|
// divr16u::@5
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|
@ -5750,13 +5711,13 @@ divr16u: {
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inc.z quotient+1
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|
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|
!:
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|
// rem = rem - divisor
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|
// [135] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 -- vwuz1=vwuz1_minus_vwuz2
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// [135] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (byte) $14-(byte) 1 -- vwuz1=vwuz1_minus_vwuc1
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|
|
lda.z rem
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sec
|
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sbc.z divisor
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|
sbc #<$14-1
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|
sta.z rem
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|
lda.z rem+1
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|
sbc.z divisor+1
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|
sbc #>$14-1
|
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|
|
sta.z rem+1
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// [136] phi from divr16u::@2 divr16u::@5 to divr16u::@3 [phi:divr16u::@2/divr16u::@5->divr16u::@3]
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// [136] phi (word) divr16u::return#0 = (word) divr16u::quotient#1 [phi:divr16u::@2/divr16u::@5->divr16u::@3#0] -- register_copy
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