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Working on CPU model.

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This commit is contained in:
jespergravgaard 2020-07-27 13:50:21 +02:00
parent 21a6e60eed
commit a8b5929adf
4 changed files with 334 additions and 3 deletions
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69
src/main/java/dk/camelot64/cpufamily6502/AsmCpu.java Normal file
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@ -0,0 +1,69 @@
package dk.camelot64.cpufamily6502;
import java.util.*;
/**
* A 6502 family CPU. The CPU has an instruction set.
*/
public class AsmCpu {
/** The CPU name. */
private final String name;
/** All opcodes in the instruction set. */
private final List<AsmOpcode> allOpcodes;
/** Maps mnemonic_addressingMode to the instruction opcode */
private final Map<String, AsmOpcode> opcodesByMnemonicAddrMode;
public AsmCpu(String name) {
this.name = name;
this.allOpcodes = new ArrayList<>();
this.opcodesByMnemonicAddrMode = new LinkedHashMap<>();
}
public AsmCpu(String name, AsmCpu basedOn) {
this.name = name;
this.allOpcodes = new ArrayList<>();
this.opcodesByMnemonicAddrMode = new LinkedHashMap<>();
for(AsmOpcode opcode : basedOn.allOpcodes) {
addOpcode(opcode);
}
}
/**
* Get a specific instruction opcode form the instruction set
*
* @param mnemonic The mnemonic
* @param addressingMode The addressing mode
* @return The opcode, if is exists. Null if the instruction set does not have the opcode.
*/
private AsmOpcode getOpcode(String mnemonic, AsmAddressingMode addressingMode) {
String key = mnemonic.toLowerCase() + "_" + addressingMode.getName();
return opcodesByMnemonicAddrMode.get(key);
}
/**
* Add an instruction opcode to the instruction set.
*
* @param opcode The numeric opcode
* @param mnemonic The lower case mnemonic
* @param addressingMode The addressing mode
* @param cycles The number of cycles
*/
protected void addOpcode(int opcode, String mnemonic, AsmAddressingMode addressingMode, double cycles, String clobberString) {
AsmOpcode asmOpcode = new AsmOpcode(opcode, mnemonic, addressingMode, cycles, clobberString);
addOpcode(asmOpcode);
}
/**
* Add an instruction opcode to the instruction set.
*
* @param opcode The opcode to add
*/
private void addOpcode(AsmOpcode asmOpcode) {
allOpcodes.add(asmOpcode);
opcodesByMnemonicAddrMode.put(asmOpcode.getMnemonic() + "_" + asmOpcode.getAddressingMode().getName(), asmOpcode);
}
}

6
src/main/java/dk/camelot64/cpufamily6502/AsmInstructionSet.java
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@ -282,7 +282,6 @@ public class AsmInstructionSet {
}
/**
* Add an instruction to the instruction set.
*
@ -304,7 +303,7 @@ public class AsmInstructionSet {
* @param addressingMode The addressing mode
* @return The opcode, if is exists. Null if the instruction set does not have the opcode.
*/
public AsmOpcode getOpcode(String mnemonic, AsmAddressingMode addressingMode) {
private AsmOpcode getOpcode(String mnemonic, AsmAddressingMode addressingMode) {
String key = mnemonic.toLowerCase() + "_" + addressingMode.getName();
return instructionsMap.get(key);
}
@ -316,7 +315,8 @@ public class AsmInstructionSet {
* @param mnemonic The mnemonic
* @param mode The addressing mode you want.
* @param isZp Indicates whether you are interested in a zeropage-based opcode.
* @return The opcode, if it exists. If you have requested an absolute addressing mode passed isZp as true the resulting opcode will have zeropage-based addressing the instruction set offers that.
* @return The opcode, if it exists. If you have requested an absolute addressing mode passed isZp as true the
* resulting opcode will have zeropage-based addressing the instruction set offers that.
*/
public static AsmOpcode getOpcode(String mnemonic, AsmAddressingMode mode, boolean isZp) {
AsmOpcode asmOpcode = null;

88
src/main/java/dk/camelot64/cpufamily6502/cpus/Cpu6502Illegal.java Normal file
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package dk.camelot64.cpufamily6502.cpus;
import dk.camelot64.cpufamily6502.AsmAddressingMode;
import dk.camelot64.cpufamily6502.AsmCpu;
/**
* The 6502 instruction set including illegal instructions.
* http://www.oxyron.de/html/opcodes02.html
*/
public class Cpu6502Illegal extends AsmCpu {
/** The 6502 with illegal CPU name. */
public final static String NAME = "6502x";
/** The 6502 with illegal CPU. */
public final static Cpu6502Illegal INSTANCE = new Cpu6502Illegal();
public Cpu6502Illegal() {
super(NAME, Cpu6502Official.INSTANCE);
addOpcode(0x03, "slo", AsmAddressingMode.IZX, 8.0, "Aczn");
addOpcode(0x07, "slo", AsmAddressingMode.ZP, 5.0, "Aczn");
addOpcode(0x0b, "anc", AsmAddressingMode.IMM, 2.0, "Aczn");
addOpcode(0x0f, "slo", AsmAddressingMode.ABS, 6.0, "Aczn");
addOpcode(0x13, "slo", AsmAddressingMode.IZY, 8.0, "Aczn");
addOpcode(0x17, "slo", AsmAddressingMode.ZPX, 6.0, "Aczn");
addOpcode(0x1b, "slo", AsmAddressingMode.ABY, 7.0, "Aczn");
addOpcode(0x1f, "slo", AsmAddressingMode.ABX, 7.0, "Aczn");
addOpcode(0x23, "rla", AsmAddressingMode.IZX, 8.0, "Aczn");
addOpcode(0x27, "rla", AsmAddressingMode.ZP, 5.0, "Aczn");
addOpcode(0x2b, "anc", AsmAddressingMode.IMM, 2.0, "Aczn");
addOpcode(0x2f, "rla", AsmAddressingMode.ABS, 6.0, "Aczn");
addOpcode(0x33, "rla", AsmAddressingMode.IZY, 8.0, "Aczn");
addOpcode(0x37, "rla", AsmAddressingMode.ZPX, 6.0, "Aczn");
addOpcode(0x3b, "rla", AsmAddressingMode.ABY, 7.0, "Aczn");
addOpcode(0x3f, "rla", AsmAddressingMode.ABX, 7.0, "Aczn");
addOpcode(0x43, "sre", AsmAddressingMode.IZX, 8.0, "Aczn");
addOpcode(0x47, "sre", AsmAddressingMode.ZP, 5.0, "Aczn");
addOpcode(0x4b, "alr", AsmAddressingMode.IMM, 2.0, "Aczn");
addOpcode(0x4f, "sre", AsmAddressingMode.ABS, 6.0, "Aczn");
addOpcode(0x53, "sre", AsmAddressingMode.IZY, 8.0, "Aczn");
addOpcode(0x57, "sre", AsmAddressingMode.ZPX, 6.0, "Aczn");
addOpcode(0x5b, "sre", AsmAddressingMode.ABY, 7.0, "Aczn");
addOpcode(0x5f, "sre", AsmAddressingMode.ABX, 7.0, "Aczn");
addOpcode(0x63, "rra", AsmAddressingMode.IZX, 8.0, "Acvzn");
addOpcode(0x67, "rra", AsmAddressingMode.ZP, 5.0, "Acvzn");
addOpcode(0x6b, "arr", AsmAddressingMode.IMM, 2.0, "Acvzn");
addOpcode(0x6f, "rra", AsmAddressingMode.ABS, 6.0, "Acvzn");
addOpcode(0x73, "rra", AsmAddressingMode.IZY, 8.0, "Acvzn");
addOpcode(0x77, "rra", AsmAddressingMode.ZPX, 6.0, "Acvzn");
addOpcode(0x7b, "rra", AsmAddressingMode.ABY, 7.0, "Acvzn");
addOpcode(0x7f, "rra", AsmAddressingMode.ABX, 7.0, "Acvzn");
addOpcode(0x83, "sax", AsmAddressingMode.IZX, 6.0, "");
addOpcode(0x87, "sax", AsmAddressingMode.ZP, 3.0, "");
addOpcode(0x8b, "xaa", AsmAddressingMode.IMM, 2.0, "Azn");
addOpcode(0x8f, "sax", AsmAddressingMode.ABS, 4.0, "");
addOpcode(0x93, "ahx", AsmAddressingMode.IZY, 6.0, "");
addOpcode(0x97, "sax", AsmAddressingMode.ZPY, 4.0, "");
addOpcode(0x9b, "tas", AsmAddressingMode.ABY, 5.0, "");
addOpcode(0x9c, "shy", AsmAddressingMode.ABX, 5.0, "");
addOpcode(0x9e, "shx", AsmAddressingMode.ABY, 5.0, "");
addOpcode(0x9f, "ahx", AsmAddressingMode.ABY, 5.0, "");
addOpcode(0xa3, "lax", AsmAddressingMode.IZX, 6.0, "AXzn");
addOpcode(0xa7, "lax", AsmAddressingMode.ZP, 3.0, "AXzn");
addOpcode(0xab, "lax", AsmAddressingMode.IMM, 2.0, "AXzn");
addOpcode(0xaf, "lax", AsmAddressingMode.ABS, 4.0, "AXzn");
addOpcode(0xb3, "lax", AsmAddressingMode.IZY, 5.5, "AXzn");
addOpcode(0xb7, "lax", AsmAddressingMode.ZPY, 4.0, "AXzn");
addOpcode(0xbb, "las", AsmAddressingMode.ABY, 4.5, "AXzn");
addOpcode(0xbf, "lax", AsmAddressingMode.ABY, 4.5, "AXzn");
addOpcode(0xc3, "dcp", AsmAddressingMode.IZX, 8.0, "czn");
addOpcode(0xc7, "dcp", AsmAddressingMode.ZP, 5.0, "czn");
addOpcode(0xcb, "axs", AsmAddressingMode.IMM, 2.0, "Xczn");
addOpcode(0xcf, "dcp", AsmAddressingMode.ABS, 6.0, "czn");
addOpcode(0xd3, "dcp", AsmAddressingMode.IZY, 8.0, "czn");
addOpcode(0xd7, "dcp", AsmAddressingMode.ZPX, 6.0, "czn");
addOpcode(0xdb, "dcp", AsmAddressingMode.ABY, 7.0, "czn");
addOpcode(0xe2, "isc", AsmAddressingMode.IZX, 8.0, "Acvzn");
addOpcode(0xe6, "isc", AsmAddressingMode.ZP, 5.0, "Acvzn");
addOpcode(0xea, "sbc", AsmAddressingMode.IMM, 2.0, "Acvzn");
addOpcode(0xee, "isc", AsmAddressingMode.ABS, 6.0, "Acvzn");
addOpcode(0xef, "dcp", AsmAddressingMode.ABX, 7.0, "czn");
addOpcode(0xf3, "isc", AsmAddressingMode.IZY, 8.0, "Acvzn");
addOpcode(0xf7, "isc", AsmAddressingMode.ZPX, 6.0, "Acvzn");
addOpcode(0xfb, "isc", AsmAddressingMode.ABY, 7.0, "Acvzn");
addOpcode(0xff, "isc", AsmAddressingMode.ABX, 7.0, "Acvzn");
}
}

174
src/main/java/dk/camelot64/cpufamily6502/cpus/Cpu6502Official.java Normal file
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@ -0,0 +1,174 @@
package dk.camelot64.cpufamily6502.cpus;
import dk.camelot64.cpufamily6502.AsmAddressingMode;
import dk.camelot64.cpufamily6502.AsmCpu;
/**
* The official 6502 instruction set (no illegal instructions).
* This is the basis for all other 6502 family CPU's and all opcodes are available in all other CPU's.
* http://archive.6502.org/datasheets/mos_6500_mpu_nov_1985.pdf
*/
public class Cpu6502Official extends AsmCpu {
/** The 6502 official CPU name. */
public final static String NAME = "6502";
/** The 6502 official CPU. */
public final static Cpu6502Official INSTANCE = new Cpu6502Official();
public Cpu6502Official() {
super(NAME);
addOpcode(0x00, "brk", AsmAddressingMode.NON, 7.0, "");
addOpcode(0x01, "ora", AsmAddressingMode.IZX, 6.0, "Azn");
addOpcode(0x05, "ora", AsmAddressingMode.ZP, 3.0, "Azn");
addOpcode(0x06, "asl", AsmAddressingMode.ZP, 5.0, "czn");
addOpcode(0x08, "php", AsmAddressingMode.NON, 3.0, "S");
addOpcode(0x09, "ora", AsmAddressingMode.IMM, 2.0, "Azn");
addOpcode(0x0a, "asl", AsmAddressingMode.NON, 2.0, "Aczn");
addOpcode(0x0d, "ora", AsmAddressingMode.ABS, 4.0, "Azn");
addOpcode(0x0e, "asl", AsmAddressingMode.ABS, 6.0, "czn");
addOpcode(0x10, "bpl", AsmAddressingMode.REL, 2.5, "P");
addOpcode(0x11, "ora", AsmAddressingMode.IZY, 5.5, "Azn");
addOpcode(0x15, "ora", AsmAddressingMode.ZPX, 4.0, "Azn");
addOpcode(0x16, "asl", AsmAddressingMode.ZPX, 6.0, "czn");
addOpcode(0x18, "clc", AsmAddressingMode.NON, 2.0, "c");
addOpcode(0x19, "ora", AsmAddressingMode.ABY, 4.5, "Azn");
addOpcode(0x1d, "ora", AsmAddressingMode.ABX, 4.5, "Azn");
addOpcode(0x1e, "asl", AsmAddressingMode.ABX, 7.0, "czn");
addOpcode(0x20, "jsr", AsmAddressingMode.ABS, 6.0, "PS");
addOpcode(0x21, "and", AsmAddressingMode.IZX, 6.0, "Azn");
addOpcode(0x24, "bit", AsmAddressingMode.ZP, 3.0, "vzn");
addOpcode(0x25, "and", AsmAddressingMode.ZP, 3.0, "Azn");
addOpcode(0x26, "rol", AsmAddressingMode.ZP, 5.0, "czn");
addOpcode(0x28, "plp", AsmAddressingMode.NON, 4.0, "cvznS");
addOpcode(0x29, "and", AsmAddressingMode.IMM, 2.0, "Azn");
addOpcode(0x2a, "rol", AsmAddressingMode.NON, 2.0, "Aczn");
addOpcode(0x2c, "bit", AsmAddressingMode.ABS, 4.0, "vzn");
addOpcode(0x2d, "and", AsmAddressingMode.ABS, 4.0, "Azn");
addOpcode(0x2e, "rol", AsmAddressingMode.ABS, 6.0, "czn");
addOpcode(0x30, "bmi", AsmAddressingMode.REL, 2.5, "P");
addOpcode(0x31, "and", AsmAddressingMode.IZY, 5.5, "Azn");
addOpcode(0x35, "and", AsmAddressingMode.ZPX, 4.0, "Azn");
addOpcode(0x36, "rol", AsmAddressingMode.ZPX, 6.0, "czn");
addOpcode(0x38, "sec", AsmAddressingMode.NON, 2.0, "c");
addOpcode(0x39, "and", AsmAddressingMode.ABY, 4.5, "Azn");
addOpcode(0x3d, "and", AsmAddressingMode.ABX, 4.5, "Azn");
addOpcode(0x3e, "rol", AsmAddressingMode.ABX, 7.0, "czn");
addOpcode(0x40, "rti", AsmAddressingMode.NON, 6.0, "cvznPS");
addOpcode(0x41, "eor", AsmAddressingMode.IZX, 6.0, "Azn");
addOpcode(0x45, "eor", AsmAddressingMode.ZP, 3.0, "Azn");
addOpcode(0x46, "lsr", AsmAddressingMode.ZP, 5.0, "czn");
addOpcode(0x48, "pha", AsmAddressingMode.NON, 3.0, "S");
addOpcode(0x49, "eor", AsmAddressingMode.IMM, 2.0, "Azn");
addOpcode(0x4a, "lsr", AsmAddressingMode.NON, 2.0, "Aczn");
addOpcode(0x4c, "jmp", AsmAddressingMode.ABS, 3.0, "P");
addOpcode(0x4d, "eor", AsmAddressingMode.ABS, 4.0, "Azn");
addOpcode(0x4e, "lsr", AsmAddressingMode.ABS, 6.0, "czn");
addOpcode(0x50, "bvc", AsmAddressingMode.REL, 2.5, "P");
addOpcode(0x51, "eor", AsmAddressingMode.IZY, 5.5, "Azn");
addOpcode(0x55, "eor", AsmAddressingMode.ZPX, 4.0, "Azn");
addOpcode(0x56, "lsr", AsmAddressingMode.ZPX, 6.0, "czn");
addOpcode(0x58, "cli", AsmAddressingMode.NON, 2.0, "i");
addOpcode(0x59, "eor", AsmAddressingMode.ABY, 4.5, "Azn");
addOpcode(0x5d, "eor", AsmAddressingMode.ABX, 4.5, "Azn");
addOpcode(0x5e, "lsr", AsmAddressingMode.ABX, 7.0, "czn");
addOpcode(0x60, "rts", AsmAddressingMode.NON, 6.0, "PS");
addOpcode(0x61, "adc", AsmAddressingMode.IZX, 6.0, "Acvzn");
addOpcode(0x65, "adc", AsmAddressingMode.ZP, 3.0, "Acvzn");
addOpcode(0x66, "ror", AsmAddressingMode.ZP, 5.0, "czn");
addOpcode(0x68, "pla", AsmAddressingMode.NON, 4.0, "AznS");
addOpcode(0x69, "adc", AsmAddressingMode.IMM, 2.0, "Acvzn");
addOpcode(0x6a, "ror", AsmAddressingMode.NON, 2.0, "Aczn");
addOpcode(0x6c, "jmp", AsmAddressingMode.IND, 5.0, "P");
addOpcode(0x6d, "adc", AsmAddressingMode.ABS, 4.0, "Acvzn");
addOpcode(0x6e, "ror", AsmAddressingMode.ABS, 6.0, "czn");
addOpcode(0x70, "bvs", AsmAddressingMode.REL, 2.5, "P");
addOpcode(0x71, "adc", AsmAddressingMode.IZY, 5.5, "Acvzn");
addOpcode(0x75, "adc", AsmAddressingMode.ZPX, 4.0, "Acvzn");
addOpcode(0x76, "ror", AsmAddressingMode.ZPX, 6.0, "czn");
addOpcode(0x78, "sei", AsmAddressingMode.NON, 2.0, "i");
addOpcode(0x79, "adc", AsmAddressingMode.ABY, 4.5, "Acvzn");
addOpcode(0x7d, "adc", AsmAddressingMode.ABX, 4.5, "Acvzn");
addOpcode(0x7e, "ror", AsmAddressingMode.ABX, 7.0, "czn");
addOpcode(0x81, "sta", AsmAddressingMode.IZX, 6.0, "");
addOpcode(0x84, "sty", AsmAddressingMode.ZP, 3.0, "");
addOpcode(0x85, "sta", AsmAddressingMode.ZP, 3.0, "");
addOpcode(0x86, "stx", AsmAddressingMode.ZP, 3.0, "");
addOpcode(0x88, "dey", AsmAddressingMode.NON, 2.0, "Yzn");
addOpcode(0x8a, "txa", AsmAddressingMode.NON, 2.0, "Azn");
addOpcode(0x8c, "sty", AsmAddressingMode.ABS, 4.0, "");
addOpcode(0x8d, "sta", AsmAddressingMode.ABS, 4.0, "");
addOpcode(0x8e, "stx", AsmAddressingMode.ABS, 4.0, "");
addOpcode(0x90, "bcc", AsmAddressingMode.REL, 2.5, "P");
addOpcode(0x91, "sta", AsmAddressingMode.IZY, 6.0, "");
addOpcode(0x94, "sty", AsmAddressingMode.ZPX, 4.0, "");
addOpcode(0x95, "sta", AsmAddressingMode.ZPX, 4.0, "");
addOpcode(0x96, "stx", AsmAddressingMode.ZPY, 4.0, "");
addOpcode(0x98, "tya", AsmAddressingMode.NON, 2.0, "Azn");
addOpcode(0x99, "sta", AsmAddressingMode.ABY, 5.0, "");
addOpcode(0x9a, "txs", AsmAddressingMode.NON, 2.0, "S");
addOpcode(0x9d, "sta", AsmAddressingMode.ABX, 5.0, "");
addOpcode(0xa0, "ldy", AsmAddressingMode.IMM, 2.0, "Yzn");
addOpcode(0xa1, "lda", AsmAddressingMode.IZX, 6.0, "Azn");
addOpcode(0xa2, "ldx", AsmAddressingMode.IMM, 2.0, "Xzn");
addOpcode(0xa4, "ldy", AsmAddressingMode.ZP, 3.0, "Yzn");
addOpcode(0xa5, "lda", AsmAddressingMode.ZP, 3.0, "Azn");
addOpcode(0xa6, "ldx", AsmAddressingMode.ZP, 3.0, "Xzn");
addOpcode(0xa8, "tay", AsmAddressingMode.NON, 2.0, "Yzn");
addOpcode(0xa9, "lda", AsmAddressingMode.IMM, 2.0, "Azn");
addOpcode(0xaa, "tax", AsmAddressingMode.NON, 2.0, "Xzn");
addOpcode(0xac, "ldy", AsmAddressingMode.ABS, 4.0, "Yzn");
addOpcode(0xad, "lda", AsmAddressingMode.ABS, 4.0, "Azn");
addOpcode(0xae, "ldx", AsmAddressingMode.ABS, 4.0, "Xzn");
addOpcode(0xb0, "bcs", AsmAddressingMode.REL, 2.5, "P");
addOpcode(0xb1, "lda", AsmAddressingMode.IZY, 5.5, "Azn");
addOpcode(0xb4, "ldy", AsmAddressingMode.ZPX, 4.0, "Yzn");
addOpcode(0xb5, "lda", AsmAddressingMode.ZPX, 4.0, "Azn");
addOpcode(0xb6, "ldx", AsmAddressingMode.ZPY, 4.0, "Xzn");
addOpcode(0xb8, "clv", AsmAddressingMode.NON, 2.0, "v");
addOpcode(0xb9, "lda", AsmAddressingMode.ABY, 4.5, "Azn");
addOpcode(0xba, "tsx", AsmAddressingMode.NON, 2.0, "Xzn");
addOpcode(0xbc, "ldy", AsmAddressingMode.ABX, 4.5, "Yzn");
addOpcode(0xbd, "lda", AsmAddressingMode.ABX, 4.5, "Azn");
addOpcode(0xbe, "ldx", AsmAddressingMode.ABY, 4.5, "Xzn");
addOpcode(0xc0, "cpy", AsmAddressingMode.IMM, 2.0, "czn");
addOpcode(0xc1, "cmp", AsmAddressingMode.IZX, 6.0, "czn");
addOpcode(0xc4, "cpy", AsmAddressingMode.ZP, 3.0, "czn");
addOpcode(0xc5, "cmp", AsmAddressingMode.ZP, 3.0, "czn");
addOpcode(0xc6, "dec", AsmAddressingMode.ZP, 5.0, "zn");
addOpcode(0xc8, "iny", AsmAddressingMode.NON, 2.0, "Yzn");
addOpcode(0xc9, "cmp", AsmAddressingMode.IMM, 2.0, "czn");
addOpcode(0xca, "dex", AsmAddressingMode.NON, 2.0, "Xzn");
addOpcode(0xcc, "cpy", AsmAddressingMode.ABS, 4.0, "czn");
addOpcode(0xcd, "cmp", AsmAddressingMode.ABS, 4.0, "czn");
addOpcode(0xce, "dec", AsmAddressingMode.ABS, 6.0, "zn");
addOpcode(0xd0, "bne", AsmAddressingMode.REL, 2.5, "P");
addOpcode(0xd1, "cmp", AsmAddressingMode.IZY, 5.5, "czn");
addOpcode(0xd5, "cmp", AsmAddressingMode.ZPX, 4.0, "czn");
addOpcode(0xd6, "dec", AsmAddressingMode.ZPX, 6.0, "zn");
addOpcode(0xd8, "cld", AsmAddressingMode.NON, 2.0, "d");
addOpcode(0xd9, "cmp", AsmAddressingMode.ABY, 4.5, "czn");
addOpcode(0xdd, "cmp", AsmAddressingMode.ABX, 4.5, "czn");
addOpcode(0xde, "dec", AsmAddressingMode.ABX, 7.0, "zn");
addOpcode(0xe0, "cpx", AsmAddressingMode.IMM, 2.0, "czn");
addOpcode(0xe1, "sbc", AsmAddressingMode.IZX, 6.0, "Acvzn");
addOpcode(0xe4, "cpx", AsmAddressingMode.ZP, 3.0, "czn");
addOpcode(0xe5, "sbc", AsmAddressingMode.ZP, 3.0, "Acvzn");
addOpcode(0xe6, "inc", AsmAddressingMode.ZP, 5.0, "zn");
addOpcode(0xe8, "inx", AsmAddressingMode.NON, 2.0, "Xzn");
addOpcode(0xe9, "sbc", AsmAddressingMode.IMM, 2.0, "Acvzn");
addOpcode(0xea, "nop", AsmAddressingMode.NON, 2.0, "");
addOpcode(0xec, "cpx", AsmAddressingMode.ABS, 4.0, "czn");
addOpcode(0xed, "sbc", AsmAddressingMode.ABS, 4.0, "Acvzn");
addOpcode(0xee, "inc", AsmAddressingMode.ABS, 6.0, "zn");
addOpcode(0xf0, "beq", AsmAddressingMode.REL, 2.5, "P");
addOpcode(0xf1, "sbc", AsmAddressingMode.IZY, 5.5, "Acvzn");
addOpcode(0xf5, "sbc", AsmAddressingMode.ZPX, 4.0, "Acvzn");
addOpcode(0xf6, "inc", AsmAddressingMode.ZPX, 6.0, "zn");
addOpcode(0xf8, "sed", AsmAddressingMode.NON, 2.0, "d");
addOpcode(0xf9, "sbc", AsmAddressingMode.ABY, 4.5, "Acvzn");
addOpcode(0xfd, "sbc", AsmAddressingMode.ABX, 4.5, "Acvzn");
addOpcode(0xfe, "inc", AsmAddressingMode.ABX, 7.0, "zn");
}
}