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Improved liverange testing

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This commit is contained in:
jespergravgaard 2020-03-23 07:26:26 +01:00
parent ae1536f429
commit e385257cf4
13 changed files with 193 additions and 231 deletions
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5
src/test/java/dk/camelot64/kickc/test/TestPrograms.java
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@ -3385,6 +3385,11 @@ public class TestPrograms {
compileAndCompare("constantmin");
}
@Test
public void testLiveRange10() throws IOException, URISyntaxException {
compileAndCompare("liverange-10");
}
@Test
public void testLiveRange9() throws IOException, URISyntaxException {
compileAndCompare("liverange-9");

34
src/test/kc/liverange-10.kc Normal file
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@ -0,0 +1,34 @@
// Test effective live range and register allocation
// Here outsw::sw and outw::w should have the same allocation
const char* SCREEN = 0x0400;
char idx = 0;
void main() {
for(signed int sw: -20..19 )
outsw(sw);
for(unsigned int w: 0..39 )
outw(w);
}
void outsw(signed int sw) {
if(sw<0) {
out('-');
sw = -sw;
}
outw((unsigned int)sw);
}
char[] HEXTAB = "0123456789abcdef";
void outw(unsigned int w) {
out(HEXTAB[(>w)<<4]);
out(HEXTAB[(>w)&0x0f]);
out(HEXTAB[(<w)<<4]);
out(HEXTAB[(<w)&0x0f]);
}
void out(char c) {
idx++;
SCREEN[idx] = c;
}

1
src/test/kc/liverange-2.kc
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@ -1,4 +1,5 @@
// Test effective live range and register allocation
// main::b and main::c should be allocated to hardware registers
void main() {
for(char a: 0..100 ) {

1
src/test/kc/liverange-6.kc
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@ -1,4 +1,5 @@
// Test effective live range and register allocation
// out::c should be a hardware register, main::i should be a hardware register, global idx should be a hardware register
byte[] msg = "hello world!";

6
src/test/kc/liverange-9.kc
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@ -15,11 +15,9 @@ void outsw(char c) {
outw(c);
}
char[] HEXTAB = "0123456789abcdef";
void outw(char c) {
out(HEXTAB[c<<4]);
out(HEXTAB[c&0x0f]);
out(c<<4);
out(c&0x0f);
}
void out(char c) {

1
src/test/ref/liverange-2.asm
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@ -1,4 +1,5 @@
// Test effective live range and register allocation
// main::b and main::c should be allocated to hardware registers
.pc = $801 "Basic"
:BasicUpstart(main)
.pc = $80d "Program"

3
src/test/ref/liverange-2.log
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@ -291,6 +291,7 @@ INITIAL ASM
Target platform is c64basic / MOS6502X
// File Comments
// Test effective live range and register allocation
// main::b and main::c should be allocated to hardware registers
// Upstart
.pc = $801 "Basic"
:BasicUpstart(__bbegin)
@ -446,6 +447,7 @@ Uplifting [main] best 35547 combination zp[1]:2 [ main::a#7 main::a#1 ]
ASSEMBLER BEFORE OPTIMIZATION
// File Comments
// Test effective live range and register allocation
// main::b and main::c should be allocated to hardware registers
// Upstart
.pc = $801 "Basic"
:BasicUpstart(__bbegin)
@ -644,6 +646,7 @@ Score: 22542
// File Comments
// Test effective live range and register allocation
// main::b and main::c should be allocated to hardware registers
// Upstart
.pc = $801 "Basic"
:BasicUpstart(main)

1
src/test/ref/liverange-6.asm
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@ -1,4 +1,5 @@
// Test effective live range and register allocation
// out::c should be a hardware register, main::i should be a hardware register, global idx should be a hardware register
.pc = $801 "Basic"
:BasicUpstart(main)
.pc = $80d "Program"

3
src/test/ref/liverange-6.log
View File

@ -213,6 +213,7 @@ INITIAL ASM
Target platform is c64basic / MOS6502X
// File Comments
// Test effective live range and register allocation
// out::c should be a hardware register, main::i should be a hardware register, global idx should be a hardware register
// Upstart
.pc = $801 "Basic"
:BasicUpstart(__bbegin)
@ -313,6 +314,7 @@ Uplifting [main] best 364 combination reg byte y [ main::i#2 main::i#1 ]
ASSEMBLER BEFORE OPTIMIZATION
// File Comments
// Test effective live range and register allocation
// out::c should be a hardware register, main::i should be a hardware register, global idx should be a hardware register
// Upstart
.pc = $801 "Basic"
:BasicUpstart(__bbegin)
@ -446,6 +448,7 @@ Score: 229
// File Comments
// Test effective live range and register allocation
// out::c should be a hardware register, main::i should be a hardware register, global idx should be a hardware register
// Upstart
.pc = $801 "Basic"
:BasicUpstart(main)

32
src/test/ref/liverange-9.asm
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@ -5,18 +5,14 @@
.pc = $80d "Program"
.label SCREEN = $400
main: {
.label c = 2
ldx #0
txa
sta.z c
ldy #0
__b1:
// outsw(c)
ldy.z c
jsr outsw
// for(char c: 0..39 )
inc.z c
lda #$28
cmp.z c
iny
cpy #$28
bne __b1
// }
rts
@ -27,30 +23,22 @@ outsw: {
lda #'-'
jsr out
// outw(c)
sty.z outw.c
jsr outw
// }
rts
}
// outw(byte zp(3) c)
// outw(byte register(Y) c)
outw: {
.label c = 3
// c<<4
lda.z c
// out(c<<4)
tya
asl
asl
asl
asl
// out(HEXTAB[c<<4])
tay
lda HEXTAB,y
jsr out
// c&0x0f
lda #$f
and.z c
// out(HEXTAB[c&0x0f])
tay
lda HEXTAB,y
// out(c&0x0f)
tya
and #$f
jsr out
// }
rts
@ -64,5 +52,3 @@ out: {
// }
rts
}
HEXTAB: .text "0123456789abcdef"
.byte 0

22
src/test/ref/liverange-9.cfg
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@ -41,26 +41,24 @@ outsw::@return: scope:[outsw] from outsw::@1
(void()) outw((byte) outw::c)
outw: scope:[outw] from outsw::@1
[16] (byte~) outw::$0 ← (byte) outw::c#0 << (byte) 4
[17] (byte) out::c#1 ← *((const byte*) HEXTAB + (byte~) outw::$0)
[18] call out
[16] (byte) out::c#1 ← (byte) outw::c#0 << (byte) 4
[17] call out
to:outw::@1
outw::@1: scope:[outw] from outw
[19] (byte~) outw::$2 ← (byte) outw::c#0 & (byte) $f
[20] (byte) out::c#2 ← *((const byte*) HEXTAB + (byte~) outw::$2)
[21] call out
[18] (byte) out::c#2 ← (byte) outw::c#0 & (byte) $f
[19] call out
to:outw::@return
outw::@return: scope:[outw] from outw::@1
[22] return
[20] return
to:@return
(void()) out((byte) out::c)
out: scope:[out] from outsw outw outw::@1
[23] (byte) out::c#3 ← phi( outsw/(byte) '-' outw/(byte) out::c#1 outw::@1/(byte) out::c#2 )
[23] (byte) idx#20 ← phi( outsw/(byte) idx#23 outw/(byte) idx#10 outw::@1/(byte) idx#10 )
[24] (byte) idx#10 ← ++ (byte) idx#20
[25] *((const byte*) SCREEN + (byte) idx#10) ← (byte) out::c#3
[21] (byte) out::c#3 ← phi( outsw/(byte) '-' outw/(byte) out::c#1 outw::@1/(byte) out::c#2 )
[21] (byte) idx#20 ← phi( outsw/(byte) idx#23 outw/(byte) idx#10 outw::@1/(byte) idx#10 )
[22] (byte) idx#10 ← ++ (byte) idx#20
[23] *((const byte*) SCREEN + (byte) idx#10) ← (byte) out::c#3
to:out::@return
out::@return: scope:[out] from out
[26] return
[24] return
to:@return

298
src/test/ref/liverange-9.log
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@ -62,7 +62,7 @@ outw: scope:[outw] from outsw::@1
(byte) idx#25 ← phi( outsw::@1/(byte) idx#3 )
(byte) outw::c#1 ← phi( outsw::@1/(byte) outw::c#0 )
(byte~) outw::$0 ← (byte) outw::c#1 << (number) 4
(byte) out::c#1 ← *((const byte*) HEXTAB + (byte~) outw::$0)
(byte) out::c#1 ← (byte~) outw::$0
call out
to:outw::@1
outw::@1: scope:[outw] from outw
@ -70,7 +70,7 @@ outw::@1: scope:[outw] from outw
(byte) idx#17 ← phi( outw/(byte) idx#10 )
(byte) idx#6 ← (byte) idx#17
(number~) outw::$2 ← (byte) outw::c#2 & (number) $f
(byte) out::c#2 ← *((const byte*) HEXTAB + (number~) outw::$2)
(byte) out::c#2 ← (number~) outw::$2
call out
to:outw::@2
outw::@2: scope:[outw] from outw::@1
@ -110,7 +110,6 @@ SYMBOL TABLE SSA
(label) @5
(label) @begin
(label) @end
(const byte*) HEXTAB[] = (byte*) "0123456789abcdef"
(const byte*) SCREEN = (byte*)(number) $400
(byte) idx
(byte) idx#0
@ -194,8 +193,10 @@ Alias idx#1 = idx#12 idx#13 idx#2
Alias outsw::c#1 = outsw::c#2
Alias idx#14 = idx#3
Alias idx#15 = idx#4 idx#16 idx#5
Alias out::c#1 = outw::$0
Alias outw::c#1 = outw::c#2
Alias idx#17 = idx#6
Alias out::c#2 = outw::$2
Alias idx#18 = idx#7 idx#19 idx#8
Alias idx#10 = idx#21 idx#9
Alias idx#0 = idx#26
@ -246,16 +247,16 @@ CALL GRAPH
Calls in [] to main:2
Calls in [main] to outsw:8
Calls in [outsw] to out:15 outw:17
Calls in [outw] to out:24 out:29
Calls in [outw] to out:23 out:27
Created 4 initial phi equivalence classes
Coalesced [12] main::c#4 ← main::c#1
Coalesced [13] idx#28 ← idx#10
Coalesced [14] idx#29 ← idx#23
Coalesced (already) [22] idx#30 ← idx#10
Coalesced [23] out::c#4 ← out::c#1
Coalesced (already) [27] idx#31 ← idx#10
Coalesced [28] out::c#5 ← out::c#2
Coalesced (already) [21] idx#30 ← idx#10
Coalesced [22] out::c#4 ← out::c#1
Coalesced (already) [25] idx#31 ← idx#10
Coalesced [26] out::c#5 ← out::c#2
Coalesced down to 3 phi equivalence classes
Culled Empty Block (label) @5
Culled Empty Block (label) main::@4
@ -313,34 +314,32 @@ outsw::@return: scope:[outsw] from outsw::@1
(void()) outw((byte) outw::c)
outw: scope:[outw] from outsw::@1
[16] (byte~) outw::$0 ← (byte) outw::c#0 << (byte) 4
[17] (byte) out::c#1 ← *((const byte*) HEXTAB + (byte~) outw::$0)
[18] call out
[16] (byte) out::c#1 ← (byte) outw::c#0 << (byte) 4
[17] call out
to:outw::@1
outw::@1: scope:[outw] from outw
[19] (byte~) outw::$2 ← (byte) outw::c#0 & (byte) $f
[20] (byte) out::c#2 ← *((const byte*) HEXTAB + (byte~) outw::$2)
[21] call out
[18] (byte) out::c#2 ← (byte) outw::c#0 & (byte) $f
[19] call out
to:outw::@return
outw::@return: scope:[outw] from outw::@1
[22] return
[20] return
to:@return
(void()) out((byte) out::c)
out: scope:[out] from outsw outw outw::@1
[23] (byte) out::c#3 ← phi( outsw/(byte) '-' outw/(byte) out::c#1 outw::@1/(byte) out::c#2 )
[23] (byte) idx#20 ← phi( outsw/(byte) idx#23 outw/(byte) idx#10 outw::@1/(byte) idx#10 )
[24] (byte) idx#10 ← ++ (byte) idx#20
[25] *((const byte*) SCREEN + (byte) idx#10) ← (byte) out::c#3
[21] (byte) out::c#3 ← phi( outsw/(byte) '-' outw/(byte) out::c#1 outw::@1/(byte) out::c#2 )
[21] (byte) idx#20 ← phi( outsw/(byte) idx#23 outw/(byte) idx#10 outw::@1/(byte) idx#10 )
[22] (byte) idx#10 ← ++ (byte) idx#20
[23] *((const byte*) SCREEN + (byte) idx#10) ← (byte) out::c#3
to:out::@return
out::@return: scope:[out] from out
[26] return
[24] return
to:@return
VARIABLE REGISTER WEIGHTS
(byte) idx
(byte) idx#10 12947.352941176468
(byte) idx#10 14673.666666666668
(byte) idx#20 121004.0
(byte) idx#23 367.33333333333337
(void()) main()
@ -356,10 +355,8 @@ VARIABLE REGISTER WEIGHTS
(byte) outsw::c
(byte) outsw::c#0 367.33333333333337
(void()) outw((byte) outw::c)
(byte~) outw::$0 20002.0
(byte~) outw::$2 20002.0
(byte) outw::c
(byte) outw::c#0 5250.75
(byte) outw::c#0 7001.0
Initial phi equivalence classes
[ main::c#2 main::c#1 ]
@ -367,23 +364,17 @@ Initial phi equivalence classes
[ out::c#3 out::c#1 out::c#2 ]
Added variable outsw::c#0 to live range equivalence class [ outsw::c#0 ]
Added variable outw::c#0 to live range equivalence class [ outw::c#0 ]
Added variable outw::$0 to live range equivalence class [ outw::$0 ]
Added variable outw::$2 to live range equivalence class [ outw::$2 ]
Complete equivalence classes
[ main::c#2 main::c#1 ]
[ idx#20 idx#23 idx#10 ]
[ out::c#3 out::c#1 out::c#2 ]
[ outsw::c#0 ]
[ outw::c#0 ]
[ outw::$0 ]
[ outw::$2 ]
Allocated zp[1]:2 [ main::c#2 main::c#1 ]
Allocated zp[1]:3 [ idx#20 idx#23 idx#10 ]
Allocated zp[1]:4 [ out::c#3 out::c#1 out::c#2 ]
Allocated zp[1]:5 [ outsw::c#0 ]
Allocated zp[1]:6 [ outw::c#0 ]
Allocated zp[1]:7 [ outw::$0 ]
Allocated zp[1]:8 [ outw::$2 ]
INITIAL ASM
Target platform is c64basic / MOS6502X
@ -459,12 +450,12 @@ main: {
outsw: {
.label c = 5
// [12] call out
// [23] phi from outsw to out [phi:outsw->out]
// [21] phi from outsw to out [phi:outsw->out]
out_from_outsw:
// [23] phi (byte) out::c#3 = (byte) '-' [phi:outsw->out#0] -- vbuz1=vbuc1
// [21] phi (byte) out::c#3 = (byte) '-' [phi:outsw->out#0] -- vbuz1=vbuc1
lda #'-'
sta.z out.c
// [23] phi (byte) idx#20 = (byte) idx#23 [phi:outsw->out#1] -- register_copy
// [21] phi (byte) idx#20 = (byte) idx#23 [phi:outsw->out#1] -- register_copy
jsr out
jmp __b1
// outsw::@1
@ -483,102 +474,83 @@ outsw: {
// outw
// outw(byte zp(6) c)
outw: {
.label __0 = 7
.label __2 = 8
.label c = 6
// [16] (byte~) outw::$0 ← (byte) outw::c#0 << (byte) 4 -- vbuz1=vbuz2_rol_4
// [16] (byte) out::c#1 ← (byte) outw::c#0 << (byte) 4 -- vbuz1=vbuz2_rol_4
lda.z c
asl
asl
asl
asl
sta.z __0
// [17] (byte) out::c#1 ← *((const byte*) HEXTAB + (byte~) outw::$0) -- vbuz1=pbuc1_derefidx_vbuz2
ldy.z __0
lda HEXTAB,y
sta.z out.c
// [18] call out
// [23] phi from outw to out [phi:outw->out]
// [17] call out
// [21] phi from outw to out [phi:outw->out]
out_from_outw:
// [23] phi (byte) out::c#3 = (byte) out::c#1 [phi:outw->out#0] -- register_copy
// [23] phi (byte) idx#20 = (byte) idx#10 [phi:outw->out#1] -- register_copy
// [21] phi (byte) out::c#3 = (byte) out::c#1 [phi:outw->out#0] -- register_copy
// [21] phi (byte) idx#20 = (byte) idx#10 [phi:outw->out#1] -- register_copy
jsr out
jmp __b1
// outw::@1
__b1:
// [19] (byte~) outw::$2 ← (byte) outw::c#0 & (byte) $f -- vbuz1=vbuz2_band_vbuc1
// [18] (byte) out::c#2 ← (byte) outw::c#0 & (byte) $f -- vbuz1=vbuz2_band_vbuc1
lda #$f
and.z c
sta.z __2
// [20] (byte) out::c#2 ← *((const byte*) HEXTAB + (byte~) outw::$2) -- vbuz1=pbuc1_derefidx_vbuz2
ldy.z __2
lda HEXTAB,y
sta.z out.c
// [21] call out
// [23] phi from outw::@1 to out [phi:outw::@1->out]
// [19] call out
// [21] phi from outw::@1 to out [phi:outw::@1->out]
out_from___b1:
// [23] phi (byte) out::c#3 = (byte) out::c#2 [phi:outw::@1->out#0] -- register_copy
// [23] phi (byte) idx#20 = (byte) idx#10 [phi:outw::@1->out#1] -- register_copy
// [21] phi (byte) out::c#3 = (byte) out::c#2 [phi:outw::@1->out#0] -- register_copy
// [21] phi (byte) idx#20 = (byte) idx#10 [phi:outw::@1->out#1] -- register_copy
jsr out
jmp __breturn
// outw::@return
__breturn:
// [22] return
// [20] return
rts
}
// out
// out(byte zp(4) c)
out: {
.label c = 4
// [24] (byte) idx#10 ← ++ (byte) idx#20 -- vbuz1=_inc_vbuz1
// [22] (byte) idx#10 ← ++ (byte) idx#20 -- vbuz1=_inc_vbuz1
inc.z idx
// [25] *((const byte*) SCREEN + (byte) idx#10) ← (byte) out::c#3 -- pbuc1_derefidx_vbuz1=vbuz2
// [23] *((const byte*) SCREEN + (byte) idx#10) ← (byte) out::c#3 -- pbuc1_derefidx_vbuz1=vbuz2
lda.z c
ldy.z idx
sta SCREEN,y
jmp __breturn
// out::@return
__breturn:
// [26] return
// [24] return
rts
}
// File Data
HEXTAB: .text "0123456789abcdef"
.byte 0
REGISTER UPLIFT POTENTIAL REGISTERS
Statement [16] (byte~) outw::$0 ← (byte) outw::c#0 << (byte) 4 [ idx#10 outw::c#0 outw::$0 ] ( main:2::outsw:7::outw:14 [ main::c#2 idx#10 outw::c#0 outw::$0 ] { { outsw::c#0 = main::c#2 outw::c#0 } { idx#10 = idx#20 } { out::c#1 = out::c#3 } } ) always clobbers reg byte a
Statement [16] (byte) out::c#1 ← (byte) outw::c#0 << (byte) 4 [ idx#10 outw::c#0 out::c#1 ] ( main:2::outsw:7::outw:14 [ main::c#2 idx#10 outw::c#0 out::c#1 ] { { outsw::c#0 = main::c#2 outw::c#0 } { idx#10 = idx#20 } { out::c#1 = out::c#3 } } ) always clobbers reg byte a
Removing always clobbered register reg byte a as potential for zp[1]:2 [ main::c#2 main::c#1 ]
Removing always clobbered register reg byte a as potential for zp[1]:3 [ idx#20 idx#23 idx#10 ]
Removing always clobbered register reg byte a as potential for zp[1]:6 [ outw::c#0 ]
Statement [19] (byte~) outw::$2 ← (byte) outw::c#0 & (byte) $f [ idx#10 outw::$2 ] ( main:2::outsw:7::outw:14 [ main::c#2 idx#10 outw::$2 ] { { outsw::c#0 = main::c#2 outw::c#0 } { idx#10 = idx#20 } { out::c#2 = out::c#3 } } ) always clobbers reg byte a
Statement [16] (byte~) outw::$0 ← (byte) outw::c#0 << (byte) 4 [ idx#10 outw::c#0 outw::$0 ] ( main:2::outsw:7::outw:14 [ main::c#2 idx#10 outw::c#0 outw::$0 ] { { outsw::c#0 = main::c#2 outw::c#0 } { idx#10 = idx#20 } { out::c#1 = out::c#3 } } ) always clobbers reg byte a
Statement [19] (byte~) outw::$2 ← (byte) outw::c#0 & (byte) $f [ idx#10 outw::$2 ] ( main:2::outsw:7::outw:14 [ main::c#2 idx#10 outw::$2 ] { { outsw::c#0 = main::c#2 outw::c#0 } { idx#10 = idx#20 } { out::c#2 = out::c#3 } } ) always clobbers reg byte a
Statement [18] (byte) out::c#2 ← (byte) outw::c#0 & (byte) $f [ idx#10 out::c#2 ] ( main:2::outsw:7::outw:14 [ main::c#2 idx#10 out::c#2 ] { { outsw::c#0 = main::c#2 outw::c#0 } { idx#10 = idx#20 } { out::c#2 = out::c#3 } } ) always clobbers reg byte a
Statement [16] (byte) out::c#1 ← (byte) outw::c#0 << (byte) 4 [ idx#10 outw::c#0 out::c#1 ] ( main:2::outsw:7::outw:14 [ main::c#2 idx#10 outw::c#0 out::c#1 ] { { outsw::c#0 = main::c#2 outw::c#0 } { idx#10 = idx#20 } { out::c#1 = out::c#3 } } ) always clobbers reg byte a
Statement [18] (byte) out::c#2 ← (byte) outw::c#0 & (byte) $f [ idx#10 out::c#2 ] ( main:2::outsw:7::outw:14 [ main::c#2 idx#10 out::c#2 ] { { outsw::c#0 = main::c#2 outw::c#0 } { idx#10 = idx#20 } { out::c#2 = out::c#3 } } ) always clobbers reg byte a
Potential registers zp[1]:2 [ main::c#2 main::c#1 ] : zp[1]:2 , reg byte x , reg byte y ,
Potential registers zp[1]:3 [ idx#20 idx#23 idx#10 ] : zp[1]:3 , reg byte x , reg byte y ,
Potential registers zp[1]:4 [ out::c#3 out::c#1 out::c#2 ] : zp[1]:4 , reg byte a , reg byte x , reg byte y ,
Potential registers zp[1]:5 [ outsw::c#0 ] : zp[1]:5 , reg byte a , reg byte x , reg byte y ,
Potential registers zp[1]:6 [ outw::c#0 ] : zp[1]:6 , reg byte x , reg byte y ,
Potential registers zp[1]:7 [ outw::$0 ] : zp[1]:7 , reg byte a , reg byte x , reg byte y ,
Potential registers zp[1]:8 [ outw::$2 ] : zp[1]:8 , reg byte a , reg byte x , reg byte y ,
REGISTER UPLIFT SCOPES
Uplift Scope [] 134,318.69: zp[1]:3 [ idx#20 idx#23 idx#10 ]
Uplift Scope [] 136,045: zp[1]:3 [ idx#20 idx#23 idx#10 ]
Uplift Scope [out] 100,005.5: zp[1]:4 [ out::c#3 out::c#1 out::c#2 ]
Uplift Scope [outw] 20,002: zp[1]:7 [ outw::$0 ] 20,002: zp[1]:8 [ outw::$2 ] 5,250.75: zp[1]:6 [ outw::c#0 ]
Uplift Scope [outw] 7,001: zp[1]:6 [ outw::c#0 ]
Uplift Scope [outsw] 367.33: zp[1]:5 [ outsw::c#0 ]
Uplift Scope [main] 252.5: zp[1]:2 [ main::c#2 main::c#1 ]
Uplifting [] best 492 combination reg byte x [ idx#20 idx#23 idx#10 ]
Uplifting [out] best 480 combination reg byte a [ out::c#3 out::c#1 out::c#2 ]
Uplifting [outw] best 472 combination reg byte a [ outw::$0 ] reg byte a [ outw::$2 ] zp[1]:6 [ outw::c#0 ]
Uplifting [outsw] best 439 combination reg byte y [ outsw::c#0 ]
Uplifting [main] best 439 combination zp[1]:2 [ main::c#2 main::c#1 ]
Attempting to uplift remaining variables inzp[1]:6 [ outw::c#0 ]
Uplifting [outw] best 439 combination zp[1]:6 [ outw::c#0 ]
Attempting to uplift remaining variables inzp[1]:2 [ main::c#2 main::c#1 ]
Uplifting [main] best 439 combination zp[1]:2 [ main::c#2 main::c#1 ]
Allocated (was zp[1]:6) zp[1]:3 [ outw::c#0 ]
Uplifting [] best 472 combination reg byte x [ idx#20 idx#23 idx#10 ]
Uplifting [out] best 460 combination reg byte a [ out::c#3 out::c#1 out::c#2 ]
Uplifting [outw] best 455 combination reg byte y [ outw::c#0 ]
Uplifting [outsw] best 422 combination reg byte y [ outsw::c#0 ]
Uplifting [main] best 302 combination reg byte y [ main::c#2 main::c#1 ]
ASSEMBLER BEFORE OPTIMIZATION
// File Comments
@ -608,14 +580,12 @@ __bend_from___b1:
__bend:
// main
main: {
.label c = 2
// [5] phi from main to main::@1 [phi:main->main::@1]
__b1_from_main:
// [5] phi (byte) idx#23 = (byte) 0 [phi:main->main::@1#0] -- vbuxx=vbuc1
ldx #0
// [5] phi (byte) main::c#2 = (byte) 0 [phi:main->main::@1#1] -- vbuz1=vbuc1
lda #0
sta.z c
// [5] phi (byte) main::c#2 = (byte) 0 [phi:main->main::@1#1] -- vbuyy=vbuc1
ldy #0
jmp __b1
// [5] phi from main::@2 to main::@1 [phi:main::@2->main::@1]
__b1_from___b2:
@ -624,8 +594,7 @@ main: {
jmp __b1
// main::@1
__b1:
// [6] (byte) outsw::c#0 ← (byte) main::c#2 -- vbuyy=vbuz1
ldy.z c
// [6] (byte) outsw::c#0 ← (byte) main::c#2
// [7] call outsw
// [11] phi from main::@1 to outsw [phi:main::@1->outsw]
outsw_from___b1:
@ -633,11 +602,10 @@ main: {
jmp __b2
// main::@2
__b2:
// [8] (byte) main::c#1 ← ++ (byte) main::c#2 -- vbuz1=_inc_vbuz1
inc.z c
// [9] if((byte) main::c#1!=(byte) $28) goto main::@1 -- vbuz1_neq_vbuc1_then_la1
lda #$28
cmp.z c
// [8] (byte) main::c#1 ← ++ (byte) main::c#2 -- vbuyy=_inc_vbuyy
iny
// [9] if((byte) main::c#1!=(byte) $28) goto main::@1 -- vbuyy_neq_vbuc1_then_la1
cpy #$28
bne __b1_from___b2
jmp __breturn
// main::@return
@ -649,17 +617,16 @@ main: {
// outsw(byte register(Y) c)
outsw: {
// [12] call out
// [23] phi from outsw to out [phi:outsw->out]
// [21] phi from outsw to out [phi:outsw->out]
out_from_outsw:
// [23] phi (byte) out::c#3 = (byte) '-' [phi:outsw->out#0] -- vbuaa=vbuc1
// [21] phi (byte) out::c#3 = (byte) '-' [phi:outsw->out#0] -- vbuaa=vbuc1
lda #'-'
// [23] phi (byte) idx#20 = (byte) idx#23 [phi:outsw->out#1] -- register_copy
// [21] phi (byte) idx#20 = (byte) idx#23 [phi:outsw->out#1] -- register_copy
jsr out
jmp __b1
// outsw::@1
__b1:
// [13] (byte) outw::c#0 ← (byte) outsw::c#0 -- vbuz1=vbuyy
sty.z outw.c
// [13] (byte) outw::c#0 ← (byte) outsw::c#0
// [14] call outw
jsr outw
jmp __breturn
@ -669,61 +636,52 @@ outsw: {
rts
}
// outw
// outw(byte zp(3) c)
// outw(byte register(Y) c)
outw: {
.label c = 3
// [16] (byte~) outw::$0 ← (byte) outw::c#0 << (byte) 4 -- vbuaa=vbuz1_rol_4
lda.z c
// [16] (byte) out::c#1 ← (byte) outw::c#0 << (byte) 4 -- vbuaa=vbuyy_rol_4
tya
asl
asl
asl
asl
// [17] (byte) out::c#1 ← *((const byte*) HEXTAB + (byte~) outw::$0) -- vbuaa=pbuc1_derefidx_vbuaa
tay
lda HEXTAB,y
// [18] call out
// [23] phi from outw to out [phi:outw->out]
// [17] call out
// [21] phi from outw to out [phi:outw->out]
out_from_outw:
// [23] phi (byte) out::c#3 = (byte) out::c#1 [phi:outw->out#0] -- register_copy
// [23] phi (byte) idx#20 = (byte) idx#10 [phi:outw->out#1] -- register_copy
// [21] phi (byte) out::c#3 = (byte) out::c#1 [phi:outw->out#0] -- register_copy
// [21] phi (byte) idx#20 = (byte) idx#10 [phi:outw->out#1] -- register_copy
jsr out
jmp __b1
// outw::@1
__b1:
// [19] (byte~) outw::$2 ← (byte) outw::c#0 & (byte) $f -- vbuaa=vbuz1_band_vbuc1
lda #$f
and.z c
// [20] (byte) out::c#2 ← *((const byte*) HEXTAB + (byte~) outw::$2) -- vbuaa=pbuc1_derefidx_vbuaa
tay
lda HEXTAB,y
// [21] call out
// [23] phi from outw::@1 to out [phi:outw::@1->out]
// [18] (byte) out::c#2 ← (byte) outw::c#0 & (byte) $f -- vbuaa=vbuyy_band_vbuc1
tya
and #$f
// [19] call out
// [21] phi from outw::@1 to out [phi:outw::@1->out]
out_from___b1:
// [23] phi (byte) out::c#3 = (byte) out::c#2 [phi:outw::@1->out#0] -- register_copy
// [23] phi (byte) idx#20 = (byte) idx#10 [phi:outw::@1->out#1] -- register_copy
// [21] phi (byte) out::c#3 = (byte) out::c#2 [phi:outw::@1->out#0] -- register_copy
// [21] phi (byte) idx#20 = (byte) idx#10 [phi:outw::@1->out#1] -- register_copy
jsr out
jmp __breturn
// outw::@return
__breturn:
// [22] return
// [20] return
rts
}
// out
// out(byte register(A) c)
out: {
// [24] (byte) idx#10 ← ++ (byte) idx#20 -- vbuxx=_inc_vbuxx
// [22] (byte) idx#10 ← ++ (byte) idx#20 -- vbuxx=_inc_vbuxx
inx
// [25] *((const byte*) SCREEN + (byte) idx#10) ← (byte) out::c#3 -- pbuc1_derefidx_vbuxx=vbuaa
// [23] *((const byte*) SCREEN + (byte) idx#10) ← (byte) out::c#3 -- pbuc1_derefidx_vbuxx=vbuaa
sta SCREEN,x
jmp __breturn
// out::@return
__breturn:
// [26] return
// [24] return
rts
}
// File Data
HEXTAB: .text "0123456789abcdef"
.byte 0
ASSEMBLER OPTIMIZATIONS
Removing instruction jmp __b1
@ -737,17 +695,16 @@ Removing instruction jmp __b1
Removing instruction jmp __breturn
Removing instruction jmp __breturn
Succesful ASM optimization Pass5NextJumpElimination
Replacing instruction lda #0 with TXA
Replacing label __b1_from___b2 with __b1
Removing instruction __b1_from___bbegin:
Removing instruction __b1:
Removing instruction main_from___b1:
Removing instruction __bend_from___b1:
Removing instruction __b1_from___b2:
Removing instruction outsw_from___b1:
Succesful ASM optimization Pass5RedundantLabelElimination
Removing instruction __bend:
Removing instruction __b1_from_main:
Removing instruction outsw_from___b1:
Removing instruction __b2:
Removing instruction __breturn:
Removing instruction out_from_outsw:
@ -771,10 +728,9 @@ FINAL SYMBOL TABLE
(label) @1
(label) @begin
(label) @end
(const byte*) HEXTAB[] = (byte*) "0123456789abcdef"
(const byte*) SCREEN = (byte*) 1024
(byte) idx
(byte) idx#10 reg byte x 12947.352941176468
(byte) idx#10 reg byte x 14673.666666666668
(byte) idx#20 reg byte x 121004.0
(byte) idx#23 reg byte x 367.33333333333337
(void()) main()
@ -782,8 +738,8 @@ FINAL SYMBOL TABLE
(label) main::@2
(label) main::@return
(byte) main::c
(byte) main::c#1 c zp[1]:2 151.5
(byte) main::c#2 c zp[1]:2 101.0
(byte) main::c#1 reg byte y 151.5
(byte) main::c#2 reg byte y 101.0
(void()) out((byte) out::c)
(label) out::@return
(byte) out::c
@ -796,24 +752,20 @@ FINAL SYMBOL TABLE
(byte) outsw::c
(byte) outsw::c#0 reg byte y 367.33333333333337
(void()) outw((byte) outw::c)
(byte~) outw::$0 reg byte a 20002.0
(byte~) outw::$2 reg byte a 20002.0
(label) outw::@1
(label) outw::@return
(byte) outw::c
(byte) outw::c#0 c zp[1]:3 5250.75
(byte) outw::c#0 reg byte y 7001.0
zp[1]:2 [ main::c#2 main::c#1 ]
reg byte y [ main::c#2 main::c#1 ]
reg byte x [ idx#20 idx#23 idx#10 ]
reg byte a [ out::c#3 out::c#1 out::c#2 ]
reg byte y [ outsw::c#0 ]
zp[1]:3 [ outw::c#0 ]
reg byte a [ outw::$0 ]
reg byte a [ outw::$2 ]
reg byte y [ outw::c#0 ]
FINAL ASSEMBLER
Score: 319
Score: 182
// File Comments
// Test effective live range and register allocation
@ -833,31 +785,27 @@ Score: 319
// @end
// main
main: {
.label c = 2
// [5] phi from main to main::@1 [phi:main->main::@1]
// [5] phi (byte) idx#23 = (byte) 0 [phi:main->main::@1#0] -- vbuxx=vbuc1
ldx #0
// [5] phi (byte) main::c#2 = (byte) 0 [phi:main->main::@1#1] -- vbuz1=vbuc1
txa
sta.z c
// [5] phi (byte) main::c#2 = (byte) 0 [phi:main->main::@1#1] -- vbuyy=vbuc1
ldy #0
// [5] phi from main::@2 to main::@1 [phi:main::@2->main::@1]
// [5] phi (byte) idx#23 = (byte) idx#10 [phi:main::@2->main::@1#0] -- register_copy
// [5] phi (byte) main::c#2 = (byte) main::c#1 [phi:main::@2->main::@1#1] -- register_copy
// main::@1
__b1:
// outsw(c)
// [6] (byte) outsw::c#0 ← (byte) main::c#2 -- vbuyy=vbuz1
ldy.z c
// [6] (byte) outsw::c#0 ← (byte) main::c#2
// [7] call outsw
// [11] phi from main::@1 to outsw [phi:main::@1->outsw]
jsr outsw
// main::@2
// for(char c: 0..39 )
// [8] (byte) main::c#1 ← ++ (byte) main::c#2 -- vbuz1=_inc_vbuz1
inc.z c
// [9] if((byte) main::c#1!=(byte) $28) goto main::@1 -- vbuz1_neq_vbuc1_then_la1
lda #$28
cmp.z c
// [8] (byte) main::c#1 ← ++ (byte) main::c#2 -- vbuyy=_inc_vbuyy
iny
// [9] if((byte) main::c#1!=(byte) $28) goto main::@1 -- vbuyy_neq_vbuc1_then_la1
cpy #$28
bne __b1
// main::@return
// }
@ -869,15 +817,14 @@ main: {
outsw: {
// out('-')
// [12] call out
// [23] phi from outsw to out [phi:outsw->out]
// [23] phi (byte) out::c#3 = (byte) '-' [phi:outsw->out#0] -- vbuaa=vbuc1
// [21] phi from outsw to out [phi:outsw->out]
// [21] phi (byte) out::c#3 = (byte) '-' [phi:outsw->out#0] -- vbuaa=vbuc1
lda #'-'
// [23] phi (byte) idx#20 = (byte) idx#23 [phi:outsw->out#1] -- register_copy
// [21] phi (byte) idx#20 = (byte) idx#23 [phi:outsw->out#1] -- register_copy
jsr out
// outsw::@1
// outw(c)
// [13] (byte) outw::c#0 ← (byte) outsw::c#0 -- vbuz1=vbuyy
sty.z outw.c
// [13] (byte) outw::c#0 ← (byte) outsw::c#0
// [14] call outw
jsr outw
// outsw::@return
@ -886,59 +833,48 @@ outsw: {
rts
}
// outw
// outw(byte zp(3) c)
// outw(byte register(Y) c)
outw: {
.label c = 3
// c<<4
// [16] (byte~) outw::$0 ← (byte) outw::c#0 << (byte) 4 -- vbuaa=vbuz1_rol_4
lda.z c
// out(c<<4)
// [16] (byte) out::c#1 ← (byte) outw::c#0 << (byte) 4 -- vbuaa=vbuyy_rol_4
tya
asl
asl
asl
asl
// out(HEXTAB[c<<4])
// [17] (byte) out::c#1 ← *((const byte*) HEXTAB + (byte~) outw::$0) -- vbuaa=pbuc1_derefidx_vbuaa
tay
lda HEXTAB,y
// [18] call out
// [23] phi from outw to out [phi:outw->out]
// [23] phi (byte) out::c#3 = (byte) out::c#1 [phi:outw->out#0] -- register_copy
// [23] phi (byte) idx#20 = (byte) idx#10 [phi:outw->out#1] -- register_copy
// [17] call out
// [21] phi from outw to out [phi:outw->out]
// [21] phi (byte) out::c#3 = (byte) out::c#1 [phi:outw->out#0] -- register_copy
// [21] phi (byte) idx#20 = (byte) idx#10 [phi:outw->out#1] -- register_copy
jsr out
// outw::@1
// c&0x0f
// [19] (byte~) outw::$2 ← (byte) outw::c#0 & (byte) $f -- vbuaa=vbuz1_band_vbuc1
lda #$f
and.z c
// out(HEXTAB[c&0x0f])
// [20] (byte) out::c#2 ← *((const byte*) HEXTAB + (byte~) outw::$2) -- vbuaa=pbuc1_derefidx_vbuaa
tay
lda HEXTAB,y
// [21] call out
// [23] phi from outw::@1 to out [phi:outw::@1->out]
// [23] phi (byte) out::c#3 = (byte) out::c#2 [phi:outw::@1->out#0] -- register_copy
// [23] phi (byte) idx#20 = (byte) idx#10 [phi:outw::@1->out#1] -- register_copy
// out(c&0x0f)
// [18] (byte) out::c#2 ← (byte) outw::c#0 & (byte) $f -- vbuaa=vbuyy_band_vbuc1
tya
and #$f
// [19] call out
// [21] phi from outw::@1 to out [phi:outw::@1->out]
// [21] phi (byte) out::c#3 = (byte) out::c#2 [phi:outw::@1->out#0] -- register_copy
// [21] phi (byte) idx#20 = (byte) idx#10 [phi:outw::@1->out#1] -- register_copy
jsr out
// outw::@return
// }
// [22] return
// [20] return
rts
}
// out
// out(byte register(A) c)
out: {
// idx++;
// [24] (byte) idx#10 ← ++ (byte) idx#20 -- vbuxx=_inc_vbuxx
// [22] (byte) idx#10 ← ++ (byte) idx#20 -- vbuxx=_inc_vbuxx
inx
// SCREEN[idx] = c
// [25] *((const byte*) SCREEN + (byte) idx#10) ← (byte) out::c#3 -- pbuc1_derefidx_vbuxx=vbuaa
// [23] *((const byte*) SCREEN + (byte) idx#10) ← (byte) out::c#3 -- pbuc1_derefidx_vbuxx=vbuaa
sta SCREEN,x
// out::@return
// }
// [26] return
// [24] return
rts
}
// File Data
HEXTAB: .text "0123456789abcdef"
.byte 0

17
src/test/ref/liverange-9.sym
View File

@ -1,10 +1,9 @@
(label) @1
(label) @begin
(label) @end
(const byte*) HEXTAB[] = (byte*) "0123456789abcdef"
(const byte*) SCREEN = (byte*) 1024
(byte) idx
(byte) idx#10 reg byte x 12947.352941176468
(byte) idx#10 reg byte x 14673.666666666668
(byte) idx#20 reg byte x 121004.0
(byte) idx#23 reg byte x 367.33333333333337
(void()) main()
@ -12,8 +11,8 @@
(label) main::@2
(label) main::@return
(byte) main::c
(byte) main::c#1 c zp[1]:2 151.5
(byte) main::c#2 c zp[1]:2 101.0
(byte) main::c#1 reg byte y 151.5
(byte) main::c#2 reg byte y 101.0
(void()) out((byte) out::c)
(label) out::@return
(byte) out::c
@ -26,17 +25,13 @@
(byte) outsw::c
(byte) outsw::c#0 reg byte y 367.33333333333337
(void()) outw((byte) outw::c)
(byte~) outw::$0 reg byte a 20002.0
(byte~) outw::$2 reg byte a 20002.0
(label) outw::@1
(label) outw::@return
(byte) outw::c
(byte) outw::c#0 c zp[1]:3 5250.75
(byte) outw::c#0 reg byte y 7001.0
zp[1]:2 [ main::c#2 main::c#1 ]
reg byte y [ main::c#2 main::c#1 ]
reg byte x [ idx#20 idx#23 idx#10 ]
reg byte a [ out::c#3 out::c#1 out::c#2 ]
reg byte y [ outsw::c#0 ]
zp[1]:3 [ outw::c#0 ]
reg byte a [ outw::$0 ]
reg byte a [ outw::$2 ]
reg byte y [ outw::c#0 ]