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Merged CX16 veralib progress.

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jespergravgaard 2021-02-01 21:52:35 +01:00
parent c32857c87f
commit fa9736d15b
8 changed files with 51864 additions and 0 deletions
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src/test/ref/examples/cx16/veralib/bitmap_8bpp_320_x_240.asm Normal file
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src/test/ref/examples/cx16/veralib/bitmap_8bpp_320_x_240.cfg Normal file
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src/test/ref/examples/cx16/veralib/tilemap_8bpp_16_x_16.asm Normal file
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src/test/ref/examples/cx16/veralib/tilemap_8bpp_16_x_16.cfg Normal file
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const nomodify byte BLACK = 0
const nomodify byte BLUE = 6
byte CONIO_SCREEN_BANK
byte CONIO_SCREEN_BANK#15 CONIO_SCREEN_BANK zp[1]:39 66.48502994011976
byte* CONIO_SCREEN_TEXT
word CONIO_SCREEN_TEXT#17 CONIO_SCREEN_TEXT zp[2]:40 0.4675925925925926
const byte RADIX::BINARY = 2
const byte RADIX::DECIMAL = $a
const byte RADIX::HEXADECIMAL = $10
const byte RADIX::OCTAL = 8
const byte SIZEOF_POINTER = 2
const nomodify byte VERA_ADDRSEL = 1
const nomodify byte* VERA_ADDRX_H = (byte*) 40738
const nomodify byte* VERA_ADDRX_L = (byte*) 40736
const nomodify byte* VERA_ADDRX_M = (byte*) 40737
const nomodify byte* VERA_CTRL = (byte*) 40741
const nomodify byte* VERA_DATA0 = (byte*) 40739
const nomodify byte* VERA_DATA1 = (byte*) 40740
const nomodify byte* VERA_DC_HSCALE = (byte*) 40746
const nomodify byte* VERA_DC_VIDEO = (byte*) 40745
const nomodify byte* VERA_DC_VSCALE = (byte*) 40747
const nomodify byte VERA_INC_1 = $10
const nomodify byte* VERA_L0_CONFIG = (byte*) 40749
const nomodify byte* VERA_L0_MAPBASE = (byte*) 40750
const nomodify byte* VERA_L0_TILEBASE = (byte*) 40751
const nomodify byte* VERA_L1_CONFIG = (byte*) 40756
const nomodify byte* VERA_L1_MAPBASE = (byte*) 40757
const nomodify byte* VERA_L1_TILEBASE = (byte*) 40758
const nomodify byte VERA_LAYER0_ENABLE = $10
const nomodify byte VERA_LAYER1_ENABLE = $20
const nomodify byte VERA_LAYER_COLOR_DEPTH_1BPP = 0
const nomodify byte VERA_LAYER_COLOR_DEPTH_2BPP = 1
const nomodify byte VERA_LAYER_COLOR_DEPTH_4BPP = 2
const nomodify byte VERA_LAYER_COLOR_DEPTH_8BPP = 3
const nomodify byte VERA_LAYER_CONFIG_256C = 8
const to_nomodify word* VERA_LAYER_HEIGHT[4] = { $20, $40, $80, $100 }
const nomodify byte VERA_LAYER_HEIGHT_128 = $80
const nomodify byte VERA_LAYER_HEIGHT_256 = $c0
const nomodify byte VERA_LAYER_HEIGHT_64 = $40
const nomodify byte VERA_LAYER_HEIGHT_MASK = $c0
const nomodify byte VERA_LAYER_TILEBASE_MASK = $fc
const to_nomodify word* VERA_LAYER_WIDTH[4] = { $20, $40, $80, $100 }
const nomodify byte VERA_LAYER_WIDTH_128 = $20
const nomodify byte VERA_LAYER_WIDTH_256 = $30
const nomodify byte VERA_LAYER_WIDTH_64 = $10
const nomodify byte VERA_LAYER_WIDTH_MASK = $30
const nomodify byte VERA_TILEBASE_HEIGHT_16 = 2
const nomodify byte VERA_TILEBASE_WIDTH_16 = 1
const nomodify byte WHITE = 1
void __start()
void clearline()
byte~ clearline::$1 reg byte a 2.00000002E8
byte~ clearline::$2 reg byte a 2.00000002E8
byte~ clearline::$5 reg byte a 2.00000002E8
byte* clearline::addr
byte* clearline::addr#0 addr zp[2]:77 1.00000001E8
word clearline::c
word clearline::c#1 c zp[2]:73 2.0000000002E10
word clearline::c#2 c zp[2]:73 7.50000000075E9
byte clearline::color
byte clearline::color#0 reg byte x 1.6833333336666665E9
void clrscr()
byte~ clrscr::$0 reg byte a 202.0
byte~ clrscr::$1 zp[1]:58 40.4
byte~ clrscr::$2 reg byte a 202.0
byte~ clrscr::$5 reg byte a 2002.0
byte~ clrscr::$6 reg byte a 2002.0
byte~ clrscr::$7 reg byte a 2002.0
byte~ clrscr::$9 reg byte a 202.0
byte clrscr::c
byte clrscr::c#1 reg byte y 20002.0
byte clrscr::c#2 reg byte y 7500.75
byte* clrscr::ch
byte clrscr::color
byte clrscr::color#0 color zp[1]:58 594.2352941176471
byte clrscr::l
byte clrscr::l#1 reg byte x 2002.0
byte clrscr::l#2 reg byte x 200.2
byte* clrscr::line_text
byte* clrscr::line_text#0 line_text zp[2]:69 18.363636363636363
byte* clrscr::line_text#1 line_text zp[2]:69 1001.0
byte* clrscr::line_text#2 line_text zp[2]:69 293.2142857142857
const byte* conio_cursor_x[2] = { 0, 0 }
const byte* conio_cursor_y[2] = { 0, 0 }
word conio_height loadstore zp[2]:34 6629.834437086093
const word* conio_line_text[2] = { 0, 0 }
byte conio_rowshift loadstore zp[1]:36 5941177.088235294
word conio_rowskip loadstore zp[2]:37 5650288.734463277
volatile byte conio_screen_height loadstore zp[1]:30 76433.29299363057
byte conio_screen_layer loadstore zp[1]:31 1374285.1199999999
volatile byte conio_screen_width loadstore zp[1]:29 5.191715029015544E7
const byte* conio_scroll_enable[2] = { 1, 1 }
word conio_width loadstore zp[2]:32 131.40522875816993
void conio_x16_init()
const nomodify byte* conio_x16_init::BASIC_CURSOR_LINE = (byte*) 214
byte conio_x16_init::line
byte conio_x16_init::line#0 line zp[1]:2 2.1999999999999997
byte conio_x16_init::line#1 line zp[1]:2 22.0
byte conio_x16_init::line#3 line zp[1]:2 33.0
void cputc(byte cputc::c)
byte~ cputc::$15 reg byte a 20002.0
word~ cputc::$16 zp[2]:71 20002.0
byte~ cputc::$2 reg byte a 20002.0
byte~ cputc::$4 reg byte a 20002.0
byte~ cputc::$5 reg byte a 20002.0
byte~ cputc::$6 reg byte a 20002.0
byte cputc::c
byte cputc::c#0 c zp[1]:63 1235.4705882352941
byte cputc::color
byte cputc::color#0 reg byte x 1428.7142857142858
byte* cputc::conio_addr
byte* cputc::conio_addr#0 conio_addr zp[2]:69 10001.0
byte* cputc::conio_addr#1 conio_addr zp[2]:69 6000.6
byte cputc::scroll_enable
byte cputc::scroll_enable#0 reg byte a 20002.0
void cputln()
byte~ cputln::$2 reg byte a 200002.0
byte~ cputln::$3 reg byte a 200002.0
word cputln::temp
word cputln::temp#0 temp zp[2]:73 200002.0
word cputln::temp#1 temp zp[2]:73 100001.0
void cputs(to_nomodify byte* cputs::s)
byte cputs::c
byte cputs::c#1 reg byte a 1001.0
to_nomodify byte* cputs::s
to_nomodify byte* cputs::s#0 s zp[2]:59 500.5
to_nomodify byte* cputs::s#10 s zp[2]:59 101.0
to_nomodify byte* cputs::s#9 s zp[2]:59 1552.0
void cscroll()
void gotoxy(byte gotoxy::x , byte gotoxy::y)
byte~ gotoxy::$5 reg byte a 2.0000002E7
word~ gotoxy::$6 zp[2]:44 2.0000002E7
word gotoxy::line_offset
word gotoxy::line_offset#0 line_offset zp[2]:44 1.0000001E7
byte gotoxy::x
byte gotoxy::y
byte gotoxy::y#0 reg byte x 22.0
byte gotoxy::y#2 reg byte x 2000002.0
byte gotoxy::y#4 reg byte x 7000004.666666666
byte gotoxy::y#5 reg byte x 4000000.4
void insertup()
byte~ insertup::$3 reg byte a 2.000000002E9
byte insertup::cy
byte insertup::cy#0 cy zp[1]:75 7.769230784615384E7
byte insertup::i
byte insertup::i#1 reg byte x 2.000000002E9
byte insertup::i#2 reg byte x 4.000000004E8
word insertup::line
word insertup::line#0 line zp[2]:71 2.000000002E9
byte* insertup::start
byte* insertup::start#0 start zp[2]:71 1.000000001E9
byte insertup::width
byte insertup::width#0 width zp[1]:76 8.416666683333334E7
byte kbhit()
const nomodify byte* kbhit::GETIN = (byte*) 65508
const nomodify byte* kbhit::IN_DEV = (byte*) 650
volatile byte kbhit::ch loadstore zp[1]:64 1001.0
const nomodify byte* kbhit::chptr = &kbhit::ch
byte kbhit::return
byte kbhit::return#0 reg byte a 2002.0
byte kbhit::return#1 reg byte a 300.75
byte kbhit::return#2 reg byte a 202.0
byte kbhit::return#3 reg byte a 202.0
void main()
byte~ main::$35 reg byte a 202.0
byte~ main::$40 reg byte a 202.0
byte main::bgcolor1_color
byte main::bgcolor2_color
byte main::c
byte main::c#1 c zp[1]:10 1501.5
byte main::c#2 c zp[1]:10 250.25
byte main::c1
byte main::c1#1 reg byte x 1501.5
byte main::c1#2 reg byte x 250.25
byte main::column
byte main::column#1 reg byte x 400.4
byte main::column#2 reg byte x 600.5999999999999
byte main::column1
byte main::column1#1 column1 zp[1]:12 400.4
byte main::column1#2 column1 zp[1]:12 600.5999999999999
byte main::p
byte main::p#1 reg byte x 1501.5
byte main::p#2 reg byte x 2002.0
byte main::r
byte main::r#1 r zp[1]:7 151.5
byte main::r#5 r zp[1]:7 16.833333333333332
byte main::r1
byte main::r1#1 r1 zp[1]:11 151.5
byte main::r1#5 r1 zp[1]:11 16.833333333333332
byte main::row
byte main::row#1 row zp[1]:6 67.33333333333333
byte main::row#10 row zp[1]:6 109.36363636363637
byte main::row#3 row zp[1]:6 67.33333333333333
byte main::row#9 row zp[1]:6 109.36363636363637
const byte* main::s[$38] = "vera in tile mode 8 x 8, color depth 8 bits per pixel.
"
const byte* main::s1[$3a] = "in this mode, tiles are 8 pixels wide and 8 pixels tall.
"
const byte* main::s2[$2f] = "each tile can have a variation of 256 colors.
"
const byte* main::s3[$44] = "the vera palette of 256 colors, can be used by setting the palette
"
const byte* main::s4[$17] = "offset for each tile.
"
const byte* main::s5[$4b] = "here each column is displaying the same tile, but with different offsets!
"
const byte* main::s6[$3f] = "each offset aligns to multiples of 16 colors in the palette!.
"
const byte* main::s7[$3e] = "however, the first color will always be transparent (black).
"
byte main::t
byte main::t#1 t zp[1]:5 151.5
byte main::t#5 t zp[1]:5 25.25
byte main::textcolor1_color
byte main::textcolor2_color
word main::tile
word main::tile#1 tile zp[2]:8 2002.0
word main::tile#10 tile zp[2]:8 202.0
word main::tile#11 tile zp[2]:8 202.0
word main::tile#12 tile zp[2]:8 350.5
word main::tile#13 tile zp[2]:8 350.5
word main::tile#4 tile zp[2]:8 2002.0
word main::tile#6 tile zp[2]:8 517.3333333333334
word main::tile#8 tile zp[2]:8 517.3333333333334
word main::tilebase
word main::tilebase#2 tilebase zp[2]:3 67.33333333333333
word main::tilebase#7 tilebase zp[2]:3 28.857142857142858
const byte* main::tiles[$100] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
byte~ main::vera_layer_hide1_$0 reg byte a 22.0
byte main::vera_layer_hide1_layer
byte main::vera_layer_show1_layer
void memcpy_in_vram(byte memcpy_in_vram::dest_bank , void* memcpy_in_vram::dest , byte memcpy_in_vram::dest_increment , byte memcpy_in_vram::src_bank , void* memcpy_in_vram::src , byte memcpy_in_vram::src_increment , word memcpy_in_vram::num)
byte~ memcpy_in_vram::$0 reg byte a 2.0000000002E10
byte~ memcpy_in_vram::$1 reg byte a 2.0000000002E10
byte~ memcpy_in_vram::$2 reg byte a 2.0000000002E10
byte~ memcpy_in_vram::$3 reg byte a 2.0000000002E10
byte~ memcpy_in_vram::$4 reg byte a 2.0000000002E10
byte~ memcpy_in_vram::$5 reg byte a 2.0000000002E10
void* memcpy_in_vram::dest
void* memcpy_in_vram::dest#0 dest zp[2]:71 6.666666673333334E8
void* memcpy_in_vram::dest#3 dest zp[2]:71 1.9090909093636363E9
byte memcpy_in_vram::dest_bank
byte memcpy_in_vram::dest_bank#3 dest_bank zp[1]:24 7.692307693076923E8
byte memcpy_in_vram::dest_increment
word memcpy_in_vram::i
word memcpy_in_vram::i#1 i zp[2]:73 2.00000000002E11
word memcpy_in_vram::i#2 i zp[2]:73 1.00000000001E11
word memcpy_in_vram::num
word memcpy_in_vram::num#0 num zp[2]:77 1.000000001E9
word memcpy_in_vram::num#4 num zp[2]:77 5.315789473789474E9
void* memcpy_in_vram::src
byte* memcpy_in_vram::src#0 src zp[2]:69 3.333333336666667E8
void* memcpy_in_vram::src#3 src zp[2]:69 5.25000000075E9
void* memcpy_in_vram::src#4 src zp[2]:69 2.000000002E9
byte memcpy_in_vram::src_bank
byte memcpy_in_vram::src_bank#3 reg byte y 1.6666666668333333E9
byte memcpy_in_vram::src_increment
void memcpy_to_vram(byte memcpy_to_vram::vbank , void* memcpy_to_vram::vdest , void* memcpy_to_vram::src , word memcpy_to_vram::num)
byte~ memcpy_to_vram::$0 reg byte a 2002.0
byte~ memcpy_to_vram::$1 reg byte a 2002.0
byte* memcpy_to_vram::end
const byte* memcpy_to_vram::end#0 end = (byte*)(void*)main::tiles+$100
word memcpy_to_vram::num
byte* memcpy_to_vram::s
byte* memcpy_to_vram::s#1 s zp[2]:77 200002.0
byte* memcpy_to_vram::s#2 s zp[2]:77 133334.66666666666
void* memcpy_to_vram::src
byte memcpy_to_vram::vbank
void* memcpy_to_vram::vdest
void* memcpy_to_vram::vdest#1 vdest zp[2]:71 202.0
void* memcpy_to_vram::vdest#2 vdest zp[2]:71 525.75
void screenlayer(byte screenlayer::layer)
word~ screenlayer::$2 zp[2]:52 202.0
byte~ screenlayer::$3 reg byte a 202.0
word~ screenlayer::$4 zp[2]:44 202.0
word~ screenlayer::$5 zp[2]:49 202.0
byte screenlayer::layer
byte~ screenlayer::vera_layer_get_height1_$0 reg byte a 202.0
byte~ screenlayer::vera_layer_get_height1_$1 reg byte a 202.0
byte~ screenlayer::vera_layer_get_height1_$2 reg byte a 202.0
byte~ screenlayer::vera_layer_get_height1_$3 reg byte a 202.0
byte* screenlayer::vera_layer_get_height1_config
byte* screenlayer::vera_layer_get_height1_config#0 vera_layer_get_height1_config zp[2]:46 202.0
byte screenlayer::vera_layer_get_height1_layer
byte screenlayer::vera_layer_get_height1_layer#0 reg byte a 202.0
word screenlayer::vera_layer_get_height1_return
word screenlayer::vera_layer_get_height1_return#0 vera_layer_get_height1_return zp[2]:49 202.0
word screenlayer::vera_layer_get_height1_return#1 vera_layer_get_height1_return zp[2]:49 202.0
byte~ screenlayer::vera_layer_get_width1_$0 reg byte a 202.0
byte~ screenlayer::vera_layer_get_width1_$1 reg byte a 202.0
byte~ screenlayer::vera_layer_get_width1_$2 reg byte a 202.0
byte~ screenlayer::vera_layer_get_width1_$3 reg byte a 202.0
byte* screenlayer::vera_layer_get_width1_config
byte* screenlayer::vera_layer_get_width1_config#0 vera_layer_get_width1_config zp[2]:42 202.0
byte screenlayer::vera_layer_get_width1_layer
byte screenlayer::vera_layer_get_width1_layer#0 reg byte a 202.0
word screenlayer::vera_layer_get_width1_return
word screenlayer::vera_layer_get_width1_return#0 vera_layer_get_width1_return zp[2]:52 202.0
word screenlayer::vera_layer_get_width1_return#1 vera_layer_get_width1_return zp[2]:52 202.0
void screensize(byte* screensize::x , byte* screensize::y)
byte~ screensize::$1 reg byte a 202.0
byte~ screensize::$3 reg byte a 202.0
byte screensize::hscale
byte screensize::hscale#0 reg byte a 202.0
byte screensize::vscale
byte screensize::vscale#0 reg byte a 202.0
byte* screensize::x
const byte* screensize::x#0 x = &conio_screen_width
byte* screensize::y
const byte* screensize::y#0 y = &conio_screen_height
const byte* vera_layer_backcolor[2] = { BLUE, BLUE }
const byte** vera_layer_config[2] = { VERA_L0_CONFIG, VERA_L1_CONFIG }
const byte* vera_layer_enable[2] = { VERA_LAYER0_ENABLE, VERA_LAYER1_ENABLE }
byte vera_layer_get_backcolor(byte vera_layer_get_backcolor::layer)
byte vera_layer_get_backcolor::layer
byte vera_layer_get_backcolor::layer#0 reg byte x 1102.0
byte vera_layer_get_backcolor::return
byte vera_layer_get_backcolor::return#0 reg byte a 367.33333333333337
byte vera_layer_get_backcolor::return#2 reg byte a 202.0
byte vera_layer_get_color(byte vera_layer_get_color::layer)
byte~ vera_layer_get_color::$0 reg byte a 2.000000002E9
byte~ vera_layer_get_color::$1 reg byte a 2.000000002E9
byte~ vera_layer_get_color::$3 reg byte a 2.000000002E9
byte* vera_layer_get_color::addr
byte* vera_layer_get_color::addr#0 addr zp[2]:77 2.000000002E9
byte vera_layer_get_color::layer
byte vera_layer_get_color::layer#0 reg byte x 20002.0
byte vera_layer_get_color::layer#1 reg byte x 2.00000002E8
byte vera_layer_get_color::layer#2 reg byte x 6.833350010000001E8
byte vera_layer_get_color::return
byte vera_layer_get_color::return#0 reg byte a 2.000000002E9
byte vera_layer_get_color::return#1 reg byte a 2.000000002E9
byte vera_layer_get_color::return#2 reg byte a 5.25002501E8
byte vera_layer_get_color::return#3 reg byte a 20002.0
byte vera_layer_get_color::return#4 reg byte a 2.00000002E8
byte vera_layer_get_mapbase_bank(byte vera_layer_get_mapbase_bank::layer)
byte vera_layer_get_mapbase_bank::layer
byte vera_layer_get_mapbase_bank::layer#0 reg byte x 1102.0
byte vera_layer_get_mapbase_bank::return
byte vera_layer_get_mapbase_bank::return#0 reg byte a 367.33333333333337
byte vera_layer_get_mapbase_bank::return#2 reg byte a 202.0
word vera_layer_get_mapbase_offset(byte vera_layer_get_mapbase_offset::layer)
byte~ vera_layer_get_mapbase_offset::$0 reg byte a 2002.0
byte vera_layer_get_mapbase_offset::layer
byte vera_layer_get_mapbase_offset::layer#0 reg byte a 1102.0
word vera_layer_get_mapbase_offset::return
word vera_layer_get_mapbase_offset::return#0 return zp[2]:44 367.33333333333337
word vera_layer_get_mapbase_offset::return#2 return zp[2]:44 202.0
byte vera_layer_get_rowshift(byte vera_layer_get_rowshift::layer)
byte vera_layer_get_rowshift::layer
byte vera_layer_get_rowshift::layer#0 reg byte x 1102.0
byte vera_layer_get_rowshift::return
byte vera_layer_get_rowshift::return#0 reg byte a 367.33333333333337
byte vera_layer_get_rowshift::return#2 reg byte a 202.0
word vera_layer_get_rowskip(byte vera_layer_get_rowskip::layer)
byte~ vera_layer_get_rowskip::$0 reg byte a 2002.0
byte vera_layer_get_rowskip::layer
byte vera_layer_get_rowskip::layer#0 reg byte a 1102.0
word vera_layer_get_rowskip::return
word vera_layer_get_rowskip::return#0 return zp[2]:44 367.33333333333337
word vera_layer_get_rowskip::return#2 return zp[2]:44 202.0
byte vera_layer_get_textcolor(byte vera_layer_get_textcolor::layer)
byte vera_layer_get_textcolor::layer
byte vera_layer_get_textcolor::layer#0 reg byte x 1102.0
byte vera_layer_get_textcolor::return
byte vera_layer_get_textcolor::return#0 reg byte a 367.33333333333337
byte vera_layer_get_textcolor::return#2 reg byte a 202.0
const to_nomodify byte* vera_layer_hflip[2] = { 0, 4 }
const byte** vera_layer_mapbase[2] = { VERA_L0_MAPBASE, VERA_L1_MAPBASE }
void vera_layer_mode_text(byte vera_layer_mode_text::layer , dword vera_layer_mode_text::mapbase_address , dword vera_layer_mode_text::tilebase_address , word vera_layer_mode_text::mapwidth , word vera_layer_mode_text::mapheight , byte vera_layer_mode_text::tilewidth , byte vera_layer_mode_text::tileheight , word vera_layer_mode_text::color_mode)
word vera_layer_mode_text::color_mode
byte vera_layer_mode_text::layer
const byte vera_layer_mode_text::layer#0 layer = 1
dword vera_layer_mode_text::mapbase_address
const dword vera_layer_mode_text::mapbase_address#0 mapbase_address = 0
word vera_layer_mode_text::mapheight
const word vera_layer_mode_text::mapheight#0 mapheight = $40
word vera_layer_mode_text::mapwidth
const word vera_layer_mode_text::mapwidth#0 mapwidth = $80
dword vera_layer_mode_text::tilebase_address
const dword vera_layer_mode_text::tilebase_address#0 tilebase_address = $f800
byte vera_layer_mode_text::tileheight
const byte vera_layer_mode_text::tileheight#0 tileheight = 8
byte vera_layer_mode_text::tilewidth
const byte vera_layer_mode_text::tilewidth#0 tilewidth = 8
void vera_layer_mode_tile(byte vera_layer_mode_tile::layer , dword vera_layer_mode_tile::mapbase_address , dword vera_layer_mode_tile::tilebase_address , word vera_layer_mode_tile::mapwidth , word vera_layer_mode_tile::mapheight , byte vera_layer_mode_tile::tilewidth , byte vera_layer_mode_tile::tileheight , byte vera_layer_mode_tile::color_depth)
word~ vera_layer_mode_tile::$1 zp[2]:46 1001.0
word~ vera_layer_mode_tile::$10 zp[2]:56 2002.0
byte~ vera_layer_mode_tile::$13 reg byte a 2002.0
byte~ vera_layer_mode_tile::$14 reg byte a 2002.0
byte~ vera_layer_mode_tile::$15 reg byte a 2002.0
byte~ vera_layer_mode_tile::$16 reg byte a 2002.0
byte~ vera_layer_mode_tile::$19 zp[1]:48 231.0
word~ vera_layer_mode_tile::$2 zp[2]:49 1001.0
byte~ vera_layer_mode_tile::$20 zp[1]:51 250.25
word~ vera_layer_mode_tile::$4 zp[2]:65 2002.0
word~ vera_layer_mode_tile::$7 zp[2]:52 2002.0
word~ vera_layer_mode_tile::$8 zp[2]:54 1001.0
byte vera_layer_mode_tile::color_depth
byte vera_layer_mode_tile::color_depth#5 reg byte x 1001.0
byte vera_layer_mode_tile::config
byte vera_layer_mode_tile::config#10 reg byte x 2002.0
byte vera_layer_mode_tile::config#11 reg byte x 2002.0
byte vera_layer_mode_tile::config#12 reg byte x 2002.0
byte vera_layer_mode_tile::config#17 reg byte x 625.625
byte vera_layer_mode_tile::config#21 reg byte x 2002.0000000000002
byte vera_layer_mode_tile::config#25 reg byte x 3003.0
byte vera_layer_mode_tile::config#6 reg byte x 500.5
byte vera_layer_mode_tile::config#7 reg byte x 500.5
byte vera_layer_mode_tile::config#8 reg byte x 500.5
byte vera_layer_mode_tile::layer
byte vera_layer_mode_tile::layer#10 layer zp[1]:13 220.80882352941177
byte vera_layer_mode_tile::mapbase
byte vera_layer_mode_tile::mapbase#0 reg byte x 1001.0
dword vera_layer_mode_tile::mapbase_address
dword vera_layer_mode_tile::mapbase_address#0 mapbase_address zp[4]:14 2002.0
dword vera_layer_mode_tile::mapbase_address#10 mapbase_address zp[4]:14 88.97777777777777
word vera_layer_mode_tile::mapheight
word vera_layer_mode_tile::mapheight#10 mapheight zp[2]:42 133.46666666666667
word vera_layer_mode_tile::mapwidth
word vera_layer_mode_tile::mapwidth#10 mapwidth zp[2]:44 400.4
byte vera_layer_mode_tile::tilebase
byte vera_layer_mode_tile::tilebase#0 reg byte a 2002.0
byte vera_layer_mode_tile::tilebase#1 reg byte x 1334.6666666666667
byte vera_layer_mode_tile::tilebase#10 reg byte x 2002.0
byte vera_layer_mode_tile::tilebase#12 reg byte x 2002.0000000000002
byte vera_layer_mode_tile::tilebase#3 reg byte x 2002.0
byte vera_layer_mode_tile::tilebase#5 reg byte x 2002.0
dword vera_layer_mode_tile::tilebase_address
dword vera_layer_mode_tile::tilebase_address#0 tilebase_address zp[4]:18 2002.0
dword vera_layer_mode_tile::tilebase_address#10 tilebase_address zp[4]:18 71.5
byte vera_layer_mode_tile::tileheight
byte vera_layer_mode_tile::tileheight#10 tileheight zp[1]:23 30.8
byte vera_layer_mode_tile::tilewidth
byte vera_layer_mode_tile::tilewidth#10 tilewidth zp[1]:22 32.81967213114754
const byte* vera_layer_rowshift[2] = { 0, 0 }
const word* vera_layer_rowskip[2] = { 0, 0 }
byte vera_layer_set_backcolor(byte vera_layer_set_backcolor::layer , byte vera_layer_set_backcolor::color)
byte vera_layer_set_backcolor::color
byte vera_layer_set_backcolor::color#3 reg byte a 101.0
byte vera_layer_set_backcolor::layer
byte vera_layer_set_backcolor::layer#1 reg byte x 22.0
byte vera_layer_set_backcolor::layer#2 reg byte x 22.0
byte vera_layer_set_backcolor::layer#3 reg byte x 123.0
byte vera_layer_set_backcolor::old
byte vera_layer_set_backcolor::return
void vera_layer_set_config(byte vera_layer_set_config::layer , byte vera_layer_set_config::config)
byte~ vera_layer_set_config::$0 reg byte a 20002.0
byte* vera_layer_set_config::addr
byte* vera_layer_set_config::addr#0 addr zp[2]:67 20002.0
byte vera_layer_set_config::config
byte vera_layer_set_config::config#0 reg byte x 3667.333333333333
byte vera_layer_set_config::layer
byte vera_layer_set_config::layer#0 reg byte a 5501.0
void vera_layer_set_mapbase(byte vera_layer_set_mapbase::layer , byte vera_layer_set_mapbase::mapbase)
byte~ vera_layer_set_mapbase::$0 reg byte a 20002.0
byte* vera_layer_set_mapbase::addr
byte* vera_layer_set_mapbase::addr#0 addr zp[2]:52 20002.0
byte vera_layer_set_mapbase::layer
byte vera_layer_set_mapbase::layer#0 reg byte a 1001.0
byte vera_layer_set_mapbase::layer#3 reg byte a 11002.0
byte vera_layer_set_mapbase::mapbase
byte vera_layer_set_mapbase::mapbase#0 reg byte x 2002.0
byte vera_layer_set_mapbase::mapbase#3 reg byte x 3667.333333333333
void vera_layer_set_text_color_mode(byte vera_layer_set_text_color_mode::layer , byte vera_layer_set_text_color_mode::color_mode)
byte* vera_layer_set_text_color_mode::addr
byte* vera_layer_set_text_color_mode::addr#0 addr zp[2]:65 2502.5
byte vera_layer_set_text_color_mode::color_mode
byte vera_layer_set_text_color_mode::layer
byte vera_layer_set_textcolor(byte vera_layer_set_textcolor::layer , byte vera_layer_set_textcolor::color)
byte vera_layer_set_textcolor::color
byte vera_layer_set_textcolor::layer
byte vera_layer_set_textcolor::layer#1 reg byte x 22.0
byte vera_layer_set_textcolor::layer#2 reg byte x 22.0
byte vera_layer_set_textcolor::layer#3 reg byte x 123.0
byte vera_layer_set_textcolor::old
byte vera_layer_set_textcolor::return
void vera_layer_set_tilebase(byte vera_layer_set_tilebase::layer , byte vera_layer_set_tilebase::tilebase)
byte~ vera_layer_set_tilebase::$0 reg byte a 20002.0
byte* vera_layer_set_tilebase::addr
byte* vera_layer_set_tilebase::addr#0 addr zp[2]:67 20002.0
byte vera_layer_set_tilebase::layer
byte vera_layer_set_tilebase::layer#0 reg byte a 5501.0
byte vera_layer_set_tilebase::tilebase
byte vera_layer_set_tilebase::tilebase#0 reg byte x 3667.333333333333
const byte* vera_layer_textcolor[2] = { WHITE, WHITE }
const byte** vera_layer_tilebase[2] = { VERA_L0_TILEBASE, VERA_L1_TILEBASE }
const to_nomodify byte* vera_layer_vflip[2] = { 0, 8 }
const dword* vera_mapbase_address[2] = { 0, 0 }
const byte* vera_mapbase_bank[2] = { 0, 0 }
const word* vera_mapbase_offset[2] = { 0, 0 }
void vera_tile_area(byte vera_tile_area::layer , word vera_tile_area::tileindex , byte vera_tile_area::x , byte vera_tile_area::y , byte vera_tile_area::w , byte vera_tile_area::h , byte vera_tile_area::hflip , byte vera_tile_area::vflip , byte vera_tile_area::offset)
word~ vera_tile_area::$10 zp[2]:69 20002.0
word~ vera_tile_area::$4 zp[2]:69 20002.0
byte~ vera_tile_area::$5 reg byte a 20002.0
byte vera_tile_area::c
byte vera_tile_area::c#1 reg byte y 2.00000002E8
byte vera_tile_area::c#2 reg byte y 7.500000075E7
byte vera_tile_area::h
byte vera_tile_area::h#6 h zp[1]:24 285714.3142857143
byte vera_tile_area::hflip
byte vera_tile_area::hflip#0 hflip zp[1]:76 5000.5
byte vera_tile_area::index_h
byte vera_tile_area::index_h#0 reg byte a 20002.0
byte vera_tile_area::index_h#1 reg byte a 20002.0
byte vera_tile_area::index_h#2 index_h zp[1]:61 3846538.5384615385
byte vera_tile_area::index_l
byte vera_tile_area::index_l#0 index_l zp[1]:62 3448620.7586206896
byte vera_tile_area::layer
dword vera_tile_area::mapbase
dword vera_tile_area::mapbase#0 mapbase zp[4]:25 1818.3636363636363
dword vera_tile_area::mapbase#1 mapbase zp[4]:25 10001.0
dword vera_tile_area::mapbase#10 mapbase zp[4]:25 2778333.6666666665
dword vera_tile_area::mapbase#2 mapbase zp[4]:25 20002.0
dword vera_tile_area::mapbase#3 mapbase zp[4]:25 1.0000001E7
byte vera_tile_area::offset
byte vera_tile_area::r
byte vera_tile_area::r#1 r zp[1]:63 2.0000002E7
byte vera_tile_area::r#2 r zp[1]:63 1578947.5263157894
word vera_tile_area::rowskip
word vera_tile_area::rowskip#0 rowskip zp[2]:59 312812.5625
byte vera_tile_area::shift
byte vera_tile_area::shift#0 shift zp[1]:75 3333.6666666666665
word vera_tile_area::tileindex
word vera_tile_area::tileindex#1 tileindex zp[2]:8 667.3333333333334
word vera_tile_area::tileindex#3 tileindex zp[2]:8 667.3333333333334
word vera_tile_area::tileindex#5 tileindex zp[2]:8 3143.4285714285716
word~ vera_tile_area::vera_vram_address01_$0 zp[2]:71 2.0000002E7
byte~ vera_tile_area::vera_vram_address01_$1 reg byte a 2.0000002E7
word~ vera_tile_area::vera_vram_address01_$2 zp[2]:77 2.0000002E7
byte~ vera_tile_area::vera_vram_address01_$3 reg byte a 2.0000002E7
word~ vera_tile_area::vera_vram_address01_$4 zp[2]:73 2.0000002E7
byte~ vera_tile_area::vera_vram_address01_$5 reg byte a 2.0000002E7
byte~ vera_tile_area::vera_vram_address01_$6 reg byte a 2.0000002E7
dword vera_tile_area::vera_vram_address01_bankaddr
byte vera_tile_area::vera_vram_address01_incr
byte vera_tile_area::vflip
byte vera_tile_area::vflip#0 vflip zp[1]:61 5000.5
byte vera_tile_area::w
byte vera_tile_area::w#11 w zp[1]:58 2857142.8857142855
byte vera_tile_area::x
byte vera_tile_area::x#1 x zp[1]:12 1001.0
byte vera_tile_area::x#3 x zp[1]:12 1001.0
byte vera_tile_area::x#5 x zp[1]:12 923.3076923076923
byte vera_tile_area::y
byte vera_tile_area::y#1 y zp[1]:6 2002.0
byte vera_tile_area::y#3 y zp[1]:6 2002.0
byte vera_tile_area::y#5 y zp[1]:6 200.2
const dword* vera_tilebase_address[2] = { 0, 0 }
const byte* vera_tilebase_bank[2] = { 0, 0 }
const word* vera_tilebase_offset[2] = { 0, 0 }
zp[1]:2 [ conio_x16_init::line#3 conio_x16_init::line#1 conio_x16_init::line#0 ]
zp[2]:3 [ main::tilebase#7 main::tilebase#2 ]
zp[1]:5 [ main::t#5 main::t#1 ]
reg byte x [ main::p#2 main::p#1 ]
zp[1]:6 [ main::row#9 main::row#1 vera_tile_area::y#5 vera_tile_area::y#3 vera_tile_area::y#1 main::row#10 main::row#3 ]
zp[1]:7 [ main::r#5 main::r#1 ]
zp[2]:8 [ main::tile#6 main::tile#10 main::tile#12 main::tile#1 vera_tile_area::tileindex#5 vera_tile_area::tileindex#3 vera_tile_area::tileindex#1 main::tile#8 main::tile#11 main::tile#13 main::tile#4 ]
reg byte x [ main::column#2 main::column#1 ]
zp[1]:10 [ main::c#2 main::c#1 ]
zp[1]:11 [ main::r1#5 main::r1#1 ]
zp[1]:12 [ main::column1#2 main::column1#1 vera_tile_area::x#5 vera_tile_area::x#3 vera_tile_area::x#1 ]
reg byte x [ main::c1#2 main::c1#1 ]
reg byte x [ vera_layer_set_textcolor::layer#3 vera_layer_set_textcolor::layer#1 vera_layer_set_textcolor::layer#2 ]
reg byte x [ vera_layer_set_backcolor::layer#3 vera_layer_set_backcolor::layer#1 vera_layer_set_backcolor::layer#2 ]
reg byte a [ vera_layer_set_backcolor::color#3 ]
reg byte a [ vera_layer_set_mapbase::layer#3 vera_layer_set_mapbase::layer#0 ]
reg byte x [ vera_layer_set_mapbase::mapbase#3 vera_layer_set_mapbase::mapbase#0 ]
reg byte x [ gotoxy::y#5 gotoxy::y#4 gotoxy::y#0 gotoxy::y#2 ]
reg byte y [ memcpy_in_vram::src_bank#3 ]
reg byte x [ vera_layer_mode_tile::color_depth#5 ]
zp[1]:13 [ vera_layer_mode_tile::layer#10 ]
zp[4]:14 [ vera_layer_mode_tile::mapbase_address#10 vera_layer_mode_tile::mapbase_address#0 ]
zp[4]:18 [ vera_layer_mode_tile::tilebase_address#10 vera_layer_mode_tile::tilebase_address#0 ]
zp[1]:22 [ vera_layer_mode_tile::tilewidth#10 ]
zp[1]:23 [ vera_layer_mode_tile::tileheight#10 ]
reg byte x [ vera_layer_mode_tile::config#25 vera_layer_mode_tile::config#21 vera_layer_mode_tile::config#17 vera_layer_mode_tile::config#6 vera_layer_mode_tile::config#7 vera_layer_mode_tile::config#8 vera_layer_mode_tile::config#10 vera_layer_mode_tile::config#11 vera_layer_mode_tile::config#12 ]
reg byte x [ vera_layer_mode_tile::tilebase#10 vera_layer_mode_tile::tilebase#12 vera_layer_mode_tile::tilebase#1 vera_layer_mode_tile::tilebase#3 vera_layer_mode_tile::tilebase#5 ]
reg byte x [ clrscr::l#2 clrscr::l#1 ]
reg byte y [ clrscr::c#2 clrscr::c#1 ]
zp[1]:24 [ vera_tile_area::h#6 memcpy_in_vram::dest_bank#3 ]
zp[4]:25 [ vera_tile_area::mapbase#10 vera_tile_area::mapbase#2 vera_tile_area::mapbase#3 vera_tile_area::mapbase#1 vera_tile_area::mapbase#0 ]
reg byte y [ vera_tile_area::c#2 vera_tile_area::c#1 ]
reg byte x [ vera_layer_get_color::layer#2 vera_layer_get_color::layer#1 vera_layer_get_color::layer#0 ]
reg byte a [ vera_layer_get_color::return#2 vera_layer_get_color::return#0 vera_layer_get_color::return#1 ]
reg byte x [ insertup::i#2 insertup::i#1 ]
zp[1]:29 [ conio_screen_width ]
zp[1]:30 [ conio_screen_height ]
zp[1]:31 [ conio_screen_layer ]
zp[2]:32 [ conio_width ]
zp[2]:34 [ conio_height ]
zp[1]:36 [ conio_rowshift ]
zp[2]:37 [ conio_rowskip ]
reg byte a [ kbhit::return#2 ]
reg byte a [ main::$35 ]
reg byte a [ kbhit::return#3 ]
reg byte a [ main::$40 ]
reg byte a [ main::vera_layer_hide1_$0 ]
reg byte a [ screensize::hscale#0 ]
reg byte a [ screensize::$1 ]
reg byte a [ screensize::vscale#0 ]
reg byte a [ screensize::$3 ]
reg byte x [ vera_layer_get_mapbase_bank::layer#0 ]
reg byte a [ vera_layer_get_mapbase_bank::return#2 ]
zp[1]:39 [ CONIO_SCREEN_BANK#15 ]
reg byte a [ vera_layer_get_mapbase_offset::layer#0 ]
zp[2]:40 [ CONIO_SCREEN_TEXT#17 ]
reg byte a [ screenlayer::vera_layer_get_width1_layer#0 ]
reg byte a [ screenlayer::vera_layer_get_width1_$2 ]
zp[2]:42 [ screenlayer::vera_layer_get_width1_config#0 vera_layer_mode_tile::mapheight#10 ]
reg byte a [ screenlayer::vera_layer_get_width1_$0 ]
reg byte a [ screenlayer::vera_layer_get_width1_$1 ]
reg byte a [ screenlayer::vera_layer_get_width1_$3 ]
reg byte x [ vera_layer_get_rowshift::layer#0 ]
reg byte a [ vera_layer_get_rowshift::return#2 ]
reg byte a [ screenlayer::$3 ]
reg byte a [ vera_layer_get_rowskip::layer#0 ]
reg byte a [ screenlayer::vera_layer_get_height1_layer#0 ]
reg byte a [ screenlayer::vera_layer_get_height1_$2 ]
reg byte a [ screenlayer::vera_layer_get_height1_$0 ]
reg byte a [ screenlayer::vera_layer_get_height1_$1 ]
reg byte a [ screenlayer::vera_layer_get_height1_$3 ]
reg byte a [ vera_layer_set_mapbase::$0 ]
zp[2]:44 [ gotoxy::$6 gotoxy::line_offset#0 vera_layer_get_rowskip::return#2 screenlayer::$4 vera_layer_get_rowskip::return#0 vera_layer_get_mapbase_offset::return#2 vera_layer_get_mapbase_offset::return#0 vera_layer_mode_tile::mapwidth#10 ]
reg byte a [ gotoxy::$5 ]
reg byte a [ memcpy_in_vram::$0 ]
reg byte a [ memcpy_in_vram::$1 ]
reg byte a [ memcpy_in_vram::$2 ]
reg byte a [ memcpy_in_vram::$3 ]
reg byte a [ memcpy_in_vram::$4 ]
reg byte a [ memcpy_in_vram::$5 ]
reg byte a [ vera_layer_mode_tile::$16 ]
reg byte a [ vera_layer_set_config::layer#0 ]
reg byte x [ vera_layer_set_config::config#0 ]
zp[2]:46 [ vera_layer_mode_tile::$1 screenlayer::vera_layer_get_height1_config#0 ]
zp[1]:48 [ vera_layer_mode_tile::$19 ]
zp[2]:49 [ vera_layer_mode_tile::$2 screenlayer::vera_layer_get_height1_return#0 screenlayer::vera_layer_get_height1_return#1 screenlayer::$5 ]
zp[1]:51 [ vera_layer_mode_tile::$20 ]
reg byte x [ vera_layer_mode_tile::mapbase#0 ]
zp[2]:52 [ vera_layer_mode_tile::$7 vera_layer_set_mapbase::addr#0 screenlayer::vera_layer_get_width1_return#0 screenlayer::vera_layer_get_width1_return#1 screenlayer::$2 ]
zp[2]:54 [ vera_layer_mode_tile::$8 ]
zp[2]:56 [ vera_layer_mode_tile::$10 ]
reg byte a [ vera_layer_mode_tile::tilebase#0 ]
reg byte a [ vera_layer_set_tilebase::layer#0 ]
reg byte x [ vera_layer_set_tilebase::tilebase#0 ]
reg byte a [ vera_layer_mode_tile::$15 ]
reg byte a [ vera_layer_mode_tile::$14 ]
reg byte a [ vera_layer_mode_tile::$13 ]
reg byte x [ vera_layer_get_backcolor::layer#0 ]
reg byte a [ vera_layer_get_backcolor::return#2 ]
reg byte a [ clrscr::$0 ]
zp[1]:58 [ clrscr::$1 clrscr::color#0 vera_tile_area::w#11 ]
reg byte x [ vera_layer_get_textcolor::layer#0 ]
reg byte a [ vera_layer_get_textcolor::return#2 ]
reg byte a [ clrscr::$2 ]
reg byte a [ clrscr::$9 ]
reg byte a [ clrscr::$5 ]
reg byte a [ clrscr::$6 ]
reg byte a [ clrscr::$7 ]
reg byte a [ memcpy_to_vram::$0 ]
reg byte a [ memcpy_to_vram::$1 ]
zp[2]:59 [ vera_tile_area::rowskip#0 cputs::s#9 cputs::s#10 cputs::s#0 ]
zp[1]:61 [ vera_tile_area::vflip#0 vera_tile_area::index_h#2 ]
zp[1]:62 [ vera_tile_area::index_l#0 ]
reg byte a [ vera_tile_area::index_h#0 ]
reg byte a [ vera_tile_area::index_h#1 ]
reg byte a [ vera_tile_area::$5 ]
reg byte a [ vera_tile_area::vera_vram_address01_$1 ]
reg byte a [ vera_tile_area::vera_vram_address01_$3 ]
reg byte a [ vera_tile_area::vera_vram_address01_$5 ]
reg byte a [ vera_tile_area::vera_vram_address01_$6 ]
reg byte a [ cputs::c#1 ]
zp[1]:63 [ cputc::c#0 vera_tile_area::r#2 vera_tile_area::r#1 ]
zp[1]:64 [ kbhit::ch ]
reg byte a [ kbhit::return#0 ]
reg byte a [ kbhit::return#1 ]
zp[2]:65 [ vera_layer_set_text_color_mode::addr#0 vera_layer_mode_tile::$4 ]
reg byte a [ vera_layer_get_mapbase_bank::return#0 ]
reg byte a [ vera_layer_get_mapbase_offset::$0 ]
reg byte a [ vera_layer_get_rowshift::return#0 ]
reg byte a [ vera_layer_get_rowskip::$0 ]
reg byte a [ vera_layer_set_config::$0 ]
reg byte a [ vera_layer_set_tilebase::$0 ]
zp[2]:67 [ vera_layer_set_tilebase::addr#0 vera_layer_set_config::addr#0 ]
reg byte a [ vera_layer_get_backcolor::return#0 ]
reg byte a [ vera_layer_get_textcolor::return#0 ]
reg byte a [ vera_layer_get_color::return#3 ]
reg byte x [ cputc::color#0 ]
reg byte a [ cputc::$15 ]
zp[2]:69 [ cputc::conio_addr#0 cputc::conio_addr#1 vera_tile_area::$10 vera_tile_area::$4 clrscr::line_text#2 clrscr::line_text#1 clrscr::line_text#0 memcpy_in_vram::src#3 memcpy_in_vram::src#4 memcpy_in_vram::src#0 ]
reg byte a [ cputc::$2 ]
reg byte a [ cputc::$4 ]
reg byte a [ cputc::$5 ]
reg byte a [ cputc::$6 ]
reg byte a [ cputc::scroll_enable#0 ]
zp[2]:71 [ cputc::$16 vera_tile_area::vera_vram_address01_$0 memcpy_to_vram::vdest#2 memcpy_to_vram::vdest#1 memcpy_in_vram::dest#3 memcpy_in_vram::dest#0 insertup::start#0 insertup::line#0 ]
reg byte a [ vera_layer_get_color::$3 ]
reg byte a [ vera_layer_get_color::$0 ]
reg byte a [ vera_layer_get_color::$1 ]
reg byte a [ cputln::$2 ]
zp[2]:73 [ cputln::temp#0 cputln::temp#1 vera_tile_area::vera_vram_address01_$4 clearline::c#2 clearline::c#1 memcpy_in_vram::i#2 memcpy_in_vram::i#1 ]
reg byte a [ cputln::$3 ]
zp[1]:75 [ insertup::cy#0 vera_tile_area::shift#0 ]
zp[1]:76 [ insertup::width#0 vera_tile_area::hflip#0 ]
reg byte a [ insertup::$3 ]
reg byte a [ clearline::$5 ]
zp[2]:77 [ clearline::addr#0 vera_layer_get_color::addr#0 vera_tile_area::vera_vram_address01_$2 memcpy_to_vram::s#2 memcpy_to_vram::s#1 memcpy_in_vram::num#4 memcpy_in_vram::num#0 ]
reg byte a [ clearline::$1 ]
reg byte a [ clearline::$2 ]
reg byte a [ vera_layer_get_color::return#4 ]
reg byte x [ clearline::color#0 ]