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This commit is contained in:
Irmen de Jong 2019-09-11 02:19:33 +02:00
parent 764710ea12
commit 3941a0b859
7 changed files with 83 additions and 75 deletions
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4
src/main/kotlin/net/razorvine/ksim65/components/Bus.kt
View File

@ -27,7 +27,7 @@ class Bus {
fun read(address: Address): UByte {
memComponents.forEach {
if(address>=it.startAddress && address<=it.endAddress)
if (address >= it.startAddress && address <= it.endAddress)
return it[address]
}
return 0xff
@ -35,7 +35,7 @@ class Bus {
fun write(address: Address, data: UByte) {
memComponents.forEach {
if(address>=it.startAddress && address<=it.endAddress)
if (address >= it.startAddress && address <= it.endAddress)
it[address] = data
}
}

11
src/main/kotlin/net/razorvine/ksim65/components/Component.kt
View File

@ -13,17 +13,17 @@ abstract class BusComponent {
abstract fun reset()
}
abstract class MemMappedComponent(val startAddress: Address, val endAddress: Address): BusComponent() {
abstract class MemMappedComponent(val startAddress: Address, val endAddress: Address) : BusComponent() {
abstract operator fun get(address: Address): UByte
abstract operator fun set(address: Address, data: UByte)
init {
require(endAddress>=startAddress)
require(startAddress>=0 && endAddress <= 0xffff) { "can only have 16-bit address space" }
require(endAddress >= startAddress)
require(startAddress >= 0 && endAddress <= 0xffff) { "can only have 16-bit address space" }
}
fun hexDump(from: Address, to: Address) {
(from .. to).chunked(16).forEach {
(from..to).chunked(16).forEach {
print("\$${it.first().toString(16).padStart(4, '0')} ")
val bytes = it.map { address -> get(address) }
bytes.forEach { byte ->
@ -36,6 +36,7 @@ abstract class MemMappedComponent(val startAddress: Address, val endAddress: Add
}
}
abstract class MemoryComponent(startAddress: Address, endAddress: Address): MemMappedComponent(startAddress, endAddress) {
abstract class MemoryComponent(startAddress: Address, endAddress: Address) :
MemMappedComponent(startAddress, endAddress) {
abstract fun cloneContents(): Array<UByte>
}

101
src/main/kotlin/net/razorvine/ksim65/components/Cpu6502.kt
View File

@ -55,20 +55,26 @@ open class Cpu6502(private val stopOnBrk: Boolean) : BusComponent() {
IzY
}
class Instruction(val opcode: UByte, val mnemonic: String, val mode: AddrMode, val cycles: Int, val execute: () -> Unit) {
class Instruction(
val opcode: UByte,
val mnemonic: String,
val mode: AddrMode,
val cycles: Int,
val execute: () -> Unit
) {
override fun toString(): String {
return "[${hexB(opcode)}: $mnemonic $mode]"
}
}
class StatusRegister(
var C: Boolean = false,
var Z: Boolean = false,
var I: Boolean = false,
var D: Boolean = false,
var B: Boolean = false,
var V: Boolean = false,
var N: Boolean = false
var C: Boolean = false,
var Z: Boolean = false,
var I: Boolean = false,
var D: Boolean = false,
var B: Boolean = false,
var V: Boolean = false,
var N: Boolean = false
) {
fun asByte(): UByte {
return (0b00100000 or
@ -126,19 +132,19 @@ open class Cpu6502(private val stopOnBrk: Boolean) : BusComponent() {
private var fetchedAddress: Address = 0
private val addressingModes = mapOf<AddrMode, () -> Unit>(
AddrMode.Imp to ::amImp,
AddrMode.Acc to ::amAcc,
AddrMode.Imm to ::amImm,
AddrMode.Zp to ::amZp,
AddrMode.ZpX to ::amZpx,
AddrMode.ZpY to ::amZpy,
AddrMode.Rel to ::amRel,
AddrMode.Abs to ::amAbs,
AddrMode.AbsX to ::amAbsx,
AddrMode.AbsY to ::amAbsy,
AddrMode.Ind to ::amInd,
AddrMode.IzX to ::amIzx,
AddrMode.IzY to ::amIzy
AddrMode.Imp to ::amImp,
AddrMode.Acc to ::amAcc,
AddrMode.Imm to ::amImm,
AddrMode.Zp to ::amZp,
AddrMode.ZpX to ::amZpx,
AddrMode.ZpY to ::amZpy,
AddrMode.Rel to ::amRel,
AddrMode.Abs to ::amAbs,
AddrMode.AbsX to ::amAbsx,
AddrMode.AbsY to ::amAbsy,
AddrMode.Ind to ::amInd,
AddrMode.IzX to ::amIzx,
AddrMode.IzY to ::amIzy
)
private val breakpoints = mutableMapOf<Address, (cpu: Cpu6502, pc: Address) -> Unit>()
@ -148,7 +154,7 @@ open class Cpu6502(private val stopOnBrk: Boolean) : BusComponent() {
}
fun disassemble(component: MemoryComponent, from: Address, to: Address) =
disassemble(component.cloneContents(), component.startAddress, from, to)
disassemble(component.cloneContents(), component.startAddress, from, to)
fun disassemble(memory: Array<UByte>, baseAddress: Address, from: Address, to: Address): List<String> {
var address = from - baseAddress
@ -198,10 +204,10 @@ open class Cpu6502(private val stopOnBrk: Boolean) : BusComponent() {
AddrMode.Rel -> {
val rel = memory[address++]
val target =
if (rel <= 0x7f)
address + rel
else
address - (256 - rel)
if (rel <= 0x7f)
address + rel
else
address - (256 - rel)
line += "${hexB(rel)} $spacing2 ${opcode.mnemonic} \$${hexW(
target,
true
@ -338,19 +344,20 @@ open class Cpu6502(private val stopOnBrk: Boolean) : BusComponent() {
}
fun printState() {
println("cycle:$totalCycles - pc=${hexW(PC)} " +
"A=${hexB(A)} " +
"X=${hexB(X)} " +
"Y=${hexB(Y)} " +
"SP=${hexB(SP)} " +
" n=" + (if (Status.N) "1" else "0") +
" v=" + (if (Status.V) "1" else "0") +
" b=" + (if (Status.B) "1" else "0") +
" d=" + (if (Status.D) "1" else "0") +
" i=" + (if (Status.I) "1" else "0") +
" z=" + (if (Status.Z) "1" else "0") +
" c=" + (if (Status.C) "1" else "0") +
" icycles=$instrCycles instr=${hexB(currentOpcode)}:${currentInstruction.mnemonic}"
println(
"cycle:$totalCycles - pc=${hexW(PC)} " +
"A=${hexB(A)} " +
"X=${hexB(X)} " +
"Y=${hexB(Y)} " +
"SP=${hexB(SP)} " +
" n=" + (if (Status.N) "1" else "0") +
" v=" + (if (Status.V) "1" else "0") +
" b=" + (if (Status.B) "1" else "0") +
" d=" + (if (Status.D) "1" else "0") +
" i=" + (if (Status.I) "1" else "0") +
" z=" + (if (Status.Z) "1" else "0") +
" c=" + (if (Status.C) "1" else "0") +
" icycles=$instrCycles instr=${hexB(currentOpcode)}:${currentInstruction.mnemonic}"
)
}
@ -440,13 +447,13 @@ open class Cpu6502(private val stopOnBrk: Boolean) : BusComponent() {
}
private fun getFetched() =
if (currentInstruction.mode == AddrMode.Imm ||
currentInstruction.mode == AddrMode.Acc ||
currentInstruction.mode == AddrMode.Imp
)
fetchedData
else
read(fetchedAddress)
if (currentInstruction.mode == AddrMode.Imm ||
currentInstruction.mode == AddrMode.Acc ||
currentInstruction.mode == AddrMode.Imp
)
fetchedData
else
read(fetchedAddress)
private fun readPc(): Int = bus.read(PC++).toInt()
@ -738,7 +745,7 @@ open class Cpu6502(private val stopOnBrk: Boolean) : BusComponent() {
Instruction(0xfc, "nop", AddrMode.AbsX, 4, ::iNop),
Instruction(0xfd, "sbc", AddrMode.AbsX, 4, ::iSbc),
Instruction(0xfe, "inc", AddrMode.AbsX, 7, ::iInc),
Instruction(0xff, "isc", AddrMode.AbsX, 7, ::iIsc )
Instruction(0xff, "isc", AddrMode.AbsX, 7, ::iIsc)
).toTypedArray()

2
src/main/kotlin/net/razorvine/ksim65/components/Cpu65C02.kt
View File

@ -1,6 +1,6 @@
package net.razorvine.ksim65.components
class Cpu65C02(stopOnBrk: Boolean): Cpu6502(stopOnBrk) {
class Cpu65C02(stopOnBrk: Boolean) : Cpu6502(stopOnBrk) {
val waiting: Boolean = false

30
src/main/kotlin/net/razorvine/ksim65/components/Ram.kt
View File

@ -2,18 +2,18 @@ package net.razorvine.ksim65.components
import java.io.File
class Ram(startAddress: Address, endAddress: Address): MemoryComponent(startAddress, endAddress) {
private val memory = ShortArray(endAddress-startAddress+1)
class Ram(startAddress: Address, endAddress: Address) : MemoryComponent(startAddress, endAddress) {
private val memory = ShortArray(endAddress - startAddress + 1)
override operator fun get(address: Address): UByte = memory[address-startAddress]
override operator fun get(address: Address): UByte = memory[address - startAddress]
override operator fun set(address: Address, data: UByte) {
memory[address-startAddress] = data
memory[address - startAddress] = data
}
override fun cloneContents(): Array<UByte> = memory.toTypedArray()
override fun clock() { }
override fun clock() {}
override fun reset() {
// contents of RAM doesn't change on a reset
@ -31,11 +31,11 @@ class Ram(startAddress: Address, endAddress: Address): MemoryComponent(startAddr
val bytes = File(filename).readBytes()
val address = (bytes[0].toInt() or (bytes[1].toInt() shl 8)) and 65535
bytes.drop(2).forEachIndexed { index, byte ->
memory[address+index] =
if(byte>=0)
byte.toShort()
else
(256+byte).toShort()
memory[address + index] =
if (byte >= 0)
byte.toShort()
else
(256 + byte).toShort()
}
}
@ -45,11 +45,11 @@ class Ram(startAddress: Address, endAddress: Address): MemoryComponent(startAddr
fun load(filename: String, address: Address) {
val bytes = File(filename).readBytes()
bytes.forEachIndexed { index, byte ->
memory[address+index] =
if(byte>=0)
byte.toShort()
else
(256+byte).toShort()
memory[address + index] =
if (byte >= 0)
byte.toShort()
else
(256 + byte).toShort()
}
}
}

8
src/main/kotlin/net/razorvine/ksim65/components/Rom.kt
View File

@ -2,10 +2,10 @@ package net.razorvine.ksim65.components
class Rom(startAddress: Address, endAddress: Address, data: Array<UByte>? = null) : MemoryComponent(startAddress, endAddress) {
private val memory =
if (data == null)
ShortArray(endAddress - startAddress - 1)
else
ShortArray(data.size) { index -> data[index] }
if (data == null)
ShortArray(endAddress - startAddress - 1)
else
ShortArray(data.size) { index -> data[index] }
init {
if (data != null)

2
src/main/kotlin/net/razorvine/ksim65/components/Timer.kt
View File

@ -14,7 +14,7 @@ class Timer(startAddress: Address, endAddress: Address, val cpu: Cpu6502) : MemM
private var nmi = false
private var enabled = false
set(value) {
if(value && !field) {
if (value && !field) {
// timer is set to enabled (was disabled) - reset the counter
counter = 0
}