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added start of 6510's IO port

This commit is contained in:
Irmen de Jong 2019-10-26 18:32:11 +02:00
parent ca2eede585
commit 3fb12eb3f6
3 changed files with 48 additions and 1 deletions

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@ -0,0 +1,45 @@
package razorvine.c64emu
import razorvine.ksim65.Cpu6502
import razorvine.ksim65.components.Address
import razorvine.ksim65.components.MemMappedComponent
import razorvine.ksim65.components.UByte
/**
* The 6510's IO port located at $00/$01
* Controlling the memory layout, and cassette port (not processed at all).
* TODO: actually mapping the roms in and out of the address space. This requires some MMU type logic in the Bus class.
*/
class CpuIoPort(val cpu: Cpu6502) : MemMappedComponent(0x0000, 0x0001) {
private var dataDirections: Int = 0
private var ioPort: Int = 0
private var loram: Boolean = false // Bit 0: LORAM signal. Selects ROM or RAM at 40960 ($A000). 1=BASIC, 0=RAM
private var hiram: Boolean = false // Bit 1: HIRAM signal. Selects ROM or RAM at 57344 ($E000). 1=Kernal, 0=RAM
private var charen: Boolean = false // Bit 2: CHAREN signal. Selects character ROM or I/O devices. 1=I/O, 0=ROM
override fun clock() { }
override fun reset() { }
override fun get(address: Address): UByte {
return if(address==0) dataDirections.toShort() else {
(ioPort or dataDirections.inv() and 0b00111111).toShort()
}
}
override fun set(address: Address, data: UByte) {
if(address==0) {
dataDirections = data.toInt()
determineRoms()
} else {
ioPort = data.toInt()
determineRoms()
}
}
private fun determineRoms() {
if (dataDirections and 0b00000001 != 0) loram = ioPort and 0b00000001 != 0
if (dataDirections and 0b00000010 != 0) hiram = ioPort and 0b00000010 != 0
if (dataDirections and 0b00000100 != 0) charen = ioPort and 0b00000100 != 0
}
}

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@ -236,7 +236,7 @@ internal class Screen(private val chargenData: ByteArray, val ram: MemoryCompone
// The vic 'sees' the charset rom at these addresses: $1000 + $1800, $9000 + $9800
// so we can use pre-loaded images to efficiently draw the characters.
// If the address is different, the vic takes charset data from RAM instead.
// TODO: currently custom charsets taken from RAM are not yet supported
// TODO: currently custom charsets taken from RAM aren't supported
val shifted = charsetAddr and 0x0800 != 0
var cached = coloredCharacterImageCache[Triple(char, color, shifted)]
if (cached == null) {

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@ -37,6 +37,7 @@ class C64Machine(title: String) : IVirtualMachine {
val cia2 = Cia(2, 0xdd00, 0xddff, cpu)
val basicRom = Rom(0xa000, 0xbfff).also { it.load(basicData) }
val kernalRom = Rom(0xe000, 0xffff).also { it.load(kernalData) }
val cpuIoPort = CpuIoPort(cpu)
private val debugWindow = DebugWindow(this)
private val hostDisplay = MainC64Window(title, chargenData, ram, cpu, cia1)
@ -53,6 +54,7 @@ class C64Machine(title: String) : IVirtualMachine {
bus += vic
bus += cia1
bus += cia2
bus += cpuIoPort
bus += ram
bus += cpu
bus.reset()