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no longer attach roms to bus old-style

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This commit is contained in:
Irmen de Jong 2020-02-05 01:22:32 +01:00
parent 81ae12b809
commit 43b2bec5da
3 changed files with 15 additions and 6 deletions
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9
src/main/kotlin/razorvine/c64emu/CpuIoPort.kt
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@ -7,11 +7,12 @@ import razorvine.ksim65.components.UByte
/**
* The 6510's IO port located at $00/$01
* Controlling the memory layout, and cassette port (not processed at all).
*
*/
class CpuIoPort(val cpu: Cpu6502) : MemMappedComponent(0x0000, 0x0001) {
private var dataDirections: Int = 0
private var ioPort: Int = 0
private var ioPort: Int = 0xff
var loram: Boolean = false // Bit 0: LORAM signal. Selects ROM or RAM at 40960 ($A000). 1=BASIC, 0=RAM
private set
var hiram: Boolean = false // Bit 1: HIRAM signal. Selects ROM or RAM at 57344 ($E000). 1=Kernal, 0=RAM
@ -20,7 +21,11 @@ class CpuIoPort(val cpu: Cpu6502) : MemMappedComponent(0x0000, 0x0001) {
private set
override fun clock() { }
override fun reset() { }
override fun reset() {
dataDirections = 0xff
ioPort = 0xff
determineRoms()
}
override operator fun get(offset: Int): UByte {
return if(offset==0) dataDirections.toShort() else {

2
src/main/kotlin/razorvine/c64emu/GUI.kt
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@ -53,7 +53,7 @@ object ScreenDefs {
val colorPalette = Palette()
}
class MainC64Window(title: String, chargen: Rom, val ram: MemoryComponent, val cpu: Cpu6502, val keypressCia: Cia) :
class MainC64Window(title: String, chargen: Rom, val ram: MemoryComponent, val cpu: Cpu6502, private val keypressCia: Cia) :
JFrame(title), KeyListener {
init {
defaultCloseOperation = EXIT_ON_CLOSE

10
src/main/kotlin/razorvine/c64emu/c64Main.kt
View File

@ -41,8 +41,14 @@ class C64Machine(title: String) : IVirtualMachine {
override val cpu = Cpu6502()
val cpuIoPort = CpuIoPort(cpu)
// This bus contains "mmu" logic to control the memory bank switching controlled by the 6510's io port in $00/$01.
// Therefore we provide it the various roms directly and not "connect" these to the bus in the default way.
override val bus = Bus6510(cpuIoPort, chargenRom, basicRom, kernalRom)
// the C64 has 64KB of RAM. Some of it may be banked out and replaced by ROM.
val ram = Ram(0x0000, 0xffff)
val vic = VicII(0xd000, 0xd3ff, cpu)
val cia1 = Cia(1, 0xdc00, 0xdcff, cpu)
val cia2 = Cia(2, 0xdd00, 0xddff, cpu)
@ -57,13 +63,11 @@ class C64Machine(title: String) : IVirtualMachine {
cpu.addBreakpoint(0xffd8, ::breakpointKernelSave) // intercept SAVE subroutine in the kernal
cpu.breakpointForBRK = ::breakpointBRK
bus += basicRom // TODO remove this
bus += kernalRom // TODO remove this
bus += vic
bus += cia1
bus += cia2
bus += cpuIoPort
bus += ram
bus += ram // note: the ROMs are mapped depending on the cpu's io port
bus += cpu
bus.reset()