diff --git a/src/main/resources/version.properties b/src/main/resources/version.properties index 010d7cc..0ff015d 100644 --- a/src/main/resources/version.properties +++ b/src/main/resources/version.properties @@ -1 +1 @@ -version=1.6 +version=1.7-SNAPSHOT diff --git a/src/test/kotlin/6502_functional_tests/6502_decimal_test.a65 b/src/test/kotlin/6502_functional_tests/6502_decimal_test.a65 index 7a76ad1..1145106 100644 --- a/src/test/kotlin/6502_functional_tests/6502_decimal_test.a65 +++ b/src/test/kotlin/6502_functional_tests/6502_decimal_test.a65 @@ -34,7 +34,8 @@ chk_z = 0 ; check zero flag chk_c = 1 ; check carry flag end_of_test macro - db $db ;execute 65C02 stop instruction + brk + ; db $db ;execute 65C02 stop instruction endm bss @@ -117,14 +118,14 @@ NEXT2 inc N2 ; [6] see text bpl LOOP1 ; loop through both values of the carry flag lda #0 ; test passed, so store 0 in ERROR sta ERROR -DONE +DONE end_of_test - + ; Calculate the actual decimal mode accumulator and flags, the accumulator ; and flag results when N1 is added to N2 using binary arithmetic, the ; predicted accumulator result, the predicted carry flag, and the predicted -; V flag -; +; V flag +; ADD sed ; decimal mode cpy #1 ; set carry if Y = 1, clear carry if Y = 0 lda N1 @@ -138,7 +139,7 @@ ADD sed ; decimal mode lda N1 adc N2 sta HA ; accumulator result of N1+N2 using binary arithmetic - + php pla sta HNVZC ; flags result of N1+N2 using binary arithmetic @@ -153,10 +154,10 @@ ADD sed ; decimal mode and #$0F sec A1 ora N1H -; +; ; if N1L + N2L < $0A, then add N2 & $F0 ; if N1L + N2L >= $0A, then add (N2 & $F0) + $0F + 1 (carry is set) -; +; adc N2H,x php bcs A2 @@ -169,16 +170,16 @@ A3 sta AR ; predicted accumulator result pla sta CF ; predicted carry result pla -; +; ; note that all 8 bits of the P register are stored in VF -; +; sta VF ; predicted V flags rts - + ; Calculate the actual decimal mode accumulator and flags, and the ; accumulator and flag results when N2 is subtracted from N1 using binary ; arithmetic -; +; SUB sed ; decimal mode cpy #1 ; set carry if Y = 1, clear carry if Y = 0 lda N1 @@ -192,15 +193,15 @@ SUB sed ; decimal mode lda N1 sbc N2 sta HA ; accumulator result of N1-N2 using binary arithmetic - + php pla sta HNVZC ; flags result of N1-N2 using binary arithmetic rts - + if cputype != 1 ; Calculate the predicted SBC accumulator result for the 6502 and 65816 -; +; SUB1 cpy #1 ; set carry if Y = 1, clear carry if Y = 0 lda N1L sbc N2L @@ -211,17 +212,17 @@ SUB1 cpy #1 ; set carry if Y = 1, clear carry if Y = 0 and #$0F clc S11 ora N1H -; +; ; if N1L - N2L >= 0, then subtract N2 & $F0 ; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear) -; +; sbc N2H,x bcs S12 sbc #$5F ; subtract $60 (carry is clear) S12 sta AR rts endif - + if cputype = 1 ; Calculate the predicted SBC accumulator result for the 6502 and 65C02 ; @@ -234,10 +235,10 @@ SUB2 cpy #1 ; set carry if Y = 1, clear carry if Y = 0 and #$0F clc S21 ora N1H -; +; ; if N1L - N2L >= 0, then subtract N2 & $F0 ; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear) -; +; sbc N2H,x bcs S22 sbc #$5F ; subtract $60 (carry is clear) @@ -247,14 +248,14 @@ S22 cpx #0 S23 sta AR ; predicted accumulator result rts endif - + ; Compare accumulator actual results to predicted results -; -; Return: +; +; Return: ; Z flag = 1 (BEQ branch) if same ; Z flag = 0 (BNE branch) if different -; -COMPARE +; +COMPARE if chk_a = 1 lda DA cmp AR @@ -284,22 +285,22 @@ COMPARE and #1 ; mask off C flag endif C1 rts - + ; These routines store the predicted values for ADC and SBC for the 6502, ; 65C02, and 65816 in AR, CF, NF, VF, and ZF if cputype = 0 A6502 lda VF ; 6502 -; +; ; since all 8 bits of the P register were stored in VF, bit 7 of VF contains ; the N flag for NF -; +; sta NF lda HNVZC sta ZF rts - + S6502 jsr SUB1 lda HNVZC sta NF @@ -317,7 +318,7 @@ A6502 lda AR ; 65C02 sta NF sta ZF rts - + S6502 jsr SUB2 lda AR php @@ -330,7 +331,7 @@ S6502 jsr SUB2 rts endif - if cputype = 2 + if cputype = 2 A6502 lda AR ; 65C816 php @@ -338,7 +339,7 @@ A6502 lda AR ; 65C816 sta NF sta ZF rts - + S6502 jsr SUB1 lda AR php diff --git a/src/test/kotlin/6502_functional_tests/6502_functional_test.a65 b/src/test/kotlin/6502_functional_tests/6502_functional_test.a65 index 2c4031c..9a2ecba 100644 --- a/src/test/kotlin/6502_functional_tests/6502_functional_test.a65 +++ b/src/test/kotlin/6502_functional_tests/6502_functional_test.a65 @@ -1,7 +1,7 @@ ; ; 6 5 0 2 F U N C T I O N A L T E S T ; -; Copyright (C) 2012-2015 Klaus Dormann +; Copyright (C) 2012-2020 Klaus Dormann ; ; This program is free software: you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by @@ -21,10 +21,11 @@ ; addressing modes with focus on propper setting of the processor status ; register bits. ; -; version 04-dec-2017 +; version 05-jan-2020 ; contact info at http://2m5.de or email K@2m5.de ; -; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/ +; assembled with AS65 written by Frank A. Kingswood +; The assembler as65_142.zip can be obtained from my GitHub repository ; command line switches: -l -m -s2 -w -h0 ; | | | | no page headers in listing ; | | | wide listing (133 char/col) @@ -76,7 +77,8 @@ ; 04-dec-2017 fixed BRK only tested with interrupts enabled ; added option to skip the remainder of a failing test ; in report.i65 - +; 05-jan-2020 fixed shifts not testing zero result and flag when last 1-bit +; is shifted out ; C O N F I G U R A T I O N @@ -96,17 +98,17 @@ load_data_direct = 1 I_flag = 3 ;configure memory - try to stay away from memory used by the system -;zero_page memory start address, $50 (80) consecutive Bytes required +;zero_page memory start address, $52 (82) consecutive Bytes required ; add 2 if I_flag = 2 zero_page = $a -;data_segment memory start address, $6A (106) consecutive Bytes required +;data_segment memory start address, $7B (123) consecutive Bytes required data_segment = $200 if (data_segment & $ff) != 0 ERROR ERROR ERROR low byte of data_segment MUST be $00 !! endif -;code_segment memory start address, 13kB of consecutive space required +;code_segment memory start address, 13.1kB of consecutive space required ; add 2.5 kB if I_flag = 2 code_segment = $400 @@ -621,7 +623,7 @@ irq_x ds 1 ;x register flag_I_on ds 1 ;or mask to load flags flag_I_off ds 1 ;and mask to load flags endif -zpt ;5 bytes store/modify test area +zpt ;6 bytes store/modify test area ;add/subtract operand generation and result/flag prediction adfc ds 1 ;carry flag before op ad1 ds 1 ;operand 1 - accumulator @@ -631,6 +633,7 @@ adrh ds 1 ;expected result bit 8 (carry) adrf ds 1 ;expected flags NV0000ZC (only binary mode) sb2 ds 1 ;operand 2 complemented for subtract zp_bss +zps db $80,1 ;additional shift pattern to test zero result & flag zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR zp7f db $7f ;test pattern for compare ;logical zeropage operands @@ -672,10 +675,10 @@ zp_bss_end test_case ds 1 ;current test number ram_chksm ds 2 ;checksum for RAM integrity test ;add/subtract operand copy - abs tests write area -abst ;5 bytes store/modify test area +abst ;6 bytes store/modify test area ada2 ds 1 ;operand 2 sba2 ds 1 ;operand 2 complemented for subtract - ds 3 ;fill remaining bytes + ds 4 ;fill remaining bytes data_bss if load_data_direct = 1 ex_andi and #0 ;execute immediate opcodes @@ -695,34 +698,35 @@ ex_orai ds 3 ex_adci ds 3 ex_sbci ds 3 endif +;zps db $80,1 ;additional shift patterns test zero result & flag abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR abs7f db $7f ;test pattern for compare ;loads -fLDx db fn,fn,0,fz ;expected flags for load +fLDx db fn,fn,0,fz ;expected flags for load ;shifts -rASL ;expected result ASL & ROL -carry -rROL db $86,$04,$82,0 ; " -rROLc db $87,$05,$83,1 ;expected result ROL +carry -rLSR ;expected result LSR & ROR -carry -rROR db $61,$41,$20,0 ; " -rRORc db $e1,$c1,$a0,$80 ;expected result ROR +carry -fASL ;expected flags for shifts -fROL db fnc,fc,fn,fz ;no carry in -fROLc db fnc,fc,fn,0 ;carry in -fLSR -fROR db fc,0,fc,fz ;no carry in -fRORc db fnc,fn,fnc,fn ;carry in +rASL ;expected result ASL & ROL -carry +rROL db 0,2,$86,$04,$82,0 +rROLc db 1,3,$87,$05,$83,1 ;expected result ROL +carry +rLSR ;expected result LSR & ROR -carry +rROR db $40,0,$61,$41,$20,0 +rRORc db $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry +fASL ;expected flags for shifts +fROL db fzc,0,fnc,fc,fn,fz ;no carry in +fROLc db fc,0,fnc,fc,fn,0 ;carry in +fLSR +fROR db 0,fzc,fc,0,fc,fz ;no carry in +fRORc db fn,fnc,fnc,fn,fnc,fn ;carry in ;increments (decrements) -rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC -fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC +rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC +fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC ;logical memory operand -absOR db 0,$1f,$71,$80 ;test pattern for OR -absAN db $0f,$ff,$7f,$80 ;test pattern for AND -absEO db $ff,$0f,$8f,$8f ;test pattern for EOR +absOR db 0,$1f,$71,$80 ;test pattern for OR +absAN db $0f,$ff,$7f,$80 ;test pattern for AND +absEO db $ff,$0f,$8f,$8f ;test pattern for EOR ;logical accu operand -absORa db 0,$f1,$1f,0 ;test pattern for OR -absANa db $f0,$ff,$ff,$ff ;test pattern for AND -absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR +absORa db 0,$f1,$1f,0 ;test pattern for OR +absANa db $f0,$ff,$ff,$ff ;test pattern for AND +absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR ;logical results absrlo db 0,$ff,$7f,$80 absflo db fz,fn,0,fn @@ -4070,91 +4074,91 @@ tstay6 lda abst,y ; testing shifts - ASL LSR ROL ROR all addressing modes ; shifts - accumulator - ldx #3 + ldx #5 tasl - set_ax zp1,0 + set_ax zps,0 asl a tst_ax rASL,fASL,0 dex bpl tasl - ldx #3 + ldx #5 tasl1 - set_ax zp1,$ff + set_ax zps,$ff asl a tst_ax rASL,fASL,$ff-fnzc dex bpl tasl1 - ldx #3 + ldx #5 tlsr - set_ax zp1,0 + set_ax zps,0 lsr a tst_ax rLSR,fLSR,0 dex bpl tlsr - ldx #3 + ldx #5 tlsr1 - set_ax zp1,$ff + set_ax zps,$ff lsr a tst_ax rLSR,fLSR,$ff-fnzc dex bpl tlsr1 - ldx #3 + ldx #5 trol - set_ax zp1,0 + set_ax zps,0 rol a tst_ax rROL,fROL,0 dex bpl trol - ldx #3 + ldx #5 trol1 - set_ax zp1,$ff-fc + set_ax zps,$ff-fc rol a tst_ax rROL,fROL,$ff-fnzc dex bpl trol1 - ldx #3 + ldx #5 trolc - set_ax zp1,fc + set_ax zps,fc rol a tst_ax rROLc,fROLc,0 dex bpl trolc - ldx #3 + ldx #5 trolc1 - set_ax zp1,$ff + set_ax zps,$ff rol a tst_ax rROLc,fROLc,$ff-fnzc dex bpl trolc1 - ldx #3 + ldx #5 tror - set_ax zp1,0 + set_ax zps,0 ror a tst_ax rROR,fROR,0 dex bpl tror - ldx #3 + ldx #5 tror1 - set_ax zp1,$ff-fc + set_ax zps,$ff-fc ror a tst_ax rROR,fROR,$ff-fnzc dex bpl tror1 - ldx #3 + ldx #5 trorc - set_ax zp1,fc + set_ax zps,fc ror a tst_ax rRORc,fRORc,0 dex bpl trorc - ldx #3 + ldx #5 trorc1 - set_ax zp1,$ff + set_ax zps,$ff ror a tst_ax rRORc,fRORc,$ff-fnzc dex @@ -4162,91 +4166,91 @@ trorc1 next_test ; shifts - zeropage - ldx #3 + ldx #5 tasl2 - set_z zp1,0 + set_z zps,0 asl zpt tst_z rASL,fASL,0 dex bpl tasl2 - ldx #3 + ldx #5 tasl3 - set_z zp1,$ff + set_z zps,$ff asl zpt tst_z rASL,fASL,$ff-fnzc dex bpl tasl3 - ldx #3 + ldx #5 tlsr2 - set_z zp1,0 + set_z zps,0 lsr zpt tst_z rLSR,fLSR,0 dex bpl tlsr2 - ldx #3 + ldx #5 tlsr3 - set_z zp1,$ff + set_z zps,$ff lsr zpt tst_z rLSR,fLSR,$ff-fnzc dex bpl tlsr3 - ldx #3 + ldx #5 trol2 - set_z zp1,0 + set_z zps,0 rol zpt tst_z rROL,fROL,0 dex bpl trol2 - ldx #3 + ldx #5 trol3 - set_z zp1,$ff-fc + set_z zps,$ff-fc rol zpt tst_z rROL,fROL,$ff-fnzc dex bpl trol3 - ldx #3 + ldx #5 trolc2 - set_z zp1,fc + set_z zps,fc rol zpt tst_z rROLc,fROLc,0 dex bpl trolc2 - ldx #3 + ldx #5 trolc3 - set_z zp1,$ff + set_z zps,$ff rol zpt tst_z rROLc,fROLc,$ff-fnzc dex bpl trolc3 - ldx #3 + ldx #5 tror2 - set_z zp1,0 + set_z zps,0 ror zpt tst_z rROR,fROR,0 dex bpl tror2 - ldx #3 + ldx #5 tror3 - set_z zp1,$ff-fc + set_z zps,$ff-fc ror zpt tst_z rROR,fROR,$ff-fnzc dex bpl tror3 - ldx #3 + ldx #5 trorc2 - set_z zp1,fc + set_z zps,fc ror zpt tst_z rRORc,fRORc,0 dex bpl trorc2 - ldx #3 + ldx #5 trorc3 - set_z zp1,$ff + set_z zps,$ff ror zpt tst_z rRORc,fRORc,$ff-fnzc dex @@ -4254,91 +4258,91 @@ trorc3 next_test ; shifts - absolute - ldx #3 + ldx #5 tasl4 - set_abs zp1,0 + set_abs zps,0 asl abst tst_abs rASL,fASL,0 dex bpl tasl4 - ldx #3 + ldx #5 tasl5 - set_abs zp1,$ff + set_abs zps,$ff asl abst tst_abs rASL,fASL,$ff-fnzc dex bpl tasl5 - ldx #3 + ldx #5 tlsr4 - set_abs zp1,0 + set_abs zps,0 lsr abst tst_abs rLSR,fLSR,0 dex bpl tlsr4 - ldx #3 + ldx #5 tlsr5 - set_abs zp1,$ff + set_abs zps,$ff lsr abst tst_abs rLSR,fLSR,$ff-fnzc dex bpl tlsr5 - ldx #3 + ldx #5 trol4 - set_abs zp1,0 + set_abs zps,0 rol abst tst_abs rROL,fROL,0 dex bpl trol4 - ldx #3 + ldx #5 trol5 - set_abs zp1,$ff-fc + set_abs zps,$ff-fc rol abst tst_abs rROL,fROL,$ff-fnzc dex bpl trol5 - ldx #3 + ldx #5 trolc4 - set_abs zp1,fc + set_abs zps,fc rol abst tst_abs rROLc,fROLc,0 dex bpl trolc4 - ldx #3 + ldx #5 trolc5 - set_abs zp1,$ff + set_abs zps,$ff rol abst tst_abs rROLc,fROLc,$ff-fnzc dex bpl trolc5 - ldx #3 + ldx #5 tror4 - set_abs zp1,0 + set_abs zps,0 ror abst tst_abs rROR,fROR,0 dex bpl tror4 - ldx #3 + ldx #5 tror5 - set_abs zp1,$ff-fc + set_abs zps,$ff-fc ror abst tst_abs rROR,fROR,$ff-fnzc dex bpl tror5 - ldx #3 + ldx #5 trorc4 - set_abs zp1,fc + set_abs zps,fc ror abst tst_abs rRORc,fRORc,0 dex bpl trorc4 - ldx #3 + ldx #5 trorc5 - set_abs zp1,$ff + set_abs zps,$ff ror abst tst_abs rRORc,fRORc,$ff-fnzc dex @@ -4346,91 +4350,91 @@ trorc5 next_test ; shifts - zp indexed - ldx #3 + ldx #5 tasl6 - set_zx zp1,0 + set_zx zps,0 asl zpt,x tst_zx rASL,fASL,0 dex bpl tasl6 - ldx #3 + ldx #5 tasl7 - set_zx zp1,$ff + set_zx zps,$ff asl zpt,x tst_zx rASL,fASL,$ff-fnzc dex bpl tasl7 - ldx #3 + ldx #5 tlsr6 - set_zx zp1,0 + set_zx zps,0 lsr zpt,x tst_zx rLSR,fLSR,0 dex bpl tlsr6 - ldx #3 + ldx #5 tlsr7 - set_zx zp1,$ff + set_zx zps,$ff lsr zpt,x tst_zx rLSR,fLSR,$ff-fnzc dex bpl tlsr7 - ldx #3 + ldx #5 trol6 - set_zx zp1,0 + set_zx zps,0 rol zpt,x tst_zx rROL,fROL,0 dex bpl trol6 - ldx #3 + ldx #5 trol7 - set_zx zp1,$ff-fc + set_zx zps,$ff-fc rol zpt,x tst_zx rROL,fROL,$ff-fnzc dex bpl trol7 - ldx #3 + ldx #5 trolc6 - set_zx zp1,fc + set_zx zps,fc rol zpt,x tst_zx rROLc,fROLc,0 dex bpl trolc6 - ldx #3 + ldx #5 trolc7 - set_zx zp1,$ff + set_zx zps,$ff rol zpt,x tst_zx rROLc,fROLc,$ff-fnzc dex bpl trolc7 - ldx #3 + ldx #5 tror6 - set_zx zp1,0 + set_zx zps,0 ror zpt,x tst_zx rROR,fROR,0 dex bpl tror6 - ldx #3 + ldx #5 tror7 - set_zx zp1,$ff-fc + set_zx zps,$ff-fc ror zpt,x tst_zx rROR,fROR,$ff-fnzc dex bpl tror7 - ldx #3 + ldx #5 trorc6 - set_zx zp1,fc + set_zx zps,fc ror zpt,x tst_zx rRORc,fRORc,0 dex bpl trorc6 - ldx #3 + ldx #5 trorc7 - set_zx zp1,$ff + set_zx zps,$ff ror zpt,x tst_zx rRORc,fRORc,$ff-fnzc dex @@ -4438,91 +4442,91 @@ trorc7 next_test ; shifts - abs indexed - ldx #3 + ldx #5 tasl8 - set_absx zp1,0 + set_absx zps,0 asl abst,x tst_absx rASL,fASL,0 dex bpl tasl8 - ldx #3 + ldx #5 tasl9 - set_absx zp1,$ff + set_absx zps,$ff asl abst,x tst_absx rASL,fASL,$ff-fnzc dex bpl tasl9 - ldx #3 + ldx #5 tlsr8 - set_absx zp1,0 + set_absx zps,0 lsr abst,x tst_absx rLSR,fLSR,0 dex bpl tlsr8 - ldx #3 + ldx #5 tlsr9 - set_absx zp1,$ff + set_absx zps,$ff lsr abst,x tst_absx rLSR,fLSR,$ff-fnzc dex bpl tlsr9 - ldx #3 + ldx #5 trol8 - set_absx zp1,0 + set_absx zps,0 rol abst,x tst_absx rROL,fROL,0 dex bpl trol8 - ldx #3 + ldx #5 trol9 - set_absx zp1,$ff-fc + set_absx zps,$ff-fc rol abst,x tst_absx rROL,fROL,$ff-fnzc dex bpl trol9 - ldx #3 + ldx #5 trolc8 - set_absx zp1,fc + set_absx zps,fc rol abst,x tst_absx rROLc,fROLc,0 dex bpl trolc8 - ldx #3 + ldx #5 trolc9 - set_absx zp1,$ff + set_absx zps,$ff rol abst,x tst_absx rROLc,fROLc,$ff-fnzc dex bpl trolc9 - ldx #3 + ldx #5 tror8 - set_absx zp1,0 + set_absx zps,0 ror abst,x tst_absx rROR,fROR,0 dex bpl tror8 - ldx #3 + ldx #5 tror9 - set_absx zp1,$ff-fc + set_absx zps,$ff-fc ror abst,x tst_absx rROR,fROR,$ff-fnzc dex bpl tror9 - ldx #3 + ldx #5 trorc8 - set_absx zp1,fc + set_absx zps,fc ror abst,x tst_absx rRORc,fRORc,0 dex bpl trorc8 - ldx #3 + ldx #5 trorc9 - set_absx zp1,$ff + set_absx zps,$ff ror abst,x tst_absx rRORc,fRORc,$ff-fnzc dex @@ -5997,6 +6001,7 @@ break2 ;BRK pass 2 ;copy of data to initialize BSS segment if load_data_direct != 1 zp_init +zps_ db $80,1 ;additional shift pattern to test zero result & flag zp1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR zp7f_ db $7f ;test pattern for compare ;logical zeropage operands @@ -6048,34 +6053,35 @@ ex_adc_ adc #0 ;execute immediate opcodes rts ex_sbc_ sbc #0 ;execute immediate opcodes rts +;zps db $80,1 ;additional shift patterns test zero result & flag abs1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR abs7f_ db $7f ;test pattern for compare ;loads -fLDx_ db fn,fn,0,fz ;expected flags for load +fLDx_ db fn,fn,0,fz ;expected flags for load ;shifts -rASL_ ;expected result ASL & ROL -carry -rROL_ db $86,$04,$82,0 ; " -rROLc_ db $87,$05,$83,1 ;expected result ROL +carry -rLSR_ ;expected result LSR & ROR -carry -rROR_ db $61,$41,$20,0 ; " -rRORc_ db $e1,$c1,$a0,$80 ;expected result ROR +carry -fASL_ ;expected flags for shifts -fROL_ db fnc,fc,fn,fz ;no carry in -fROLc_ db fnc,fc,fn,0 ;carry in +rASL_ ;expected result ASL & ROL -carry +rROL_ db 0,2,$86,$04,$82,0 +rROLc_ db 1,3,$87,$05,$83,1 ;expected result ROL +carry +rLSR_ ;expected result LSR & ROR -carry +rROR_ db $40,0,$61,$41,$20,0 +rRORc_ db $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry +fASL_ ;expected flags for shifts +fROL_ db fzc,0,fnc,fc,fn,fz ;no carry in +fROLc_ db fc,0,fnc,fc,fn,0 ;carry in fLSR_ -fROR_ db fc,0,fc,fz ;no carry in -fRORc_ db fnc,fn,fnc,fn ;carry in +fROR_ db 0,fzc,fc,0,fc,fz ;no carry in +fRORc_ db fn,fnc,fnc,fn,fnc,fn ;carry in ;increments (decrements) -rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC -fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC +rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC +fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC ;logical memory operand -absOR_ db 0,$1f,$71,$80 ;test pattern for OR -absAN_ db $0f,$ff,$7f,$80 ;test pattern for AND -absEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR +absOR_ db 0,$1f,$71,$80 ;test pattern for OR +absAN_ db $0f,$ff,$7f,$80 ;test pattern for AND +absEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR ;logical accu operand -absORa_ db 0,$f1,$1f,0 ;test pattern for OR -absANa_ db $f0,$ff,$ff,$ff ;test pattern for AND -absEOa_ db $ff,$f0,$f0,$0f ;test pattern for EOR +absORa_ db 0,$f1,$1f,0 ;test pattern for OR +absANa_ db $f0,$ff,$ff,$ff ;test pattern for AND +absEOa_ db $ff,$f0,$f0,$0f ;test pattern for EOR ;logical results absrlo_ db 0,$ff,$7f,$80 absflo_ db fz,fn,0,fn diff --git a/src/test/kotlin/6502_functional_tests/65C02_decimal_test.a65 b/src/test/kotlin/6502_functional_tests/65C02_decimal_test.a65 new file mode 100644 index 0000000..5fcc0c6 --- /dev/null +++ b/src/test/kotlin/6502_functional_tests/65C02_decimal_test.a65 @@ -0,0 +1,356 @@ +; Verify decimal mode behavior +; Written by Bruce Clark. This code is public domain. +; see http://www.6502.org/tutorials/decimal_mode.html +; +; Returns: +; ERROR = 0 if the test passed +; ERROR = 1 if the test failed +; modify the code at the DONE label for desired program end +; +; This routine requires 17 bytes of RAM -- 1 byte each for: +; AR, CF, DA, DNVZC, ERROR, HA, HNVZC, N1, N1H, N1L, N2, N2L, NF, VF, and ZF +; and 2 bytes for N2H +; +; Variables: +; N1 and N2 are the two numbers to be added or subtracted +; N1H, N1L, N2H, and N2L are the upper 4 bits and lower 4 bits of N1 and N2 +; DA and DNVZC are the actual accumulator and flag results in decimal mode +; HA and HNVZC are the accumulator and flag results when N1 and N2 are +; added or subtracted using binary arithmetic +; AR, NF, VF, ZF, and CF are the predicted decimal mode accumulator and +; flag results, calculated using binary arithmetic +; +; This program takes approximately 1 minute at 1 MHz (a few seconds more on +; a 65C02 than a 6502 or 65816) +; + +; Configuration: +cputype = 1 ; 0 = 6502, 1 = 65C02, 2 = 65C816 +vld_bcd = 0 ; 0 = allow invalid bcd, 1 = valid bcd only +chk_a = 1 ; check accumulator +chk_n = 0 ; check sign (negative) flag +chk_v = 0 ; check overflow flag +chk_z = 0 ; check zero flag +chk_c = 1 ; check carry flag + +end_of_test macro + brk + ; db $db ;execute 65C02 stop instruction + endm + + bss + org 0 +; operands - register Y = carry in +N1 ds 1 +N2 ds 1 +; binary result +HA ds 1 +HNVZC ds 1 + ;04 +; decimal result +DA ds 1 +DNVZC ds 1 +; predicted results +AR ds 1 +NF ds 1 + ;08 +VF ds 1 +ZF ds 1 +CF ds 1 +ERROR ds 1 + ;0C +; workspace +N1L ds 1 +N1H ds 1 +N2L ds 1 +N2H ds 2 + + code + org $200 +TEST ldy #1 ; initialize Y (used to loop through carry flag values) + sty ERROR ; store 1 in ERROR until the test passes + lda #0 ; initialize N1 and N2 + sta N1 + sta N2 +LOOP1 lda N2 ; N2L = N2 & $0F + and #$0F ; [1] see text + if vld_bcd = 1 + cmp #$0a + bcs NEXT2 + endif + sta N2L + lda N2 ; N2H = N2 & $F0 + and #$F0 ; [2] see text + if vld_bcd = 1 + cmp #$a0 + bcs NEXT2 + endif + sta N2H + ora #$0F ; N2H+1 = (N2 & $F0) + $0F + sta N2H+1 +LOOP2 lda N1 ; N1L = N1 & $0F + and #$0F ; [3] see text + if vld_bcd = 1 + cmp #$0a + bcs NEXT1 + endif + sta N1L + lda N1 ; N1H = N1 & $F0 + and #$F0 ; [4] see text + if vld_bcd = 1 + cmp #$a0 + bcs NEXT1 + endif + sta N1H + jsr ADD + jsr A6502 + jsr COMPARE + bne DONE + jsr SUB + jsr S6502 + jsr COMPARE + bne DONE +NEXT1 inc N1 ; [5] see text + bne LOOP2 ; loop through all 256 values of N1 +NEXT2 inc N2 ; [6] see text + bne LOOP1 ; loop through all 256 values of N2 + dey + bpl LOOP1 ; loop through both values of the carry flag + lda #0 ; test passed, so store 0 in ERROR + sta ERROR +DONE + end_of_test + +; Calculate the actual decimal mode accumulator and flags, the accumulator +; and flag results when N1 is added to N2 using binary arithmetic, the +; predicted accumulator result, the predicted carry flag, and the predicted +; V flag +; +ADD sed ; decimal mode + cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1 + adc N2 + sta DA ; actual accumulator result in decimal mode + php + pla + sta DNVZC ; actual flags result in decimal mode + cld ; binary mode + cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1 + adc N2 + sta HA ; accumulator result of N1+N2 using binary arithmetic + + php + pla + sta HNVZC ; flags result of N1+N2 using binary arithmetic + cpy #1 + lda N1L + adc N2L + cmp #$0A + ldx #0 + bcc A1 + inx + adc #5 ; add 6 (carry is set) + and #$0F + sec +A1 ora N1H +; +; if N1L + N2L < $0A, then add N2 & $F0 +; if N1L + N2L >= $0A, then add (N2 & $F0) + $0F + 1 (carry is set) +; + adc N2H,x + php + bcs A2 + cmp #$A0 + bcc A3 +A2 adc #$5F ; add $60 (carry is set) + sec +A3 sta AR ; predicted accumulator result + php + pla + sta CF ; predicted carry result + pla +; +; note that all 8 bits of the P register are stored in VF +; + sta VF ; predicted V flags + rts + +; Calculate the actual decimal mode accumulator and flags, and the +; accumulator and flag results when N2 is subtracted from N1 using binary +; arithmetic +; +SUB sed ; decimal mode + cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1 + sbc N2 + sta DA ; actual accumulator result in decimal mode + php + pla + sta DNVZC ; actual flags result in decimal mode + cld ; binary mode + cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1 + sbc N2 + sta HA ; accumulator result of N1-N2 using binary arithmetic + + php + pla + sta HNVZC ; flags result of N1-N2 using binary arithmetic + rts + + if cputype != 1 +; Calculate the predicted SBC accumulator result for the 6502 and 65816 +; +SUB1 cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1L + sbc N2L + ldx #0 + bcs S11 + inx + sbc #5 ; subtract 6 (carry is clear) + and #$0F + clc +S11 ora N1H +; +; if N1L - N2L >= 0, then subtract N2 & $F0 +; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear) +; + sbc N2H,x + bcs S12 + sbc #$5F ; subtract $60 (carry is clear) +S12 sta AR + rts + endif + + if cputype = 1 +; Calculate the predicted SBC accumulator result for the 6502 and 65C02 +; +SUB2 cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1L + sbc N2L + ldx #0 + bcs S21 + inx + and #$0F + clc +S21 ora N1H +; +; if N1L - N2L >= 0, then subtract N2 & $F0 +; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear) +; + sbc N2H,x + bcs S22 + sbc #$5F ; subtract $60 (carry is clear) +S22 cpx #0 + beq S23 + sbc #6 +S23 sta AR ; predicted accumulator result + rts + endif + +; Compare accumulator actual results to predicted results +; +; Return: +; Z flag = 1 (BEQ branch) if same +; Z flag = 0 (BNE branch) if different +; +COMPARE + if chk_a = 1 + lda DA + cmp AR + bne C1 + endif + if chk_n = 1 + lda DNVZC ; [7] see text + eor NF + and #$80 ; mask off N flag + bne C1 + endif + if chk_v = 1 + lda DNVZC ; [8] see text + eor VF + and #$40 ; mask off V flag + bne C1 ; [9] see text + endif + if chk_z = 1 + lda DNVZC + eor ZF ; mask off Z flag + and #2 + bne C1 ; [10] see text + endif + if chk_c = 1 + lda DNVZC + eor CF + and #1 ; mask off C flag + endif +C1 rts + +; These routines store the predicted values for ADC and SBC for the 6502, +; 65C02, and 65816 in AR, CF, NF, VF, and ZF + + if cputype = 0 + +A6502 lda VF ; 6502 +; +; since all 8 bits of the P register were stored in VF, bit 7 of VF contains +; the N flag for NF +; + sta NF + lda HNVZC + sta ZF + rts + +S6502 jsr SUB1 + lda HNVZC + sta NF + sta VF + sta ZF + sta CF + rts + + endif + if cputype = 1 + +A6502 lda AR ; 65C02 + php + pla + sta NF + sta ZF + rts + +S6502 jsr SUB2 + lda AR + php + pla + sta NF + sta ZF + lda HNVZC + sta VF + sta CF + rts + + endif + if cputype = 2 + +A6502 lda AR ; 65C816 + php + pla + sta NF + sta ZF + rts + +S6502 jsr SUB1 + lda AR + php + pla + sta NF + sta ZF + lda HNVZC + sta VF + sta CF + rts + + endif + + end TEST diff --git a/src/test/kotlin/6502_functional_tests/as65_142.zip b/src/test/kotlin/6502_functional_tests/as65_142.zip new file mode 100644 index 0000000..5bf9492 Binary files /dev/null and b/src/test/kotlin/6502_functional_tests/as65_142.zip differ diff --git a/src/test/kotlin/6502_functional_tests/bin_files/6502_decimal_test.bin b/src/test/kotlin/6502_functional_tests/bin_files/6502_decimal_test.bin new file mode 100644 index 0000000..7d367a5 Binary files /dev/null and b/src/test/kotlin/6502_functional_tests/bin_files/6502_decimal_test.bin differ diff --git a/src/test/kotlin/6502_functional_tests/bin_files/6502_decimal_test.lst b/src/test/kotlin/6502_functional_tests/bin_files/6502_decimal_test.lst new file mode 100644 index 0000000..19f3ede --- /dev/null +++ b/src/test/kotlin/6502_functional_tests/bin_files/6502_decimal_test.lst @@ -0,0 +1,9 @@ +AS65 Assembler for R6502 [1.42]. Page 1 +--------------------------- 6502_decimal_test.a65 ---------------------------- + +356 lines read, no errors in pass 1. +No errors in pass 2. +Wrote binary from address $0200 through $02e9. +Total size 234 bytes. +Program start address is at $0200 (512). + \ No newline at end of file diff --git a/src/test/kotlin/6502_functional_tests/bin_files/6502_functional_test.bin b/src/test/kotlin/6502_functional_tests/bin_files/6502_functional_test.bin index c9a35e1..5b6686a 100644 Binary files a/src/test/kotlin/6502_functional_tests/bin_files/6502_functional_test.bin and b/src/test/kotlin/6502_functional_tests/bin_files/6502_functional_test.bin differ diff --git a/src/test/kotlin/6502_functional_tests/bin_files/6502_functional_test.lst b/src/test/kotlin/6502_functional_tests/bin_files/6502_functional_test.lst index d178888..ca5fd45 100644 --- a/src/test/kotlin/6502_functional_tests/bin_files/6502_functional_test.lst +++ b/src/test/kotlin/6502_functional_tests/bin_files/6502_functional_test.lst @@ -1,11 +1,11 @@ AS65 Assembler for R6502 [1.42]. Copyright 1994-2007, Frank A. Kingswood Page 1 ---------------------------------------------------- 6502_functional_test.a65 ---------------------------------------------------- -6104 lines read, no errors in pass 1. +6108 lines read, no errors in pass 1. ; ; 6 5 0 2 F U N C T I O N A L T E S T ; - ; Copyright (C) 2012-2015 Klaus Dormann + ; Copyright (C) 2012-2020 Klaus Dormann ; ; This program is free software: you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by @@ -25,10 +25,11 @@ AS65 Assembler for R6502 [1.42]. Copyright 1994-2007, Frank A. Kingswood ; addressing modes with focus on propper setting of the processor status ; register bits. ; - ; version 04-dec-2017 + ; version 05-jan-2020 ; contact info at http://2m5.de or email K@2m5.de ; - ; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/ + ; assembled with AS65 written by Frank A. Kingswood + ; The assembler as65_142.zip can be obtained from my GitHub repository ; command line switches: -l -m -s2 -w -h0 ; | | | | no page headers in listing ; | | | wide listing (133 char/col) @@ -80,7 +81,8 @@ AS65 Assembler for R6502 [1.42]. Copyright 1994-2007, Frank A. Kingswood ; 04-dec-2017 fixed BRK only tested with interrupts enabled ; added option to skip the remainder of a failing test ; in report.i65 - + ; 05-jan-2020 fixed shifts not testing zero result and flag when last 1-bit + ; is shifted out ; C O N F I G U R A T I O N @@ -100,17 +102,17 @@ AS65 Assembler for R6502 [1.42]. Copyright 1994-2007, Frank A. Kingswood 0003 = I_flag = 3 ;configure memory - try to stay away from memory used by the system - ;zero_page memory start address, $50 (80) consecutive Bytes required + ;zero_page memory start address, $52 (82) consecutive Bytes required ; add 2 if I_flag = 2 000a = zero_page = $a - ;data_segment memory start address, $6A (106) consecutive Bytes required + ;data_segment memory start address, $7B (123) consecutive Bytes required 0200 = data_segment = $200 if (data_segment & $ff) != 0 ERROR ERROR ERROR low byte of data_segment MUST be $00 !! endif - ;code_segment memory start address, 13kB of consecutive space required + ;code_segment memory start address, 13.1kB of consecutive space required ; add 2.5 kB if I_flag = 2 0400 = code_segment = $400 @@ -616,9 +618,7 @@ ffff = ram_top = -1 else bss ;uninitialized segment, copy of data at end of code! endif - ; org zero_page -0000 = org 0 ;edited to provide binaries loading from 0 -0000 : 00000000000000.. ds zero_page +000a = org zero_page ;break test interrupt save 000a : 00 irq_a ds 1 ;a register 000b : 00 irq_x ds 1 ;x register @@ -627,7 +627,7 @@ ffff = ram_top = -1 flag_I_on ds 1 ;or mask to load flags flag_I_off ds 1 ;and mask to load flags endif -000c : zpt ;5 bytes store/modify test area +000c : zpt ;6 bytes store/modify test area ;add/subtract operand generation and result/flag prediction 000c : 00 adfc ds 1 ;carry flag before op 000d : 00 ad1 ds 1 ;operand 1 - accumulator @@ -637,63 +637,64 @@ ffff = ram_top = -1 0011 : 00 adrf ds 1 ;expected flags NV0000ZC (only binary mode) 0012 : 00 sb2 ds 1 ;operand 2 complemented for subtract 0013 : zp_bss -0013 : c3824100 zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR -0017 : 7f zp7f db $7f ;test pattern for compare +0013 : 8001 zps db $80,1 ;additional shift pattern to test zero result & flag +0015 : c3824100 zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +0019 : 7f zp7f db $7f ;test pattern for compare ;logical zeropage operands -0018 : 001f7180 zpOR db 0,$1f,$71,$80 ;test pattern for OR -001c : 0fff7f80 zpAN db $0f,$ff,$7f,$80 ;test pattern for AND -0020 : ff0f8f8f zpEO db $ff,$0f,$8f,$8f ;test pattern for EOR +001a : 001f7180 zpOR db 0,$1f,$71,$80 ;test pattern for OR +001e : 0fff7f80 zpAN db $0f,$ff,$7f,$80 ;test pattern for AND +0022 : ff0f8f8f zpEO db $ff,$0f,$8f,$8f ;test pattern for EOR ;indirect addressing pointers -0024 : 1702 ind1 dw abs1 ;indirect pointer to pattern in absolute memory -0026 : 1802 dw abs1+1 -0028 : 1902 dw abs1+2 -002a : 1a02 dw abs1+3 -002c : 1b02 dw abs7f -002e : 1f01 inw1 dw abs1-$f8 ;indirect pointer for wrap-test pattern -0030 : 0302 indt dw abst ;indirect pointer to store area in absolute memory -0032 : 0402 dw abst+1 -0034 : 0502 dw abst+2 -0036 : 0602 dw abst+3 -0038 : 0b01 inwt dw abst-$f8 ;indirect pointer for wrap-test store -003a : 4e02 indAN dw absAN ;indirect pointer to AND pattern in absolute memory -003c : 4f02 dw absAN+1 -003e : 5002 dw absAN+2 -0040 : 5102 dw absAN+3 -0042 : 5202 indEO dw absEO ;indirect pointer to EOR pattern in absolute memory -0044 : 5302 dw absEO+1 -0046 : 5402 dw absEO+2 -0048 : 5502 dw absEO+3 -004a : 4a02 indOR dw absOR ;indirect pointer to OR pattern in absolute memory -004c : 4b02 dw absOR+1 -004e : 4c02 dw absOR+2 -0050 : 4d02 dw absOR+3 +0026 : 1802 ind1 dw abs1 ;indirect pointer to pattern in absolute memory +0028 : 1902 dw abs1+1 +002a : 1a02 dw abs1+2 +002c : 1b02 dw abs1+3 +002e : 1c02 dw abs7f +0030 : 2001 inw1 dw abs1-$f8 ;indirect pointer for wrap-test pattern +0032 : 0302 indt dw abst ;indirect pointer to store area in absolute memory +0034 : 0402 dw abst+1 +0036 : 0502 dw abst+2 +0038 : 0602 dw abst+3 +003a : 0b01 inwt dw abst-$f8 ;indirect pointer for wrap-test store +003c : 5f02 indAN dw absAN ;indirect pointer to AND pattern in absolute memory +003e : 6002 dw absAN+1 +0040 : 6102 dw absAN+2 +0042 : 6202 dw absAN+3 +0044 : 6302 indEO dw absEO ;indirect pointer to EOR pattern in absolute memory +0046 : 6402 dw absEO+1 +0048 : 6502 dw absEO+2 +004a : 6602 dw absEO+3 +004c : 5b02 indOR dw absOR ;indirect pointer to OR pattern in absolute memory +004e : 5c02 dw absOR+1 +0050 : 5d02 dw absOR+2 +0052 : 5e02 dw absOR+3 ;add/subtract indirect pointers -0052 : 0302 adi2 dw ada2 ;indirect pointer to operand 2 in absolute memory -0054 : 0402 sbi2 dw sba2 ;indirect pointer to complemented operand 2 (SBC) -0056 : 0401 adiy2 dw ada2-$ff ;with offset for indirect indexed -0058 : 0501 sbiy2 dw sba2-$ff -005a : zp_bss_end +0054 : 0302 adi2 dw ada2 ;indirect pointer to operand 2 in absolute memory +0056 : 0402 sbi2 dw sba2 ;indirect pointer to complemented operand 2 (SBC) +0058 : 0401 adiy2 dw ada2-$ff ;with offset for indirect indexed +005a : 0501 sbiy2 dw sba2-$ff +005c : zp_bss_end 0200 = org data_segment 0200 : 00 test_case ds 1 ;current test number 0201 : 0000 ram_chksm ds 2 ;checksum for RAM integrity test ;add/subtract operand copy - abs tests write area -0203 : abst ;5 bytes store/modify test area +0203 : abst ;6 bytes store/modify test area 0203 : 00 ada2 ds 1 ;operand 2 0204 : 00 sba2 ds 1 ;operand 2 complemented for subtract -0205 : 000000 ds 3 ;fill remaining bytes -0208 : data_bss +0205 : 00000000 ds 4 ;fill remaining bytes +0209 : data_bss if load_data_direct = 1 -0208 : 2900 ex_andi and #0 ;execute immediate opcodes -020a : 60 rts -020b : 4900 ex_eori eor #0 ;execute immediate opcodes -020d : 60 rts -020e : 0900 ex_orai ora #0 ;execute immediate opcodes -0210 : 60 rts -0211 : 6900 ex_adci adc #0 ;execute immediate opcodes -0213 : 60 rts -0214 : e900 ex_sbci sbc #0 ;execute immediate opcodes -0216 : 60 rts +0209 : 2900 ex_andi and #0 ;execute immediate opcodes +020b : 60 rts +020c : 4900 ex_eori eor #0 ;execute immediate opcodes +020e : 60 rts +020f : 0900 ex_orai ora #0 ;execute immediate opcodes +0211 : 60 rts +0212 : 6900 ex_adci adc #0 ;execute immediate opcodes +0214 : 60 rts +0215 : e900 ex_sbci sbc #0 ;execute immediate opcodes +0217 : 60 rts else ex_andi ds 3 ex_eori ds 3 @@ -701,38 +702,39 @@ ffff = ram_top = -1 ex_adci ds 3 ex_sbci ds 3 endif -0217 : c3824100 abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR -021b : 7f abs7f db $7f ;test pattern for compare + ;zps db $80,1 ;additional shift patterns test zero result & flag +0218 : c3824100 abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +021c : 7f abs7f db $7f ;test pattern for compare ;loads -021c : 80800002 fLDx db fn,fn,0,fz ;expected flags for load +021d : 80800002 fLDx db fn,fn,0,fz ;expected flags for load ;shifts -0220 : rASL ;expected result ASL & ROL -carry -0220 : 86048200 rROL db $86,$04,$82,0 ; " -0224 : 87058301 rROLc db $87,$05,$83,1 ;expected result ROL +carry -0228 : rLSR ;expected result LSR & ROR -carry -0228 : 61412000 rROR db $61,$41,$20,0 ; " -022c : e1c1a080 rRORc db $e1,$c1,$a0,$80 ;expected result ROR +carry -0230 : fASL ;expected flags for shifts -0230 : 81018002 fROL db fnc,fc,fn,fz ;no carry in -0234 : 81018000 fROLc db fnc,fc,fn,0 ;carry in -0238 : fLSR -0238 : 01000102 fROR db fc,0,fc,fz ;no carry in -023c : 81808180 fRORc db fnc,fn,fnc,fn ;carry in +0221 : rASL ;expected result ASL & ROL -carry +0221 : 000286048200 rROL db 0,2,$86,$04,$82,0 +0227 : 010387058301 rROLc db 1,3,$87,$05,$83,1 ;expected result ROL +carry +022d : rLSR ;expected result LSR & ROR -carry +022d : 400061412000 rROR db $40,0,$61,$41,$20,0 +0233 : c080e1c1a080 rRORc db $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry +0239 : fASL ;expected flags for shifts +0239 : 030081018002 fROL db fzc,0,fnc,fc,fn,fz ;no carry in +023f : 010081018000 fROLc db fc,0,fnc,fc,fn,0 ;carry in +0245 : fLSR +0245 : 000301000102 fROR db 0,fzc,fc,0,fc,fz ;no carry in +024b : 808181808180 fRORc db fn,fnc,fnc,fn,fnc,fn ;carry in ;increments (decrements) -0240 : 7f80ff0001 rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC -0245 : 0080800200 fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC +0251 : 7f80ff0001 rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC +0256 : 0080800200 fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC ;logical memory operand -024a : 001f7180 absOR db 0,$1f,$71,$80 ;test pattern for OR -024e : 0fff7f80 absAN db $0f,$ff,$7f,$80 ;test pattern for AND -0252 : ff0f8f8f absEO db $ff,$0f,$8f,$8f ;test pattern for EOR +025b : 001f7180 absOR db 0,$1f,$71,$80 ;test pattern for OR +025f : 0fff7f80 absAN db $0f,$ff,$7f,$80 ;test pattern for AND +0263 : ff0f8f8f absEO db $ff,$0f,$8f,$8f ;test pattern for EOR ;logical accu operand -0256 : 00f11f00 absORa db 0,$f1,$1f,0 ;test pattern for OR -025a : f0ffffff absANa db $f0,$ff,$ff,$ff ;test pattern for AND -025e : fff0f00f absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR +0267 : 00f11f00 absORa db 0,$f1,$1f,0 ;test pattern for OR +026b : f0ffffff absANa db $f0,$ff,$ff,$ff ;test pattern for AND +026f : fff0f00f absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR ;logical results -0262 : 00ff7f80 absrlo db 0,$ff,$7f,$80 -0266 : 02800080 absflo db fz,fn,0,fn -026a : data_bss_end +0273 : 00ff7f80 absrlo db 0,$ff,$7f,$80 +0277 : 02800080 absflo db fz,fn,0,fn +027b : data_bss_end code @@ -3930,7 +3932,7 @@ ffff = ram_top = -1 0e56 : 48 > pha ;use stack to load status 0e57 : 28 > plp -0e58 : b613 ldx zp1,y +0e58 : b615 ldx zp1,y 0e5a : 08 php ;test stores do not alter flags 0e5b : 8a txa 0e5c : 49c3 eor #$c3 @@ -3938,7 +3940,7 @@ ffff = ram_top = -1 0e5f : 990302 sta abst,y 0e62 : 08 php ;flags after load/store sequence 0e63 : 49c3 eor #$c3 -0e65 : d91702 cmp abs1,y ;test result +0e65 : d91802 cmp abs1,y ;test result trap_ne 0e68 : d0fe > bne * ;failed not equal (non zero) @@ -3946,7 +3948,7 @@ ffff = ram_top = -1 eor_flag 0 0e6b : 4930 > eor #0|fao ;invert expected flags + always on bits -0e6d : d91c02 cmp fLDx,y ;test flags +0e6d : d91d02 cmp fLDx,y ;test flags trap_ne 0e70 : d0fe > bne * ;failed not equal (non zero) @@ -3962,7 +3964,7 @@ ffff = ram_top = -1 0e79 : 48 > pha ;use stack to load status 0e7a : 28 > plp -0e7b : b613 ldx zp1,y +0e7b : b615 ldx zp1,y 0e7d : 08 php ;test stores do not alter flags 0e7e : 8a txa 0e7f : 49c3 eor #$c3 @@ -3970,7 +3972,7 @@ ffff = ram_top = -1 0e82 : 990302 sta abst,y 0e85 : 08 php ;flags after load/store sequence 0e86 : 49c3 eor #$c3 -0e88 : d91702 cmp abs1,y ;test result +0e88 : d91802 cmp abs1,y ;test result trap_ne 0e8b : d0fe > bne * ;failed not equal (non zero) @@ -3978,7 +3980,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 0e8e : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -0e90 : d91c02 cmp fLDx,y ;test flags +0e90 : d91d02 cmp fLDx,y ;test flags trap_ne 0e93 : d0fe > bne * ;failed not equal (non zero) @@ -3994,7 +3996,7 @@ ffff = ram_top = -1 0e9c : 48 > pha ;use stack to load status 0e9d : 28 > plp -0e9e : be1702 ldx abs1,y +0e9e : be1802 ldx abs1,y 0ea1 : 08 php ;test stores do not alter flags 0ea2 : 8a txa 0ea3 : 49c3 eor #$c3 @@ -4003,7 +4005,7 @@ ffff = ram_top = -1 0ea7 : 960c stx zpt,y 0ea9 : 08 php ;flags after load/store sequence 0eaa : 49c3 eor #$c3 -0eac : d91300 cmp zp1,y ;test result +0eac : d91500 cmp zp1,y ;test result trap_ne 0eaf : d0fe > bne * ;failed not equal (non zero) @@ -4011,7 +4013,7 @@ ffff = ram_top = -1 eor_flag 0 0eb2 : 4930 > eor #0|fao ;invert expected flags + always on bits -0eb4 : d91c02 cmp fLDx,y ;test flags +0eb4 : d91d02 cmp fLDx,y ;test flags trap_ne 0eb7 : d0fe > bne * ;failed not equal (non zero) @@ -4027,7 +4029,7 @@ ffff = ram_top = -1 0ec0 : 48 > pha ;use stack to load status 0ec1 : 28 > plp -0ec2 : be1702 ldx abs1,y +0ec2 : be1802 ldx abs1,y 0ec5 : 08 php ;test stores do not alter flags 0ec6 : 8a txa 0ec7 : 49c3 eor #$c3 @@ -4036,7 +4038,7 @@ ffff = ram_top = -1 0ecb : 960c stx zpt,y 0ecd : 08 php ;flags after load/store sequence 0ece : 49c3 eor #$c3 -0ed0 : d91300 cmp zp1,y ;test result +0ed0 : d91500 cmp zp1,y ;test result trap_ne 0ed3 : d0fe > bne * ;failed not equal (non zero) @@ -4044,7 +4046,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 0ed6 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -0ed8 : d91c02 cmp fLDx,y ;test flags +0ed8 : d91d02 cmp fLDx,y ;test flags trap_ne 0edb : d0fe > bne * ;failed not equal (non zero) @@ -4055,14 +4057,14 @@ ffff = ram_top = -1 0ee2 : a200 ldx #0 0ee4 : b90c00 tstx lda zpt,y 0ee7 : 49c3 eor #$c3 -0ee9 : d91300 cmp zp1,y +0ee9 : d91500 cmp zp1,y trap_ne ;store to zp data 0eec : d0fe > bne * ;failed not equal (non zero) 0eee : 960c stx zpt,y ;clear 0ef0 : b90302 lda abst,y 0ef3 : 49c3 eor #$c3 -0ef5 : d91702 cmp abs1,y +0ef5 : d91802 cmp abs1,y trap_ne ;store to abs data 0ef8 : d0fe > bne * ;failed not equal (non zero) @@ -4084,14 +4086,14 @@ ffff = ram_top = -1 ; indexed wraparound test (only zp should wrap) 0f0d : a0fd ldy #3+$fa -0f0f : b619 tldx4 ldx zp1-$fa&$ff,y ;wrap on indexed zp +0f0f : b61b tldx4 ldx zp1-$fa&$ff,y ;wrap on indexed zp 0f11 : 8a txa 0f12 : 990901 sta abst-$fa,y ;no STX abs,y! 0f15 : 88 dey 0f16 : c0fa cpy #$fa 0f18 : b0f5 bcs tldx4 0f1a : a0fd ldy #3+$fa -0f1c : be1d01 tldx5 ldx abs1-$fa,y ;no wrap on indexed abs +0f1c : be1e01 tldx5 ldx abs1-$fa,y ;no wrap on indexed abs 0f1f : 9612 stx zpt-$fa&$ff,y 0f21 : 88 dey 0f22 : c0fa cpy #$fa @@ -4099,13 +4101,13 @@ ffff = ram_top = -1 0f26 : a003 ldy #3 ;testing wraparound result 0f28 : a200 ldx #0 0f2a : b90c00 tstx1 lda zpt,y -0f2d : d91300 cmp zp1,y +0f2d : d91500 cmp zp1,y trap_ne ;store to zp data 0f30 : d0fe > bne * ;failed not equal (non zero) 0f32 : 960c stx zpt,y ;clear 0f34 : b90302 lda abst,y -0f37 : d91702 cmp abs1,y +0f37 : d91802 cmp abs1,y trap_ne ;store to abs data 0f3a : d0fe > bne * ;failed not equal (non zero) @@ -4135,7 +4137,7 @@ ffff = ram_top = -1 0f53 : 48 > pha ;use stack to load status 0f54 : 28 > plp -0f55 : b413 ldy zp1,x +0f55 : b415 ldy zp1,x 0f57 : 08 php ;test stores do not alter flags 0f58 : 98 tya 0f59 : 49c3 eor #$c3 @@ -4143,7 +4145,7 @@ ffff = ram_top = -1 0f5c : 9d0302 sta abst,x 0f5f : 08 php ;flags after load/store sequence 0f60 : 49c3 eor #$c3 -0f62 : dd1702 cmp abs1,x ;test result +0f62 : dd1802 cmp abs1,x ;test result trap_ne 0f65 : d0fe > bne * ;failed not equal (non zero) @@ -4151,7 +4153,7 @@ ffff = ram_top = -1 eor_flag 0 0f68 : 4930 > eor #0|fao ;invert expected flags + always on bits -0f6a : dd1c02 cmp fLDx,x ;test flags +0f6a : dd1d02 cmp fLDx,x ;test flags trap_ne 0f6d : d0fe > bne * ;failed not equal (non zero) @@ -4167,7 +4169,7 @@ ffff = ram_top = -1 0f76 : 48 > pha ;use stack to load status 0f77 : 28 > plp -0f78 : b413 ldy zp1,x +0f78 : b415 ldy zp1,x 0f7a : 08 php ;test stores do not alter flags 0f7b : 98 tya 0f7c : 49c3 eor #$c3 @@ -4175,7 +4177,7 @@ ffff = ram_top = -1 0f7f : 9d0302 sta abst,x 0f82 : 08 php ;flags after load/store sequence 0f83 : 49c3 eor #$c3 -0f85 : dd1702 cmp abs1,x ;test result +0f85 : dd1802 cmp abs1,x ;test result trap_ne 0f88 : d0fe > bne * ;failed not equal (non zero) @@ -4183,7 +4185,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 0f8b : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -0f8d : dd1c02 cmp fLDx,x ;test flags +0f8d : dd1d02 cmp fLDx,x ;test flags trap_ne 0f90 : d0fe > bne * ;failed not equal (non zero) @@ -4199,7 +4201,7 @@ ffff = ram_top = -1 0f99 : 48 > pha ;use stack to load status 0f9a : 28 > plp -0f9b : bc1702 ldy abs1,x +0f9b : bc1802 ldy abs1,x 0f9e : 08 php ;test stores do not alter flags 0f9f : 98 tya 0fa0 : 49c3 eor #$c3 @@ -4208,7 +4210,7 @@ ffff = ram_top = -1 0fa4 : 940c sty zpt,x 0fa6 : 08 php ;flags after load/store sequence 0fa7 : 49c3 eor #$c3 -0fa9 : d513 cmp zp1,x ;test result +0fa9 : d515 cmp zp1,x ;test result trap_ne 0fab : d0fe > bne * ;failed not equal (non zero) @@ -4216,7 +4218,7 @@ ffff = ram_top = -1 eor_flag 0 0fae : 4930 > eor #0|fao ;invert expected flags + always on bits -0fb0 : dd1c02 cmp fLDx,x ;test flags +0fb0 : dd1d02 cmp fLDx,x ;test flags trap_ne 0fb3 : d0fe > bne * ;failed not equal (non zero) @@ -4232,7 +4234,7 @@ ffff = ram_top = -1 0fbc : 48 > pha ;use stack to load status 0fbd : 28 > plp -0fbe : bc1702 ldy abs1,x +0fbe : bc1802 ldy abs1,x 0fc1 : 08 php ;test stores do not alter flags 0fc2 : 98 tya 0fc3 : 49c3 eor #$c3 @@ -4241,7 +4243,7 @@ ffff = ram_top = -1 0fc7 : 940c sty zpt,x 0fc9 : 08 php ;flags after load/store sequence 0fca : 49c3 eor #$c3 -0fcc : d513 cmp zp1,x ;test result +0fcc : d515 cmp zp1,x ;test result trap_ne 0fce : d0fe > bne * ;failed not equal (non zero) @@ -4249,7 +4251,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 0fd1 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -0fd3 : dd1c02 cmp fLDx,x ;test flags +0fd3 : dd1d02 cmp fLDx,x ;test flags trap_ne 0fd6 : d0fe > bne * ;failed not equal (non zero) @@ -4260,14 +4262,14 @@ ffff = ram_top = -1 0fdd : a000 ldy #0 0fdf : b50c tsty lda zpt,x 0fe1 : 49c3 eor #$c3 -0fe3 : d513 cmp zp1,x +0fe3 : d515 cmp zp1,x trap_ne ;store to zp,x data 0fe5 : d0fe > bne * ;failed not equal (non zero) 0fe7 : 940c sty zpt,x ;clear 0fe9 : bd0302 lda abst,x 0fec : 49c3 eor #$c3 -0fee : dd1702 cmp abs1,x +0fee : dd1802 cmp abs1,x trap_ne ;store to abs,x data 0ff1 : d0fe > bne * ;failed not equal (non zero) @@ -4289,14 +4291,14 @@ ffff = ram_top = -1 ; indexed wraparound test (only zp should wrap) 1006 : a2fd ldx #3+$fa -1008 : b419 tldy4 ldy zp1-$fa&$ff,x ;wrap on indexed zp +1008 : b41b tldy4 ldy zp1-$fa&$ff,x ;wrap on indexed zp 100a : 98 tya 100b : 9d0901 sta abst-$fa,x ;no STX abs,x! 100e : ca dex 100f : e0fa cpx #$fa 1011 : b0f5 bcs tldy4 1013 : a2fd ldx #3+$fa -1015 : bc1d01 tldy5 ldy abs1-$fa,x ;no wrap on indexed abs +1015 : bc1e01 tldy5 ldy abs1-$fa,x ;no wrap on indexed abs 1018 : 9412 sty zpt-$fa&$ff,x 101a : ca dex 101b : e0fa cpx #$fa @@ -4304,13 +4306,13 @@ ffff = ram_top = -1 101f : a203 ldx #3 ;testing wraparound result 1021 : a000 ldy #0 1023 : b50c tsty1 lda zpt,x -1025 : d513 cmp zp1,x +1025 : d515 cmp zp1,x trap_ne ;store to zp,x data 1027 : d0fe > bne * ;failed not equal (non zero) 1029 : 940c sty zpt,x ;clear 102b : bd0302 lda abst,x -102e : dd1702 cmp abs1,x +102e : dd1802 cmp abs1,x trap_ne ;store to abs,x data 1031 : d0fe > bne * ;failed not equal (non zero) @@ -4338,7 +4340,7 @@ ffff = ram_top = -1 1048 : 48 > pha ;use stack to load status 1049 : 28 > plp -104a : a613 ldx zp1 +104a : a615 ldx zp1 104c : 08 php ;test stores do not alter flags 104d : 8a txa 104e : 49c3 eor #$c3 @@ -4356,7 +4358,7 @@ ffff = ram_top = -1 eor_flag 0 105e : 4930 > eor #0|fao ;invert expected flags + always on bits -1060 : cd1c02 cmp fLDx ;test flags +1060 : cd1d02 cmp fLDx ;test flags trap_ne 1063 : d0fe > bne * ;failed not equal (non zero) @@ -4367,7 +4369,7 @@ ffff = ram_top = -1 1067 : 48 > pha ;use stack to load status 1068 : 28 > plp -1069 : a614 ldx zp1+1 +1069 : a616 ldx zp1+1 106b : 08 php ;test stores do not alter flags 106c : 8a txa 106d : 49c3 eor #$c3 @@ -4385,7 +4387,7 @@ ffff = ram_top = -1 eor_flag 0 107d : 4930 > eor #0|fao ;invert expected flags + always on bits -107f : cd1d02 cmp fLDx+1 ;test flags +107f : cd1e02 cmp fLDx+1 ;test flags trap_ne 1082 : d0fe > bne * ;failed not equal (non zero) @@ -4396,7 +4398,7 @@ ffff = ram_top = -1 1086 : 48 > pha ;use stack to load status 1087 : 28 > plp -1088 : a615 ldx zp1+2 +1088 : a617 ldx zp1+2 108a : 08 php ;test stores do not alter flags 108b : 8a txa 108c : 49c3 eor #$c3 @@ -4414,7 +4416,7 @@ ffff = ram_top = -1 eor_flag 0 109c : 4930 > eor #0|fao ;invert expected flags + always on bits -109e : cd1e02 cmp fLDx+2 ;test flags +109e : cd1f02 cmp fLDx+2 ;test flags trap_ne 10a1 : d0fe > bne * ;failed not equal (non zero) @@ -4425,7 +4427,7 @@ ffff = ram_top = -1 10a5 : 48 > pha ;use stack to load status 10a6 : 28 > plp -10a7 : a616 ldx zp1+3 +10a7 : a618 ldx zp1+3 10a9 : 08 php ;test stores do not alter flags 10aa : 8a txa 10ab : 49c3 eor #$c3 @@ -4443,7 +4445,7 @@ ffff = ram_top = -1 eor_flag 0 10bb : 4930 > eor #0|fao ;invert expected flags + always on bits -10bd : cd1f02 cmp fLDx+3 ;test flags +10bd : cd2002 cmp fLDx+3 ;test flags trap_ne 10c0 : d0fe > bne * ;failed not equal (non zero) @@ -4455,7 +4457,7 @@ ffff = ram_top = -1 10c4 : 48 > pha ;use stack to load status 10c5 : 28 > plp -10c6 : a613 ldx zp1 +10c6 : a615 ldx zp1 10c8 : 08 php ;test stores do not alter flags 10c9 : 8a txa 10ca : 49c3 eor #$c3 @@ -4473,7 +4475,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 10da : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -10dc : cd1c02 cmp fLDx ;test flags +10dc : cd1d02 cmp fLDx ;test flags trap_ne 10df : d0fe > bne * ;failed not equal (non zero) @@ -4484,7 +4486,7 @@ ffff = ram_top = -1 10e3 : 48 > pha ;use stack to load status 10e4 : 28 > plp -10e5 : a614 ldx zp1+1 +10e5 : a616 ldx zp1+1 10e7 : 08 php ;test stores do not alter flags 10e8 : 8a txa 10e9 : 49c3 eor #$c3 @@ -4502,7 +4504,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 10f9 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -10fb : cd1d02 cmp fLDx+1 ;test flags +10fb : cd1e02 cmp fLDx+1 ;test flags trap_ne 10fe : d0fe > bne * ;failed not equal (non zero) @@ -4513,7 +4515,7 @@ ffff = ram_top = -1 1102 : 48 > pha ;use stack to load status 1103 : 28 > plp -1104 : a615 ldx zp1+2 +1104 : a617 ldx zp1+2 1106 : 08 php ;test stores do not alter flags 1107 : 8a txa 1108 : 49c3 eor #$c3 @@ -4531,7 +4533,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1118 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -111a : cd1e02 cmp fLDx+2 ;test flags +111a : cd1f02 cmp fLDx+2 ;test flags trap_ne 111d : d0fe > bne * ;failed not equal (non zero) @@ -4542,7 +4544,7 @@ ffff = ram_top = -1 1121 : 48 > pha ;use stack to load status 1122 : 28 > plp -1123 : a616 ldx zp1+3 +1123 : a618 ldx zp1+3 1125 : 08 php ;test stores do not alter flags 1126 : 8a txa 1127 : 49c3 eor #$c3 @@ -4560,7 +4562,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1137 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1139 : cd1f02 cmp fLDx+3 ;test flags +1139 : cd2002 cmp fLDx+3 ;test flags trap_ne 113c : d0fe > bne * ;failed not equal (non zero) @@ -4572,7 +4574,7 @@ ffff = ram_top = -1 1140 : 48 > pha ;use stack to load status 1141 : 28 > plp -1142 : ae1702 ldx abs1 +1142 : ae1802 ldx abs1 1145 : 08 php ;test stores do not alter flags 1146 : 8a txa 1147 : 49c3 eor #$c3 @@ -4581,7 +4583,7 @@ ffff = ram_top = -1 114b : 860c stx zpt 114d : 08 php ;flags after load/store sequence 114e : 49c3 eor #$c3 -1150 : c513 cmp zp1 ;test result +1150 : c515 cmp zp1 ;test result trap_ne 1152 : d0fe > bne * ;failed not equal (non zero) @@ -4589,7 +4591,7 @@ ffff = ram_top = -1 eor_flag 0 1155 : 4930 > eor #0|fao ;invert expected flags + always on bits -1157 : cd1c02 cmp fLDx ;test flags +1157 : cd1d02 cmp fLDx ;test flags trap_ne 115a : d0fe > bne * ;failed not equal (non zero) @@ -4600,7 +4602,7 @@ ffff = ram_top = -1 115e : 48 > pha ;use stack to load status 115f : 28 > plp -1160 : ae1802 ldx abs1+1 +1160 : ae1902 ldx abs1+1 1163 : 08 php ;test stores do not alter flags 1164 : 8a txa 1165 : 49c3 eor #$c3 @@ -4609,7 +4611,7 @@ ffff = ram_top = -1 1169 : 860d stx zpt+1 116b : 08 php ;flags after load/store sequence 116c : 49c3 eor #$c3 -116e : c514 cmp zp1+1 ;test result +116e : c516 cmp zp1+1 ;test result trap_ne 1170 : d0fe > bne * ;failed not equal (non zero) @@ -4617,7 +4619,7 @@ ffff = ram_top = -1 eor_flag 0 1173 : 4930 > eor #0|fao ;invert expected flags + always on bits -1175 : cd1d02 cmp fLDx+1 ;test flags +1175 : cd1e02 cmp fLDx+1 ;test flags trap_ne 1178 : d0fe > bne * ;failed not equal (non zero) @@ -4628,7 +4630,7 @@ ffff = ram_top = -1 117c : 48 > pha ;use stack to load status 117d : 28 > plp -117e : ae1902 ldx abs1+2 +117e : ae1a02 ldx abs1+2 1181 : 08 php ;test stores do not alter flags 1182 : 8a txa 1183 : 49c3 eor #$c3 @@ -4637,7 +4639,7 @@ ffff = ram_top = -1 1187 : 860e stx zpt+2 1189 : 08 php ;flags after load/store sequence 118a : 49c3 eor #$c3 -118c : c515 cmp zp1+2 ;test result +118c : c517 cmp zp1+2 ;test result trap_ne 118e : d0fe > bne * ;failed not equal (non zero) @@ -4645,7 +4647,7 @@ ffff = ram_top = -1 eor_flag 0 1191 : 4930 > eor #0|fao ;invert expected flags + always on bits -1193 : cd1e02 cmp fLDx+2 ;test flags +1193 : cd1f02 cmp fLDx+2 ;test flags trap_ne 1196 : d0fe > bne * ;failed not equal (non zero) @@ -4656,7 +4658,7 @@ ffff = ram_top = -1 119a : 48 > pha ;use stack to load status 119b : 28 > plp -119c : ae1a02 ldx abs1+3 +119c : ae1b02 ldx abs1+3 119f : 08 php ;test stores do not alter flags 11a0 : 8a txa 11a1 : 49c3 eor #$c3 @@ -4665,7 +4667,7 @@ ffff = ram_top = -1 11a5 : 860f stx zpt+3 11a7 : 08 php ;flags after load/store sequence 11a8 : 49c3 eor #$c3 -11aa : c516 cmp zp1+3 ;test result +11aa : c518 cmp zp1+3 ;test result trap_ne 11ac : d0fe > bne * ;failed not equal (non zero) @@ -4673,7 +4675,7 @@ ffff = ram_top = -1 eor_flag 0 11af : 4930 > eor #0|fao ;invert expected flags + always on bits -11b1 : cd1f02 cmp fLDx+3 ;test flags +11b1 : cd2002 cmp fLDx+3 ;test flags trap_ne 11b4 : d0fe > bne * ;failed not equal (non zero) @@ -4685,7 +4687,7 @@ ffff = ram_top = -1 11b8 : 48 > pha ;use stack to load status 11b9 : 28 > plp -11ba : ae1702 ldx abs1 +11ba : ae1802 ldx abs1 11bd : 08 php ;test stores do not alter flags 11be : 8a txa 11bf : 49c3 eor #$c3 @@ -4695,7 +4697,7 @@ ffff = ram_top = -1 11c5 : 08 php ;flags after load/store sequence 11c6 : 49c3 eor #$c3 11c8 : aa tax -11c9 : e413 cpx zp1 ;test result +11c9 : e415 cpx zp1 ;test result trap_ne 11cb : d0fe > bne * ;failed not equal (non zero) @@ -4703,7 +4705,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 11ce : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -11d0 : cd1c02 cmp fLDx ;test flags +11d0 : cd1d02 cmp fLDx ;test flags trap_ne 11d3 : d0fe > bne * ;failed not equal (non zero) @@ -4714,7 +4716,7 @@ ffff = ram_top = -1 11d7 : 48 > pha ;use stack to load status 11d8 : 28 > plp -11d9 : ae1802 ldx abs1+1 +11d9 : ae1902 ldx abs1+1 11dc : 08 php ;test stores do not alter flags 11dd : 8a txa 11de : 49c3 eor #$c3 @@ -4724,7 +4726,7 @@ ffff = ram_top = -1 11e4 : 08 php ;flags after load/store sequence 11e5 : 49c3 eor #$c3 11e7 : aa tax -11e8 : e414 cpx zp1+1 ;test result +11e8 : e416 cpx zp1+1 ;test result trap_ne 11ea : d0fe > bne * ;failed not equal (non zero) @@ -4732,7 +4734,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 11ed : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -11ef : cd1d02 cmp fLDx+1 ;test flags +11ef : cd1e02 cmp fLDx+1 ;test flags trap_ne 11f2 : d0fe > bne * ;failed not equal (non zero) @@ -4743,7 +4745,7 @@ ffff = ram_top = -1 11f6 : 48 > pha ;use stack to load status 11f7 : 28 > plp -11f8 : ae1902 ldx abs1+2 +11f8 : ae1a02 ldx abs1+2 11fb : 08 php ;test stores do not alter flags 11fc : 8a txa 11fd : 49c3 eor #$c3 @@ -4753,7 +4755,7 @@ ffff = ram_top = -1 1203 : 08 php ;flags after load/store sequence 1204 : 49c3 eor #$c3 1206 : aa tax -1207 : e415 cpx zp1+2 ;test result +1207 : e417 cpx zp1+2 ;test result trap_ne 1209 : d0fe > bne * ;failed not equal (non zero) @@ -4761,7 +4763,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 120c : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -120e : cd1e02 cmp fLDx+2 ;test flags +120e : cd1f02 cmp fLDx+2 ;test flags trap_ne 1211 : d0fe > bne * ;failed not equal (non zero) @@ -4772,7 +4774,7 @@ ffff = ram_top = -1 1215 : 48 > pha ;use stack to load status 1216 : 28 > plp -1217 : ae1a02 ldx abs1+3 +1217 : ae1b02 ldx abs1+3 121a : 08 php ;test stores do not alter flags 121b : 8a txa 121c : 49c3 eor #$c3 @@ -4782,7 +4784,7 @@ ffff = ram_top = -1 1222 : 08 php ;flags after load/store sequence 1223 : 49c3 eor #$c3 1225 : aa tax -1226 : e416 cpx zp1+3 ;test result +1226 : e418 cpx zp1+3 ;test result trap_ne 1228 : d0fe > bne * ;failed not equal (non zero) @@ -4790,7 +4792,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 122b : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -122d : cd1f02 cmp fLDx+3 ;test flags +122d : cd2002 cmp fLDx+3 ;test flags trap_ne 1230 : d0fe > bne * ;failed not equal (non zero) @@ -4804,7 +4806,7 @@ ffff = ram_top = -1 1236 : a2c3 ldx #$c3 1238 : 08 php -1239 : ec1702 cpx abs1 ;test result +1239 : ec1802 cpx abs1 ;test result trap_ne 123c : d0fe > bne * ;failed not equal (non zero) @@ -4812,7 +4814,7 @@ ffff = ram_top = -1 eor_flag 0 123f : 4930 > eor #0|fao ;invert expected flags + always on bits -1241 : cd1c02 cmp fLDx ;test flags +1241 : cd1d02 cmp fLDx ;test flags trap_ne 1244 : d0fe > bne * ;failed not equal (non zero) @@ -4825,7 +4827,7 @@ ffff = ram_top = -1 124a : a282 ldx #$82 124c : 08 php -124d : ec1802 cpx abs1+1 ;test result +124d : ec1902 cpx abs1+1 ;test result trap_ne 1250 : d0fe > bne * ;failed not equal (non zero) @@ -4833,7 +4835,7 @@ ffff = ram_top = -1 eor_flag 0 1253 : 4930 > eor #0|fao ;invert expected flags + always on bits -1255 : cd1d02 cmp fLDx+1 ;test flags +1255 : cd1e02 cmp fLDx+1 ;test flags trap_ne 1258 : d0fe > bne * ;failed not equal (non zero) @@ -4846,7 +4848,7 @@ ffff = ram_top = -1 125e : a241 ldx #$41 1260 : 08 php -1261 : ec1902 cpx abs1+2 ;test result +1261 : ec1a02 cpx abs1+2 ;test result trap_ne 1264 : d0fe > bne * ;failed not equal (non zero) @@ -4854,7 +4856,7 @@ ffff = ram_top = -1 eor_flag 0 1267 : 4930 > eor #0|fao ;invert expected flags + always on bits -1269 : cd1e02 cmp fLDx+2 ;test flags +1269 : cd1f02 cmp fLDx+2 ;test flags trap_ne 126c : d0fe > bne * ;failed not equal (non zero) @@ -4867,7 +4869,7 @@ ffff = ram_top = -1 1272 : a200 ldx #0 1274 : 08 php -1275 : ec1a02 cpx abs1+3 ;test result +1275 : ec1b02 cpx abs1+3 ;test result trap_ne 1278 : d0fe > bne * ;failed not equal (non zero) @@ -4875,7 +4877,7 @@ ffff = ram_top = -1 eor_flag 0 127b : 4930 > eor #0|fao ;invert expected flags + always on bits -127d : cd1f02 cmp fLDx+3 ;test flags +127d : cd2002 cmp fLDx+3 ;test flags trap_ne 1280 : d0fe > bne * ;failed not equal (non zero) @@ -4889,7 +4891,7 @@ ffff = ram_top = -1 1286 : a2c3 ldx #$c3 1288 : 08 php -1289 : ec1702 cpx abs1 ;test result +1289 : ec1802 cpx abs1 ;test result trap_ne 128c : d0fe > bne * ;failed not equal (non zero) @@ -4897,7 +4899,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 128f : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1291 : cd1c02 cmp fLDx ;test flags +1291 : cd1d02 cmp fLDx ;test flags trap_ne 1294 : d0fe > bne * ;failed not equal (non zero) @@ -4910,7 +4912,7 @@ ffff = ram_top = -1 129a : a282 ldx #$82 129c : 08 php -129d : ec1802 cpx abs1+1 ;test result +129d : ec1902 cpx abs1+1 ;test result trap_ne 12a0 : d0fe > bne * ;failed not equal (non zero) @@ -4918,7 +4920,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 12a3 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -12a5 : cd1d02 cmp fLDx+1 ;test flags +12a5 : cd1e02 cmp fLDx+1 ;test flags trap_ne 12a8 : d0fe > bne * ;failed not equal (non zero) @@ -4931,7 +4933,7 @@ ffff = ram_top = -1 12ae : a241 ldx #$41 12b0 : 08 php -12b1 : ec1902 cpx abs1+2 ;test result +12b1 : ec1a02 cpx abs1+2 ;test result trap_ne 12b4 : d0fe > bne * ;failed not equal (non zero) @@ -4939,7 +4941,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 12b7 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -12b9 : cd1e02 cmp fLDx+2 ;test flags +12b9 : cd1f02 cmp fLDx+2 ;test flags trap_ne 12bc : d0fe > bne * ;failed not equal (non zero) @@ -4952,7 +4954,7 @@ ffff = ram_top = -1 12c2 : a200 ldx #0 12c4 : 08 php -12c5 : ec1a02 cpx abs1+3 ;test result +12c5 : ec1b02 cpx abs1+3 ;test result trap_ne 12c8 : d0fe > bne * ;failed not equal (non zero) @@ -4960,7 +4962,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 12cb : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -12cd : cd1f02 cmp fLDx+3 ;test flags +12cd : cd2002 cmp fLDx+3 ;test flags trap_ne 12d0 : d0fe > bne * ;failed not equal (non zero) @@ -4968,56 +4970,56 @@ ffff = ram_top = -1 12d2 : a200 ldx #0 12d4 : a50c lda zpt 12d6 : 49c3 eor #$c3 -12d8 : c513 cmp zp1 +12d8 : c515 cmp zp1 trap_ne ;store to zp data 12da : d0fe > bne * ;failed not equal (non zero) 12dc : 860c stx zpt ;clear 12de : ad0302 lda abst 12e1 : 49c3 eor #$c3 -12e3 : cd1702 cmp abs1 +12e3 : cd1802 cmp abs1 trap_ne ;store to abs data 12e6 : d0fe > bne * ;failed not equal (non zero) 12e8 : 8e0302 stx abst ;clear 12eb : a50d lda zpt+1 12ed : 49c3 eor #$c3 -12ef : c514 cmp zp1+1 +12ef : c516 cmp zp1+1 trap_ne ;store to zp data 12f1 : d0fe > bne * ;failed not equal (non zero) 12f3 : 860d stx zpt+1 ;clear 12f5 : ad0402 lda abst+1 12f8 : 49c3 eor #$c3 -12fa : cd1802 cmp abs1+1 +12fa : cd1902 cmp abs1+1 trap_ne ;store to abs data 12fd : d0fe > bne * ;failed not equal (non zero) 12ff : 8e0402 stx abst+1 ;clear 1302 : a50e lda zpt+2 1304 : 49c3 eor #$c3 -1306 : c515 cmp zp1+2 +1306 : c517 cmp zp1+2 trap_ne ;store to zp data 1308 : d0fe > bne * ;failed not equal (non zero) 130a : 860e stx zpt+2 ;clear 130c : ad0502 lda abst+2 130f : 49c3 eor #$c3 -1311 : cd1902 cmp abs1+2 +1311 : cd1a02 cmp abs1+2 trap_ne ;store to abs data 1314 : d0fe > bne * ;failed not equal (non zero) 1316 : 8e0502 stx abst+2 ;clear 1319 : a50f lda zpt+3 131b : 49c3 eor #$c3 -131d : c516 cmp zp1+3 +131d : c518 cmp zp1+3 trap_ne ;store to zp data 131f : d0fe > bne * ;failed not equal (non zero) 1321 : 860f stx zpt+3 ;clear 1323 : ad0602 lda abst+3 1326 : 49c3 eor #$c3 -1328 : cd1a02 cmp abs1+3 +1328 : cd1b02 cmp abs1+3 trap_ne ;store to abs data 132b : d0fe > bne * ;failed not equal (non zero) @@ -5042,7 +5044,7 @@ ffff = ram_top = -1 133e : 48 > pha ;use stack to load status 133f : 28 > plp -1340 : a413 ldy zp1 +1340 : a415 ldy zp1 1342 : 08 php ;test stores do not alter flags 1343 : 98 tya 1344 : 49c3 eor #$c3 @@ -5060,7 +5062,7 @@ ffff = ram_top = -1 eor_flag 0 1354 : 4930 > eor #0|fao ;invert expected flags + always on bits -1356 : cd1c02 cmp fLDx ;test flags +1356 : cd1d02 cmp fLDx ;test flags trap_ne 1359 : d0fe > bne * ;failed not equal (non zero) @@ -5071,7 +5073,7 @@ ffff = ram_top = -1 135d : 48 > pha ;use stack to load status 135e : 28 > plp -135f : a414 ldy zp1+1 +135f : a416 ldy zp1+1 1361 : 08 php ;test stores do not alter flags 1362 : 98 tya 1363 : 49c3 eor #$c3 @@ -5089,7 +5091,7 @@ ffff = ram_top = -1 eor_flag 0 1373 : 4930 > eor #0|fao ;invert expected flags + always on bits -1375 : cd1d02 cmp fLDx+1 ;test flags +1375 : cd1e02 cmp fLDx+1 ;test flags trap_ne 1378 : d0fe > bne * ;failed not equal (non zero) @@ -5100,7 +5102,7 @@ ffff = ram_top = -1 137c : 48 > pha ;use stack to load status 137d : 28 > plp -137e : a415 ldy zp1+2 +137e : a417 ldy zp1+2 1380 : 08 php ;test stores do not alter flags 1381 : 98 tya 1382 : 49c3 eor #$c3 @@ -5118,7 +5120,7 @@ ffff = ram_top = -1 eor_flag 0 1392 : 4930 > eor #0|fao ;invert expected flags + always on bits -1394 : cd1e02 cmp fLDx+2 ;test flags +1394 : cd1f02 cmp fLDx+2 ;test flags trap_ne 1397 : d0fe > bne * ;failed not equal (non zero) @@ -5129,7 +5131,7 @@ ffff = ram_top = -1 139b : 48 > pha ;use stack to load status 139c : 28 > plp -139d : a416 ldy zp1+3 +139d : a418 ldy zp1+3 139f : 08 php ;test stores do not alter flags 13a0 : 98 tya 13a1 : 49c3 eor #$c3 @@ -5147,7 +5149,7 @@ ffff = ram_top = -1 eor_flag 0 13b1 : 4930 > eor #0|fao ;invert expected flags + always on bits -13b3 : cd1f02 cmp fLDx+3 ;test flags +13b3 : cd2002 cmp fLDx+3 ;test flags trap_ne 13b6 : d0fe > bne * ;failed not equal (non zero) @@ -5159,7 +5161,7 @@ ffff = ram_top = -1 13ba : 48 > pha ;use stack to load status 13bb : 28 > plp -13bc : a413 ldy zp1 +13bc : a415 ldy zp1 13be : 08 php ;test stores do not alter flags 13bf : 98 tya 13c0 : 49c3 eor #$c3 @@ -5177,7 +5179,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 13d0 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -13d2 : cd1c02 cmp fLDx ;test flags +13d2 : cd1d02 cmp fLDx ;test flags trap_ne 13d5 : d0fe > bne * ;failed not equal (non zero) @@ -5188,7 +5190,7 @@ ffff = ram_top = -1 13d9 : 48 > pha ;use stack to load status 13da : 28 > plp -13db : a414 ldy zp1+1 +13db : a416 ldy zp1+1 13dd : 08 php ;test stores do not alter flags 13de : 98 tya 13df : 49c3 eor #$c3 @@ -5206,7 +5208,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 13ef : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -13f1 : cd1d02 cmp fLDx+1 ;test flags +13f1 : cd1e02 cmp fLDx+1 ;test flags trap_ne 13f4 : d0fe > bne * ;failed not equal (non zero) @@ -5217,7 +5219,7 @@ ffff = ram_top = -1 13f8 : 48 > pha ;use stack to load status 13f9 : 28 > plp -13fa : a415 ldy zp1+2 +13fa : a417 ldy zp1+2 13fc : 08 php ;test stores do not alter flags 13fd : 98 tya 13fe : 49c3 eor #$c3 @@ -5235,7 +5237,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 140e : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1410 : cd1e02 cmp fLDx+2 ;test flags +1410 : cd1f02 cmp fLDx+2 ;test flags trap_ne 1413 : d0fe > bne * ;failed not equal (non zero) @@ -5246,7 +5248,7 @@ ffff = ram_top = -1 1417 : 48 > pha ;use stack to load status 1418 : 28 > plp -1419 : a416 ldy zp1+3 +1419 : a418 ldy zp1+3 141b : 08 php ;test stores do not alter flags 141c : 98 tya 141d : 49c3 eor #$c3 @@ -5264,7 +5266,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 142d : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -142f : cd1f02 cmp fLDx+3 ;test flags +142f : cd2002 cmp fLDx+3 ;test flags trap_ne 1432 : d0fe > bne * ;failed not equal (non zero) @@ -5276,7 +5278,7 @@ ffff = ram_top = -1 1436 : 48 > pha ;use stack to load status 1437 : 28 > plp -1438 : ac1702 ldy abs1 +1438 : ac1802 ldy abs1 143b : 08 php ;test stores do not alter flags 143c : 98 tya 143d : 49c3 eor #$c3 @@ -5286,7 +5288,7 @@ ffff = ram_top = -1 1443 : 08 php ;flags after load/store sequence 1444 : 49c3 eor #$c3 1446 : a8 tay -1447 : c413 cpy zp1 ;test result +1447 : c415 cpy zp1 ;test result trap_ne 1449 : d0fe > bne * ;failed not equal (non zero) @@ -5294,7 +5296,7 @@ ffff = ram_top = -1 eor_flag 0 144c : 4930 > eor #0|fao ;invert expected flags + always on bits -144e : cd1c02 cmp fLDx ;test flags +144e : cd1d02 cmp fLDx ;test flags trap_ne 1451 : d0fe > bne * ;failed not equal (non zero) @@ -5305,7 +5307,7 @@ ffff = ram_top = -1 1455 : 48 > pha ;use stack to load status 1456 : 28 > plp -1457 : ac1802 ldy abs1+1 +1457 : ac1902 ldy abs1+1 145a : 08 php ;test stores do not alter flags 145b : 98 tya 145c : 49c3 eor #$c3 @@ -5315,7 +5317,7 @@ ffff = ram_top = -1 1462 : 08 php ;flags after load/store sequence 1463 : 49c3 eor #$c3 1465 : a8 tay -1466 : c414 cpy zp1+1 ;test result +1466 : c416 cpy zp1+1 ;test result trap_ne 1468 : d0fe > bne * ;failed not equal (non zero) @@ -5323,7 +5325,7 @@ ffff = ram_top = -1 eor_flag 0 146b : 4930 > eor #0|fao ;invert expected flags + always on bits -146d : cd1d02 cmp fLDx+1 ;test flags +146d : cd1e02 cmp fLDx+1 ;test flags trap_ne 1470 : d0fe > bne * ;failed not equal (non zero) @@ -5334,7 +5336,7 @@ ffff = ram_top = -1 1474 : 48 > pha ;use stack to load status 1475 : 28 > plp -1476 : ac1902 ldy abs1+2 +1476 : ac1a02 ldy abs1+2 1479 : 08 php ;test stores do not alter flags 147a : 98 tya 147b : 49c3 eor #$c3 @@ -5344,7 +5346,7 @@ ffff = ram_top = -1 1481 : 08 php ;flags after load/store sequence 1482 : 49c3 eor #$c3 1484 : a8 tay -1485 : c415 cpy zp1+2 ;test result +1485 : c417 cpy zp1+2 ;test result trap_ne 1487 : d0fe > bne * ;failed not equal (non zero) @@ -5352,7 +5354,7 @@ ffff = ram_top = -1 eor_flag 0 148a : 4930 > eor #0|fao ;invert expected flags + always on bits -148c : cd1e02 cmp fLDx+2 ;test flags +148c : cd1f02 cmp fLDx+2 ;test flags trap_ne 148f : d0fe > bne * ;failed not equal (non zero) @@ -5363,7 +5365,7 @@ ffff = ram_top = -1 1493 : 48 > pha ;use stack to load status 1494 : 28 > plp -1495 : ac1a02 ldy abs1+3 +1495 : ac1b02 ldy abs1+3 1498 : 08 php ;test stores do not alter flags 1499 : 98 tya 149a : 49c3 eor #$c3 @@ -5373,7 +5375,7 @@ ffff = ram_top = -1 14a0 : 08 php ;flags after load/store sequence 14a1 : 49c3 eor #$c3 14a3 : a8 tay -14a4 : c416 cpy zp1+3 ;test result +14a4 : c418 cpy zp1+3 ;test result trap_ne 14a6 : d0fe > bne * ;failed not equal (non zero) @@ -5381,7 +5383,7 @@ ffff = ram_top = -1 eor_flag 0 14a9 : 4930 > eor #0|fao ;invert expected flags + always on bits -14ab : cd1f02 cmp fLDx+3 ;test flags +14ab : cd2002 cmp fLDx+3 ;test flags trap_ne 14ae : d0fe > bne * ;failed not equal (non zero) @@ -5393,7 +5395,7 @@ ffff = ram_top = -1 14b2 : 48 > pha ;use stack to load status 14b3 : 28 > plp -14b4 : ac1702 ldy abs1 +14b4 : ac1802 ldy abs1 14b7 : 08 php ;test stores do not alter flags 14b8 : 98 tya 14b9 : 49c3 eor #$c3 @@ -5403,7 +5405,7 @@ ffff = ram_top = -1 14bf : 08 php ;flags after load/store sequence 14c0 : 49c3 eor #$c3 14c2 : a8 tay -14c3 : c513 cmp zp1 ;test result +14c3 : c515 cmp zp1 ;test result trap_ne 14c5 : d0fe > bne * ;failed not equal (non zero) @@ -5411,7 +5413,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 14c8 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -14ca : cd1c02 cmp fLDx ;test flags +14ca : cd1d02 cmp fLDx ;test flags trap_ne 14cd : d0fe > bne * ;failed not equal (non zero) @@ -5422,7 +5424,7 @@ ffff = ram_top = -1 14d1 : 48 > pha ;use stack to load status 14d2 : 28 > plp -14d3 : ac1802 ldy abs1+1 +14d3 : ac1902 ldy abs1+1 14d6 : 08 php ;test stores do not alter flags 14d7 : 98 tya 14d8 : 49c3 eor #$c3 @@ -5432,7 +5434,7 @@ ffff = ram_top = -1 14de : 08 php ;flags after load/store sequence 14df : 49c3 eor #$c3 14e1 : a8 tay -14e2 : c514 cmp zp1+1 ;test result +14e2 : c516 cmp zp1+1 ;test result trap_ne 14e4 : d0fe > bne * ;failed not equal (non zero) @@ -5440,7 +5442,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 14e7 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -14e9 : cd1d02 cmp fLDx+1 ;test flags +14e9 : cd1e02 cmp fLDx+1 ;test flags trap_ne 14ec : d0fe > bne * ;failed not equal (non zero) @@ -5451,7 +5453,7 @@ ffff = ram_top = -1 14f0 : 48 > pha ;use stack to load status 14f1 : 28 > plp -14f2 : ac1902 ldy abs1+2 +14f2 : ac1a02 ldy abs1+2 14f5 : 08 php ;test stores do not alter flags 14f6 : 98 tya 14f7 : 49c3 eor #$c3 @@ -5461,7 +5463,7 @@ ffff = ram_top = -1 14fd : 08 php ;flags after load/store sequence 14fe : 49c3 eor #$c3 1500 : a8 tay -1501 : c515 cmp zp1+2 ;test result +1501 : c517 cmp zp1+2 ;test result trap_ne 1503 : d0fe > bne * ;failed not equal (non zero) @@ -5469,7 +5471,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1506 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1508 : cd1e02 cmp fLDx+2 ;test flags +1508 : cd1f02 cmp fLDx+2 ;test flags trap_ne 150b : d0fe > bne * ;failed not equal (non zero) @@ -5480,7 +5482,7 @@ ffff = ram_top = -1 150f : 48 > pha ;use stack to load status 1510 : 28 > plp -1511 : ac1a02 ldy abs1+3 +1511 : ac1b02 ldy abs1+3 1514 : 08 php ;test stores do not alter flags 1515 : 98 tya 1516 : 49c3 eor #$c3 @@ -5490,7 +5492,7 @@ ffff = ram_top = -1 151c : 08 php ;flags after load/store sequence 151d : 49c3 eor #$c3 151f : a8 tay -1520 : c516 cmp zp1+3 ;test result +1520 : c518 cmp zp1+3 ;test result trap_ne 1522 : d0fe > bne * ;failed not equal (non zero) @@ -5498,7 +5500,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1525 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1527 : cd1f02 cmp fLDx+3 ;test flags +1527 : cd2002 cmp fLDx+3 ;test flags trap_ne 152a : d0fe > bne * ;failed not equal (non zero) @@ -5513,7 +5515,7 @@ ffff = ram_top = -1 1530 : a0c3 ldy #$c3 1532 : 08 php -1533 : cc1702 cpy abs1 ;test result +1533 : cc1802 cpy abs1 ;test result trap_ne 1536 : d0fe > bne * ;failed not equal (non zero) @@ -5521,7 +5523,7 @@ ffff = ram_top = -1 eor_flag 0 1539 : 4930 > eor #0|fao ;invert expected flags + always on bits -153b : cd1c02 cmp fLDx ;test flags +153b : cd1d02 cmp fLDx ;test flags trap_ne 153e : d0fe > bne * ;failed not equal (non zero) @@ -5534,7 +5536,7 @@ ffff = ram_top = -1 1544 : a082 ldy #$82 1546 : 08 php -1547 : cc1802 cpy abs1+1 ;test result +1547 : cc1902 cpy abs1+1 ;test result trap_ne 154a : d0fe > bne * ;failed not equal (non zero) @@ -5542,7 +5544,7 @@ ffff = ram_top = -1 eor_flag 0 154d : 4930 > eor #0|fao ;invert expected flags + always on bits -154f : cd1d02 cmp fLDx+1 ;test flags +154f : cd1e02 cmp fLDx+1 ;test flags trap_ne 1552 : d0fe > bne * ;failed not equal (non zero) @@ -5555,7 +5557,7 @@ ffff = ram_top = -1 1558 : a041 ldy #$41 155a : 08 php -155b : cc1902 cpy abs1+2 ;test result +155b : cc1a02 cpy abs1+2 ;test result trap_ne 155e : d0fe > bne * ;failed not equal (non zero) @@ -5563,7 +5565,7 @@ ffff = ram_top = -1 eor_flag 0 1561 : 4930 > eor #0|fao ;invert expected flags + always on bits -1563 : cd1e02 cmp fLDx+2 ;test flags +1563 : cd1f02 cmp fLDx+2 ;test flags trap_ne 1566 : d0fe > bne * ;failed not equal (non zero) @@ -5576,7 +5578,7 @@ ffff = ram_top = -1 156c : a000 ldy #0 156e : 08 php -156f : cc1a02 cpy abs1+3 ;test result +156f : cc1b02 cpy abs1+3 ;test result trap_ne 1572 : d0fe > bne * ;failed not equal (non zero) @@ -5584,7 +5586,7 @@ ffff = ram_top = -1 eor_flag 0 1575 : 4930 > eor #0|fao ;invert expected flags + always on bits -1577 : cd1f02 cmp fLDx+3 ;test flags +1577 : cd2002 cmp fLDx+3 ;test flags trap_ne 157a : d0fe > bne * ;failed not equal (non zero) @@ -5598,7 +5600,7 @@ ffff = ram_top = -1 1580 : a0c3 ldy #$c3 1582 : 08 php -1583 : cc1702 cpy abs1 ;test result +1583 : cc1802 cpy abs1 ;test result trap_ne 1586 : d0fe > bne * ;failed not equal (non zero) @@ -5606,7 +5608,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1589 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -158b : cd1c02 cmp fLDx ;test flags +158b : cd1d02 cmp fLDx ;test flags trap_ne 158e : d0fe > bne * ;failed not equal (non zero) @@ -5619,7 +5621,7 @@ ffff = ram_top = -1 1594 : a082 ldy #$82 1596 : 08 php -1597 : cc1802 cpy abs1+1 ;test result +1597 : cc1902 cpy abs1+1 ;test result trap_ne 159a : d0fe > bne * ;failed not equal (non zero) @@ -5627,7 +5629,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 159d : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -159f : cd1d02 cmp fLDx+1 ;test flags +159f : cd1e02 cmp fLDx+1 ;test flags trap_ne 15a2 : d0fe > bne * ;failed not equal (non zero) @@ -5640,7 +5642,7 @@ ffff = ram_top = -1 15a8 : a041 ldy #$41 15aa : 08 php -15ab : cc1902 cpy abs1+2 ;test result +15ab : cc1a02 cpy abs1+2 ;test result trap_ne 15ae : d0fe > bne * ;failed not equal (non zero) @@ -5648,7 +5650,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 15b1 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -15b3 : cd1e02 cmp fLDx+2 ;test flags +15b3 : cd1f02 cmp fLDx+2 ;test flags trap_ne 15b6 : d0fe > bne * ;failed not equal (non zero) @@ -5661,7 +5663,7 @@ ffff = ram_top = -1 15bc : a000 ldy #0 15be : 08 php -15bf : cc1a02 cpy abs1+3 ;test result +15bf : cc1b02 cpy abs1+3 ;test result trap_ne 15c2 : d0fe > bne * ;failed not equal (non zero) @@ -5669,7 +5671,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 15c5 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -15c7 : cd1f02 cmp fLDx+3 ;test flags +15c7 : cd2002 cmp fLDx+3 ;test flags trap_ne 15ca : d0fe > bne * ;failed not equal (non zero) @@ -5677,56 +5679,56 @@ ffff = ram_top = -1 15cc : a000 ldy #0 15ce : a50c lda zpt 15d0 : 49c3 eor #$c3 -15d2 : c513 cmp zp1 +15d2 : c515 cmp zp1 trap_ne ;store to zp data 15d4 : d0fe > bne * ;failed not equal (non zero) 15d6 : 840c sty zpt ;clear 15d8 : ad0302 lda abst 15db : 49c3 eor #$c3 -15dd : cd1702 cmp abs1 +15dd : cd1802 cmp abs1 trap_ne ;store to abs data 15e0 : d0fe > bne * ;failed not equal (non zero) 15e2 : 8c0302 sty abst ;clear 15e5 : a50d lda zpt+1 15e7 : 49c3 eor #$c3 -15e9 : c514 cmp zp1+1 +15e9 : c516 cmp zp1+1 trap_ne ;store to zp+1 data 15eb : d0fe > bne * ;failed not equal (non zero) 15ed : 840d sty zpt+1 ;clear 15ef : ad0402 lda abst+1 15f2 : 49c3 eor #$c3 -15f4 : cd1802 cmp abs1+1 +15f4 : cd1902 cmp abs1+1 trap_ne ;store to abs+1 data 15f7 : d0fe > bne * ;failed not equal (non zero) 15f9 : 8c0402 sty abst+1 ;clear 15fc : a50e lda zpt+2 15fe : 49c3 eor #$c3 -1600 : c515 cmp zp1+2 +1600 : c517 cmp zp1+2 trap_ne ;store to zp+2 data 1602 : d0fe > bne * ;failed not equal (non zero) 1604 : 840e sty zpt+2 ;clear 1606 : ad0502 lda abst+2 1609 : 49c3 eor #$c3 -160b : cd1902 cmp abs1+2 +160b : cd1a02 cmp abs1+2 trap_ne ;store to abs+2 data 160e : d0fe > bne * ;failed not equal (non zero) 1610 : 8c0502 sty abst+2 ;clear 1613 : a50f lda zpt+3 1615 : 49c3 eor #$c3 -1617 : c516 cmp zp1+3 +1617 : c518 cmp zp1+3 trap_ne ;store to zp+3 data 1619 : d0fe > bne * ;failed not equal (non zero) 161b : 840f sty zpt+3 ;clear 161d : ad0602 lda abst+3 1620 : 49c3 eor #$c3 -1622 : cd1a02 cmp abs1+3 +1622 : cd1b02 cmp abs1+3 trap_ne ;store to abs+3 data 1625 : d0fe > bne * ;failed not equal (non zero) @@ -5754,14 +5756,14 @@ ffff = ram_top = -1 163a : 48 > pha ;use stack to load status 163b : 28 > plp -163c : b513 lda zp1,x +163c : b515 lda zp1,x 163e : 08 php ;test stores do not alter flags 163f : 49c3 eor #$c3 1641 : 28 plp 1642 : 9d0302 sta abst,x 1645 : 08 php ;flags after load/store sequence 1646 : 49c3 eor #$c3 -1648 : dd1702 cmp abs1,x ;test result +1648 : dd1802 cmp abs1,x ;test result trap_ne 164b : d0fe > bne * ;failed not equal (non zero) @@ -5769,7 +5771,7 @@ ffff = ram_top = -1 eor_flag 0 164e : 4930 > eor #0|fao ;invert expected flags + always on bits -1650 : dd1c02 cmp fLDx,x ;test flags +1650 : dd1d02 cmp fLDx,x ;test flags trap_ne 1653 : d0fe > bne * ;failed not equal (non zero) @@ -5785,14 +5787,14 @@ ffff = ram_top = -1 165c : 48 > pha ;use stack to load status 165d : 28 > plp -165e : b513 lda zp1,x +165e : b515 lda zp1,x 1660 : 08 php ;test stores do not alter flags 1661 : 49c3 eor #$c3 1663 : 28 plp 1664 : 9d0302 sta abst,x 1667 : 08 php ;flags after load/store sequence 1668 : 49c3 eor #$c3 -166a : dd1702 cmp abs1,x ;test result +166a : dd1802 cmp abs1,x ;test result trap_ne 166d : d0fe > bne * ;failed not equal (non zero) @@ -5800,7 +5802,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1670 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1672 : dd1c02 cmp fLDx,x ;test flags +1672 : dd1d02 cmp fLDx,x ;test flags trap_ne 1675 : d0fe > bne * ;failed not equal (non zero) @@ -5816,14 +5818,14 @@ ffff = ram_top = -1 167e : 48 > pha ;use stack to load status 167f : 28 > plp -1680 : bd1702 lda abs1,x +1680 : bd1802 lda abs1,x 1683 : 08 php ;test stores do not alter flags 1684 : 49c3 eor #$c3 1686 : 28 plp 1687 : 950c sta zpt,x 1689 : 08 php ;flags after load/store sequence 168a : 49c3 eor #$c3 -168c : d513 cmp zp1,x ;test result +168c : d515 cmp zp1,x ;test result trap_ne 168e : d0fe > bne * ;failed not equal (non zero) @@ -5831,7 +5833,7 @@ ffff = ram_top = -1 eor_flag 0 1691 : 4930 > eor #0|fao ;invert expected flags + always on bits -1693 : dd1c02 cmp fLDx,x ;test flags +1693 : dd1d02 cmp fLDx,x ;test flags trap_ne 1696 : d0fe > bne * ;failed not equal (non zero) @@ -5847,14 +5849,14 @@ ffff = ram_top = -1 169f : 48 > pha ;use stack to load status 16a0 : 28 > plp -16a1 : bd1702 lda abs1,x +16a1 : bd1802 lda abs1,x 16a4 : 08 php ;test stores do not alter flags 16a5 : 49c3 eor #$c3 16a7 : 28 plp 16a8 : 950c sta zpt,x 16aa : 08 php ;flags after load/store sequence 16ab : 49c3 eor #$c3 -16ad : d513 cmp zp1,x ;test result +16ad : d515 cmp zp1,x ;test result trap_ne 16af : d0fe > bne * ;failed not equal (non zero) @@ -5862,7 +5864,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 16b2 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -16b4 : dd1c02 cmp fLDx,x ;test flags +16b4 : dd1d02 cmp fLDx,x ;test flags trap_ne 16b7 : d0fe > bne * ;failed not equal (non zero) @@ -5873,14 +5875,14 @@ ffff = ram_top = -1 16be : a000 ldy #0 16c0 : b50c tstax lda zpt,x 16c2 : 49c3 eor #$c3 -16c4 : d513 cmp zp1,x +16c4 : d515 cmp zp1,x trap_ne ;store to zp,x data 16c6 : d0fe > bne * ;failed not equal (non zero) 16c8 : 940c sty zpt,x ;clear 16ca : bd0302 lda abst,x 16cd : 49c3 eor #$c3 -16cf : dd1702 cmp abs1,x +16cf : dd1802 cmp abs1,x trap_ne ;store to abs,x data 16d2 : d0fe > bne * ;failed not equal (non zero) @@ -5910,14 +5912,14 @@ ffff = ram_top = -1 16eb : 48 > pha ;use stack to load status 16ec : 28 > plp -16ed : b124 lda (ind1),y +16ed : b126 lda (ind1),y 16ef : 08 php ;test stores do not alter flags 16f0 : 49c3 eor #$c3 16f2 : 28 plp 16f3 : 990302 sta abst,y 16f6 : 08 php ;flags after load/store sequence 16f7 : 49c3 eor #$c3 -16f9 : d91702 cmp abs1,y ;test result +16f9 : d91802 cmp abs1,y ;test result trap_ne 16fc : d0fe > bne * ;failed not equal (non zero) @@ -5925,7 +5927,7 @@ ffff = ram_top = -1 eor_flag 0 16ff : 4930 > eor #0|fao ;invert expected flags + always on bits -1701 : d91c02 cmp fLDx,y ;test flags +1701 : d91d02 cmp fLDx,y ;test flags trap_ne 1704 : d0fe > bne * ;failed not equal (non zero) @@ -5941,14 +5943,14 @@ ffff = ram_top = -1 170d : 48 > pha ;use stack to load status 170e : 28 > plp -170f : b124 lda (ind1),y +170f : b126 lda (ind1),y 1711 : 08 php ;test stores do not alter flags 1712 : 49c3 eor #$c3 1714 : 28 plp 1715 : 990302 sta abst,y 1718 : 08 php ;flags after load/store sequence 1719 : 49c3 eor #$c3 -171b : d91702 cmp abs1,y ;test result +171b : d91802 cmp abs1,y ;test result trap_ne 171e : d0fe > bne * ;failed not equal (non zero) @@ -5956,7 +5958,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1721 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1723 : d91c02 cmp fLDx,y ;test flags +1723 : d91d02 cmp fLDx,y ;test flags trap_ne 1726 : d0fe > bne * ;failed not equal (non zero) @@ -5967,7 +5969,7 @@ ffff = ram_top = -1 172d : a200 ldx #0 172f : b90302 tstay lda abst,y 1732 : 49c3 eor #$c3 -1734 : d91702 cmp abs1,y +1734 : d91802 cmp abs1,y trap_ne ;store to abs data 1737 : d0fe > bne * ;failed not equal (non zero) @@ -5985,14 +5987,14 @@ ffff = ram_top = -1 1744 : 48 > pha ;use stack to load status 1745 : 28 > plp -1746 : b91702 lda abs1,y +1746 : b91802 lda abs1,y 1749 : 08 php ;test stores do not alter flags 174a : 49c3 eor #$c3 174c : 28 plp -174d : 9130 sta (indt),y +174d : 9132 sta (indt),y 174f : 08 php ;flags after load/store sequence 1750 : 49c3 eor #$c3 -1752 : d124 cmp (ind1),y ;test result +1752 : d126 cmp (ind1),y ;test result trap_ne 1754 : d0fe > bne * ;failed not equal (non zero) @@ -6000,7 +6002,7 @@ ffff = ram_top = -1 eor_flag 0 1757 : 4930 > eor #0|fao ;invert expected flags + always on bits -1759 : d91c02 cmp fLDx,y ;test flags +1759 : d91d02 cmp fLDx,y ;test flags trap_ne 175c : d0fe > bne * ;failed not equal (non zero) @@ -6016,14 +6018,14 @@ ffff = ram_top = -1 1765 : 48 > pha ;use stack to load status 1766 : 28 > plp -1767 : b91702 lda abs1,y +1767 : b91802 lda abs1,y 176a : 08 php ;test stores do not alter flags 176b : 49c3 eor #$c3 176d : 28 plp -176e : 9130 sta (indt),y +176e : 9132 sta (indt),y 1770 : 08 php ;flags after load/store sequence 1771 : 49c3 eor #$c3 -1773 : d124 cmp (ind1),y ;test result +1773 : d126 cmp (ind1),y ;test result trap_ne 1775 : d0fe > bne * ;failed not equal (non zero) @@ -6031,7 +6033,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1778 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -177a : d91c02 cmp fLDx,y ;test flags +177a : d91d02 cmp fLDx,y ;test flags trap_ne 177d : d0fe > bne * ;failed not equal (non zero) @@ -6042,7 +6044,7 @@ ffff = ram_top = -1 1784 : a200 ldx #0 1786 : b90302 tstay1 lda abst,y 1789 : 49c3 eor #$c3 -178b : d91702 cmp abs1,y +178b : d91802 cmp abs1,y trap_ne ;store to abs data 178e : d0fe > bne * ;failed not equal (non zero) @@ -6061,14 +6063,14 @@ ffff = ram_top = -1 179d : 48 > pha ;use stack to load status 179e : 28 > plp -179f : a124 lda (ind1,x) +179f : a126 lda (ind1,x) 17a1 : 08 php ;test stores do not alter flags 17a2 : 49c3 eor #$c3 17a4 : 28 plp -17a5 : 8130 sta (indt,x) +17a5 : 8132 sta (indt,x) 17a7 : 08 php ;flags after load/store sequence 17a8 : 49c3 eor #$c3 -17aa : d91702 cmp abs1,y ;test result +17aa : d91802 cmp abs1,y ;test result trap_ne 17ad : d0fe > bne * ;failed not equal (non zero) @@ -6076,7 +6078,7 @@ ffff = ram_top = -1 eor_flag 0 17b0 : 4930 > eor #0|fao ;invert expected flags + always on bits -17b2 : d91c02 cmp fLDx,y ;test flags +17b2 : d91d02 cmp fLDx,y ;test flags trap_ne 17b5 : d0fe > bne * ;failed not equal (non zero) @@ -6095,14 +6097,14 @@ ffff = ram_top = -1 17c2 : 48 > pha ;use stack to load status 17c3 : 28 > plp -17c4 : a124 lda (ind1,x) +17c4 : a126 lda (ind1,x) 17c6 : 08 php ;test stores do not alter flags 17c7 : 49c3 eor #$c3 17c9 : 28 plp -17ca : 8130 sta (indt,x) +17ca : 8132 sta (indt,x) 17cc : 08 php ;flags after load/store sequence 17cd : 49c3 eor #$c3 -17cf : d91702 cmp abs1,y ;test result +17cf : d91802 cmp abs1,y ;test result trap_ne 17d2 : d0fe > bne * ;failed not equal (non zero) @@ -6110,7 +6112,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 17d5 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -17d7 : d91c02 cmp fLDx,y ;test flags +17d7 : d91d02 cmp fLDx,y ;test flags trap_ne 17da : d0fe > bne * ;failed not equal (non zero) @@ -6123,7 +6125,7 @@ ffff = ram_top = -1 17e3 : a200 ldx #0 17e5 : b90302 tstay2 lda abst,y 17e8 : 49c3 eor #$c3 -17ea : d91702 cmp abs1,y +17ea : d91802 cmp abs1,y trap_ne ;store to abs data 17ed : d0fe > bne * ;failed not equal (non zero) @@ -6145,13 +6147,13 @@ ffff = ram_top = -1 ; indexed wraparound test (only zp should wrap) 1802 : a2fd ldx #3+$fa -1804 : b519 tldax6 lda zp1-$fa&$ff,x ;wrap on indexed zp +1804 : b51b tldax6 lda zp1-$fa&$ff,x ;wrap on indexed zp 1806 : 9d0901 sta abst-$fa,x ;no STX abs,x! 1809 : ca dex 180a : e0fa cpx #$fa 180c : b0f6 bcs tldax6 180e : a2fd ldx #3+$fa -1810 : bd1d01 tldax7 lda abs1-$fa,x ;no wrap on indexed abs +1810 : bd1e01 tldax7 lda abs1-$fa,x ;no wrap on indexed abs 1813 : 9512 sta zpt-$fa&$ff,x 1815 : ca dex 1816 : e0fa cpx #$fa @@ -6160,13 +6162,13 @@ ffff = ram_top = -1 181a : a203 ldx #3 ;testing wraparound result 181c : a000 ldy #0 181e : b50c tstax1 lda zpt,x -1820 : d513 cmp zp1,x +1820 : d515 cmp zp1,x trap_ne ;store to zp,x data 1822 : d0fe > bne * ;failed not equal (non zero) 1824 : 940c sty zpt,x ;clear 1826 : bd0302 lda abst,x -1829 : dd1702 cmp abs1,x +1829 : dd1802 cmp abs1,x trap_ne ;store to abs,x data 182c : d0fe > bne * ;failed not equal (non zero) @@ -6177,7 +6179,7 @@ ffff = ram_top = -1 1835 : a0fb ldy #3+$f8 1837 : a2fe ldx #6+$f8 -1839 : a12c tlday4 lda (ind1-$f8&$ff,x) ;wrap on indexed zp indirect +1839 : a12e tlday4 lda (ind1-$f8&$ff,x) ;wrap on indexed zp indirect 183b : 990b01 sta abst-$f8,y 183e : ca dex 183f : ca dex @@ -6187,7 +6189,7 @@ ffff = ram_top = -1 1845 : a003 ldy #3 ;testing wraparound result 1847 : a200 ldx #0 1849 : b90302 tstay4 lda abst,y -184c : d91702 cmp abs1,y +184c : d91802 cmp abs1,y trap_ne ;store to abs data 184f : d0fe > bne * ;failed not equal (non zero) @@ -6197,15 +6199,15 @@ ffff = ram_top = -1 1856 : 10f1 bpl tstay4 1858 : a0fb ldy #3+$f8 -185a : b91f01 tlday5 lda abs1-$f8,y ;no wrap on indexed abs -185d : 9138 sta (inwt),y +185a : b92001 tlday5 lda abs1-$f8,y ;no wrap on indexed abs +185d : 913a sta (inwt),y 185f : 88 dey 1860 : c0f8 cpy #$f8 1862 : b0f6 bcs tlday5 1864 : a003 ldy #3 ;testing wraparound result 1866 : a200 ldx #0 1868 : b90302 tstay5 lda abst,y -186b : d91702 cmp abs1,y +186b : d91802 cmp abs1,y trap_ne ;store to abs data 186e : d0fe > bne * ;failed not equal (non zero) @@ -6216,8 +6218,8 @@ ffff = ram_top = -1 1877 : a0fb ldy #3+$f8 1879 : a2fe ldx #6+$f8 -187b : b12e tlday6 lda (inw1),y ;no wrap on zp indirect indexed -187d : 8138 sta (indt-$f8&$ff,x) +187b : b130 tlday6 lda (inw1),y ;no wrap on zp indirect indexed +187d : 813a sta (indt-$f8&$ff,x) 187f : ca dex 1880 : ca dex 1881 : 88 dey @@ -6226,7 +6228,7 @@ ffff = ram_top = -1 1886 : a003 ldy #3 ;testing wraparound result 1888 : a200 ldx #0 188a : b90302 tstay6 lda abst,y -188d : d91702 cmp abs1,y +188d : d91802 cmp abs1,y trap_ne ;store to abs data 1890 : d0fe > bne * ;failed not equal (non zero) @@ -6254,7 +6256,7 @@ ffff = ram_top = -1 18a7 : 48 > pha ;use stack to load status 18a8 : 28 > plp -18a9 : a513 lda zp1 +18a9 : a515 lda zp1 18ab : 08 php ;test stores do not alter flags 18ac : 49c3 eor #$c3 18ae : 28 plp @@ -6269,7 +6271,7 @@ ffff = ram_top = -1 eor_flag 0 18ba : 4930 > eor #0|fao ;invert expected flags + always on bits -18bc : cd1c02 cmp fLDx ;test flags +18bc : cd1d02 cmp fLDx ;test flags trap_ne 18bf : d0fe > bne * ;failed not equal (non zero) @@ -6280,7 +6282,7 @@ ffff = ram_top = -1 18c3 : 48 > pha ;use stack to load status 18c4 : 28 > plp -18c5 : a514 lda zp1+1 +18c5 : a516 lda zp1+1 18c7 : 08 php ;test stores do not alter flags 18c8 : 49c3 eor #$c3 18ca : 28 plp @@ -6295,7 +6297,7 @@ ffff = ram_top = -1 eor_flag 0 18d6 : 4930 > eor #0|fao ;invert expected flags + always on bits -18d8 : cd1d02 cmp fLDx+1 ;test flags +18d8 : cd1e02 cmp fLDx+1 ;test flags trap_ne 18db : d0fe > bne * ;failed not equal (non zero) @@ -6306,7 +6308,7 @@ ffff = ram_top = -1 18df : 48 > pha ;use stack to load status 18e0 : 28 > plp -18e1 : a515 lda zp1+2 +18e1 : a517 lda zp1+2 18e3 : 08 php ;test stores do not alter flags 18e4 : 49c3 eor #$c3 18e6 : 28 plp @@ -6321,7 +6323,7 @@ ffff = ram_top = -1 eor_flag 0 18f2 : 4930 > eor #0|fao ;invert expected flags + always on bits -18f4 : cd1e02 cmp fLDx+2 ;test flags +18f4 : cd1f02 cmp fLDx+2 ;test flags trap_ne 18f7 : d0fe > bne * ;failed not equal (non zero) @@ -6332,7 +6334,7 @@ ffff = ram_top = -1 18fb : 48 > pha ;use stack to load status 18fc : 28 > plp -18fd : a516 lda zp1+3 +18fd : a518 lda zp1+3 18ff : 08 php ;test stores do not alter flags 1900 : 49c3 eor #$c3 1902 : 28 plp @@ -6347,7 +6349,7 @@ ffff = ram_top = -1 eor_flag 0 190e : 4930 > eor #0|fao ;invert expected flags + always on bits -1910 : cd1f02 cmp fLDx+3 ;test flags +1910 : cd2002 cmp fLDx+3 ;test flags trap_ne 1913 : d0fe > bne * ;failed not equal (non zero) @@ -6358,7 +6360,7 @@ ffff = ram_top = -1 1917 : 48 > pha ;use stack to load status 1918 : 28 > plp -1919 : a513 lda zp1 +1919 : a515 lda zp1 191b : 08 php ;test stores do not alter flags 191c : 49c3 eor #$c3 191e : 28 plp @@ -6373,7 +6375,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 192a : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -192c : cd1c02 cmp fLDx ;test flags +192c : cd1d02 cmp fLDx ;test flags trap_ne 192f : d0fe > bne * ;failed not equal (non zero) @@ -6384,7 +6386,7 @@ ffff = ram_top = -1 1933 : 48 > pha ;use stack to load status 1934 : 28 > plp -1935 : a514 lda zp1+1 +1935 : a516 lda zp1+1 1937 : 08 php ;test stores do not alter flags 1938 : 49c3 eor #$c3 193a : 28 plp @@ -6399,7 +6401,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1946 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1948 : cd1d02 cmp fLDx+1 ;test flags +1948 : cd1e02 cmp fLDx+1 ;test flags trap_ne 194b : d0fe > bne * ;failed not equal (non zero) @@ -6410,7 +6412,7 @@ ffff = ram_top = -1 194f : 48 > pha ;use stack to load status 1950 : 28 > plp -1951 : a515 lda zp1+2 +1951 : a517 lda zp1+2 1953 : 08 php ;test stores do not alter flags 1954 : 49c3 eor #$c3 1956 : 28 plp @@ -6425,7 +6427,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1962 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1964 : cd1e02 cmp fLDx+2 ;test flags +1964 : cd1f02 cmp fLDx+2 ;test flags trap_ne 1967 : d0fe > bne * ;failed not equal (non zero) @@ -6436,7 +6438,7 @@ ffff = ram_top = -1 196b : 48 > pha ;use stack to load status 196c : 28 > plp -196d : a516 lda zp1+3 +196d : a518 lda zp1+3 196f : 08 php ;test stores do not alter flags 1970 : 49c3 eor #$c3 1972 : 28 plp @@ -6451,7 +6453,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 197e : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1980 : cd1f02 cmp fLDx+3 ;test flags +1980 : cd2002 cmp fLDx+3 ;test flags trap_ne 1983 : d0fe > bne * ;failed not equal (non zero) @@ -6462,14 +6464,14 @@ ffff = ram_top = -1 1987 : 48 > pha ;use stack to load status 1988 : 28 > plp -1989 : ad1702 lda abs1 +1989 : ad1802 lda abs1 198c : 08 php ;test stores do not alter flags 198d : 49c3 eor #$c3 198f : 28 plp 1990 : 850c sta zpt 1992 : 08 php ;flags after load/store sequence 1993 : 49c3 eor #$c3 -1995 : c513 cmp zp1 ;test result +1995 : c515 cmp zp1 ;test result trap_ne 1997 : d0fe > bne * ;failed not equal (non zero) @@ -6477,7 +6479,7 @@ ffff = ram_top = -1 eor_flag 0 199a : 4930 > eor #0|fao ;invert expected flags + always on bits -199c : cd1c02 cmp fLDx ;test flags +199c : cd1d02 cmp fLDx ;test flags trap_ne 199f : d0fe > bne * ;failed not equal (non zero) @@ -6488,14 +6490,14 @@ ffff = ram_top = -1 19a3 : 48 > pha ;use stack to load status 19a4 : 28 > plp -19a5 : ad1802 lda abs1+1 +19a5 : ad1902 lda abs1+1 19a8 : 08 php ;test stores do not alter flags 19a9 : 49c3 eor #$c3 19ab : 28 plp 19ac : 850d sta zpt+1 19ae : 08 php ;flags after load/store sequence 19af : 49c3 eor #$c3 -19b1 : c514 cmp zp1+1 ;test result +19b1 : c516 cmp zp1+1 ;test result trap_ne 19b3 : d0fe > bne * ;failed not equal (non zero) @@ -6503,7 +6505,7 @@ ffff = ram_top = -1 eor_flag 0 19b6 : 4930 > eor #0|fao ;invert expected flags + always on bits -19b8 : cd1d02 cmp fLDx+1 ;test flags +19b8 : cd1e02 cmp fLDx+1 ;test flags trap_ne 19bb : d0fe > bne * ;failed not equal (non zero) @@ -6514,14 +6516,14 @@ ffff = ram_top = -1 19bf : 48 > pha ;use stack to load status 19c0 : 28 > plp -19c1 : ad1902 lda abs1+2 +19c1 : ad1a02 lda abs1+2 19c4 : 08 php ;test stores do not alter flags 19c5 : 49c3 eor #$c3 19c7 : 28 plp 19c8 : 850e sta zpt+2 19ca : 08 php ;flags after load/store sequence 19cb : 49c3 eor #$c3 -19cd : c515 cmp zp1+2 ;test result +19cd : c517 cmp zp1+2 ;test result trap_ne 19cf : d0fe > bne * ;failed not equal (non zero) @@ -6529,7 +6531,7 @@ ffff = ram_top = -1 eor_flag 0 19d2 : 4930 > eor #0|fao ;invert expected flags + always on bits -19d4 : cd1e02 cmp fLDx+2 ;test flags +19d4 : cd1f02 cmp fLDx+2 ;test flags trap_ne 19d7 : d0fe > bne * ;failed not equal (non zero) @@ -6540,14 +6542,14 @@ ffff = ram_top = -1 19db : 48 > pha ;use stack to load status 19dc : 28 > plp -19dd : ad1a02 lda abs1+3 +19dd : ad1b02 lda abs1+3 19e0 : 08 php ;test stores do not alter flags 19e1 : 49c3 eor #$c3 19e3 : 28 plp 19e4 : 850f sta zpt+3 19e6 : 08 php ;flags after load/store sequence 19e7 : 49c3 eor #$c3 -19e9 : c516 cmp zp1+3 ;test result +19e9 : c518 cmp zp1+3 ;test result trap_ne 19eb : d0fe > bne * ;failed not equal (non zero) @@ -6555,7 +6557,7 @@ ffff = ram_top = -1 eor_flag 0 19ee : 4930 > eor #0|fao ;invert expected flags + always on bits -19f0 : cd1f02 cmp fLDx+3 ;test flags +19f0 : cd2002 cmp fLDx+3 ;test flags trap_ne 19f3 : d0fe > bne * ;failed not equal (non zero) @@ -6566,14 +6568,14 @@ ffff = ram_top = -1 19f7 : 48 > pha ;use stack to load status 19f8 : 28 > plp -19f9 : ad1702 lda abs1 +19f9 : ad1802 lda abs1 19fc : 08 php ;test stores do not alter flags 19fd : 49c3 eor #$c3 19ff : 28 plp 1a00 : 850c sta zpt 1a02 : 08 php ;flags after load/store sequence 1a03 : 49c3 eor #$c3 -1a05 : c513 cmp zp1 ;test result +1a05 : c515 cmp zp1 ;test result trap_ne 1a07 : d0fe > bne * ;failed not equal (non zero) @@ -6581,7 +6583,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1a0a : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1a0c : cd1c02 cmp fLDx ;test flags +1a0c : cd1d02 cmp fLDx ;test flags trap_ne 1a0f : d0fe > bne * ;failed not equal (non zero) @@ -6592,14 +6594,14 @@ ffff = ram_top = -1 1a13 : 48 > pha ;use stack to load status 1a14 : 28 > plp -1a15 : ad1802 lda abs1+1 +1a15 : ad1902 lda abs1+1 1a18 : 08 php ;test stores do not alter flags 1a19 : 49c3 eor #$c3 1a1b : 28 plp 1a1c : 850d sta zpt+1 1a1e : 08 php ;flags after load/store sequence 1a1f : 49c3 eor #$c3 -1a21 : c514 cmp zp1+1 ;test result +1a21 : c516 cmp zp1+1 ;test result trap_ne 1a23 : d0fe > bne * ;failed not equal (non zero) @@ -6607,7 +6609,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1a26 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1a28 : cd1d02 cmp fLDx+1 ;test flags +1a28 : cd1e02 cmp fLDx+1 ;test flags trap_ne 1a2b : d0fe > bne * ;failed not equal (non zero) @@ -6618,14 +6620,14 @@ ffff = ram_top = -1 1a2f : 48 > pha ;use stack to load status 1a30 : 28 > plp -1a31 : ad1902 lda abs1+2 +1a31 : ad1a02 lda abs1+2 1a34 : 08 php ;test stores do not alter flags 1a35 : 49c3 eor #$c3 1a37 : 28 plp 1a38 : 850e sta zpt+2 1a3a : 08 php ;flags after load/store sequence 1a3b : 49c3 eor #$c3 -1a3d : c515 cmp zp1+2 ;test result +1a3d : c517 cmp zp1+2 ;test result trap_ne 1a3f : d0fe > bne * ;failed not equal (non zero) @@ -6633,7 +6635,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1a42 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1a44 : cd1e02 cmp fLDx+2 ;test flags +1a44 : cd1f02 cmp fLDx+2 ;test flags trap_ne 1a47 : d0fe > bne * ;failed not equal (non zero) @@ -6644,14 +6646,14 @@ ffff = ram_top = -1 1a4b : 48 > pha ;use stack to load status 1a4c : 28 > plp -1a4d : ad1a02 lda abs1+3 +1a4d : ad1b02 lda abs1+3 1a50 : 08 php ;test stores do not alter flags 1a51 : 49c3 eor #$c3 1a53 : 28 plp 1a54 : 850f sta zpt+3 1a56 : 08 php ;flags after load/store sequence 1a57 : 49c3 eor #$c3 -1a59 : c516 cmp zp1+3 ;test result +1a59 : c518 cmp zp1+3 ;test result trap_ne 1a5b : d0fe > bne * ;failed not equal (non zero) @@ -6659,7 +6661,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1a5e : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1a60 : cd1f02 cmp fLDx+3 ;test flags +1a60 : cd2002 cmp fLDx+3 ;test flags trap_ne 1a63 : d0fe > bne * ;failed not equal (non zero) @@ -6672,7 +6674,7 @@ ffff = ram_top = -1 1a69 : a9c3 lda #$c3 1a6b : 08 php -1a6c : cd1702 cmp abs1 ;test result +1a6c : cd1802 cmp abs1 ;test result trap_ne 1a6f : d0fe > bne * ;failed not equal (non zero) @@ -6680,7 +6682,7 @@ ffff = ram_top = -1 eor_flag 0 1a72 : 4930 > eor #0|fao ;invert expected flags + always on bits -1a74 : cd1c02 cmp fLDx ;test flags +1a74 : cd1d02 cmp fLDx ;test flags trap_ne 1a77 : d0fe > bne * ;failed not equal (non zero) @@ -6693,7 +6695,7 @@ ffff = ram_top = -1 1a7d : a982 lda #$82 1a7f : 08 php -1a80 : cd1802 cmp abs1+1 ;test result +1a80 : cd1902 cmp abs1+1 ;test result trap_ne 1a83 : d0fe > bne * ;failed not equal (non zero) @@ -6701,7 +6703,7 @@ ffff = ram_top = -1 eor_flag 0 1a86 : 4930 > eor #0|fao ;invert expected flags + always on bits -1a88 : cd1d02 cmp fLDx+1 ;test flags +1a88 : cd1e02 cmp fLDx+1 ;test flags trap_ne 1a8b : d0fe > bne * ;failed not equal (non zero) @@ -6714,7 +6716,7 @@ ffff = ram_top = -1 1a91 : a941 lda #$41 1a93 : 08 php -1a94 : cd1902 cmp abs1+2 ;test result +1a94 : cd1a02 cmp abs1+2 ;test result trap_ne 1a97 : d0fe > bne * ;failed not equal (non zero) @@ -6722,7 +6724,7 @@ ffff = ram_top = -1 eor_flag 0 1a9a : 4930 > eor #0|fao ;invert expected flags + always on bits -1a9c : cd1e02 cmp fLDx+2 ;test flags +1a9c : cd1f02 cmp fLDx+2 ;test flags trap_ne 1a9f : d0fe > bne * ;failed not equal (non zero) @@ -6735,7 +6737,7 @@ ffff = ram_top = -1 1aa5 : a900 lda #0 1aa7 : 08 php -1aa8 : cd1a02 cmp abs1+3 ;test result +1aa8 : cd1b02 cmp abs1+3 ;test result trap_ne 1aab : d0fe > bne * ;failed not equal (non zero) @@ -6743,7 +6745,7 @@ ffff = ram_top = -1 eor_flag 0 1aae : 4930 > eor #0|fao ;invert expected flags + always on bits -1ab0 : cd1f02 cmp fLDx+3 ;test flags +1ab0 : cd2002 cmp fLDx+3 ;test flags trap_ne 1ab3 : d0fe > bne * ;failed not equal (non zero) @@ -6757,7 +6759,7 @@ ffff = ram_top = -1 1ab9 : a9c3 lda #$c3 1abb : 08 php -1abc : cd1702 cmp abs1 ;test result +1abc : cd1802 cmp abs1 ;test result trap_ne 1abf : d0fe > bne * ;failed not equal (non zero) @@ -6765,7 +6767,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1ac2 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1ac4 : cd1c02 cmp fLDx ;test flags +1ac4 : cd1d02 cmp fLDx ;test flags trap_ne 1ac7 : d0fe > bne * ;failed not equal (non zero) @@ -6778,7 +6780,7 @@ ffff = ram_top = -1 1acd : a982 lda #$82 1acf : 08 php -1ad0 : cd1802 cmp abs1+1 ;test result +1ad0 : cd1902 cmp abs1+1 ;test result trap_ne 1ad3 : d0fe > bne * ;failed not equal (non zero) @@ -6786,7 +6788,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1ad6 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1ad8 : cd1d02 cmp fLDx+1 ;test flags +1ad8 : cd1e02 cmp fLDx+1 ;test flags trap_ne 1adb : d0fe > bne * ;failed not equal (non zero) @@ -6799,7 +6801,7 @@ ffff = ram_top = -1 1ae1 : a941 lda #$41 1ae3 : 08 php -1ae4 : cd1902 cmp abs1+2 ;test result +1ae4 : cd1a02 cmp abs1+2 ;test result trap_ne 1ae7 : d0fe > bne * ;failed not equal (non zero) @@ -6807,7 +6809,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1aea : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1aec : cd1e02 cmp fLDx+2 ;test flags +1aec : cd1f02 cmp fLDx+2 ;test flags trap_ne 1aef : d0fe > bne * ;failed not equal (non zero) @@ -6820,7 +6822,7 @@ ffff = ram_top = -1 1af5 : a900 lda #0 1af7 : 08 php -1af8 : cd1a02 cmp abs1+3 ;test result +1af8 : cd1b02 cmp abs1+3 ;test result trap_ne 1afb : d0fe > bne * ;failed not equal (non zero) @@ -6828,7 +6830,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1afe : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1b00 : cd1f02 cmp fLDx+3 ;test flags +1b00 : cd2002 cmp fLDx+3 ;test flags trap_ne 1b03 : d0fe > bne * ;failed not equal (non zero) @@ -6836,56 +6838,56 @@ ffff = ram_top = -1 1b05 : a200 ldx #0 1b07 : a50c lda zpt 1b09 : 49c3 eor #$c3 -1b0b : c513 cmp zp1 +1b0b : c515 cmp zp1 trap_ne ;store to zp data 1b0d : d0fe > bne * ;failed not equal (non zero) 1b0f : 860c stx zpt ;clear 1b11 : ad0302 lda abst 1b14 : 49c3 eor #$c3 -1b16 : cd1702 cmp abs1 +1b16 : cd1802 cmp abs1 trap_ne ;store to abs data 1b19 : d0fe > bne * ;failed not equal (non zero) 1b1b : 8e0302 stx abst ;clear 1b1e : a50d lda zpt+1 1b20 : 49c3 eor #$c3 -1b22 : c514 cmp zp1+1 +1b22 : c516 cmp zp1+1 trap_ne ;store to zp data 1b24 : d0fe > bne * ;failed not equal (non zero) 1b26 : 860d stx zpt+1 ;clear 1b28 : ad0402 lda abst+1 1b2b : 49c3 eor #$c3 -1b2d : cd1802 cmp abs1+1 +1b2d : cd1902 cmp abs1+1 trap_ne ;store to abs data 1b30 : d0fe > bne * ;failed not equal (non zero) 1b32 : 8e0402 stx abst+1 ;clear 1b35 : a50e lda zpt+2 1b37 : 49c3 eor #$c3 -1b39 : c515 cmp zp1+2 +1b39 : c517 cmp zp1+2 trap_ne ;store to zp data 1b3b : d0fe > bne * ;failed not equal (non zero) 1b3d : 860e stx zpt+2 ;clear 1b3f : ad0502 lda abst+2 1b42 : 49c3 eor #$c3 -1b44 : cd1902 cmp abs1+2 +1b44 : cd1a02 cmp abs1+2 trap_ne ;store to abs data 1b47 : d0fe > bne * ;failed not equal (non zero) 1b49 : 8e0502 stx abst+2 ;clear 1b4c : a50f lda zpt+3 1b4e : 49c3 eor #$c3 -1b50 : c516 cmp zp1+3 +1b50 : c518 cmp zp1+3 trap_ne ;store to zp data 1b52 : d0fe > bne * ;failed not equal (non zero) 1b54 : 860f stx zpt+3 ;clear 1b56 : ad0602 lda abst+3 1b59 : 49c3 eor #$c3 -1b5b : cd1a02 cmp abs1+3 +1b5b : cd1b02 cmp abs1+3 trap_ne ;store to abs data 1b5e : d0fe > bne * ;failed not equal (non zero) @@ -6912,7 +6914,7 @@ ffff = ram_top = -1 1b72 : a9ff > lda #$ff ;precharge accu 1b74 : 28 > plp -1b75 : 2416 bit zp1+3 ;00 - should set Z / clear NV +1b75 : 2418 bit zp1+3 ;00 - should set Z / clear NV tst_a $ff,fz 1b77 : 08 > php ;save flags 1b78 : c9ff > cmp #$ff ;test result @@ -6937,7 +6939,7 @@ ffff = ram_top = -1 1b86 : a901 > lda #1 ;precharge accu 1b88 : 28 > plp -1b89 : 2415 bit zp1+2 ;41 - should set V (M6) / clear NZ +1b89 : 2417 bit zp1+2 ;41 - should set V (M6) / clear NZ tst_a 1,fv 1b8b : 08 > php ;save flags 1b8c : c901 > cmp #1 ;test result @@ -6962,7 +6964,7 @@ ffff = ram_top = -1 1b9a : a901 > lda #1 ;precharge accu 1b9c : 28 > plp -1b9d : 2414 bit zp1+1 ;82 - should set N (M7) & Z / clear V +1b9d : 2416 bit zp1+1 ;82 - should set N (M7) & Z / clear V tst_a 1,fnz 1b9f : 08 > php ;save flags 1ba0 : c901 > cmp #1 ;test result @@ -6987,7 +6989,7 @@ ffff = ram_top = -1 1bae : a901 > lda #1 ;precharge accu 1bb0 : 28 > plp -1bb1 : 2413 bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z +1bb1 : 2415 bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z tst_a 1,fnv 1bb3 : 08 > php ;save flags 1bb4 : c901 > cmp #1 ;test result @@ -7013,7 +7015,7 @@ ffff = ram_top = -1 1bc2 : a9ff > lda #$ff ;precharge accu 1bc4 : 28 > plp -1bc5 : 2416 bit zp1+3 ;00 - should set Z / clear NV +1bc5 : 2418 bit zp1+3 ;00 - should set Z / clear NV tst_a $ff,~fnv 1bc7 : 08 > php ;save flags 1bc8 : c9ff > cmp #$ff ;test result @@ -7038,7 +7040,7 @@ ffff = ram_top = -1 1bd6 : a901 > lda #1 ;precharge accu 1bd8 : 28 > plp -1bd9 : 2415 bit zp1+2 ;41 - should set V (M6) / clear NZ +1bd9 : 2417 bit zp1+2 ;41 - should set V (M6) / clear NZ tst_a 1,~fnz 1bdb : 08 > php ;save flags 1bdc : c901 > cmp #1 ;test result @@ -7063,7 +7065,7 @@ ffff = ram_top = -1 1bea : a901 > lda #1 ;precharge accu 1bec : 28 > plp -1bed : 2414 bit zp1+1 ;82 - should set N (M7) & Z / clear V +1bed : 2416 bit zp1+1 ;82 - should set N (M7) & Z / clear V tst_a 1,~fv 1bef : 08 > php ;save flags 1bf0 : c901 > cmp #1 ;test result @@ -7088,7 +7090,7 @@ ffff = ram_top = -1 1bfe : a901 > lda #1 ;precharge accu 1c00 : 28 > plp -1c01 : 2413 bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z +1c01 : 2415 bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z tst_a 1,~fz 1c03 : 08 > php ;save flags 1c04 : c901 > cmp #1 ;test result @@ -7114,7 +7116,7 @@ ffff = ram_top = -1 1c12 : a9ff > lda #$ff ;precharge accu 1c14 : 28 > plp -1c15 : 2c1a02 bit abs1+3 ;00 - should set Z / clear NV +1c15 : 2c1b02 bit abs1+3 ;00 - should set Z / clear NV tst_a $ff,fz 1c18 : 08 > php ;save flags 1c19 : c9ff > cmp #$ff ;test result @@ -7139,7 +7141,7 @@ ffff = ram_top = -1 1c27 : a901 > lda #1 ;precharge accu 1c29 : 28 > plp -1c2a : 2c1902 bit abs1+2 ;41 - should set V (M6) / clear NZ +1c2a : 2c1a02 bit abs1+2 ;41 - should set V (M6) / clear NZ tst_a 1,fv 1c2d : 08 > php ;save flags 1c2e : c901 > cmp #1 ;test result @@ -7164,7 +7166,7 @@ ffff = ram_top = -1 1c3c : a901 > lda #1 ;precharge accu 1c3e : 28 > plp -1c3f : 2c1802 bit abs1+1 ;82 - should set N (M7) & Z / clear V +1c3f : 2c1902 bit abs1+1 ;82 - should set N (M7) & Z / clear V tst_a 1,fnz 1c42 : 08 > php ;save flags 1c43 : c901 > cmp #1 ;test result @@ -7189,7 +7191,7 @@ ffff = ram_top = -1 1c51 : a901 > lda #1 ;precharge accu 1c53 : 28 > plp -1c54 : 2c1702 bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z +1c54 : 2c1802 bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z tst_a 1,fnv 1c57 : 08 > php ;save flags 1c58 : c901 > cmp #1 ;test result @@ -7215,7 +7217,7 @@ ffff = ram_top = -1 1c66 : a9ff > lda #$ff ;precharge accu 1c68 : 28 > plp -1c69 : 2c1a02 bit abs1+3 ;00 - should set Z / clear NV +1c69 : 2c1b02 bit abs1+3 ;00 - should set Z / clear NV tst_a $ff,~fnv 1c6c : 08 > php ;save flags 1c6d : c9ff > cmp #$ff ;test result @@ -7240,7 +7242,7 @@ ffff = ram_top = -1 1c7b : a901 > lda #1 ;precharge accu 1c7d : 28 > plp -1c7e : 2c1902 bit abs1+2 ;41 - should set V (M6) / clear NZ +1c7e : 2c1a02 bit abs1+2 ;41 - should set V (M6) / clear NZ tst_a 1,~fnz 1c81 : 08 > php ;save flags 1c82 : c901 > cmp #1 ;test result @@ -7265,7 +7267,7 @@ ffff = ram_top = -1 1c90 : a901 > lda #1 ;precharge accu 1c92 : 28 > plp -1c93 : 2c1802 bit abs1+1 ;82 - should set N (M7) & Z / clear V +1c93 : 2c1902 bit abs1+1 ;82 - should set N (M7) & Z / clear V tst_a 1,~fv 1c96 : 08 > php ;save flags 1c97 : c901 > cmp #1 ;test result @@ -7290,7 +7292,7 @@ ffff = ram_top = -1 1ca5 : a901 > lda #1 ;precharge accu 1ca7 : 28 > plp -1ca8 : 2c1702 bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z +1ca8 : 2c1802 bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z tst_a 1,~fz 1cab : 08 > php ;save flags 1cac : c901 > cmp #1 ;test result @@ -7328,7 +7330,7 @@ ffff = ram_top = -1 1cc6 : a280 > ldx #$80 ;precharge index x 1cc8 : 28 > plp -1cc9 : e417 cpx zp7f +1cc9 : e419 cpx zp7f tst_stat fc 1ccb : 08 > php ;save status 1ccc : 68 > pla ;use stack to retrieve status @@ -7342,7 +7344,7 @@ ffff = ram_top = -1 1cd2 : 28 > plp ;restore status 1cd3 : ca dex -1cd4 : e417 cpx zp7f +1cd4 : e419 cpx zp7f tst_stat fzc 1cd6 : 08 > php ;save status 1cd7 : 68 > pla ;use stack to retrieve status @@ -7356,7 +7358,7 @@ ffff = ram_top = -1 1cdd : 28 > plp ;restore status 1cde : ca dex -1cdf : e417 cpx zp7f +1cdf : e419 cpx zp7f tst_x $7e,fn 1ce1 : 08 > php ;save flags 1ce2 : e07e > cpx #$7e ;test result @@ -7381,7 +7383,7 @@ ffff = ram_top = -1 1cf0 : a280 > ldx #$80 ;precharge index x 1cf2 : 28 > plp -1cf3 : e417 cpx zp7f +1cf3 : e419 cpx zp7f tst_stat ~fnz 1cf5 : 08 > php ;save status 1cf6 : 68 > pla ;use stack to retrieve status @@ -7395,7 +7397,7 @@ ffff = ram_top = -1 1cfc : 28 > plp ;restore status 1cfd : ca dex -1cfe : e417 cpx zp7f +1cfe : e419 cpx zp7f tst_stat ~fn 1d00 : 08 > php ;save status 1d01 : 68 > pla ;use stack to retrieve status @@ -7409,7 +7411,7 @@ ffff = ram_top = -1 1d07 : 28 > plp ;restore status 1d08 : ca dex -1d09 : e417 cpx zp7f +1d09 : e419 cpx zp7f tst_x $7e,~fzc 1d0b : 08 > php ;save flags 1d0c : e07e > cpx #$7e ;test result @@ -7435,7 +7437,7 @@ ffff = ram_top = -1 1d1a : a280 > ldx #$80 ;precharge index x 1d1c : 28 > plp -1d1d : ec1b02 cpx abs7f +1d1d : ec1c02 cpx abs7f tst_stat fc 1d20 : 08 > php ;save status 1d21 : 68 > pla ;use stack to retrieve status @@ -7449,7 +7451,7 @@ ffff = ram_top = -1 1d27 : 28 > plp ;restore status 1d28 : ca dex -1d29 : ec1b02 cpx abs7f +1d29 : ec1c02 cpx abs7f tst_stat fzc 1d2c : 08 > php ;save status 1d2d : 68 > pla ;use stack to retrieve status @@ -7463,7 +7465,7 @@ ffff = ram_top = -1 1d33 : 28 > plp ;restore status 1d34 : ca dex -1d35 : ec1b02 cpx abs7f +1d35 : ec1c02 cpx abs7f tst_x $7e,fn 1d38 : 08 > php ;save flags 1d39 : e07e > cpx #$7e ;test result @@ -7488,7 +7490,7 @@ ffff = ram_top = -1 1d47 : a280 > ldx #$80 ;precharge index x 1d49 : 28 > plp -1d4a : ec1b02 cpx abs7f +1d4a : ec1c02 cpx abs7f tst_stat ~fnz 1d4d : 08 > php ;save status 1d4e : 68 > pla ;use stack to retrieve status @@ -7502,7 +7504,7 @@ ffff = ram_top = -1 1d54 : 28 > plp ;restore status 1d55 : ca dex -1d56 : ec1b02 cpx abs7f +1d56 : ec1c02 cpx abs7f tst_stat ~fn 1d59 : 08 > php ;save status 1d5a : 68 > pla ;use stack to retrieve status @@ -7516,7 +7518,7 @@ ffff = ram_top = -1 1d60 : 28 > plp ;restore status 1d61 : ca dex -1d62 : ec1b02 cpx abs7f +1d62 : ec1c02 cpx abs7f tst_x $7e,~fzc 1d65 : 08 > php ;save flags 1d66 : e07e > cpx #$7e ;test result @@ -7661,7 +7663,7 @@ ffff = ram_top = -1 1dd4 : a080 > ldy #$80 ;precharge index y 1dd6 : 28 > plp -1dd7 : c417 cpy zp7f +1dd7 : c419 cpy zp7f tst_stat fc 1dd9 : 08 > php ;save status 1dda : 68 > pla ;use stack to retrieve status @@ -7675,7 +7677,7 @@ ffff = ram_top = -1 1de0 : 28 > plp ;restore status 1de1 : 88 dey -1de2 : c417 cpy zp7f +1de2 : c419 cpy zp7f tst_stat fzc 1de4 : 08 > php ;save status 1de5 : 68 > pla ;use stack to retrieve status @@ -7689,7 +7691,7 @@ ffff = ram_top = -1 1deb : 28 > plp ;restore status 1dec : 88 dey -1ded : c417 cpy zp7f +1ded : c419 cpy zp7f tst_y $7e,fn 1def : 08 > php ;save flags 1df0 : c07e > cpy #$7e ;test result @@ -7714,7 +7716,7 @@ ffff = ram_top = -1 1dfe : a080 > ldy #$80 ;precharge index y 1e00 : 28 > plp -1e01 : c417 cpy zp7f +1e01 : c419 cpy zp7f tst_stat ~fnz 1e03 : 08 > php ;save status 1e04 : 68 > pla ;use stack to retrieve status @@ -7728,7 +7730,7 @@ ffff = ram_top = -1 1e0a : 28 > plp ;restore status 1e0b : 88 dey -1e0c : c417 cpy zp7f +1e0c : c419 cpy zp7f tst_stat ~fn 1e0e : 08 > php ;save status 1e0f : 68 > pla ;use stack to retrieve status @@ -7742,7 +7744,7 @@ ffff = ram_top = -1 1e15 : 28 > plp ;restore status 1e16 : 88 dey -1e17 : c417 cpy zp7f +1e17 : c419 cpy zp7f tst_y $7e,~fzc 1e19 : 08 > php ;save flags 1e1a : c07e > cpy #$7e ;test result @@ -7768,7 +7770,7 @@ ffff = ram_top = -1 1e28 : a080 > ldy #$80 ;precharge index y 1e2a : 28 > plp -1e2b : cc1b02 cpy abs7f +1e2b : cc1c02 cpy abs7f tst_stat fc 1e2e : 08 > php ;save status 1e2f : 68 > pla ;use stack to retrieve status @@ -7782,7 +7784,7 @@ ffff = ram_top = -1 1e35 : 28 > plp ;restore status 1e36 : 88 dey -1e37 : cc1b02 cpy abs7f +1e37 : cc1c02 cpy abs7f tst_stat fzc 1e3a : 08 > php ;save status 1e3b : 68 > pla ;use stack to retrieve status @@ -7796,7 +7798,7 @@ ffff = ram_top = -1 1e41 : 28 > plp ;restore status 1e42 : 88 dey -1e43 : cc1b02 cpy abs7f +1e43 : cc1c02 cpy abs7f tst_y $7e,fn 1e46 : 08 > php ;save flags 1e47 : c07e > cpy #$7e ;test result @@ -7821,7 +7823,7 @@ ffff = ram_top = -1 1e55 : a080 > ldy #$80 ;precharge index y 1e57 : 28 > plp -1e58 : cc1b02 cpy abs7f +1e58 : cc1c02 cpy abs7f tst_stat ~fnz 1e5b : 08 > php ;save status 1e5c : 68 > pla ;use stack to retrieve status @@ -7835,7 +7837,7 @@ ffff = ram_top = -1 1e62 : 28 > plp ;restore status 1e63 : 88 dey -1e64 : cc1b02 cpy abs7f +1e64 : cc1c02 cpy abs7f tst_stat ~fn 1e67 : 08 > php ;save status 1e68 : 68 > pla ;use stack to retrieve status @@ -7849,7 +7851,7 @@ ffff = ram_top = -1 1e6e : 28 > plp ;restore status 1e6f : 88 dey -1e70 : cc1b02 cpy abs7f +1e70 : cc1c02 cpy abs7f tst_y $7e,~fzc 1e73 : 08 > php ;save flags 1e74 : c07e > cpy #$7e ;test result @@ -7994,7 +7996,7 @@ ffff = ram_top = -1 1ee2 : a980 > lda #$80 ;precharge accu 1ee4 : 28 > plp -1ee5 : c517 cmp zp7f +1ee5 : c519 cmp zp7f tst_a $80,fc 1ee7 : 08 > php ;save flags 1ee8 : c980 > cmp #$80 ;test result @@ -8019,7 +8021,7 @@ ffff = ram_top = -1 1ef6 : a97f > lda #$7f ;precharge accu 1ef8 : 28 > plp -1ef9 : c517 cmp zp7f +1ef9 : c519 cmp zp7f tst_a $7f,fzc 1efb : 08 > php ;save flags 1efc : c97f > cmp #$7f ;test result @@ -8044,7 +8046,7 @@ ffff = ram_top = -1 1f0a : a97e > lda #$7e ;precharge accu 1f0c : 28 > plp -1f0d : c517 cmp zp7f +1f0d : c519 cmp zp7f tst_a $7e,fn 1f0f : 08 > php ;save flags 1f10 : c97e > cmp #$7e ;test result @@ -8069,7 +8071,7 @@ ffff = ram_top = -1 1f1e : a980 > lda #$80 ;precharge accu 1f20 : 28 > plp -1f21 : c517 cmp zp7f +1f21 : c519 cmp zp7f tst_a $80,~fnz 1f23 : 08 > php ;save flags 1f24 : c980 > cmp #$80 ;test result @@ -8094,7 +8096,7 @@ ffff = ram_top = -1 1f32 : a97f > lda #$7f ;precharge accu 1f34 : 28 > plp -1f35 : c517 cmp zp7f +1f35 : c519 cmp zp7f tst_a $7f,~fn 1f37 : 08 > php ;save flags 1f38 : c97f > cmp #$7f ;test result @@ -8119,7 +8121,7 @@ ffff = ram_top = -1 1f46 : a97e > lda #$7e ;precharge accu 1f48 : 28 > plp -1f49 : c517 cmp zp7f +1f49 : c519 cmp zp7f tst_a $7e,~fzc 1f4b : 08 > php ;save flags 1f4c : c97e > cmp #$7e ;test result @@ -8145,7 +8147,7 @@ ffff = ram_top = -1 1f5a : a980 > lda #$80 ;precharge accu 1f5c : 28 > plp -1f5d : cd1b02 cmp abs7f +1f5d : cd1c02 cmp abs7f tst_a $80,fc 1f60 : 08 > php ;save flags 1f61 : c980 > cmp #$80 ;test result @@ -8170,7 +8172,7 @@ ffff = ram_top = -1 1f6f : a97f > lda #$7f ;precharge accu 1f71 : 28 > plp -1f72 : cd1b02 cmp abs7f +1f72 : cd1c02 cmp abs7f tst_a $7f,fzc 1f75 : 08 > php ;save flags 1f76 : c97f > cmp #$7f ;test result @@ -8195,7 +8197,7 @@ ffff = ram_top = -1 1f84 : a97e > lda #$7e ;precharge accu 1f86 : 28 > plp -1f87 : cd1b02 cmp abs7f +1f87 : cd1c02 cmp abs7f tst_a $7e,fn 1f8a : 08 > php ;save flags 1f8b : c97e > cmp #$7e ;test result @@ -8220,7 +8222,7 @@ ffff = ram_top = -1 1f99 : a980 > lda #$80 ;precharge accu 1f9b : 28 > plp -1f9c : cd1b02 cmp abs7f +1f9c : cd1c02 cmp abs7f tst_a $80,~fnz 1f9f : 08 > php ;save flags 1fa0 : c980 > cmp #$80 ;test result @@ -8245,7 +8247,7 @@ ffff = ram_top = -1 1fae : a97f > lda #$7f ;precharge accu 1fb0 : 28 > plp -1fb1 : cd1b02 cmp abs7f +1fb1 : cd1c02 cmp abs7f tst_a $7f,~fn 1fb4 : 08 > php ;save flags 1fb5 : c97f > cmp #$7f ;test result @@ -8270,7 +8272,7 @@ ffff = ram_top = -1 1fc3 : a97e > lda #$7e ;precharge accu 1fc5 : 28 > plp -1fc6 : cd1b02 cmp abs7f +1fc6 : cd1c02 cmp abs7f tst_a $7e,~fzc 1fc9 : 08 > php ;save flags 1fca : c97e > cmp #$7e ;test result @@ -8448,7 +8450,7 @@ ffff = ram_top = -1 2052 : a980 > lda #$80 ;precharge accu 2054 : 28 > plp -2055 : d513 cmp zp1,x +2055 : d515 cmp zp1,x tst_a $80,fc 2057 : 08 > php ;save flags 2058 : c980 > cmp #$80 ;test result @@ -8473,7 +8475,7 @@ ffff = ram_top = -1 2066 : a97f > lda #$7f ;precharge accu 2068 : 28 > plp -2069 : d513 cmp zp1,x +2069 : d515 cmp zp1,x tst_a $7f,fzc 206b : 08 > php ;save flags 206c : c97f > cmp #$7f ;test result @@ -8498,7 +8500,7 @@ ffff = ram_top = -1 207a : a97e > lda #$7e ;precharge accu 207c : 28 > plp -207d : d513 cmp zp1,x +207d : d515 cmp zp1,x tst_a $7e,fn 207f : 08 > php ;save flags 2080 : c97e > cmp #$7e ;test result @@ -8523,7 +8525,7 @@ ffff = ram_top = -1 208e : a980 > lda #$80 ;precharge accu 2090 : 28 > plp -2091 : d513 cmp zp1,x +2091 : d515 cmp zp1,x tst_a $80,~fnz 2093 : 08 > php ;save flags 2094 : c980 > cmp #$80 ;test result @@ -8548,7 +8550,7 @@ ffff = ram_top = -1 20a2 : a97f > lda #$7f ;precharge accu 20a4 : 28 > plp -20a5 : d513 cmp zp1,x +20a5 : d515 cmp zp1,x tst_a $7f,~fn 20a7 : 08 > php ;save flags 20a8 : c97f > cmp #$7f ;test result @@ -8573,7 +8575,7 @@ ffff = ram_top = -1 20b6 : a97e > lda #$7e ;precharge accu 20b8 : 28 > plp -20b9 : d513 cmp zp1,x +20b9 : d515 cmp zp1,x tst_a $7e,~fzc 20bb : 08 > php ;save flags 20bc : c97e > cmp #$7e ;test result @@ -8599,7 +8601,7 @@ ffff = ram_top = -1 20ca : a980 > lda #$80 ;precharge accu 20cc : 28 > plp -20cd : dd1702 cmp abs1,x +20cd : dd1802 cmp abs1,x tst_a $80,fc 20d0 : 08 > php ;save flags 20d1 : c980 > cmp #$80 ;test result @@ -8624,7 +8626,7 @@ ffff = ram_top = -1 20df : a97f > lda #$7f ;precharge accu 20e1 : 28 > plp -20e2 : dd1702 cmp abs1,x +20e2 : dd1802 cmp abs1,x tst_a $7f,fzc 20e5 : 08 > php ;save flags 20e6 : c97f > cmp #$7f ;test result @@ -8649,7 +8651,7 @@ ffff = ram_top = -1 20f4 : a97e > lda #$7e ;precharge accu 20f6 : 28 > plp -20f7 : dd1702 cmp abs1,x +20f7 : dd1802 cmp abs1,x tst_a $7e,fn 20fa : 08 > php ;save flags 20fb : c97e > cmp #$7e ;test result @@ -8674,7 +8676,7 @@ ffff = ram_top = -1 2109 : a980 > lda #$80 ;precharge accu 210b : 28 > plp -210c : dd1702 cmp abs1,x +210c : dd1802 cmp abs1,x tst_a $80,~fnz 210f : 08 > php ;save flags 2110 : c980 > cmp #$80 ;test result @@ -8699,7 +8701,7 @@ ffff = ram_top = -1 211e : a97f > lda #$7f ;precharge accu 2120 : 28 > plp -2121 : dd1702 cmp abs1,x +2121 : dd1802 cmp abs1,x tst_a $7f,~fn 2124 : 08 > php ;save flags 2125 : c97f > cmp #$7f ;test result @@ -8724,7 +8726,7 @@ ffff = ram_top = -1 2133 : a97e > lda #$7e ;precharge accu 2135 : 28 > plp -2136 : dd1702 cmp abs1,x +2136 : dd1802 cmp abs1,x tst_a $7e,~fzc 2139 : 08 > php ;save flags 213a : c97e > cmp #$7e ;test result @@ -8752,7 +8754,7 @@ ffff = ram_top = -1 214c : a980 > lda #$80 ;precharge accu 214e : 28 > plp -214f : d91702 cmp abs1,y +214f : d91802 cmp abs1,y tst_a $80,fc 2152 : 08 > php ;save flags 2153 : c980 > cmp #$80 ;test result @@ -8777,7 +8779,7 @@ ffff = ram_top = -1 2161 : a97f > lda #$7f ;precharge accu 2163 : 28 > plp -2164 : d91702 cmp abs1,y +2164 : d91802 cmp abs1,y tst_a $7f,fzc 2167 : 08 > php ;save flags 2168 : c97f > cmp #$7f ;test result @@ -8802,7 +8804,7 @@ ffff = ram_top = -1 2176 : a97e > lda #$7e ;precharge accu 2178 : 28 > plp -2179 : d91702 cmp abs1,y +2179 : d91802 cmp abs1,y tst_a $7e,fn 217c : 08 > php ;save flags 217d : c97e > cmp #$7e ;test result @@ -8827,7 +8829,7 @@ ffff = ram_top = -1 218b : a980 > lda #$80 ;precharge accu 218d : 28 > plp -218e : d91702 cmp abs1,y +218e : d91802 cmp abs1,y tst_a $80,~fnz 2191 : 08 > php ;save flags 2192 : c980 > cmp #$80 ;test result @@ -8852,7 +8854,7 @@ ffff = ram_top = -1 21a0 : a97f > lda #$7f ;precharge accu 21a2 : 28 > plp -21a3 : d91702 cmp abs1,y +21a3 : d91802 cmp abs1,y tst_a $7f,~fn 21a6 : 08 > php ;save flags 21a7 : c97f > cmp #$7f ;test result @@ -8877,7 +8879,7 @@ ffff = ram_top = -1 21b5 : a97e > lda #$7e ;precharge accu 21b7 : 28 > plp -21b8 : d91702 cmp abs1,y +21b8 : d91802 cmp abs1,y tst_a $7e,~fzc 21bb : 08 > php ;save flags 21bc : c97e > cmp #$7e ;test result @@ -8903,7 +8905,7 @@ ffff = ram_top = -1 21ca : a980 > lda #$80 ;precharge accu 21cc : 28 > plp -21cd : c124 cmp (ind1,x) +21cd : c126 cmp (ind1,x) tst_a $80,fc 21cf : 08 > php ;save flags 21d0 : c980 > cmp #$80 ;test result @@ -8928,7 +8930,7 @@ ffff = ram_top = -1 21de : a97f > lda #$7f ;precharge accu 21e0 : 28 > plp -21e1 : c124 cmp (ind1,x) +21e1 : c126 cmp (ind1,x) tst_a $7f,fzc 21e3 : 08 > php ;save flags 21e4 : c97f > cmp #$7f ;test result @@ -8953,7 +8955,7 @@ ffff = ram_top = -1 21f2 : a97e > lda #$7e ;precharge accu 21f4 : 28 > plp -21f5 : c124 cmp (ind1,x) +21f5 : c126 cmp (ind1,x) tst_a $7e,fn 21f7 : 08 > php ;save flags 21f8 : c97e > cmp #$7e ;test result @@ -8978,7 +8980,7 @@ ffff = ram_top = -1 2206 : a980 > lda #$80 ;precharge accu 2208 : 28 > plp -2209 : c124 cmp (ind1,x) +2209 : c126 cmp (ind1,x) tst_a $80,~fnz 220b : 08 > php ;save flags 220c : c980 > cmp #$80 ;test result @@ -9003,7 +9005,7 @@ ffff = ram_top = -1 221a : a97f > lda #$7f ;precharge accu 221c : 28 > plp -221d : c124 cmp (ind1,x) +221d : c126 cmp (ind1,x) tst_a $7f,~fn 221f : 08 > php ;save flags 2220 : c97f > cmp #$7f ;test result @@ -9028,7 +9030,7 @@ ffff = ram_top = -1 222e : a97e > lda #$7e ;precharge accu 2230 : 28 > plp -2231 : c124 cmp (ind1,x) +2231 : c126 cmp (ind1,x) tst_a $7e,~fzc 2233 : 08 > php ;save flags 2234 : c97e > cmp #$7e ;test result @@ -9054,7 +9056,7 @@ ffff = ram_top = -1 2242 : a980 > lda #$80 ;precharge accu 2244 : 28 > plp -2245 : d124 cmp (ind1),y +2245 : d126 cmp (ind1),y tst_a $80,fc 2247 : 08 > php ;save flags 2248 : c980 > cmp #$80 ;test result @@ -9079,7 +9081,7 @@ ffff = ram_top = -1 2256 : a97f > lda #$7f ;precharge accu 2258 : 28 > plp -2259 : d124 cmp (ind1),y +2259 : d126 cmp (ind1),y tst_a $7f,fzc 225b : 08 > php ;save flags 225c : c97f > cmp #$7f ;test result @@ -9104,7 +9106,7 @@ ffff = ram_top = -1 226a : a97e > lda #$7e ;precharge accu 226c : 28 > plp -226d : d124 cmp (ind1),y +226d : d126 cmp (ind1),y tst_a $7e,fn 226f : 08 > php ;save flags 2270 : c97e > cmp #$7e ;test result @@ -9129,7 +9131,7 @@ ffff = ram_top = -1 227e : a980 > lda #$80 ;precharge accu 2280 : 28 > plp -2281 : d124 cmp (ind1),y +2281 : d126 cmp (ind1),y tst_a $80,~fnz 2283 : 08 > php ;save flags 2284 : c980 > cmp #$80 ;test result @@ -9154,7 +9156,7 @@ ffff = ram_top = -1 2292 : a97f > lda #$7f ;precharge accu 2294 : 28 > plp -2295 : d124 cmp (ind1),y +2295 : d126 cmp (ind1),y tst_a $7f,~fn 2297 : 08 > php ;save flags 2298 : c97f > cmp #$7f ;test result @@ -9179,7 +9181,7 @@ ffff = ram_top = -1 22a6 : a97e > lda #$7e ;precharge accu 22a8 : 28 > plp -22a9 : d124 cmp (ind1),y +22a9 : d126 cmp (ind1),y tst_a $7e,~fzc 22ab : 08 > php ;save flags 22ac : c97e > cmp #$7e ;test result @@ -9210,20 +9212,20 @@ ffff = ram_top = -1 ; testing shifts - ASL LSR ROL ROR all addressing modes ; shifts - accumulator -22c3 : a203 ldx #3 +22c3 : a205 ldx #5 22c5 : tasl - set_ax zp1,0 + set_ax zps,0 > load_flag 0 22c5 : a900 > lda #0 ;allow test to change I-flag (no mask) > 22c7 : 48 > pha ;use stack to load status -22c8 : b513 > lda zp1,x ;precharge accu +22c8 : b513 > lda zps,x ;precharge accu 22ca : 28 > plp 22cb : 0a asl a tst_ax rASL,fASL,0 22cc : 08 > php ;save flags -22cd : dd2002 > cmp rASL,x ;test result +22cd : dd2102 > cmp rASL,x ;test result > trap_ne 22d0 : d0fe > bne * ;failed not equal (non zero) > @@ -9231,27 +9233,27 @@ ffff = ram_top = -1 > eor_flag 0 22d3 : 4930 > eor #0|fao ;invert expected flags + always on bits > -22d5 : dd3002 > cmp fASL,x ;test flags +22d5 : dd3902 > cmp fASL,x ;test flags > trap_ne ; 22d8 : d0fe > bne * ;failed not equal (non zero) > 22da : ca dex 22db : 10e8 bpl tasl -22dd : a203 ldx #3 +22dd : a205 ldx #5 22df : tasl1 - set_ax zp1,$ff + set_ax zps,$ff > load_flag $ff 22df : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 22e1 : 48 > pha ;use stack to load status -22e2 : b513 > lda zp1,x ;precharge accu +22e2 : b513 > lda zps,x ;precharge accu 22e4 : 28 > plp 22e5 : 0a asl a tst_ax rASL,fASL,$ff-fnzc 22e6 : 08 > php ;save flags -22e7 : dd2002 > cmp rASL,x ;test result +22e7 : dd2102 > cmp rASL,x ;test result > trap_ne 22ea : d0fe > bne * ;failed not equal (non zero) > @@ -9259,7 +9261,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 22ed : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -22ef : dd3002 > cmp fASL,x ;test flags +22ef : dd3902 > cmp fASL,x ;test flags > trap_ne ; 22f2 : d0fe > bne * ;failed not equal (non zero) > @@ -9267,20 +9269,20 @@ ffff = ram_top = -1 22f4 : ca dex 22f5 : 10e8 bpl tasl1 -22f7 : a203 ldx #3 +22f7 : a205 ldx #5 22f9 : tlsr - set_ax zp1,0 + set_ax zps,0 > load_flag 0 22f9 : a900 > lda #0 ;allow test to change I-flag (no mask) > 22fb : 48 > pha ;use stack to load status -22fc : b513 > lda zp1,x ;precharge accu +22fc : b513 > lda zps,x ;precharge accu 22fe : 28 > plp 22ff : 4a lsr a tst_ax rLSR,fLSR,0 2300 : 08 > php ;save flags -2301 : dd2802 > cmp rLSR,x ;test result +2301 : dd2d02 > cmp rLSR,x ;test result > trap_ne 2304 : d0fe > bne * ;failed not equal (non zero) > @@ -9288,27 +9290,27 @@ ffff = ram_top = -1 > eor_flag 0 2307 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2309 : dd3802 > cmp fLSR,x ;test flags +2309 : dd4502 > cmp fLSR,x ;test flags > trap_ne ; 230c : d0fe > bne * ;failed not equal (non zero) > 230e : ca dex 230f : 10e8 bpl tlsr -2311 : a203 ldx #3 +2311 : a205 ldx #5 2313 : tlsr1 - set_ax zp1,$ff + set_ax zps,$ff > load_flag $ff 2313 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2315 : 48 > pha ;use stack to load status -2316 : b513 > lda zp1,x ;precharge accu +2316 : b513 > lda zps,x ;precharge accu 2318 : 28 > plp 2319 : 4a lsr a tst_ax rLSR,fLSR,$ff-fnzc 231a : 08 > php ;save flags -231b : dd2802 > cmp rLSR,x ;test result +231b : dd2d02 > cmp rLSR,x ;test result > trap_ne 231e : d0fe > bne * ;failed not equal (non zero) > @@ -9316,7 +9318,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2321 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2323 : dd3802 > cmp fLSR,x ;test flags +2323 : dd4502 > cmp fLSR,x ;test flags > trap_ne ; 2326 : d0fe > bne * ;failed not equal (non zero) > @@ -9324,20 +9326,20 @@ ffff = ram_top = -1 2328 : ca dex 2329 : 10e8 bpl tlsr1 -232b : a203 ldx #3 +232b : a205 ldx #5 232d : trol - set_ax zp1,0 + set_ax zps,0 > load_flag 0 232d : a900 > lda #0 ;allow test to change I-flag (no mask) > 232f : 48 > pha ;use stack to load status -2330 : b513 > lda zp1,x ;precharge accu +2330 : b513 > lda zps,x ;precharge accu 2332 : 28 > plp 2333 : 2a rol a tst_ax rROL,fROL,0 2334 : 08 > php ;save flags -2335 : dd2002 > cmp rROL,x ;test result +2335 : dd2102 > cmp rROL,x ;test result > trap_ne 2338 : d0fe > bne * ;failed not equal (non zero) > @@ -9345,27 +9347,27 @@ ffff = ram_top = -1 > eor_flag 0 233b : 4930 > eor #0|fao ;invert expected flags + always on bits > -233d : dd3002 > cmp fROL,x ;test flags +233d : dd3902 > cmp fROL,x ;test flags > trap_ne ; 2340 : d0fe > bne * ;failed not equal (non zero) > 2342 : ca dex 2343 : 10e8 bpl trol -2345 : a203 ldx #3 +2345 : a205 ldx #5 2347 : trol1 - set_ax zp1,$ff-fc + set_ax zps,$ff-fc > load_flag $ff-fc 2347 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 2349 : 48 > pha ;use stack to load status -234a : b513 > lda zp1,x ;precharge accu +234a : b513 > lda zps,x ;precharge accu 234c : 28 > plp 234d : 2a rol a tst_ax rROL,fROL,$ff-fnzc 234e : 08 > php ;save flags -234f : dd2002 > cmp rROL,x ;test result +234f : dd2102 > cmp rROL,x ;test result > trap_ne 2352 : d0fe > bne * ;failed not equal (non zero) > @@ -9373,7 +9375,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2355 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2357 : dd3002 > cmp fROL,x ;test flags +2357 : dd3902 > cmp fROL,x ;test flags > trap_ne ; 235a : d0fe > bne * ;failed not equal (non zero) > @@ -9381,20 +9383,20 @@ ffff = ram_top = -1 235c : ca dex 235d : 10e8 bpl trol1 -235f : a203 ldx #3 +235f : a205 ldx #5 2361 : trolc - set_ax zp1,fc + set_ax zps,fc > load_flag fc 2361 : a901 > lda #fc ;allow test to change I-flag (no mask) > 2363 : 48 > pha ;use stack to load status -2364 : b513 > lda zp1,x ;precharge accu +2364 : b513 > lda zps,x ;precharge accu 2366 : 28 > plp 2367 : 2a rol a tst_ax rROLc,fROLc,0 2368 : 08 > php ;save flags -2369 : dd2402 > cmp rROLc,x ;test result +2369 : dd2702 > cmp rROLc,x ;test result > trap_ne 236c : d0fe > bne * ;failed not equal (non zero) > @@ -9402,27 +9404,27 @@ ffff = ram_top = -1 > eor_flag 0 236f : 4930 > eor #0|fao ;invert expected flags + always on bits > -2371 : dd3402 > cmp fROLc,x ;test flags +2371 : dd3f02 > cmp fROLc,x ;test flags > trap_ne ; 2374 : d0fe > bne * ;failed not equal (non zero) > 2376 : ca dex 2377 : 10e8 bpl trolc -2379 : a203 ldx #3 +2379 : a205 ldx #5 237b : trolc1 - set_ax zp1,$ff + set_ax zps,$ff > load_flag $ff 237b : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 237d : 48 > pha ;use stack to load status -237e : b513 > lda zp1,x ;precharge accu +237e : b513 > lda zps,x ;precharge accu 2380 : 28 > plp 2381 : 2a rol a tst_ax rROLc,fROLc,$ff-fnzc 2382 : 08 > php ;save flags -2383 : dd2402 > cmp rROLc,x ;test result +2383 : dd2702 > cmp rROLc,x ;test result > trap_ne 2386 : d0fe > bne * ;failed not equal (non zero) > @@ -9430,7 +9432,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2389 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -238b : dd3402 > cmp fROLc,x ;test flags +238b : dd3f02 > cmp fROLc,x ;test flags > trap_ne ; 238e : d0fe > bne * ;failed not equal (non zero) > @@ -9438,20 +9440,20 @@ ffff = ram_top = -1 2390 : ca dex 2391 : 10e8 bpl trolc1 -2393 : a203 ldx #3 +2393 : a205 ldx #5 2395 : tror - set_ax zp1,0 + set_ax zps,0 > load_flag 0 2395 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2397 : 48 > pha ;use stack to load status -2398 : b513 > lda zp1,x ;precharge accu +2398 : b513 > lda zps,x ;precharge accu 239a : 28 > plp 239b : 6a ror a tst_ax rROR,fROR,0 239c : 08 > php ;save flags -239d : dd2802 > cmp rROR,x ;test result +239d : dd2d02 > cmp rROR,x ;test result > trap_ne 23a0 : d0fe > bne * ;failed not equal (non zero) > @@ -9459,27 +9461,27 @@ ffff = ram_top = -1 > eor_flag 0 23a3 : 4930 > eor #0|fao ;invert expected flags + always on bits > -23a5 : dd3802 > cmp fROR,x ;test flags +23a5 : dd4502 > cmp fROR,x ;test flags > trap_ne ; 23a8 : d0fe > bne * ;failed not equal (non zero) > 23aa : ca dex 23ab : 10e8 bpl tror -23ad : a203 ldx #3 +23ad : a205 ldx #5 23af : tror1 - set_ax zp1,$ff-fc + set_ax zps,$ff-fc > load_flag $ff-fc 23af : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 23b1 : 48 > pha ;use stack to load status -23b2 : b513 > lda zp1,x ;precharge accu +23b2 : b513 > lda zps,x ;precharge accu 23b4 : 28 > plp 23b5 : 6a ror a tst_ax rROR,fROR,$ff-fnzc 23b6 : 08 > php ;save flags -23b7 : dd2802 > cmp rROR,x ;test result +23b7 : dd2d02 > cmp rROR,x ;test result > trap_ne 23ba : d0fe > bne * ;failed not equal (non zero) > @@ -9487,7 +9489,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 23bd : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -23bf : dd3802 > cmp fROR,x ;test flags +23bf : dd4502 > cmp fROR,x ;test flags > trap_ne ; 23c2 : d0fe > bne * ;failed not equal (non zero) > @@ -9495,20 +9497,20 @@ ffff = ram_top = -1 23c4 : ca dex 23c5 : 10e8 bpl tror1 -23c7 : a203 ldx #3 +23c7 : a205 ldx #5 23c9 : trorc - set_ax zp1,fc + set_ax zps,fc > load_flag fc 23c9 : a901 > lda #fc ;allow test to change I-flag (no mask) > 23cb : 48 > pha ;use stack to load status -23cc : b513 > lda zp1,x ;precharge accu +23cc : b513 > lda zps,x ;precharge accu 23ce : 28 > plp 23cf : 6a ror a tst_ax rRORc,fRORc,0 23d0 : 08 > php ;save flags -23d1 : dd2c02 > cmp rRORc,x ;test result +23d1 : dd3302 > cmp rRORc,x ;test result > trap_ne 23d4 : d0fe > bne * ;failed not equal (non zero) > @@ -9516,27 +9518,27 @@ ffff = ram_top = -1 > eor_flag 0 23d7 : 4930 > eor #0|fao ;invert expected flags + always on bits > -23d9 : dd3c02 > cmp fRORc,x ;test flags +23d9 : dd4b02 > cmp fRORc,x ;test flags > trap_ne ; 23dc : d0fe > bne * ;failed not equal (non zero) > 23de : ca dex 23df : 10e8 bpl trorc -23e1 : a203 ldx #3 +23e1 : a205 ldx #5 23e3 : trorc1 - set_ax zp1,$ff + set_ax zps,$ff > load_flag $ff 23e3 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 23e5 : 48 > pha ;use stack to load status -23e6 : b513 > lda zp1,x ;precharge accu +23e6 : b513 > lda zps,x ;precharge accu 23e8 : 28 > plp 23e9 : 6a ror a tst_ax rRORc,fRORc,$ff-fnzc 23ea : 08 > php ;save flags -23eb : dd2c02 > cmp rRORc,x ;test result +23eb : dd3302 > cmp rRORc,x ;test result > trap_ne 23ee : d0fe > bne * ;failed not equal (non zero) > @@ -9544,7 +9546,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 23f1 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -23f3 : dd3c02 > cmp fRORc,x ;test flags +23f3 : dd4b02 > cmp fRORc,x ;test flags > trap_ne ; 23f6 : d0fe > bne * ;failed not equal (non zero) > @@ -9564,14 +9566,14 @@ ffff = ram_top = -1 ; shifts - zeropage -2407 : a203 ldx #3 +2407 : a205 ldx #5 2409 : tasl2 - set_z zp1,0 + set_z zps,0 > load_flag 0 2409 : a900 > lda #0 ;allow test to change I-flag (no mask) > 240b : 48 > pha ;use stack to load status -240c : b513 > lda zp1,x ;load to zeropage +240c : b513 > lda zps,x ;load to zeropage 240e : 850c > sta zpt 2410 : 28 > plp @@ -9579,7 +9581,7 @@ ffff = ram_top = -1 tst_z rASL,fASL,0 2413 : 08 > php ;save flags 2414 : a50c > lda zpt -2416 : dd2002 > cmp rASL,x ;test result +2416 : dd2102 > cmp rASL,x ;test result > trap_ne 2419 : d0fe > bne * ;failed not equal (non zero) > @@ -9587,21 +9589,21 @@ ffff = ram_top = -1 > eor_flag 0 241c : 4930 > eor #0|fao ;invert expected flags + always on bits > -241e : dd3002 > cmp fASL,x ;test flags +241e : dd3902 > cmp fASL,x ;test flags > trap_ne 2421 : d0fe > bne * ;failed not equal (non zero) > 2423 : ca dex 2424 : 10e3 bpl tasl2 -2426 : a203 ldx #3 +2426 : a205 ldx #5 2428 : tasl3 - set_z zp1,$ff + set_z zps,$ff > load_flag $ff 2428 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 242a : 48 > pha ;use stack to load status -242b : b513 > lda zp1,x ;load to zeropage +242b : b513 > lda zps,x ;load to zeropage 242d : 850c > sta zpt 242f : 28 > plp @@ -9609,7 +9611,7 @@ ffff = ram_top = -1 tst_z rASL,fASL,$ff-fnzc 2432 : 08 > php ;save flags 2433 : a50c > lda zpt -2435 : dd2002 > cmp rASL,x ;test result +2435 : dd2102 > cmp rASL,x ;test result > trap_ne 2438 : d0fe > bne * ;failed not equal (non zero) > @@ -9617,7 +9619,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 243b : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -243d : dd3002 > cmp fASL,x ;test flags +243d : dd3902 > cmp fASL,x ;test flags > trap_ne 2440 : d0fe > bne * ;failed not equal (non zero) > @@ -9625,14 +9627,14 @@ ffff = ram_top = -1 2442 : ca dex 2443 : 10e3 bpl tasl3 -2445 : a203 ldx #3 +2445 : a205 ldx #5 2447 : tlsr2 - set_z zp1,0 + set_z zps,0 > load_flag 0 2447 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2449 : 48 > pha ;use stack to load status -244a : b513 > lda zp1,x ;load to zeropage +244a : b513 > lda zps,x ;load to zeropage 244c : 850c > sta zpt 244e : 28 > plp @@ -9640,7 +9642,7 @@ ffff = ram_top = -1 tst_z rLSR,fLSR,0 2451 : 08 > php ;save flags 2452 : a50c > lda zpt -2454 : dd2802 > cmp rLSR,x ;test result +2454 : dd2d02 > cmp rLSR,x ;test result > trap_ne 2457 : d0fe > bne * ;failed not equal (non zero) > @@ -9648,21 +9650,21 @@ ffff = ram_top = -1 > eor_flag 0 245a : 4930 > eor #0|fao ;invert expected flags + always on bits > -245c : dd3802 > cmp fLSR,x ;test flags +245c : dd4502 > cmp fLSR,x ;test flags > trap_ne 245f : d0fe > bne * ;failed not equal (non zero) > 2461 : ca dex 2462 : 10e3 bpl tlsr2 -2464 : a203 ldx #3 +2464 : a205 ldx #5 2466 : tlsr3 - set_z zp1,$ff + set_z zps,$ff > load_flag $ff 2466 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2468 : 48 > pha ;use stack to load status -2469 : b513 > lda zp1,x ;load to zeropage +2469 : b513 > lda zps,x ;load to zeropage 246b : 850c > sta zpt 246d : 28 > plp @@ -9670,7 +9672,7 @@ ffff = ram_top = -1 tst_z rLSR,fLSR,$ff-fnzc 2470 : 08 > php ;save flags 2471 : a50c > lda zpt -2473 : dd2802 > cmp rLSR,x ;test result +2473 : dd2d02 > cmp rLSR,x ;test result > trap_ne 2476 : d0fe > bne * ;failed not equal (non zero) > @@ -9678,7 +9680,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2479 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -247b : dd3802 > cmp fLSR,x ;test flags +247b : dd4502 > cmp fLSR,x ;test flags > trap_ne 247e : d0fe > bne * ;failed not equal (non zero) > @@ -9686,14 +9688,14 @@ ffff = ram_top = -1 2480 : ca dex 2481 : 10e3 bpl tlsr3 -2483 : a203 ldx #3 +2483 : a205 ldx #5 2485 : trol2 - set_z zp1,0 + set_z zps,0 > load_flag 0 2485 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2487 : 48 > pha ;use stack to load status -2488 : b513 > lda zp1,x ;load to zeropage +2488 : b513 > lda zps,x ;load to zeropage 248a : 850c > sta zpt 248c : 28 > plp @@ -9701,7 +9703,7 @@ ffff = ram_top = -1 tst_z rROL,fROL,0 248f : 08 > php ;save flags 2490 : a50c > lda zpt -2492 : dd2002 > cmp rROL,x ;test result +2492 : dd2102 > cmp rROL,x ;test result > trap_ne 2495 : d0fe > bne * ;failed not equal (non zero) > @@ -9709,21 +9711,21 @@ ffff = ram_top = -1 > eor_flag 0 2498 : 4930 > eor #0|fao ;invert expected flags + always on bits > -249a : dd3002 > cmp fROL,x ;test flags +249a : dd3902 > cmp fROL,x ;test flags > trap_ne 249d : d0fe > bne * ;failed not equal (non zero) > 249f : ca dex 24a0 : 10e3 bpl trol2 -24a2 : a203 ldx #3 +24a2 : a205 ldx #5 24a4 : trol3 - set_z zp1,$ff-fc + set_z zps,$ff-fc > load_flag $ff-fc 24a4 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 24a6 : 48 > pha ;use stack to load status -24a7 : b513 > lda zp1,x ;load to zeropage +24a7 : b513 > lda zps,x ;load to zeropage 24a9 : 850c > sta zpt 24ab : 28 > plp @@ -9731,7 +9733,7 @@ ffff = ram_top = -1 tst_z rROL,fROL,$ff-fnzc 24ae : 08 > php ;save flags 24af : a50c > lda zpt -24b1 : dd2002 > cmp rROL,x ;test result +24b1 : dd2102 > cmp rROL,x ;test result > trap_ne 24b4 : d0fe > bne * ;failed not equal (non zero) > @@ -9739,7 +9741,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 24b7 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -24b9 : dd3002 > cmp fROL,x ;test flags +24b9 : dd3902 > cmp fROL,x ;test flags > trap_ne 24bc : d0fe > bne * ;failed not equal (non zero) > @@ -9747,14 +9749,14 @@ ffff = ram_top = -1 24be : ca dex 24bf : 10e3 bpl trol3 -24c1 : a203 ldx #3 +24c1 : a205 ldx #5 24c3 : trolc2 - set_z zp1,fc + set_z zps,fc > load_flag fc 24c3 : a901 > lda #fc ;allow test to change I-flag (no mask) > 24c5 : 48 > pha ;use stack to load status -24c6 : b513 > lda zp1,x ;load to zeropage +24c6 : b513 > lda zps,x ;load to zeropage 24c8 : 850c > sta zpt 24ca : 28 > plp @@ -9762,7 +9764,7 @@ ffff = ram_top = -1 tst_z rROLc,fROLc,0 24cd : 08 > php ;save flags 24ce : a50c > lda zpt -24d0 : dd2402 > cmp rROLc,x ;test result +24d0 : dd2702 > cmp rROLc,x ;test result > trap_ne 24d3 : d0fe > bne * ;failed not equal (non zero) > @@ -9770,21 +9772,21 @@ ffff = ram_top = -1 > eor_flag 0 24d6 : 4930 > eor #0|fao ;invert expected flags + always on bits > -24d8 : dd3402 > cmp fROLc,x ;test flags +24d8 : dd3f02 > cmp fROLc,x ;test flags > trap_ne 24db : d0fe > bne * ;failed not equal (non zero) > 24dd : ca dex 24de : 10e3 bpl trolc2 -24e0 : a203 ldx #3 +24e0 : a205 ldx #5 24e2 : trolc3 - set_z zp1,$ff + set_z zps,$ff > load_flag $ff 24e2 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 24e4 : 48 > pha ;use stack to load status -24e5 : b513 > lda zp1,x ;load to zeropage +24e5 : b513 > lda zps,x ;load to zeropage 24e7 : 850c > sta zpt 24e9 : 28 > plp @@ -9792,7 +9794,7 @@ ffff = ram_top = -1 tst_z rROLc,fROLc,$ff-fnzc 24ec : 08 > php ;save flags 24ed : a50c > lda zpt -24ef : dd2402 > cmp rROLc,x ;test result +24ef : dd2702 > cmp rROLc,x ;test result > trap_ne 24f2 : d0fe > bne * ;failed not equal (non zero) > @@ -9800,7 +9802,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 24f5 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -24f7 : dd3402 > cmp fROLc,x ;test flags +24f7 : dd3f02 > cmp fROLc,x ;test flags > trap_ne 24fa : d0fe > bne * ;failed not equal (non zero) > @@ -9808,14 +9810,14 @@ ffff = ram_top = -1 24fc : ca dex 24fd : 10e3 bpl trolc3 -24ff : a203 ldx #3 +24ff : a205 ldx #5 2501 : tror2 - set_z zp1,0 + set_z zps,0 > load_flag 0 2501 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2503 : 48 > pha ;use stack to load status -2504 : b513 > lda zp1,x ;load to zeropage +2504 : b513 > lda zps,x ;load to zeropage 2506 : 850c > sta zpt 2508 : 28 > plp @@ -9823,7 +9825,7 @@ ffff = ram_top = -1 tst_z rROR,fROR,0 250b : 08 > php ;save flags 250c : a50c > lda zpt -250e : dd2802 > cmp rROR,x ;test result +250e : dd2d02 > cmp rROR,x ;test result > trap_ne 2511 : d0fe > bne * ;failed not equal (non zero) > @@ -9831,21 +9833,21 @@ ffff = ram_top = -1 > eor_flag 0 2514 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2516 : dd3802 > cmp fROR,x ;test flags +2516 : dd4502 > cmp fROR,x ;test flags > trap_ne 2519 : d0fe > bne * ;failed not equal (non zero) > 251b : ca dex 251c : 10e3 bpl tror2 -251e : a203 ldx #3 +251e : a205 ldx #5 2520 : tror3 - set_z zp1,$ff-fc + set_z zps,$ff-fc > load_flag $ff-fc 2520 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 2522 : 48 > pha ;use stack to load status -2523 : b513 > lda zp1,x ;load to zeropage +2523 : b513 > lda zps,x ;load to zeropage 2525 : 850c > sta zpt 2527 : 28 > plp @@ -9853,7 +9855,7 @@ ffff = ram_top = -1 tst_z rROR,fROR,$ff-fnzc 252a : 08 > php ;save flags 252b : a50c > lda zpt -252d : dd2802 > cmp rROR,x ;test result +252d : dd2d02 > cmp rROR,x ;test result > trap_ne 2530 : d0fe > bne * ;failed not equal (non zero) > @@ -9861,7 +9863,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2533 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2535 : dd3802 > cmp fROR,x ;test flags +2535 : dd4502 > cmp fROR,x ;test flags > trap_ne 2538 : d0fe > bne * ;failed not equal (non zero) > @@ -9869,14 +9871,14 @@ ffff = ram_top = -1 253a : ca dex 253b : 10e3 bpl tror3 -253d : a203 ldx #3 +253d : a205 ldx #5 253f : trorc2 - set_z zp1,fc + set_z zps,fc > load_flag fc 253f : a901 > lda #fc ;allow test to change I-flag (no mask) > 2541 : 48 > pha ;use stack to load status -2542 : b513 > lda zp1,x ;load to zeropage +2542 : b513 > lda zps,x ;load to zeropage 2544 : 850c > sta zpt 2546 : 28 > plp @@ -9884,7 +9886,7 @@ ffff = ram_top = -1 tst_z rRORc,fRORc,0 2549 : 08 > php ;save flags 254a : a50c > lda zpt -254c : dd2c02 > cmp rRORc,x ;test result +254c : dd3302 > cmp rRORc,x ;test result > trap_ne 254f : d0fe > bne * ;failed not equal (non zero) > @@ -9892,21 +9894,21 @@ ffff = ram_top = -1 > eor_flag 0 2552 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2554 : dd3c02 > cmp fRORc,x ;test flags +2554 : dd4b02 > cmp fRORc,x ;test flags > trap_ne 2557 : d0fe > bne * ;failed not equal (non zero) > 2559 : ca dex 255a : 10e3 bpl trorc2 -255c : a203 ldx #3 +255c : a205 ldx #5 255e : trorc3 - set_z zp1,$ff + set_z zps,$ff > load_flag $ff 255e : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2560 : 48 > pha ;use stack to load status -2561 : b513 > lda zp1,x ;load to zeropage +2561 : b513 > lda zps,x ;load to zeropage 2563 : 850c > sta zpt 2565 : 28 > plp @@ -9914,7 +9916,7 @@ ffff = ram_top = -1 tst_z rRORc,fRORc,$ff-fnzc 2568 : 08 > php ;save flags 2569 : a50c > lda zpt -256b : dd2c02 > cmp rRORc,x ;test result +256b : dd3302 > cmp rRORc,x ;test result > trap_ne 256e : d0fe > bne * ;failed not equal (non zero) > @@ -9922,7 +9924,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2571 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2573 : dd3c02 > cmp fRORc,x ;test flags +2573 : dd4b02 > cmp fRORc,x ;test flags > trap_ne 2576 : d0fe > bne * ;failed not equal (non zero) > @@ -9942,14 +9944,14 @@ ffff = ram_top = -1 ; shifts - absolute -2587 : a203 ldx #3 +2587 : a205 ldx #5 2589 : tasl4 - set_abs zp1,0 + set_abs zps,0 > load_flag 0 2589 : a900 > lda #0 ;allow test to change I-flag (no mask) > 258b : 48 > pha ;use stack to load status -258c : b513 > lda zp1,x ;load to memory +258c : b513 > lda zps,x ;load to memory 258e : 8d0302 > sta abst 2591 : 28 > plp @@ -9957,7 +9959,7 @@ ffff = ram_top = -1 tst_abs rASL,fASL,0 2595 : 08 > php ;save flags 2596 : ad0302 > lda abst -2599 : dd2002 > cmp rASL,x ;test result +2599 : dd2102 > cmp rASL,x ;test result > trap_ne 259c : d0fe > bne * ;failed not equal (non zero) > @@ -9965,21 +9967,21 @@ ffff = ram_top = -1 > eor_flag 0 259f : 4930 > eor #0|fao ;invert expected flags + always on bits > -25a1 : dd3002 > cmp fASL,x ;test flags +25a1 : dd3902 > cmp fASL,x ;test flags > trap_ne 25a4 : d0fe > bne * ;failed not equal (non zero) > 25a6 : ca dex 25a7 : 10e0 bpl tasl4 -25a9 : a203 ldx #3 +25a9 : a205 ldx #5 25ab : tasl5 - set_abs zp1,$ff + set_abs zps,$ff > load_flag $ff 25ab : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 25ad : 48 > pha ;use stack to load status -25ae : b513 > lda zp1,x ;load to memory +25ae : b513 > lda zps,x ;load to memory 25b0 : 8d0302 > sta abst 25b3 : 28 > plp @@ -9987,7 +9989,7 @@ ffff = ram_top = -1 tst_abs rASL,fASL,$ff-fnzc 25b7 : 08 > php ;save flags 25b8 : ad0302 > lda abst -25bb : dd2002 > cmp rASL,x ;test result +25bb : dd2102 > cmp rASL,x ;test result > trap_ne 25be : d0fe > bne * ;failed not equal (non zero) > @@ -9995,7 +9997,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 25c1 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -25c3 : dd3002 > cmp fASL,x ;test flags +25c3 : dd3902 > cmp fASL,x ;test flags > trap_ne 25c6 : d0fe > bne * ;failed not equal (non zero) > @@ -10003,14 +10005,14 @@ ffff = ram_top = -1 25c8 : ca dex 25c9 : 10e0 bpl tasl5 -25cb : a203 ldx #3 +25cb : a205 ldx #5 25cd : tlsr4 - set_abs zp1,0 + set_abs zps,0 > load_flag 0 25cd : a900 > lda #0 ;allow test to change I-flag (no mask) > 25cf : 48 > pha ;use stack to load status -25d0 : b513 > lda zp1,x ;load to memory +25d0 : b513 > lda zps,x ;load to memory 25d2 : 8d0302 > sta abst 25d5 : 28 > plp @@ -10018,7 +10020,7 @@ ffff = ram_top = -1 tst_abs rLSR,fLSR,0 25d9 : 08 > php ;save flags 25da : ad0302 > lda abst -25dd : dd2802 > cmp rLSR,x ;test result +25dd : dd2d02 > cmp rLSR,x ;test result > trap_ne 25e0 : d0fe > bne * ;failed not equal (non zero) > @@ -10026,21 +10028,21 @@ ffff = ram_top = -1 > eor_flag 0 25e3 : 4930 > eor #0|fao ;invert expected flags + always on bits > -25e5 : dd3802 > cmp fLSR,x ;test flags +25e5 : dd4502 > cmp fLSR,x ;test flags > trap_ne 25e8 : d0fe > bne * ;failed not equal (non zero) > 25ea : ca dex 25eb : 10e0 bpl tlsr4 -25ed : a203 ldx #3 +25ed : a205 ldx #5 25ef : tlsr5 - set_abs zp1,$ff + set_abs zps,$ff > load_flag $ff 25ef : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 25f1 : 48 > pha ;use stack to load status -25f2 : b513 > lda zp1,x ;load to memory +25f2 : b513 > lda zps,x ;load to memory 25f4 : 8d0302 > sta abst 25f7 : 28 > plp @@ -10048,7 +10050,7 @@ ffff = ram_top = -1 tst_abs rLSR,fLSR,$ff-fnzc 25fb : 08 > php ;save flags 25fc : ad0302 > lda abst -25ff : dd2802 > cmp rLSR,x ;test result +25ff : dd2d02 > cmp rLSR,x ;test result > trap_ne 2602 : d0fe > bne * ;failed not equal (non zero) > @@ -10056,7 +10058,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2605 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2607 : dd3802 > cmp fLSR,x ;test flags +2607 : dd4502 > cmp fLSR,x ;test flags > trap_ne 260a : d0fe > bne * ;failed not equal (non zero) > @@ -10064,14 +10066,14 @@ ffff = ram_top = -1 260c : ca dex 260d : 10e0 bpl tlsr5 -260f : a203 ldx #3 +260f : a205 ldx #5 2611 : trol4 - set_abs zp1,0 + set_abs zps,0 > load_flag 0 2611 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2613 : 48 > pha ;use stack to load status -2614 : b513 > lda zp1,x ;load to memory +2614 : b513 > lda zps,x ;load to memory 2616 : 8d0302 > sta abst 2619 : 28 > plp @@ -10079,7 +10081,7 @@ ffff = ram_top = -1 tst_abs rROL,fROL,0 261d : 08 > php ;save flags 261e : ad0302 > lda abst -2621 : dd2002 > cmp rROL,x ;test result +2621 : dd2102 > cmp rROL,x ;test result > trap_ne 2624 : d0fe > bne * ;failed not equal (non zero) > @@ -10087,21 +10089,21 @@ ffff = ram_top = -1 > eor_flag 0 2627 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2629 : dd3002 > cmp fROL,x ;test flags +2629 : dd3902 > cmp fROL,x ;test flags > trap_ne 262c : d0fe > bne * ;failed not equal (non zero) > 262e : ca dex 262f : 10e0 bpl trol4 -2631 : a203 ldx #3 +2631 : a205 ldx #5 2633 : trol5 - set_abs zp1,$ff-fc + set_abs zps,$ff-fc > load_flag $ff-fc 2633 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 2635 : 48 > pha ;use stack to load status -2636 : b513 > lda zp1,x ;load to memory +2636 : b513 > lda zps,x ;load to memory 2638 : 8d0302 > sta abst 263b : 28 > plp @@ -10109,7 +10111,7 @@ ffff = ram_top = -1 tst_abs rROL,fROL,$ff-fnzc 263f : 08 > php ;save flags 2640 : ad0302 > lda abst -2643 : dd2002 > cmp rROL,x ;test result +2643 : dd2102 > cmp rROL,x ;test result > trap_ne 2646 : d0fe > bne * ;failed not equal (non zero) > @@ -10117,7 +10119,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2649 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -264b : dd3002 > cmp fROL,x ;test flags +264b : dd3902 > cmp fROL,x ;test flags > trap_ne 264e : d0fe > bne * ;failed not equal (non zero) > @@ -10125,14 +10127,14 @@ ffff = ram_top = -1 2650 : ca dex 2651 : 10e0 bpl trol5 -2653 : a203 ldx #3 +2653 : a205 ldx #5 2655 : trolc4 - set_abs zp1,fc + set_abs zps,fc > load_flag fc 2655 : a901 > lda #fc ;allow test to change I-flag (no mask) > 2657 : 48 > pha ;use stack to load status -2658 : b513 > lda zp1,x ;load to memory +2658 : b513 > lda zps,x ;load to memory 265a : 8d0302 > sta abst 265d : 28 > plp @@ -10140,7 +10142,7 @@ ffff = ram_top = -1 tst_abs rROLc,fROLc,0 2661 : 08 > php ;save flags 2662 : ad0302 > lda abst -2665 : dd2402 > cmp rROLc,x ;test result +2665 : dd2702 > cmp rROLc,x ;test result > trap_ne 2668 : d0fe > bne * ;failed not equal (non zero) > @@ -10148,21 +10150,21 @@ ffff = ram_top = -1 > eor_flag 0 266b : 4930 > eor #0|fao ;invert expected flags + always on bits > -266d : dd3402 > cmp fROLc,x ;test flags +266d : dd3f02 > cmp fROLc,x ;test flags > trap_ne 2670 : d0fe > bne * ;failed not equal (non zero) > 2672 : ca dex 2673 : 10e0 bpl trolc4 -2675 : a203 ldx #3 +2675 : a205 ldx #5 2677 : trolc5 - set_abs zp1,$ff + set_abs zps,$ff > load_flag $ff 2677 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2679 : 48 > pha ;use stack to load status -267a : b513 > lda zp1,x ;load to memory +267a : b513 > lda zps,x ;load to memory 267c : 8d0302 > sta abst 267f : 28 > plp @@ -10170,7 +10172,7 @@ ffff = ram_top = -1 tst_abs rROLc,fROLc,$ff-fnzc 2683 : 08 > php ;save flags 2684 : ad0302 > lda abst -2687 : dd2402 > cmp rROLc,x ;test result +2687 : dd2702 > cmp rROLc,x ;test result > trap_ne 268a : d0fe > bne * ;failed not equal (non zero) > @@ -10178,7 +10180,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 268d : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -268f : dd3402 > cmp fROLc,x ;test flags +268f : dd3f02 > cmp fROLc,x ;test flags > trap_ne 2692 : d0fe > bne * ;failed not equal (non zero) > @@ -10186,14 +10188,14 @@ ffff = ram_top = -1 2694 : ca dex 2695 : 10e0 bpl trolc5 -2697 : a203 ldx #3 +2697 : a205 ldx #5 2699 : tror4 - set_abs zp1,0 + set_abs zps,0 > load_flag 0 2699 : a900 > lda #0 ;allow test to change I-flag (no mask) > 269b : 48 > pha ;use stack to load status -269c : b513 > lda zp1,x ;load to memory +269c : b513 > lda zps,x ;load to memory 269e : 8d0302 > sta abst 26a1 : 28 > plp @@ -10201,7 +10203,7 @@ ffff = ram_top = -1 tst_abs rROR,fROR,0 26a5 : 08 > php ;save flags 26a6 : ad0302 > lda abst -26a9 : dd2802 > cmp rROR,x ;test result +26a9 : dd2d02 > cmp rROR,x ;test result > trap_ne 26ac : d0fe > bne * ;failed not equal (non zero) > @@ -10209,21 +10211,21 @@ ffff = ram_top = -1 > eor_flag 0 26af : 4930 > eor #0|fao ;invert expected flags + always on bits > -26b1 : dd3802 > cmp fROR,x ;test flags +26b1 : dd4502 > cmp fROR,x ;test flags > trap_ne 26b4 : d0fe > bne * ;failed not equal (non zero) > 26b6 : ca dex 26b7 : 10e0 bpl tror4 -26b9 : a203 ldx #3 +26b9 : a205 ldx #5 26bb : tror5 - set_abs zp1,$ff-fc + set_abs zps,$ff-fc > load_flag $ff-fc 26bb : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 26bd : 48 > pha ;use stack to load status -26be : b513 > lda zp1,x ;load to memory +26be : b513 > lda zps,x ;load to memory 26c0 : 8d0302 > sta abst 26c3 : 28 > plp @@ -10231,7 +10233,7 @@ ffff = ram_top = -1 tst_abs rROR,fROR,$ff-fnzc 26c7 : 08 > php ;save flags 26c8 : ad0302 > lda abst -26cb : dd2802 > cmp rROR,x ;test result +26cb : dd2d02 > cmp rROR,x ;test result > trap_ne 26ce : d0fe > bne * ;failed not equal (non zero) > @@ -10239,7 +10241,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 26d1 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -26d3 : dd3802 > cmp fROR,x ;test flags +26d3 : dd4502 > cmp fROR,x ;test flags > trap_ne 26d6 : d0fe > bne * ;failed not equal (non zero) > @@ -10247,14 +10249,14 @@ ffff = ram_top = -1 26d8 : ca dex 26d9 : 10e0 bpl tror5 -26db : a203 ldx #3 +26db : a205 ldx #5 26dd : trorc4 - set_abs zp1,fc + set_abs zps,fc > load_flag fc 26dd : a901 > lda #fc ;allow test to change I-flag (no mask) > 26df : 48 > pha ;use stack to load status -26e0 : b513 > lda zp1,x ;load to memory +26e0 : b513 > lda zps,x ;load to memory 26e2 : 8d0302 > sta abst 26e5 : 28 > plp @@ -10262,7 +10264,7 @@ ffff = ram_top = -1 tst_abs rRORc,fRORc,0 26e9 : 08 > php ;save flags 26ea : ad0302 > lda abst -26ed : dd2c02 > cmp rRORc,x ;test result +26ed : dd3302 > cmp rRORc,x ;test result > trap_ne 26f0 : d0fe > bne * ;failed not equal (non zero) > @@ -10270,21 +10272,21 @@ ffff = ram_top = -1 > eor_flag 0 26f3 : 4930 > eor #0|fao ;invert expected flags + always on bits > -26f5 : dd3c02 > cmp fRORc,x ;test flags +26f5 : dd4b02 > cmp fRORc,x ;test flags > trap_ne 26f8 : d0fe > bne * ;failed not equal (non zero) > 26fa : ca dex 26fb : 10e0 bpl trorc4 -26fd : a203 ldx #3 +26fd : a205 ldx #5 26ff : trorc5 - set_abs zp1,$ff + set_abs zps,$ff > load_flag $ff 26ff : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2701 : 48 > pha ;use stack to load status -2702 : b513 > lda zp1,x ;load to memory +2702 : b513 > lda zps,x ;load to memory 2704 : 8d0302 > sta abst 2707 : 28 > plp @@ -10292,7 +10294,7 @@ ffff = ram_top = -1 tst_abs rRORc,fRORc,$ff-fnzc 270b : 08 > php ;save flags 270c : ad0302 > lda abst -270f : dd2c02 > cmp rRORc,x ;test result +270f : dd3302 > cmp rRORc,x ;test result > trap_ne 2712 : d0fe > bne * ;failed not equal (non zero) > @@ -10300,7 +10302,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2715 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2717 : dd3c02 > cmp fRORc,x ;test flags +2717 : dd4b02 > cmp fRORc,x ;test flags > trap_ne 271a : d0fe > bne * ;failed not equal (non zero) > @@ -10320,14 +10322,14 @@ ffff = ram_top = -1 ; shifts - zp indexed -272b : a203 ldx #3 +272b : a205 ldx #5 272d : tasl6 - set_zx zp1,0 + set_zx zps,0 > load_flag 0 272d : a900 > lda #0 ;allow test to change I-flag (no mask) > 272f : 48 > pha ;use stack to load status -2730 : b513 > lda zp1,x ;load to indexed zeropage +2730 : b513 > lda zps,x ;load to indexed zeropage 2732 : 950c > sta zpt,x 2734 : 28 > plp @@ -10335,7 +10337,7 @@ ffff = ram_top = -1 tst_zx rASL,fASL,0 2737 : 08 > php ;save flags 2738 : b50c > lda zpt,x -273a : dd2002 > cmp rASL,x ;test result +273a : dd2102 > cmp rASL,x ;test result > trap_ne 273d : d0fe > bne * ;failed not equal (non zero) > @@ -10343,21 +10345,21 @@ ffff = ram_top = -1 > eor_flag 0 2740 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2742 : dd3002 > cmp fASL,x ;test flags +2742 : dd3902 > cmp fASL,x ;test flags > trap_ne 2745 : d0fe > bne * ;failed not equal (non zero) > 2747 : ca dex 2748 : 10e3 bpl tasl6 -274a : a203 ldx #3 +274a : a205 ldx #5 274c : tasl7 - set_zx zp1,$ff + set_zx zps,$ff > load_flag $ff 274c : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 274e : 48 > pha ;use stack to load status -274f : b513 > lda zp1,x ;load to indexed zeropage +274f : b513 > lda zps,x ;load to indexed zeropage 2751 : 950c > sta zpt,x 2753 : 28 > plp @@ -10365,7 +10367,7 @@ ffff = ram_top = -1 tst_zx rASL,fASL,$ff-fnzc 2756 : 08 > php ;save flags 2757 : b50c > lda zpt,x -2759 : dd2002 > cmp rASL,x ;test result +2759 : dd2102 > cmp rASL,x ;test result > trap_ne 275c : d0fe > bne * ;failed not equal (non zero) > @@ -10373,7 +10375,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 275f : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2761 : dd3002 > cmp fASL,x ;test flags +2761 : dd3902 > cmp fASL,x ;test flags > trap_ne 2764 : d0fe > bne * ;failed not equal (non zero) > @@ -10381,14 +10383,14 @@ ffff = ram_top = -1 2766 : ca dex 2767 : 10e3 bpl tasl7 -2769 : a203 ldx #3 +2769 : a205 ldx #5 276b : tlsr6 - set_zx zp1,0 + set_zx zps,0 > load_flag 0 276b : a900 > lda #0 ;allow test to change I-flag (no mask) > 276d : 48 > pha ;use stack to load status -276e : b513 > lda zp1,x ;load to indexed zeropage +276e : b513 > lda zps,x ;load to indexed zeropage 2770 : 950c > sta zpt,x 2772 : 28 > plp @@ -10396,7 +10398,7 @@ ffff = ram_top = -1 tst_zx rLSR,fLSR,0 2775 : 08 > php ;save flags 2776 : b50c > lda zpt,x -2778 : dd2802 > cmp rLSR,x ;test result +2778 : dd2d02 > cmp rLSR,x ;test result > trap_ne 277b : d0fe > bne * ;failed not equal (non zero) > @@ -10404,21 +10406,21 @@ ffff = ram_top = -1 > eor_flag 0 277e : 4930 > eor #0|fao ;invert expected flags + always on bits > -2780 : dd3802 > cmp fLSR,x ;test flags +2780 : dd4502 > cmp fLSR,x ;test flags > trap_ne 2783 : d0fe > bne * ;failed not equal (non zero) > 2785 : ca dex 2786 : 10e3 bpl tlsr6 -2788 : a203 ldx #3 +2788 : a205 ldx #5 278a : tlsr7 - set_zx zp1,$ff + set_zx zps,$ff > load_flag $ff 278a : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 278c : 48 > pha ;use stack to load status -278d : b513 > lda zp1,x ;load to indexed zeropage +278d : b513 > lda zps,x ;load to indexed zeropage 278f : 950c > sta zpt,x 2791 : 28 > plp @@ -10426,7 +10428,7 @@ ffff = ram_top = -1 tst_zx rLSR,fLSR,$ff-fnzc 2794 : 08 > php ;save flags 2795 : b50c > lda zpt,x -2797 : dd2802 > cmp rLSR,x ;test result +2797 : dd2d02 > cmp rLSR,x ;test result > trap_ne 279a : d0fe > bne * ;failed not equal (non zero) > @@ -10434,7 +10436,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 279d : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -279f : dd3802 > cmp fLSR,x ;test flags +279f : dd4502 > cmp fLSR,x ;test flags > trap_ne 27a2 : d0fe > bne * ;failed not equal (non zero) > @@ -10442,14 +10444,14 @@ ffff = ram_top = -1 27a4 : ca dex 27a5 : 10e3 bpl tlsr7 -27a7 : a203 ldx #3 +27a7 : a205 ldx #5 27a9 : trol6 - set_zx zp1,0 + set_zx zps,0 > load_flag 0 27a9 : a900 > lda #0 ;allow test to change I-flag (no mask) > 27ab : 48 > pha ;use stack to load status -27ac : b513 > lda zp1,x ;load to indexed zeropage +27ac : b513 > lda zps,x ;load to indexed zeropage 27ae : 950c > sta zpt,x 27b0 : 28 > plp @@ -10457,7 +10459,7 @@ ffff = ram_top = -1 tst_zx rROL,fROL,0 27b3 : 08 > php ;save flags 27b4 : b50c > lda zpt,x -27b6 : dd2002 > cmp rROL,x ;test result +27b6 : dd2102 > cmp rROL,x ;test result > trap_ne 27b9 : d0fe > bne * ;failed not equal (non zero) > @@ -10465,21 +10467,21 @@ ffff = ram_top = -1 > eor_flag 0 27bc : 4930 > eor #0|fao ;invert expected flags + always on bits > -27be : dd3002 > cmp fROL,x ;test flags +27be : dd3902 > cmp fROL,x ;test flags > trap_ne 27c1 : d0fe > bne * ;failed not equal (non zero) > 27c3 : ca dex 27c4 : 10e3 bpl trol6 -27c6 : a203 ldx #3 +27c6 : a205 ldx #5 27c8 : trol7 - set_zx zp1,$ff-fc + set_zx zps,$ff-fc > load_flag $ff-fc 27c8 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 27ca : 48 > pha ;use stack to load status -27cb : b513 > lda zp1,x ;load to indexed zeropage +27cb : b513 > lda zps,x ;load to indexed zeropage 27cd : 950c > sta zpt,x 27cf : 28 > plp @@ -10487,7 +10489,7 @@ ffff = ram_top = -1 tst_zx rROL,fROL,$ff-fnzc 27d2 : 08 > php ;save flags 27d3 : b50c > lda zpt,x -27d5 : dd2002 > cmp rROL,x ;test result +27d5 : dd2102 > cmp rROL,x ;test result > trap_ne 27d8 : d0fe > bne * ;failed not equal (non zero) > @@ -10495,7 +10497,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 27db : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -27dd : dd3002 > cmp fROL,x ;test flags +27dd : dd3902 > cmp fROL,x ;test flags > trap_ne 27e0 : d0fe > bne * ;failed not equal (non zero) > @@ -10503,14 +10505,14 @@ ffff = ram_top = -1 27e2 : ca dex 27e3 : 10e3 bpl trol7 -27e5 : a203 ldx #3 +27e5 : a205 ldx #5 27e7 : trolc6 - set_zx zp1,fc + set_zx zps,fc > load_flag fc 27e7 : a901 > lda #fc ;allow test to change I-flag (no mask) > 27e9 : 48 > pha ;use stack to load status -27ea : b513 > lda zp1,x ;load to indexed zeropage +27ea : b513 > lda zps,x ;load to indexed zeropage 27ec : 950c > sta zpt,x 27ee : 28 > plp @@ -10518,7 +10520,7 @@ ffff = ram_top = -1 tst_zx rROLc,fROLc,0 27f1 : 08 > php ;save flags 27f2 : b50c > lda zpt,x -27f4 : dd2402 > cmp rROLc,x ;test result +27f4 : dd2702 > cmp rROLc,x ;test result > trap_ne 27f7 : d0fe > bne * ;failed not equal (non zero) > @@ -10526,21 +10528,21 @@ ffff = ram_top = -1 > eor_flag 0 27fa : 4930 > eor #0|fao ;invert expected flags + always on bits > -27fc : dd3402 > cmp fROLc,x ;test flags +27fc : dd3f02 > cmp fROLc,x ;test flags > trap_ne 27ff : d0fe > bne * ;failed not equal (non zero) > 2801 : ca dex 2802 : 10e3 bpl trolc6 -2804 : a203 ldx #3 +2804 : a205 ldx #5 2806 : trolc7 - set_zx zp1,$ff + set_zx zps,$ff > load_flag $ff 2806 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2808 : 48 > pha ;use stack to load status -2809 : b513 > lda zp1,x ;load to indexed zeropage +2809 : b513 > lda zps,x ;load to indexed zeropage 280b : 950c > sta zpt,x 280d : 28 > plp @@ -10548,7 +10550,7 @@ ffff = ram_top = -1 tst_zx rROLc,fROLc,$ff-fnzc 2810 : 08 > php ;save flags 2811 : b50c > lda zpt,x -2813 : dd2402 > cmp rROLc,x ;test result +2813 : dd2702 > cmp rROLc,x ;test result > trap_ne 2816 : d0fe > bne * ;failed not equal (non zero) > @@ -10556,7 +10558,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2819 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -281b : dd3402 > cmp fROLc,x ;test flags +281b : dd3f02 > cmp fROLc,x ;test flags > trap_ne 281e : d0fe > bne * ;failed not equal (non zero) > @@ -10564,14 +10566,14 @@ ffff = ram_top = -1 2820 : ca dex 2821 : 10e3 bpl trolc7 -2823 : a203 ldx #3 +2823 : a205 ldx #5 2825 : tror6 - set_zx zp1,0 + set_zx zps,0 > load_flag 0 2825 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2827 : 48 > pha ;use stack to load status -2828 : b513 > lda zp1,x ;load to indexed zeropage +2828 : b513 > lda zps,x ;load to indexed zeropage 282a : 950c > sta zpt,x 282c : 28 > plp @@ -10579,7 +10581,7 @@ ffff = ram_top = -1 tst_zx rROR,fROR,0 282f : 08 > php ;save flags 2830 : b50c > lda zpt,x -2832 : dd2802 > cmp rROR,x ;test result +2832 : dd2d02 > cmp rROR,x ;test result > trap_ne 2835 : d0fe > bne * ;failed not equal (non zero) > @@ -10587,21 +10589,21 @@ ffff = ram_top = -1 > eor_flag 0 2838 : 4930 > eor #0|fao ;invert expected flags + always on bits > -283a : dd3802 > cmp fROR,x ;test flags +283a : dd4502 > cmp fROR,x ;test flags > trap_ne 283d : d0fe > bne * ;failed not equal (non zero) > 283f : ca dex 2840 : 10e3 bpl tror6 -2842 : a203 ldx #3 +2842 : a205 ldx #5 2844 : tror7 - set_zx zp1,$ff-fc + set_zx zps,$ff-fc > load_flag $ff-fc 2844 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 2846 : 48 > pha ;use stack to load status -2847 : b513 > lda zp1,x ;load to indexed zeropage +2847 : b513 > lda zps,x ;load to indexed zeropage 2849 : 950c > sta zpt,x 284b : 28 > plp @@ -10609,7 +10611,7 @@ ffff = ram_top = -1 tst_zx rROR,fROR,$ff-fnzc 284e : 08 > php ;save flags 284f : b50c > lda zpt,x -2851 : dd2802 > cmp rROR,x ;test result +2851 : dd2d02 > cmp rROR,x ;test result > trap_ne 2854 : d0fe > bne * ;failed not equal (non zero) > @@ -10617,7 +10619,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2857 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2859 : dd3802 > cmp fROR,x ;test flags +2859 : dd4502 > cmp fROR,x ;test flags > trap_ne 285c : d0fe > bne * ;failed not equal (non zero) > @@ -10625,14 +10627,14 @@ ffff = ram_top = -1 285e : ca dex 285f : 10e3 bpl tror7 -2861 : a203 ldx #3 +2861 : a205 ldx #5 2863 : trorc6 - set_zx zp1,fc + set_zx zps,fc > load_flag fc 2863 : a901 > lda #fc ;allow test to change I-flag (no mask) > 2865 : 48 > pha ;use stack to load status -2866 : b513 > lda zp1,x ;load to indexed zeropage +2866 : b513 > lda zps,x ;load to indexed zeropage 2868 : 950c > sta zpt,x 286a : 28 > plp @@ -10640,7 +10642,7 @@ ffff = ram_top = -1 tst_zx rRORc,fRORc,0 286d : 08 > php ;save flags 286e : b50c > lda zpt,x -2870 : dd2c02 > cmp rRORc,x ;test result +2870 : dd3302 > cmp rRORc,x ;test result > trap_ne 2873 : d0fe > bne * ;failed not equal (non zero) > @@ -10648,21 +10650,21 @@ ffff = ram_top = -1 > eor_flag 0 2876 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2878 : dd3c02 > cmp fRORc,x ;test flags +2878 : dd4b02 > cmp fRORc,x ;test flags > trap_ne 287b : d0fe > bne * ;failed not equal (non zero) > 287d : ca dex 287e : 10e3 bpl trorc6 -2880 : a203 ldx #3 +2880 : a205 ldx #5 2882 : trorc7 - set_zx zp1,$ff + set_zx zps,$ff > load_flag $ff 2882 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2884 : 48 > pha ;use stack to load status -2885 : b513 > lda zp1,x ;load to indexed zeropage +2885 : b513 > lda zps,x ;load to indexed zeropage 2887 : 950c > sta zpt,x 2889 : 28 > plp @@ -10670,7 +10672,7 @@ ffff = ram_top = -1 tst_zx rRORc,fRORc,$ff-fnzc 288c : 08 > php ;save flags 288d : b50c > lda zpt,x -288f : dd2c02 > cmp rRORc,x ;test result +288f : dd3302 > cmp rRORc,x ;test result > trap_ne 2892 : d0fe > bne * ;failed not equal (non zero) > @@ -10678,7 +10680,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2895 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2897 : dd3c02 > cmp fRORc,x ;test flags +2897 : dd4b02 > cmp fRORc,x ;test flags > trap_ne 289a : d0fe > bne * ;failed not equal (non zero) > @@ -10698,14 +10700,14 @@ ffff = ram_top = -1 ; shifts - abs indexed -28ab : a203 ldx #3 +28ab : a205 ldx #5 28ad : tasl8 - set_absx zp1,0 + set_absx zps,0 > load_flag 0 28ad : a900 > lda #0 ;allow test to change I-flag (no mask) > 28af : 48 > pha ;use stack to load status -28b0 : b513 > lda zp1,x ;load to indexed memory +28b0 : b513 > lda zps,x ;load to indexed memory 28b2 : 9d0302 > sta abst,x 28b5 : 28 > plp @@ -10713,7 +10715,7 @@ ffff = ram_top = -1 tst_absx rASL,fASL,0 28b9 : 08 > php ;save flags 28ba : bd0302 > lda abst,x -28bd : dd2002 > cmp rASL,x ;test result +28bd : dd2102 > cmp rASL,x ;test result > trap_ne 28c0 : d0fe > bne * ;failed not equal (non zero) > @@ -10721,21 +10723,21 @@ ffff = ram_top = -1 > eor_flag 0 28c3 : 4930 > eor #0|fao ;invert expected flags + always on bits > -28c5 : dd3002 > cmp fASL,x ;test flags +28c5 : dd3902 > cmp fASL,x ;test flags > trap_ne 28c8 : d0fe > bne * ;failed not equal (non zero) > 28ca : ca dex 28cb : 10e0 bpl tasl8 -28cd : a203 ldx #3 +28cd : a205 ldx #5 28cf : tasl9 - set_absx zp1,$ff + set_absx zps,$ff > load_flag $ff 28cf : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 28d1 : 48 > pha ;use stack to load status -28d2 : b513 > lda zp1,x ;load to indexed memory +28d2 : b513 > lda zps,x ;load to indexed memory 28d4 : 9d0302 > sta abst,x 28d7 : 28 > plp @@ -10743,7 +10745,7 @@ ffff = ram_top = -1 tst_absx rASL,fASL,$ff-fnzc 28db : 08 > php ;save flags 28dc : bd0302 > lda abst,x -28df : dd2002 > cmp rASL,x ;test result +28df : dd2102 > cmp rASL,x ;test result > trap_ne 28e2 : d0fe > bne * ;failed not equal (non zero) > @@ -10751,7 +10753,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 28e5 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -28e7 : dd3002 > cmp fASL,x ;test flags +28e7 : dd3902 > cmp fASL,x ;test flags > trap_ne 28ea : d0fe > bne * ;failed not equal (non zero) > @@ -10759,14 +10761,14 @@ ffff = ram_top = -1 28ec : ca dex 28ed : 10e0 bpl tasl9 -28ef : a203 ldx #3 +28ef : a205 ldx #5 28f1 : tlsr8 - set_absx zp1,0 + set_absx zps,0 > load_flag 0 28f1 : a900 > lda #0 ;allow test to change I-flag (no mask) > 28f3 : 48 > pha ;use stack to load status -28f4 : b513 > lda zp1,x ;load to indexed memory +28f4 : b513 > lda zps,x ;load to indexed memory 28f6 : 9d0302 > sta abst,x 28f9 : 28 > plp @@ -10774,7 +10776,7 @@ ffff = ram_top = -1 tst_absx rLSR,fLSR,0 28fd : 08 > php ;save flags 28fe : bd0302 > lda abst,x -2901 : dd2802 > cmp rLSR,x ;test result +2901 : dd2d02 > cmp rLSR,x ;test result > trap_ne 2904 : d0fe > bne * ;failed not equal (non zero) > @@ -10782,21 +10784,21 @@ ffff = ram_top = -1 > eor_flag 0 2907 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2909 : dd3802 > cmp fLSR,x ;test flags +2909 : dd4502 > cmp fLSR,x ;test flags > trap_ne 290c : d0fe > bne * ;failed not equal (non zero) > 290e : ca dex 290f : 10e0 bpl tlsr8 -2911 : a203 ldx #3 +2911 : a205 ldx #5 2913 : tlsr9 - set_absx zp1,$ff + set_absx zps,$ff > load_flag $ff 2913 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2915 : 48 > pha ;use stack to load status -2916 : b513 > lda zp1,x ;load to indexed memory +2916 : b513 > lda zps,x ;load to indexed memory 2918 : 9d0302 > sta abst,x 291b : 28 > plp @@ -10804,7 +10806,7 @@ ffff = ram_top = -1 tst_absx rLSR,fLSR,$ff-fnzc 291f : 08 > php ;save flags 2920 : bd0302 > lda abst,x -2923 : dd2802 > cmp rLSR,x ;test result +2923 : dd2d02 > cmp rLSR,x ;test result > trap_ne 2926 : d0fe > bne * ;failed not equal (non zero) > @@ -10812,7 +10814,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2929 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -292b : dd3802 > cmp fLSR,x ;test flags +292b : dd4502 > cmp fLSR,x ;test flags > trap_ne 292e : d0fe > bne * ;failed not equal (non zero) > @@ -10820,14 +10822,14 @@ ffff = ram_top = -1 2930 : ca dex 2931 : 10e0 bpl tlsr9 -2933 : a203 ldx #3 +2933 : a205 ldx #5 2935 : trol8 - set_absx zp1,0 + set_absx zps,0 > load_flag 0 2935 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2937 : 48 > pha ;use stack to load status -2938 : b513 > lda zp1,x ;load to indexed memory +2938 : b513 > lda zps,x ;load to indexed memory 293a : 9d0302 > sta abst,x 293d : 28 > plp @@ -10835,7 +10837,7 @@ ffff = ram_top = -1 tst_absx rROL,fROL,0 2941 : 08 > php ;save flags 2942 : bd0302 > lda abst,x -2945 : dd2002 > cmp rROL,x ;test result +2945 : dd2102 > cmp rROL,x ;test result > trap_ne 2948 : d0fe > bne * ;failed not equal (non zero) > @@ -10843,21 +10845,21 @@ ffff = ram_top = -1 > eor_flag 0 294b : 4930 > eor #0|fao ;invert expected flags + always on bits > -294d : dd3002 > cmp fROL,x ;test flags +294d : dd3902 > cmp fROL,x ;test flags > trap_ne 2950 : d0fe > bne * ;failed not equal (non zero) > 2952 : ca dex 2953 : 10e0 bpl trol8 -2955 : a203 ldx #3 +2955 : a205 ldx #5 2957 : trol9 - set_absx zp1,$ff-fc + set_absx zps,$ff-fc > load_flag $ff-fc 2957 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 2959 : 48 > pha ;use stack to load status -295a : b513 > lda zp1,x ;load to indexed memory +295a : b513 > lda zps,x ;load to indexed memory 295c : 9d0302 > sta abst,x 295f : 28 > plp @@ -10865,7 +10867,7 @@ ffff = ram_top = -1 tst_absx rROL,fROL,$ff-fnzc 2963 : 08 > php ;save flags 2964 : bd0302 > lda abst,x -2967 : dd2002 > cmp rROL,x ;test result +2967 : dd2102 > cmp rROL,x ;test result > trap_ne 296a : d0fe > bne * ;failed not equal (non zero) > @@ -10873,7 +10875,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 296d : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -296f : dd3002 > cmp fROL,x ;test flags +296f : dd3902 > cmp fROL,x ;test flags > trap_ne 2972 : d0fe > bne * ;failed not equal (non zero) > @@ -10881,14 +10883,14 @@ ffff = ram_top = -1 2974 : ca dex 2975 : 10e0 bpl trol9 -2977 : a203 ldx #3 +2977 : a205 ldx #5 2979 : trolc8 - set_absx zp1,fc + set_absx zps,fc > load_flag fc 2979 : a901 > lda #fc ;allow test to change I-flag (no mask) > 297b : 48 > pha ;use stack to load status -297c : b513 > lda zp1,x ;load to indexed memory +297c : b513 > lda zps,x ;load to indexed memory 297e : 9d0302 > sta abst,x 2981 : 28 > plp @@ -10896,7 +10898,7 @@ ffff = ram_top = -1 tst_absx rROLc,fROLc,0 2985 : 08 > php ;save flags 2986 : bd0302 > lda abst,x -2989 : dd2402 > cmp rROLc,x ;test result +2989 : dd2702 > cmp rROLc,x ;test result > trap_ne 298c : d0fe > bne * ;failed not equal (non zero) > @@ -10904,21 +10906,21 @@ ffff = ram_top = -1 > eor_flag 0 298f : 4930 > eor #0|fao ;invert expected flags + always on bits > -2991 : dd3402 > cmp fROLc,x ;test flags +2991 : dd3f02 > cmp fROLc,x ;test flags > trap_ne 2994 : d0fe > bne * ;failed not equal (non zero) > 2996 : ca dex 2997 : 10e0 bpl trolc8 -2999 : a203 ldx #3 +2999 : a205 ldx #5 299b : trolc9 - set_absx zp1,$ff + set_absx zps,$ff > load_flag $ff 299b : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 299d : 48 > pha ;use stack to load status -299e : b513 > lda zp1,x ;load to indexed memory +299e : b513 > lda zps,x ;load to indexed memory 29a0 : 9d0302 > sta abst,x 29a3 : 28 > plp @@ -10926,7 +10928,7 @@ ffff = ram_top = -1 tst_absx rROLc,fROLc,$ff-fnzc 29a7 : 08 > php ;save flags 29a8 : bd0302 > lda abst,x -29ab : dd2402 > cmp rROLc,x ;test result +29ab : dd2702 > cmp rROLc,x ;test result > trap_ne 29ae : d0fe > bne * ;failed not equal (non zero) > @@ -10934,7 +10936,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 29b1 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -29b3 : dd3402 > cmp fROLc,x ;test flags +29b3 : dd3f02 > cmp fROLc,x ;test flags > trap_ne 29b6 : d0fe > bne * ;failed not equal (non zero) > @@ -10942,14 +10944,14 @@ ffff = ram_top = -1 29b8 : ca dex 29b9 : 10e0 bpl trolc9 -29bb : a203 ldx #3 +29bb : a205 ldx #5 29bd : tror8 - set_absx zp1,0 + set_absx zps,0 > load_flag 0 29bd : a900 > lda #0 ;allow test to change I-flag (no mask) > 29bf : 48 > pha ;use stack to load status -29c0 : b513 > lda zp1,x ;load to indexed memory +29c0 : b513 > lda zps,x ;load to indexed memory 29c2 : 9d0302 > sta abst,x 29c5 : 28 > plp @@ -10957,7 +10959,7 @@ ffff = ram_top = -1 tst_absx rROR,fROR,0 29c9 : 08 > php ;save flags 29ca : bd0302 > lda abst,x -29cd : dd2802 > cmp rROR,x ;test result +29cd : dd2d02 > cmp rROR,x ;test result > trap_ne 29d0 : d0fe > bne * ;failed not equal (non zero) > @@ -10965,21 +10967,21 @@ ffff = ram_top = -1 > eor_flag 0 29d3 : 4930 > eor #0|fao ;invert expected flags + always on bits > -29d5 : dd3802 > cmp fROR,x ;test flags +29d5 : dd4502 > cmp fROR,x ;test flags > trap_ne 29d8 : d0fe > bne * ;failed not equal (non zero) > 29da : ca dex 29db : 10e0 bpl tror8 -29dd : a203 ldx #3 +29dd : a205 ldx #5 29df : tror9 - set_absx zp1,$ff-fc + set_absx zps,$ff-fc > load_flag $ff-fc 29df : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 29e1 : 48 > pha ;use stack to load status -29e2 : b513 > lda zp1,x ;load to indexed memory +29e2 : b513 > lda zps,x ;load to indexed memory 29e4 : 9d0302 > sta abst,x 29e7 : 28 > plp @@ -10987,7 +10989,7 @@ ffff = ram_top = -1 tst_absx rROR,fROR,$ff-fnzc 29eb : 08 > php ;save flags 29ec : bd0302 > lda abst,x -29ef : dd2802 > cmp rROR,x ;test result +29ef : dd2d02 > cmp rROR,x ;test result > trap_ne 29f2 : d0fe > bne * ;failed not equal (non zero) > @@ -10995,7 +10997,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 29f5 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -29f7 : dd3802 > cmp fROR,x ;test flags +29f7 : dd4502 > cmp fROR,x ;test flags > trap_ne 29fa : d0fe > bne * ;failed not equal (non zero) > @@ -11003,14 +11005,14 @@ ffff = ram_top = -1 29fc : ca dex 29fd : 10e0 bpl tror9 -29ff : a203 ldx #3 +29ff : a205 ldx #5 2a01 : trorc8 - set_absx zp1,fc + set_absx zps,fc > load_flag fc 2a01 : a901 > lda #fc ;allow test to change I-flag (no mask) > 2a03 : 48 > pha ;use stack to load status -2a04 : b513 > lda zp1,x ;load to indexed memory +2a04 : b513 > lda zps,x ;load to indexed memory 2a06 : 9d0302 > sta abst,x 2a09 : 28 > plp @@ -11018,7 +11020,7 @@ ffff = ram_top = -1 tst_absx rRORc,fRORc,0 2a0d : 08 > php ;save flags 2a0e : bd0302 > lda abst,x -2a11 : dd2c02 > cmp rRORc,x ;test result +2a11 : dd3302 > cmp rRORc,x ;test result > trap_ne 2a14 : d0fe > bne * ;failed not equal (non zero) > @@ -11026,21 +11028,21 @@ ffff = ram_top = -1 > eor_flag 0 2a17 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2a19 : dd3c02 > cmp fRORc,x ;test flags +2a19 : dd4b02 > cmp fRORc,x ;test flags > trap_ne 2a1c : d0fe > bne * ;failed not equal (non zero) > 2a1e : ca dex 2a1f : 10e0 bpl trorc8 -2a21 : a203 ldx #3 +2a21 : a205 ldx #5 2a23 : trorc9 - set_absx zp1,$ff + set_absx zps,$ff > load_flag $ff 2a23 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2a25 : 48 > pha ;use stack to load status -2a26 : b513 > lda zp1,x ;load to indexed memory +2a26 : b513 > lda zps,x ;load to indexed memory 2a28 : 9d0302 > sta abst,x 2a2b : 28 > plp @@ -11048,7 +11050,7 @@ ffff = ram_top = -1 tst_absx rRORc,fRORc,$ff-fnzc 2a2f : 08 > php ;save flags 2a30 : bd0302 > lda abst,x -2a33 : dd2c02 > cmp rRORc,x ;test result +2a33 : dd3302 > cmp rRORc,x ;test result > trap_ne 2a36 : d0fe > bne * ;failed not equal (non zero) > @@ -11056,7 +11058,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2a39 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2a3b : dd3c02 > cmp fRORc,x ;test flags +2a3b : dd4b02 > cmp fRORc,x ;test flags > trap_ne 2a3e : d0fe > bne * ;failed not equal (non zero) > @@ -11092,7 +11094,7 @@ ffff = ram_top = -1 tst_z rINC,fINC,0 2a5b : 08 > php ;save flags 2a5c : a50c > lda zpt -2a5e : dd4002 > cmp rINC,x ;test result +2a5e : dd5102 > cmp rINC,x ;test result > trap_ne 2a61 : d0fe > bne * ;failed not equal (non zero) > @@ -11100,7 +11102,7 @@ ffff = ram_top = -1 > eor_flag 0 2a64 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2a66 : dd4502 > cmp fINC,x ;test flags +2a66 : dd5602 > cmp fINC,x ;test flags > trap_ne 2a69 : d0fe > bne * ;failed not equal (non zero) > @@ -11126,7 +11128,7 @@ ffff = ram_top = -1 tst_z rINC,fINC,0 2a81 : 08 > php ;save flags 2a82 : a50c > lda zpt -2a84 : dd4002 > cmp rINC,x ;test result +2a84 : dd5102 > cmp rINC,x ;test result > trap_ne 2a87 : d0fe > bne * ;failed not equal (non zero) > @@ -11134,7 +11136,7 @@ ffff = ram_top = -1 > eor_flag 0 2a8a : 4930 > eor #0|fao ;invert expected flags + always on bits > -2a8c : dd4502 > cmp fINC,x ;test flags +2a8c : dd5602 > cmp fINC,x ;test flags > trap_ne 2a8f : d0fe > bne * ;failed not equal (non zero) > @@ -11162,7 +11164,7 @@ ffff = ram_top = -1 tst_z rINC,fINC,$ff-fnz 2aaa : 08 > php ;save flags 2aab : a50c > lda zpt -2aad : dd4002 > cmp rINC,x ;test result +2aad : dd5102 > cmp rINC,x ;test result > trap_ne 2ab0 : d0fe > bne * ;failed not equal (non zero) > @@ -11170,7 +11172,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2ab3 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2ab5 : dd4502 > cmp fINC,x ;test flags +2ab5 : dd5602 > cmp fINC,x ;test flags > trap_ne 2ab8 : d0fe > bne * ;failed not equal (non zero) > @@ -11196,7 +11198,7 @@ ffff = ram_top = -1 tst_z rINC,fINC,$ff-fnz 2ad0 : 08 > php ;save flags 2ad1 : a50c > lda zpt -2ad3 : dd4002 > cmp rINC,x ;test result +2ad3 : dd5102 > cmp rINC,x ;test result > trap_ne 2ad6 : d0fe > bne * ;failed not equal (non zero) > @@ -11204,7 +11206,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2ad9 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2adb : dd4502 > cmp fINC,x ;test flags +2adb : dd5602 > cmp fINC,x ;test flags > trap_ne 2ade : d0fe > bne * ;failed not equal (non zero) > @@ -11245,7 +11247,7 @@ ffff = ram_top = -1 tst_abs rINC,fINC,0 2b07 : 08 > php ;save flags 2b08 : ad0302 > lda abst -2b0b : dd4002 > cmp rINC,x ;test result +2b0b : dd5102 > cmp rINC,x ;test result > trap_ne 2b0e : d0fe > bne * ;failed not equal (non zero) > @@ -11253,7 +11255,7 @@ ffff = ram_top = -1 > eor_flag 0 2b11 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2b13 : dd4502 > cmp fINC,x ;test flags +2b13 : dd5602 > cmp fINC,x ;test flags > trap_ne 2b16 : d0fe > bne * ;failed not equal (non zero) > @@ -11279,7 +11281,7 @@ ffff = ram_top = -1 tst_abs rINC,fINC,0 2b31 : 08 > php ;save flags 2b32 : ad0302 > lda abst -2b35 : dd4002 > cmp rINC,x ;test result +2b35 : dd5102 > cmp rINC,x ;test result > trap_ne 2b38 : d0fe > bne * ;failed not equal (non zero) > @@ -11287,7 +11289,7 @@ ffff = ram_top = -1 > eor_flag 0 2b3b : 4930 > eor #0|fao ;invert expected flags + always on bits > -2b3d : dd4502 > cmp fINC,x ;test flags +2b3d : dd5602 > cmp fINC,x ;test flags > trap_ne 2b40 : d0fe > bne * ;failed not equal (non zero) > @@ -11315,7 +11317,7 @@ ffff = ram_top = -1 tst_abs rINC,fINC,$ff-fnz 2b5e : 08 > php ;save flags 2b5f : ad0302 > lda abst -2b62 : dd4002 > cmp rINC,x ;test result +2b62 : dd5102 > cmp rINC,x ;test result > trap_ne 2b65 : d0fe > bne * ;failed not equal (non zero) > @@ -11323,7 +11325,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2b68 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2b6a : dd4502 > cmp fINC,x ;test flags +2b6a : dd5602 > cmp fINC,x ;test flags > trap_ne 2b6d : d0fe > bne * ;failed not equal (non zero) > @@ -11349,7 +11351,7 @@ ffff = ram_top = -1 tst_abs rINC,fINC,$ff-fnz 2b88 : 08 > php ;save flags 2b89 : ad0302 > lda abst -2b8c : dd4002 > cmp rINC,x ;test result +2b8c : dd5102 > cmp rINC,x ;test result > trap_ne 2b8f : d0fe > bne * ;failed not equal (non zero) > @@ -11357,7 +11359,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2b92 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2b94 : dd4502 > cmp fINC,x ;test flags +2b94 : dd5602 > cmp fINC,x ;test flags > trap_ne 2b97 : d0fe > bne * ;failed not equal (non zero) > @@ -11397,7 +11399,7 @@ ffff = ram_top = -1 tst_zx rINC,fINC,0 2bbf : 08 > php ;save flags 2bc0 : b50c > lda zpt,x -2bc2 : dd4002 > cmp rINC,x ;test result +2bc2 : dd5102 > cmp rINC,x ;test result > trap_ne 2bc5 : d0fe > bne * ;failed not equal (non zero) > @@ -11405,7 +11407,7 @@ ffff = ram_top = -1 > eor_flag 0 2bc8 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2bca : dd4502 > cmp fINC,x ;test flags +2bca : dd5602 > cmp fINC,x ;test flags > trap_ne 2bcd : d0fe > bne * ;failed not equal (non zero) > @@ -11431,7 +11433,7 @@ ffff = ram_top = -1 tst_zx rINC,fINC,0 2be7 : 08 > php ;save flags 2be8 : b50c > lda zpt,x -2bea : dd4002 > cmp rINC,x ;test result +2bea : dd5102 > cmp rINC,x ;test result > trap_ne 2bed : d0fe > bne * ;failed not equal (non zero) > @@ -11439,7 +11441,7 @@ ffff = ram_top = -1 > eor_flag 0 2bf0 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2bf2 : dd4502 > cmp fINC,x ;test flags +2bf2 : dd5602 > cmp fINC,x ;test flags > trap_ne 2bf5 : d0fe > bne * ;failed not equal (non zero) > @@ -11466,7 +11468,7 @@ ffff = ram_top = -1 tst_zx rINC,fINC,$ff-fnz 2c10 : 08 > php ;save flags 2c11 : b50c > lda zpt,x -2c13 : dd4002 > cmp rINC,x ;test result +2c13 : dd5102 > cmp rINC,x ;test result > trap_ne 2c16 : d0fe > bne * ;failed not equal (non zero) > @@ -11474,7 +11476,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2c19 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2c1b : dd4502 > cmp fINC,x ;test flags +2c1b : dd5602 > cmp fINC,x ;test flags > trap_ne 2c1e : d0fe > bne * ;failed not equal (non zero) > @@ -11500,7 +11502,7 @@ ffff = ram_top = -1 tst_zx rINC,fINC,$ff-fnz 2c38 : 08 > php ;save flags 2c39 : b50c > lda zpt,x -2c3b : dd4002 > cmp rINC,x ;test result +2c3b : dd5102 > cmp rINC,x ;test result > trap_ne 2c3e : d0fe > bne * ;failed not equal (non zero) > @@ -11508,7 +11510,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2c41 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2c43 : dd4502 > cmp fINC,x ;test flags +2c43 : dd5602 > cmp fINC,x ;test flags > trap_ne 2c46 : d0fe > bne * ;failed not equal (non zero) > @@ -11548,7 +11550,7 @@ ffff = ram_top = -1 tst_absx rINC,fINC,0 2c6f : 08 > php ;save flags 2c70 : bd0302 > lda abst,x -2c73 : dd4002 > cmp rINC,x ;test result +2c73 : dd5102 > cmp rINC,x ;test result > trap_ne 2c76 : d0fe > bne * ;failed not equal (non zero) > @@ -11556,7 +11558,7 @@ ffff = ram_top = -1 > eor_flag 0 2c79 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2c7b : dd4502 > cmp fINC,x ;test flags +2c7b : dd5602 > cmp fINC,x ;test flags > trap_ne 2c7e : d0fe > bne * ;failed not equal (non zero) > @@ -11582,7 +11584,7 @@ ffff = ram_top = -1 tst_absx rINC,fINC,0 2c9b : 08 > php ;save flags 2c9c : bd0302 > lda abst,x -2c9f : dd4002 > cmp rINC,x ;test result +2c9f : dd5102 > cmp rINC,x ;test result > trap_ne 2ca2 : d0fe > bne * ;failed not equal (non zero) > @@ -11590,7 +11592,7 @@ ffff = ram_top = -1 > eor_flag 0 2ca5 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2ca7 : dd4502 > cmp fINC,x ;test flags +2ca7 : dd5602 > cmp fINC,x ;test flags > trap_ne 2caa : d0fe > bne * ;failed not equal (non zero) > @@ -11617,7 +11619,7 @@ ffff = ram_top = -1 tst_absx rINC,fINC,$ff-fnz 2cc8 : 08 > php ;save flags 2cc9 : bd0302 > lda abst,x -2ccc : dd4002 > cmp rINC,x ;test result +2ccc : dd5102 > cmp rINC,x ;test result > trap_ne 2ccf : d0fe > bne * ;failed not equal (non zero) > @@ -11625,7 +11627,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2cd2 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2cd4 : dd4502 > cmp fINC,x ;test flags +2cd4 : dd5602 > cmp fINC,x ;test flags > trap_ne 2cd7 : d0fe > bne * ;failed not equal (non zero) > @@ -11651,7 +11653,7 @@ ffff = ram_top = -1 tst_absx rINC,fINC,$ff-fnz 2cf4 : 08 > php ;save flags 2cf5 : bd0302 > lda abst,x -2cf8 : dd4002 > cmp rINC,x ;test result +2cf8 : dd5102 > cmp rINC,x ;test result > trap_ne 2cfb : d0fe > bne * ;failed not equal (non zero) > @@ -11659,7 +11661,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2cfe : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2d00 : dd4502 > cmp fINC,x ;test flags +2d00 : dd5602 > cmp fINC,x ;test flags > trap_ne 2d03 : d0fe > bne * ;failed not equal (non zero) > @@ -11687,20 +11689,20 @@ ffff = ram_top = -1 ; testing logical instructions - AND EOR ORA all addressing modes ; AND 2d1f : a203 ldx #3 ;immediate -2d21 : b51c tand lda zpAN,x -2d23 : 8d0902 sta ex_andi+1 ;set AND # operand +2d21 : b51e tand lda zpAN,x +2d23 : 8d0a02 sta ex_andi+1 ;set AND # operand set_ax absANa,0 > load_flag 0 2d26 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2d28 : 48 > pha ;use stack to load status -2d29 : bd5a02 > lda absANa,x ;precharge accu +2d29 : bd6b02 > lda absANa,x ;precharge accu 2d2c : 28 > plp -2d2d : 200802 jsr ex_andi ;execute AND # in RAM +2d2d : 200902 jsr ex_andi ;execute AND # in RAM tst_ax absrlo,absflo,0 2d30 : 08 > php ;save flags -2d31 : dd6202 > cmp absrlo,x ;test result +2d31 : dd7302 > cmp absrlo,x ;test result > trap_ne 2d34 : d0fe > bne * ;failed not equal (non zero) > @@ -11708,7 +11710,7 @@ ffff = ram_top = -1 > eor_flag 0 2d37 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2d39 : dd6602 > cmp absflo,x ;test flags +2d39 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2d3c : d0fe > bne * ;failed not equal (non zero) > @@ -11716,20 +11718,20 @@ ffff = ram_top = -1 2d3e : ca dex 2d3f : 10e0 bpl tand 2d41 : a203 ldx #3 -2d43 : b51c tand1 lda zpAN,x -2d45 : 8d0902 sta ex_andi+1 ;set AND # operand +2d43 : b51e tand1 lda zpAN,x +2d45 : 8d0a02 sta ex_andi+1 ;set AND # operand set_ax absANa,$ff > load_flag $ff 2d48 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2d4a : 48 > pha ;use stack to load status -2d4b : bd5a02 > lda absANa,x ;precharge accu +2d4b : bd6b02 > lda absANa,x ;precharge accu 2d4e : 28 > plp -2d4f : 200802 jsr ex_andi ;execute AND # in RAM +2d4f : 200902 jsr ex_andi ;execute AND # in RAM tst_ax absrlo,absflo,$ff-fnz 2d52 : 08 > php ;save flags -2d53 : dd6202 > cmp absrlo,x ;test result +2d53 : dd7302 > cmp absrlo,x ;test result > trap_ne 2d56 : d0fe > bne * ;failed not equal (non zero) > @@ -11737,7 +11739,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2d59 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2d5b : dd6602 > cmp absflo,x ;test flags +2d5b : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2d5e : d0fe > bne * ;failed not equal (non zero) > @@ -11746,20 +11748,20 @@ ffff = ram_top = -1 2d61 : 10e0 bpl tand1 2d63 : a203 ldx #3 ;zp -2d65 : b51c tand2 lda zpAN,x +2d65 : b51e tand2 lda zpAN,x 2d67 : 850c sta zpt set_ax absANa,0 > load_flag 0 2d69 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2d6b : 48 > pha ;use stack to load status -2d6c : bd5a02 > lda absANa,x ;precharge accu +2d6c : bd6b02 > lda absANa,x ;precharge accu 2d6f : 28 > plp 2d70 : 250c and zpt tst_ax absrlo,absflo,0 2d72 : 08 > php ;save flags -2d73 : dd6202 > cmp absrlo,x ;test result +2d73 : dd7302 > cmp absrlo,x ;test result > trap_ne 2d76 : d0fe > bne * ;failed not equal (non zero) > @@ -11767,7 +11769,7 @@ ffff = ram_top = -1 > eor_flag 0 2d79 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2d7b : dd6602 > cmp absflo,x ;test flags +2d7b : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2d7e : d0fe > bne * ;failed not equal (non zero) > @@ -11775,20 +11777,20 @@ ffff = ram_top = -1 2d80 : ca dex 2d81 : 10e2 bpl tand2 2d83 : a203 ldx #3 -2d85 : b51c tand3 lda zpAN,x +2d85 : b51e tand3 lda zpAN,x 2d87 : 850c sta zpt set_ax absANa,$ff > load_flag $ff 2d89 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2d8b : 48 > pha ;use stack to load status -2d8c : bd5a02 > lda absANa,x ;precharge accu +2d8c : bd6b02 > lda absANa,x ;precharge accu 2d8f : 28 > plp 2d90 : 250c and zpt tst_ax absrlo,absflo,$ff-fnz 2d92 : 08 > php ;save flags -2d93 : dd6202 > cmp absrlo,x ;test result +2d93 : dd7302 > cmp absrlo,x ;test result > trap_ne 2d96 : d0fe > bne * ;failed not equal (non zero) > @@ -11796,7 +11798,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2d99 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2d9b : dd6602 > cmp absflo,x ;test flags +2d9b : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2d9e : d0fe > bne * ;failed not equal (non zero) > @@ -11805,20 +11807,20 @@ ffff = ram_top = -1 2da1 : 10e2 bpl tand3 2da3 : a203 ldx #3 ;abs -2da5 : b51c tand4 lda zpAN,x +2da5 : b51e tand4 lda zpAN,x 2da7 : 8d0302 sta abst set_ax absANa,0 > load_flag 0 2daa : a900 > lda #0 ;allow test to change I-flag (no mask) > 2dac : 48 > pha ;use stack to load status -2dad : bd5a02 > lda absANa,x ;precharge accu +2dad : bd6b02 > lda absANa,x ;precharge accu 2db0 : 28 > plp 2db1 : 2d0302 and abst tst_ax absrlo,absflo,0 2db4 : 08 > php ;save flags -2db5 : dd6202 > cmp absrlo,x ;test result +2db5 : dd7302 > cmp absrlo,x ;test result > trap_ne 2db8 : d0fe > bne * ;failed not equal (non zero) > @@ -11826,7 +11828,7 @@ ffff = ram_top = -1 > eor_flag 0 2dbb : 4930 > eor #0|fao ;invert expected flags + always on bits > -2dbd : dd6602 > cmp absflo,x ;test flags +2dbd : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2dc0 : d0fe > bne * ;failed not equal (non zero) > @@ -11834,20 +11836,20 @@ ffff = ram_top = -1 2dc2 : ca dex 2dc3 : 10e0 bpl tand4 2dc5 : a203 ldx #3 -2dc7 : b51c tand5 lda zpAN,x +2dc7 : b51e tand5 lda zpAN,x 2dc9 : 8d0302 sta abst set_ax absANa,$ff > load_flag $ff 2dcc : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2dce : 48 > pha ;use stack to load status -2dcf : bd5a02 > lda absANa,x ;precharge accu +2dcf : bd6b02 > lda absANa,x ;precharge accu 2dd2 : 28 > plp 2dd3 : 2d0302 and abst tst_ax absrlo,absflo,$ff-fnz 2dd6 : 08 > php ;save flags -2dd7 : dd6202 > cmp absrlo,x ;test result +2dd7 : dd7302 > cmp absrlo,x ;test result > trap_ne 2dda : d0fe > bne * ;failed not equal (non zero) > @@ -11855,7 +11857,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2ddd : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2ddf : dd6602 > cmp absflo,x ;test flags +2ddf : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2de2 : d0fe > bne * ;failed not equal (non zero) > @@ -11870,13 +11872,13 @@ ffff = ram_top = -1 2de9 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2deb : 48 > pha ;use stack to load status -2dec : bd5a02 > lda absANa,x ;precharge accu +2dec : bd6b02 > lda absANa,x ;precharge accu 2def : 28 > plp -2df0 : 351c and zpAN,x +2df0 : 351e and zpAN,x tst_ax absrlo,absflo,0 2df2 : 08 > php ;save flags -2df3 : dd6202 > cmp absrlo,x ;test result +2df3 : dd7302 > cmp absrlo,x ;test result > trap_ne 2df6 : d0fe > bne * ;failed not equal (non zero) > @@ -11884,7 +11886,7 @@ ffff = ram_top = -1 > eor_flag 0 2df9 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2dfb : dd6602 > cmp absflo,x ;test flags +2dfb : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2dfe : d0fe > bne * ;failed not equal (non zero) > @@ -11898,13 +11900,13 @@ ffff = ram_top = -1 2e05 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2e07 : 48 > pha ;use stack to load status -2e08 : bd5a02 > lda absANa,x ;precharge accu +2e08 : bd6b02 > lda absANa,x ;precharge accu 2e0b : 28 > plp -2e0c : 351c and zpAN,x +2e0c : 351e and zpAN,x tst_ax absrlo,absflo,$ff-fnz 2e0e : 08 > php ;save flags -2e0f : dd6202 > cmp absrlo,x ;test result +2e0f : dd7302 > cmp absrlo,x ;test result > trap_ne 2e12 : d0fe > bne * ;failed not equal (non zero) > @@ -11912,7 +11914,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2e15 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2e17 : dd6602 > cmp absflo,x ;test flags +2e17 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2e1a : d0fe > bne * ;failed not equal (non zero) > @@ -11927,13 +11929,13 @@ ffff = ram_top = -1 2e21 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2e23 : 48 > pha ;use stack to load status -2e24 : bd5a02 > lda absANa,x ;precharge accu +2e24 : bd6b02 > lda absANa,x ;precharge accu 2e27 : 28 > plp -2e28 : 3d4e02 and absAN,x +2e28 : 3d5f02 and absAN,x tst_ax absrlo,absflo,0 2e2b : 08 > php ;save flags -2e2c : dd6202 > cmp absrlo,x ;test result +2e2c : dd7302 > cmp absrlo,x ;test result > trap_ne 2e2f : d0fe > bne * ;failed not equal (non zero) > @@ -11941,7 +11943,7 @@ ffff = ram_top = -1 > eor_flag 0 2e32 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2e34 : dd6602 > cmp absflo,x ;test flags +2e34 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2e37 : d0fe > bne * ;failed not equal (non zero) > @@ -11955,13 +11957,13 @@ ffff = ram_top = -1 2e3e : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2e40 : 48 > pha ;use stack to load status -2e41 : bd5a02 > lda absANa,x ;precharge accu +2e41 : bd6b02 > lda absANa,x ;precharge accu 2e44 : 28 > plp -2e45 : 3d4e02 and absAN,x +2e45 : 3d5f02 and absAN,x tst_ax absrlo,absflo,$ff-fnz 2e48 : 08 > php ;save flags -2e49 : dd6202 > cmp absrlo,x ;test result +2e49 : dd7302 > cmp absrlo,x ;test result > trap_ne 2e4c : d0fe > bne * ;failed not equal (non zero) > @@ -11969,7 +11971,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2e4f : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2e51 : dd6602 > cmp absflo,x ;test flags +2e51 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2e54 : d0fe > bne * ;failed not equal (non zero) > @@ -11984,13 +11986,13 @@ ffff = ram_top = -1 2e5b : a900 > lda #0 ;allow test to change I-flag (no mask) > 2e5d : 48 > pha ;use stack to load status -2e5e : b95a02 > lda absANa,y ;precharge accu +2e5e : b96b02 > lda absANa,y ;precharge accu 2e61 : 28 > plp -2e62 : 394e02 and absAN,y +2e62 : 395f02 and absAN,y tst_ay absrlo,absflo,0 2e65 : 08 > php ;save flags -2e66 : d96202 > cmp absrlo,y ;test result +2e66 : d97302 > cmp absrlo,y ;test result > trap_ne ; 2e69 : d0fe > bne * ;failed not equal (non zero) > @@ -11998,7 +12000,7 @@ ffff = ram_top = -1 > eor_flag 0 2e6c : 4930 > eor #0|fao ;invert expected flags + always on bits > -2e6e : d96602 > cmp absflo,y ;test flags +2e6e : d97702 > cmp absflo,y ;test flags > trap_ne 2e71 : d0fe > bne * ;failed not equal (non zero) > @@ -12012,13 +12014,13 @@ ffff = ram_top = -1 2e78 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2e7a : 48 > pha ;use stack to load status -2e7b : b95a02 > lda absANa,y ;precharge accu +2e7b : b96b02 > lda absANa,y ;precharge accu 2e7e : 28 > plp -2e7f : 394e02 and absAN,y +2e7f : 395f02 and absAN,y tst_ay absrlo,absflo,$ff-fnz 2e82 : 08 > php ;save flags -2e83 : d96202 > cmp absrlo,y ;test result +2e83 : d97302 > cmp absrlo,y ;test result > trap_ne ; 2e86 : d0fe > bne * ;failed not equal (non zero) > @@ -12026,7 +12028,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2e89 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2e8b : d96602 > cmp absflo,y ;test flags +2e8b : d97702 > cmp absflo,y ;test flags > trap_ne 2e8e : d0fe > bne * ;failed not equal (non zero) > @@ -12042,13 +12044,13 @@ ffff = ram_top = -1 2e97 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2e99 : 48 > pha ;use stack to load status -2e9a : b95a02 > lda absANa,y ;precharge accu +2e9a : b96b02 > lda absANa,y ;precharge accu 2e9d : 28 > plp -2e9e : 213a and (indAN,x) +2e9e : 213c and (indAN,x) tst_ay absrlo,absflo,0 2ea0 : 08 > php ;save flags -2ea1 : d96202 > cmp absrlo,y ;test result +2ea1 : d97302 > cmp absrlo,y ;test result > trap_ne ; 2ea4 : d0fe > bne * ;failed not equal (non zero) > @@ -12056,7 +12058,7 @@ ffff = ram_top = -1 > eor_flag 0 2ea7 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2ea9 : d96602 > cmp absflo,y ;test flags +2ea9 : d97702 > cmp absflo,y ;test flags > trap_ne 2eac : d0fe > bne * ;failed not equal (non zero) > @@ -12073,13 +12075,13 @@ ffff = ram_top = -1 2eb7 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2eb9 : 48 > pha ;use stack to load status -2eba : b95a02 > lda absANa,y ;precharge accu +2eba : b96b02 > lda absANa,y ;precharge accu 2ebd : 28 > plp -2ebe : 213a and (indAN,x) +2ebe : 213c and (indAN,x) tst_ay absrlo,absflo,$ff-fnz 2ec0 : 08 > php ;save flags -2ec1 : d96202 > cmp absrlo,y ;test result +2ec1 : d97302 > cmp absrlo,y ;test result > trap_ne ; 2ec4 : d0fe > bne * ;failed not equal (non zero) > @@ -12087,7 +12089,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2ec7 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2ec9 : d96602 > cmp absflo,y ;test flags +2ec9 : d97702 > cmp absflo,y ;test flags > trap_ne 2ecc : d0fe > bne * ;failed not equal (non zero) > @@ -12104,13 +12106,13 @@ ffff = ram_top = -1 2ed5 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2ed7 : 48 > pha ;use stack to load status -2ed8 : b95a02 > lda absANa,y ;precharge accu +2ed8 : b96b02 > lda absANa,y ;precharge accu 2edb : 28 > plp -2edc : 313a and (indAN),y +2edc : 313c and (indAN),y tst_ay absrlo,absflo,0 2ede : 08 > php ;save flags -2edf : d96202 > cmp absrlo,y ;test result +2edf : d97302 > cmp absrlo,y ;test result > trap_ne ; 2ee2 : d0fe > bne * ;failed not equal (non zero) > @@ -12118,7 +12120,7 @@ ffff = ram_top = -1 > eor_flag 0 2ee5 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2ee7 : d96602 > cmp absflo,y ;test flags +2ee7 : d97702 > cmp absflo,y ;test flags > trap_ne 2eea : d0fe > bne * ;failed not equal (non zero) > @@ -12132,13 +12134,13 @@ ffff = ram_top = -1 2ef1 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2ef3 : 48 > pha ;use stack to load status -2ef4 : b95a02 > lda absANa,y ;precharge accu +2ef4 : b96b02 > lda absANa,y ;precharge accu 2ef7 : 28 > plp -2ef8 : 313a and (indAN),y +2ef8 : 313c and (indAN),y tst_ay absrlo,absflo,$ff-fnz 2efa : 08 > php ;save flags -2efb : d96202 > cmp absrlo,y ;test result +2efb : d97302 > cmp absrlo,y ;test result > trap_ne ; 2efe : d0fe > bne * ;failed not equal (non zero) > @@ -12146,7 +12148,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2f01 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2f03 : d96602 > cmp absflo,y ;test flags +2f03 : d97702 > cmp absflo,y ;test flags > trap_ne 2f06 : d0fe > bne * ;failed not equal (non zero) > @@ -12167,20 +12169,20 @@ ffff = ram_top = -1 ; EOR 2f17 : a203 ldx #3 ;immediate - self modifying code -2f19 : b520 teor lda zpEO,x -2f1b : 8d0c02 sta ex_eori+1 ;set EOR # operand +2f19 : b522 teor lda zpEO,x +2f1b : 8d0d02 sta ex_eori+1 ;set EOR # operand set_ax absEOa,0 > load_flag 0 2f1e : a900 > lda #0 ;allow test to change I-flag (no mask) > 2f20 : 48 > pha ;use stack to load status -2f21 : bd5e02 > lda absEOa,x ;precharge accu +2f21 : bd6f02 > lda absEOa,x ;precharge accu 2f24 : 28 > plp -2f25 : 200b02 jsr ex_eori ;execute EOR # in RAM +2f25 : 200c02 jsr ex_eori ;execute EOR # in RAM tst_ax absrlo,absflo,0 2f28 : 08 > php ;save flags -2f29 : dd6202 > cmp absrlo,x ;test result +2f29 : dd7302 > cmp absrlo,x ;test result > trap_ne 2f2c : d0fe > bne * ;failed not equal (non zero) > @@ -12188,7 +12190,7 @@ ffff = ram_top = -1 > eor_flag 0 2f2f : 4930 > eor #0|fao ;invert expected flags + always on bits > -2f31 : dd6602 > cmp absflo,x ;test flags +2f31 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2f34 : d0fe > bne * ;failed not equal (non zero) > @@ -12196,20 +12198,20 @@ ffff = ram_top = -1 2f36 : ca dex 2f37 : 10e0 bpl teor 2f39 : a203 ldx #3 -2f3b : b520 teor1 lda zpEO,x -2f3d : 8d0c02 sta ex_eori+1 ;set EOR # operand +2f3b : b522 teor1 lda zpEO,x +2f3d : 8d0d02 sta ex_eori+1 ;set EOR # operand set_ax absEOa,$ff > load_flag $ff 2f40 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2f42 : 48 > pha ;use stack to load status -2f43 : bd5e02 > lda absEOa,x ;precharge accu +2f43 : bd6f02 > lda absEOa,x ;precharge accu 2f46 : 28 > plp -2f47 : 200b02 jsr ex_eori ;execute EOR # in RAM +2f47 : 200c02 jsr ex_eori ;execute EOR # in RAM tst_ax absrlo,absflo,$ff-fnz 2f4a : 08 > php ;save flags -2f4b : dd6202 > cmp absrlo,x ;test result +2f4b : dd7302 > cmp absrlo,x ;test result > trap_ne 2f4e : d0fe > bne * ;failed not equal (non zero) > @@ -12217,7 +12219,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2f51 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2f53 : dd6602 > cmp absflo,x ;test flags +2f53 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2f56 : d0fe > bne * ;failed not equal (non zero) > @@ -12226,20 +12228,20 @@ ffff = ram_top = -1 2f59 : 10e0 bpl teor1 2f5b : a203 ldx #3 ;zp -2f5d : b520 teor2 lda zpEO,x +2f5d : b522 teor2 lda zpEO,x 2f5f : 850c sta zpt set_ax absEOa,0 > load_flag 0 2f61 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2f63 : 48 > pha ;use stack to load status -2f64 : bd5e02 > lda absEOa,x ;precharge accu +2f64 : bd6f02 > lda absEOa,x ;precharge accu 2f67 : 28 > plp 2f68 : 450c eor zpt tst_ax absrlo,absflo,0 2f6a : 08 > php ;save flags -2f6b : dd6202 > cmp absrlo,x ;test result +2f6b : dd7302 > cmp absrlo,x ;test result > trap_ne 2f6e : d0fe > bne * ;failed not equal (non zero) > @@ -12247,7 +12249,7 @@ ffff = ram_top = -1 > eor_flag 0 2f71 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2f73 : dd6602 > cmp absflo,x ;test flags +2f73 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2f76 : d0fe > bne * ;failed not equal (non zero) > @@ -12255,20 +12257,20 @@ ffff = ram_top = -1 2f78 : ca dex 2f79 : 10e2 bpl teor2 2f7b : a203 ldx #3 -2f7d : b520 teor3 lda zpEO,x +2f7d : b522 teor3 lda zpEO,x 2f7f : 850c sta zpt set_ax absEOa,$ff > load_flag $ff 2f81 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2f83 : 48 > pha ;use stack to load status -2f84 : bd5e02 > lda absEOa,x ;precharge accu +2f84 : bd6f02 > lda absEOa,x ;precharge accu 2f87 : 28 > plp 2f88 : 450c eor zpt tst_ax absrlo,absflo,$ff-fnz 2f8a : 08 > php ;save flags -2f8b : dd6202 > cmp absrlo,x ;test result +2f8b : dd7302 > cmp absrlo,x ;test result > trap_ne 2f8e : d0fe > bne * ;failed not equal (non zero) > @@ -12276,7 +12278,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2f91 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2f93 : dd6602 > cmp absflo,x ;test flags +2f93 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2f96 : d0fe > bne * ;failed not equal (non zero) > @@ -12285,20 +12287,20 @@ ffff = ram_top = -1 2f99 : 10e2 bpl teor3 2f9b : a203 ldx #3 ;abs -2f9d : b520 teor4 lda zpEO,x +2f9d : b522 teor4 lda zpEO,x 2f9f : 8d0302 sta abst set_ax absEOa,0 > load_flag 0 2fa2 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2fa4 : 48 > pha ;use stack to load status -2fa5 : bd5e02 > lda absEOa,x ;precharge accu +2fa5 : bd6f02 > lda absEOa,x ;precharge accu 2fa8 : 28 > plp 2fa9 : 4d0302 eor abst tst_ax absrlo,absflo,0 2fac : 08 > php ;save flags -2fad : dd6202 > cmp absrlo,x ;test result +2fad : dd7302 > cmp absrlo,x ;test result > trap_ne 2fb0 : d0fe > bne * ;failed not equal (non zero) > @@ -12306,7 +12308,7 @@ ffff = ram_top = -1 > eor_flag 0 2fb3 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2fb5 : dd6602 > cmp absflo,x ;test flags +2fb5 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2fb8 : d0fe > bne * ;failed not equal (non zero) > @@ -12314,20 +12316,20 @@ ffff = ram_top = -1 2fba : ca dex 2fbb : 10e0 bpl teor4 2fbd : a203 ldx #3 -2fbf : b520 teor5 lda zpEO,x +2fbf : b522 teor5 lda zpEO,x 2fc1 : 8d0302 sta abst set_ax absEOa,$ff > load_flag $ff 2fc4 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2fc6 : 48 > pha ;use stack to load status -2fc7 : bd5e02 > lda absEOa,x ;precharge accu +2fc7 : bd6f02 > lda absEOa,x ;precharge accu 2fca : 28 > plp 2fcb : 4d0302 eor abst tst_ax absrlo,absflo,$ff-fnz 2fce : 08 > php ;save flags -2fcf : dd6202 > cmp absrlo,x ;test result +2fcf : dd7302 > cmp absrlo,x ;test result > trap_ne 2fd2 : d0fe > bne * ;failed not equal (non zero) > @@ -12335,7 +12337,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2fd5 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2fd7 : dd6602 > cmp absflo,x ;test flags +2fd7 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2fda : d0fe > bne * ;failed not equal (non zero) > @@ -12350,13 +12352,13 @@ ffff = ram_top = -1 2fe1 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2fe3 : 48 > pha ;use stack to load status -2fe4 : bd5e02 > lda absEOa,x ;precharge accu +2fe4 : bd6f02 > lda absEOa,x ;precharge accu 2fe7 : 28 > plp -2fe8 : 5520 eor zpEO,x +2fe8 : 5522 eor zpEO,x tst_ax absrlo,absflo,0 2fea : 08 > php ;save flags -2feb : dd6202 > cmp absrlo,x ;test result +2feb : dd7302 > cmp absrlo,x ;test result > trap_ne 2fee : d0fe > bne * ;failed not equal (non zero) > @@ -12364,7 +12366,7 @@ ffff = ram_top = -1 > eor_flag 0 2ff1 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2ff3 : dd6602 > cmp absflo,x ;test flags +2ff3 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2ff6 : d0fe > bne * ;failed not equal (non zero) > @@ -12378,13 +12380,13 @@ ffff = ram_top = -1 2ffd : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2fff : 48 > pha ;use stack to load status -3000 : bd5e02 > lda absEOa,x ;precharge accu +3000 : bd6f02 > lda absEOa,x ;precharge accu 3003 : 28 > plp -3004 : 5520 eor zpEO,x +3004 : 5522 eor zpEO,x tst_ax absrlo,absflo,$ff-fnz 3006 : 08 > php ;save flags -3007 : dd6202 > cmp absrlo,x ;test result +3007 : dd7302 > cmp absrlo,x ;test result > trap_ne 300a : d0fe > bne * ;failed not equal (non zero) > @@ -12392,7 +12394,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 300d : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -300f : dd6602 > cmp absflo,x ;test flags +300f : dd7702 > cmp absflo,x ;test flags > trap_ne ; 3012 : d0fe > bne * ;failed not equal (non zero) > @@ -12407,13 +12409,13 @@ ffff = ram_top = -1 3019 : a900 > lda #0 ;allow test to change I-flag (no mask) > 301b : 48 > pha ;use stack to load status -301c : bd5e02 > lda absEOa,x ;precharge accu +301c : bd6f02 > lda absEOa,x ;precharge accu 301f : 28 > plp -3020 : 5d5202 eor absEO,x +3020 : 5d6302 eor absEO,x tst_ax absrlo,absflo,0 3023 : 08 > php ;save flags -3024 : dd6202 > cmp absrlo,x ;test result +3024 : dd7302 > cmp absrlo,x ;test result > trap_ne 3027 : d0fe > bne * ;failed not equal (non zero) > @@ -12421,7 +12423,7 @@ ffff = ram_top = -1 > eor_flag 0 302a : 4930 > eor #0|fao ;invert expected flags + always on bits > -302c : dd6602 > cmp absflo,x ;test flags +302c : dd7702 > cmp absflo,x ;test flags > trap_ne ; 302f : d0fe > bne * ;failed not equal (non zero) > @@ -12435,13 +12437,13 @@ ffff = ram_top = -1 3036 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 3038 : 48 > pha ;use stack to load status -3039 : bd5e02 > lda absEOa,x ;precharge accu +3039 : bd6f02 > lda absEOa,x ;precharge accu 303c : 28 > plp -303d : 5d5202 eor absEO,x +303d : 5d6302 eor absEO,x tst_ax absrlo,absflo,$ff-fnz 3040 : 08 > php ;save flags -3041 : dd6202 > cmp absrlo,x ;test result +3041 : dd7302 > cmp absrlo,x ;test result > trap_ne 3044 : d0fe > bne * ;failed not equal (non zero) > @@ -12449,7 +12451,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 3047 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -3049 : dd6602 > cmp absflo,x ;test flags +3049 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 304c : d0fe > bne * ;failed not equal (non zero) > @@ -12464,13 +12466,13 @@ ffff = ram_top = -1 3053 : a900 > lda #0 ;allow test to change I-flag (no mask) > 3055 : 48 > pha ;use stack to load status -3056 : b95e02 > lda absEOa,y ;precharge accu +3056 : b96f02 > lda absEOa,y ;precharge accu 3059 : 28 > plp -305a : 595202 eor absEO,y +305a : 596302 eor absEO,y tst_ay absrlo,absflo,0 305d : 08 > php ;save flags -305e : d96202 > cmp absrlo,y ;test result +305e : d97302 > cmp absrlo,y ;test result > trap_ne ; 3061 : d0fe > bne * ;failed not equal (non zero) > @@ -12478,7 +12480,7 @@ ffff = ram_top = -1 > eor_flag 0 3064 : 4930 > eor #0|fao ;invert expected flags + always on bits > -3066 : d96602 > cmp absflo,y ;test flags +3066 : d97702 > cmp absflo,y ;test flags > trap_ne 3069 : d0fe > bne * ;failed not equal (non zero) > @@ -12492,13 +12494,13 @@ ffff = ram_top = -1 3070 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 3072 : 48 > pha ;use stack to load status -3073 : b95e02 > lda absEOa,y ;precharge accu +3073 : b96f02 > lda absEOa,y ;precharge accu 3076 : 28 > plp -3077 : 595202 eor absEO,y +3077 : 596302 eor absEO,y tst_ay absrlo,absflo,$ff-fnz 307a : 08 > php ;save flags -307b : d96202 > cmp absrlo,y ;test result +307b : d97302 > cmp absrlo,y ;test result > trap_ne ; 307e : d0fe > bne * ;failed not equal (non zero) > @@ -12506,7 +12508,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 3081 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -3083 : d96602 > cmp absflo,y ;test flags +3083 : d97702 > cmp absflo,y ;test flags > trap_ne 3086 : d0fe > bne * ;failed not equal (non zero) > @@ -12522,13 +12524,13 @@ ffff = ram_top = -1 308f : a900 > lda #0 ;allow test to change I-flag (no mask) > 3091 : 48 > pha ;use stack to load status -3092 : b95e02 > lda absEOa,y ;precharge accu +3092 : b96f02 > lda absEOa,y ;precharge accu 3095 : 28 > plp -3096 : 4142 eor (indEO,x) +3096 : 4144 eor (indEO,x) tst_ay absrlo,absflo,0 3098 : 08 > php ;save flags -3099 : d96202 > cmp absrlo,y ;test result +3099 : d97302 > cmp absrlo,y ;test result > trap_ne ; 309c : d0fe > bne * ;failed not equal (non zero) > @@ -12536,7 +12538,7 @@ ffff = ram_top = -1 > eor_flag 0 309f : 4930 > eor #0|fao ;invert expected flags + always on bits > -30a1 : d96602 > cmp absflo,y ;test flags +30a1 : d97702 > cmp absflo,y ;test flags > trap_ne 30a4 : d0fe > bne * ;failed not equal (non zero) > @@ -12553,13 +12555,13 @@ ffff = ram_top = -1 30af : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 30b1 : 48 > pha ;use stack to load status -30b2 : b95e02 > lda absEOa,y ;precharge accu +30b2 : b96f02 > lda absEOa,y ;precharge accu 30b5 : 28 > plp -30b6 : 4142 eor (indEO,x) +30b6 : 4144 eor (indEO,x) tst_ay absrlo,absflo,$ff-fnz 30b8 : 08 > php ;save flags -30b9 : d96202 > cmp absrlo,y ;test result +30b9 : d97302 > cmp absrlo,y ;test result > trap_ne ; 30bc : d0fe > bne * ;failed not equal (non zero) > @@ -12567,7 +12569,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 30bf : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -30c1 : d96602 > cmp absflo,y ;test flags +30c1 : d97702 > cmp absflo,y ;test flags > trap_ne 30c4 : d0fe > bne * ;failed not equal (non zero) > @@ -12584,13 +12586,13 @@ ffff = ram_top = -1 30cd : a900 > lda #0 ;allow test to change I-flag (no mask) > 30cf : 48 > pha ;use stack to load status -30d0 : b95e02 > lda absEOa,y ;precharge accu +30d0 : b96f02 > lda absEOa,y ;precharge accu 30d3 : 28 > plp -30d4 : 5142 eor (indEO),y +30d4 : 5144 eor (indEO),y tst_ay absrlo,absflo,0 30d6 : 08 > php ;save flags -30d7 : d96202 > cmp absrlo,y ;test result +30d7 : d97302 > cmp absrlo,y ;test result > trap_ne ; 30da : d0fe > bne * ;failed not equal (non zero) > @@ -12598,7 +12600,7 @@ ffff = ram_top = -1 > eor_flag 0 30dd : 4930 > eor #0|fao ;invert expected flags + always on bits > -30df : d96602 > cmp absflo,y ;test flags +30df : d97702 > cmp absflo,y ;test flags > trap_ne 30e2 : d0fe > bne * ;failed not equal (non zero) > @@ -12612,13 +12614,13 @@ ffff = ram_top = -1 30e9 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 30eb : 48 > pha ;use stack to load status -30ec : b95e02 > lda absEOa,y ;precharge accu +30ec : b96f02 > lda absEOa,y ;precharge accu 30ef : 28 > plp -30f0 : 5142 eor (indEO),y +30f0 : 5144 eor (indEO),y tst_ay absrlo,absflo,$ff-fnz 30f2 : 08 > php ;save flags -30f3 : d96202 > cmp absrlo,y ;test result +30f3 : d97302 > cmp absrlo,y ;test result > trap_ne ; 30f6 : d0fe > bne * ;failed not equal (non zero) > @@ -12626,7 +12628,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 30f9 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -30fb : d96602 > cmp absflo,y ;test flags +30fb : d97702 > cmp absflo,y ;test flags > trap_ne 30fe : d0fe > bne * ;failed not equal (non zero) > @@ -12647,20 +12649,20 @@ ffff = ram_top = -1 ; OR 310f : a203 ldx #3 ;immediate - self modifying code -3111 : b518 tora lda zpOR,x -3113 : 8d0f02 sta ex_orai+1 ;set ORA # operand +3111 : b51a tora lda zpOR,x +3113 : 8d1002 sta ex_orai+1 ;set ORA # operand set_ax absORa,0 > load_flag 0 3116 : a900 > lda #0 ;allow test to change I-flag (no mask) > 3118 : 48 > pha ;use stack to load status -3119 : bd5602 > lda absORa,x ;precharge accu +3119 : bd6702 > lda absORa,x ;precharge accu 311c : 28 > plp -311d : 200e02 jsr ex_orai ;execute ORA # in RAM +311d : 200f02 jsr ex_orai ;execute ORA # in RAM tst_ax absrlo,absflo,0 3120 : 08 > php ;save flags -3121 : dd6202 > cmp absrlo,x ;test result +3121 : dd7302 > cmp absrlo,x ;test result > trap_ne 3124 : d0fe > bne * ;failed not equal (non zero) > @@ -12668,7 +12670,7 @@ ffff = ram_top = -1 > eor_flag 0 3127 : 4930 > eor #0|fao ;invert expected flags + always on bits > -3129 : dd6602 > cmp absflo,x ;test flags +3129 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 312c : d0fe > bne * ;failed not equal (non zero) > @@ -12676,20 +12678,20 @@ ffff = ram_top = -1 312e : ca dex 312f : 10e0 bpl tora 3131 : a203 ldx #3 -3133 : b518 tora1 lda zpOR,x -3135 : 8d0f02 sta ex_orai+1 ;set ORA # operand +3133 : b51a tora1 lda zpOR,x +3135 : 8d1002 sta ex_orai+1 ;set ORA # operand set_ax absORa,$ff > load_flag $ff 3138 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 313a : 48 > pha ;use stack to load status -313b : bd5602 > lda absORa,x ;precharge accu +313b : bd6702 > lda absORa,x ;precharge accu 313e : 28 > plp -313f : 200e02 jsr ex_orai ;execute ORA # in RAM +313f : 200f02 jsr ex_orai ;execute ORA # in RAM tst_ax absrlo,absflo,$ff-fnz 3142 : 08 > php ;save flags -3143 : dd6202 > cmp absrlo,x ;test result +3143 : dd7302 > cmp absrlo,x ;test result > trap_ne 3146 : d0fe > bne * ;failed not equal (non zero) > @@ -12697,7 +12699,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 3149 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -314b : dd6602 > cmp absflo,x ;test flags +314b : dd7702 > cmp absflo,x ;test flags > trap_ne ; 314e : d0fe > bne * ;failed not equal (non zero) > @@ -12706,20 +12708,20 @@ ffff = ram_top = -1 3151 : 10e0 bpl tora1 3153 : a203 ldx #3 ;zp -3155 : b518 tora2 lda zpOR,x +3155 : b51a tora2 lda zpOR,x 3157 : 850c sta zpt set_ax absORa,0 > load_flag 0 3159 : a900 > lda #0 ;allow test to change I-flag (no mask) > 315b : 48 > pha ;use stack to load status -315c : bd5602 > lda absORa,x ;precharge accu +315c : bd6702 > lda absORa,x ;precharge accu 315f : 28 > plp 3160 : 050c ora zpt tst_ax absrlo,absflo,0 3162 : 08 > php ;save flags -3163 : dd6202 > cmp absrlo,x ;test result +3163 : dd7302 > cmp absrlo,x ;test result > trap_ne 3166 : d0fe > bne * ;failed not equal (non zero) > @@ -12727,7 +12729,7 @@ ffff = ram_top = -1 > eor_flag 0 3169 : 4930 > eor #0|fao ;invert expected flags + always on bits > -316b : dd6602 > cmp absflo,x ;test flags +316b : dd7702 > cmp absflo,x ;test flags > trap_ne ; 316e : d0fe > bne * ;failed not equal (non zero) > @@ -12735,20 +12737,20 @@ ffff = ram_top = -1 3170 : ca dex 3171 : 10e2 bpl tora2 3173 : a203 ldx #3 -3175 : b518 tora3 lda zpOR,x +3175 : b51a tora3 lda zpOR,x 3177 : 850c sta zpt set_ax absORa,$ff > load_flag $ff 3179 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 317b : 48 > pha ;use stack to load status -317c : bd5602 > lda absORa,x ;precharge accu +317c : bd6702 > lda absORa,x ;precharge accu 317f : 28 > plp 3180 : 050c ora zpt tst_ax absrlo,absflo,$ff-fnz 3182 : 08 > php ;save flags -3183 : dd6202 > cmp absrlo,x ;test result +3183 : dd7302 > cmp absrlo,x ;test result > trap_ne 3186 : d0fe > bne * ;failed not equal (non zero) > @@ -12756,7 +12758,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 3189 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -318b : dd6602 > cmp absflo,x ;test flags +318b : dd7702 > cmp absflo,x ;test flags > trap_ne ; 318e : d0fe > bne * ;failed not equal (non zero) > @@ -12765,20 +12767,20 @@ ffff = ram_top = -1 3191 : 10e2 bpl tora3 3193 : a203 ldx #3 ;abs -3195 : b518 tora4 lda zpOR,x +3195 : b51a tora4 lda zpOR,x 3197 : 8d0302 sta abst set_ax absORa,0 > load_flag 0 319a : a900 > lda #0 ;allow test to change I-flag (no mask) > 319c : 48 > pha ;use stack to load status -319d : bd5602 > lda absORa,x ;precharge accu +319d : bd6702 > lda absORa,x ;precharge accu 31a0 : 28 > plp 31a1 : 0d0302 ora abst tst_ax absrlo,absflo,0 31a4 : 08 > php ;save flags -31a5 : dd6202 > cmp absrlo,x ;test result +31a5 : dd7302 > cmp absrlo,x ;test result > trap_ne 31a8 : d0fe > bne * ;failed not equal (non zero) > @@ -12786,7 +12788,7 @@ ffff = ram_top = -1 > eor_flag 0 31ab : 4930 > eor #0|fao ;invert expected flags + always on bits > -31ad : dd6602 > cmp absflo,x ;test flags +31ad : dd7702 > cmp absflo,x ;test flags > trap_ne ; 31b0 : d0fe > bne * ;failed not equal (non zero) > @@ -12794,20 +12796,20 @@ ffff = ram_top = -1 31b2 : ca dex 31b3 : 10e0 bpl tora4 31b5 : a203 ldx #3 -31b7 : b518 tora5 lda zpOR,x +31b7 : b51a tora5 lda zpOR,x 31b9 : 8d0302 sta abst set_ax absORa,$ff > load_flag $ff 31bc : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 31be : 48 > pha ;use stack to load status -31bf : bd5602 > lda absORa,x ;precharge accu +31bf : bd6702 > lda absORa,x ;precharge accu 31c2 : 28 > plp 31c3 : 0d0302 ora abst tst_ax absrlo,absflo,$ff-fnz 31c6 : 08 > php ;save flags -31c7 : dd6202 > cmp absrlo,x ;test result +31c7 : dd7302 > cmp absrlo,x ;test result > trap_ne 31ca : d0fe > bne * ;failed not equal (non zero) > @@ -12815,7 +12817,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 31cd : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -31cf : dd6602 > cmp absflo,x ;test flags +31cf : dd7702 > cmp absflo,x ;test flags > trap_ne ; 31d2 : d0fe > bne * ;failed not equal (non zero) > @@ -12830,13 +12832,13 @@ ffff = ram_top = -1 31d9 : a900 > lda #0 ;allow test to change I-flag (no mask) > 31db : 48 > pha ;use stack to load status -31dc : bd5602 > lda absORa,x ;precharge accu +31dc : bd6702 > lda absORa,x ;precharge accu 31df : 28 > plp -31e0 : 1518 ora zpOR,x +31e0 : 151a ora zpOR,x tst_ax absrlo,absflo,0 31e2 : 08 > php ;save flags -31e3 : dd6202 > cmp absrlo,x ;test result +31e3 : dd7302 > cmp absrlo,x ;test result > trap_ne 31e6 : d0fe > bne * ;failed not equal (non zero) > @@ -12844,7 +12846,7 @@ ffff = ram_top = -1 > eor_flag 0 31e9 : 4930 > eor #0|fao ;invert expected flags + always on bits > -31eb : dd6602 > cmp absflo,x ;test flags +31eb : dd7702 > cmp absflo,x ;test flags > trap_ne ; 31ee : d0fe > bne * ;failed not equal (non zero) > @@ -12858,13 +12860,13 @@ ffff = ram_top = -1 31f5 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 31f7 : 48 > pha ;use stack to load status -31f8 : bd5602 > lda absORa,x ;precharge accu +31f8 : bd6702 > lda absORa,x ;precharge accu 31fb : 28 > plp -31fc : 1518 ora zpOR,x +31fc : 151a ora zpOR,x tst_ax absrlo,absflo,$ff-fnz 31fe : 08 > php ;save flags -31ff : dd6202 > cmp absrlo,x ;test result +31ff : dd7302 > cmp absrlo,x ;test result > trap_ne 3202 : d0fe > bne * ;failed not equal (non zero) > @@ -12872,7 +12874,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 3205 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -3207 : dd6602 > cmp absflo,x ;test flags +3207 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 320a : d0fe > bne * ;failed not equal (non zero) > @@ -12887,13 +12889,13 @@ ffff = ram_top = -1 3211 : a900 > lda #0 ;allow test to change I-flag (no mask) > 3213 : 48 > pha ;use stack to load status -3214 : bd5602 > lda absORa,x ;precharge accu +3214 : bd6702 > lda absORa,x ;precharge accu 3217 : 28 > plp -3218 : 1d4a02 ora absOR,x +3218 : 1d5b02 ora absOR,x tst_ax absrlo,absflo,0 321b : 08 > php ;save flags -321c : dd6202 > cmp absrlo,x ;test result +321c : dd7302 > cmp absrlo,x ;test result > trap_ne 321f : d0fe > bne * ;failed not equal (non zero) > @@ -12901,7 +12903,7 @@ ffff = ram_top = -1 > eor_flag 0 3222 : 4930 > eor #0|fao ;invert expected flags + always on bits > -3224 : dd6602 > cmp absflo,x ;test flags +3224 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 3227 : d0fe > bne * ;failed not equal (non zero) > @@ -12915,13 +12917,13 @@ ffff = ram_top = -1 322e : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 3230 : 48 > pha ;use stack to load status -3231 : bd5602 > lda absORa,x ;precharge accu +3231 : bd6702 > lda absORa,x ;precharge accu 3234 : 28 > plp -3235 : 1d4a02 ora absOR,x +3235 : 1d5b02 ora absOR,x tst_ax absrlo,absflo,$ff-fnz 3238 : 08 > php ;save flags -3239 : dd6202 > cmp absrlo,x ;test result +3239 : dd7302 > cmp absrlo,x ;test result > trap_ne 323c : d0fe > bne * ;failed not equal (non zero) > @@ -12929,7 +12931,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 323f : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -3241 : dd6602 > cmp absflo,x ;test flags +3241 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 3244 : d0fe > bne * ;failed not equal (non zero) > @@ -12944,13 +12946,13 @@ ffff = ram_top = -1 324b : a900 > lda #0 ;allow test to change I-flag (no mask) > 324d : 48 > pha ;use stack to load status -324e : b95602 > lda absORa,y ;precharge accu +324e : b96702 > lda absORa,y ;precharge accu 3251 : 28 > plp -3252 : 194a02 ora absOR,y +3252 : 195b02 ora absOR,y tst_ay absrlo,absflo,0 3255 : 08 > php ;save flags -3256 : d96202 > cmp absrlo,y ;test result +3256 : d97302 > cmp absrlo,y ;test result > trap_ne ; 3259 : d0fe > bne * ;failed not equal (non zero) > @@ -12958,7 +12960,7 @@ ffff = ram_top = -1 > eor_flag 0 325c : 4930 > eor #0|fao ;invert expected flags + always on bits > -325e : d96602 > cmp absflo,y ;test flags +325e : d97702 > cmp absflo,y ;test flags > trap_ne 3261 : d0fe > bne * ;failed not equal (non zero) > @@ -12972,13 +12974,13 @@ ffff = ram_top = -1 3268 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 326a : 48 > pha ;use stack to load status -326b : b95602 > lda absORa,y ;precharge accu +326b : b96702 > lda absORa,y ;precharge accu 326e : 28 > plp -326f : 194a02 ora absOR,y +326f : 195b02 ora absOR,y tst_ay absrlo,absflo,$ff-fnz 3272 : 08 > php ;save flags -3273 : d96202 > cmp absrlo,y ;test result +3273 : d97302 > cmp absrlo,y ;test result > trap_ne ; 3276 : d0fe > bne * ;failed not equal (non zero) > @@ -12986,7 +12988,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 3279 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -327b : d96602 > cmp absflo,y ;test flags +327b : d97702 > cmp absflo,y ;test flags > trap_ne 327e : d0fe > bne * ;failed not equal (non zero) > @@ -13002,13 +13004,13 @@ ffff = ram_top = -1 3287 : a900 > lda #0 ;allow test to change I-flag (no mask) > 3289 : 48 > pha ;use stack to load status -328a : b95602 > lda absORa,y ;precharge accu +328a : b96702 > lda absORa,y ;precharge accu 328d : 28 > plp -328e : 014a ora (indOR,x) +328e : 014c ora (indOR,x) tst_ay absrlo,absflo,0 3290 : 08 > php ;save flags -3291 : d96202 > cmp absrlo,y ;test result +3291 : d97302 > cmp absrlo,y ;test result > trap_ne ; 3294 : d0fe > bne * ;failed not equal (non zero) > @@ -13016,7 +13018,7 @@ ffff = ram_top = -1 > eor_flag 0 3297 : 4930 > eor #0|fao ;invert expected flags + always on bits > -3299 : d96602 > cmp absflo,y ;test flags +3299 : d97702 > cmp absflo,y ;test flags > trap_ne 329c : d0fe > bne * ;failed not equal (non zero) > @@ -13033,13 +13035,13 @@ ffff = ram_top = -1 32a7 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 32a9 : 48 > pha ;use stack to load status -32aa : b95602 > lda absORa,y ;precharge accu +32aa : b96702 > lda absORa,y ;precharge accu 32ad : 28 > plp -32ae : 014a ora (indOR,x) +32ae : 014c ora (indOR,x) tst_ay absrlo,absflo,$ff-fnz 32b0 : 08 > php ;save flags -32b1 : d96202 > cmp absrlo,y ;test result +32b1 : d97302 > cmp absrlo,y ;test result > trap_ne ; 32b4 : d0fe > bne * ;failed not equal (non zero) > @@ -13047,7 +13049,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 32b7 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -32b9 : d96602 > cmp absflo,y ;test flags +32b9 : d97702 > cmp absflo,y ;test flags > trap_ne 32bc : d0fe > bne * ;failed not equal (non zero) > @@ -13064,13 +13066,13 @@ ffff = ram_top = -1 32c5 : a900 > lda #0 ;allow test to change I-flag (no mask) > 32c7 : 48 > pha ;use stack to load status -32c8 : b95602 > lda absORa,y ;precharge accu +32c8 : b96702 > lda absORa,y ;precharge accu 32cb : 28 > plp -32cc : 114a ora (indOR),y +32cc : 114c ora (indOR),y tst_ay absrlo,absflo,0 32ce : 08 > php ;save flags -32cf : d96202 > cmp absrlo,y ;test result +32cf : d97302 > cmp absrlo,y ;test result > trap_ne ; 32d2 : d0fe > bne * ;failed not equal (non zero) > @@ -13078,7 +13080,7 @@ ffff = ram_top = -1 > eor_flag 0 32d5 : 4930 > eor #0|fao ;invert expected flags + always on bits > -32d7 : d96602 > cmp absflo,y ;test flags +32d7 : d97702 > cmp absflo,y ;test flags > trap_ne 32da : d0fe > bne * ;failed not equal (non zero) > @@ -13092,13 +13094,13 @@ ffff = ram_top = -1 32e1 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 32e3 : 48 > pha ;use stack to load status -32e4 : b95602 > lda absORa,y ;precharge accu +32e4 : b96702 > lda absORa,y ;precharge accu 32e7 : 28 > plp -32e8 : 114a ora (indOR),y +32e8 : 114c ora (indOR),y tst_ay absrlo,absflo,$ff-fnz 32ea : 08 > php ;save flags -32eb : d96202 > cmp absrlo,y ;test result +32eb : d97302 > cmp absrlo,y ;test result > trap_ne ; 32ee : d0fe > bne * ;failed not equal (non zero) > @@ -13106,7 +13108,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 32f1 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -32f3 : d96602 > cmp absflo,y ;test flags +32f3 : d97702 > cmp absflo,y ;test flags > trap_ne 32f6 : d0fe > bne * ;failed not equal (non zero) > @@ -13452,9 +13454,9 @@ ffff = ram_top = -1 ; decimal ADC / SBC # 34b9 : 08 php ;save carry for subtract 34ba : a50e lda ad2 -34bc : 8d1202 sta ex_adci+1 ;set ADC # operand +34bc : 8d1302 sta ex_adci+1 ;set ADC # operand 34bf : a50d lda ad1 -34c1 : 201102 jsr ex_adci ;execute ADC # in RAM +34c1 : 201202 jsr ex_adci ;execute ADC # in RAM 34c4 : 08 php 34c5 : c50f cmp adrl ;check result trap_ne ;bad result @@ -13469,9 +13471,9 @@ ffff = ram_top = -1 34d0 : 28 plp 34d1 : 08 php ;save carry for next add 34d2 : a512 lda sb2 -34d4 : 8d1502 sta ex_sbci+1 ;set SBC # operand +34d4 : 8d1602 sta ex_sbci+1 ;set SBC # operand 34d7 : a50d lda ad1 -34d9 : 201402 jsr ex_sbci ;execute SBC # in RAM +34d9 : 201502 jsr ex_sbci ;execute SBC # in RAM 34dc : 08 php 34dd : c50f cmp adrl ;check result trap_ne ;bad result @@ -13580,7 +13582,7 @@ ffff = ram_top = -1 ; decimal ADC / SBC (zp,x) 3559 : 08 php ;save carry for subtract 355a : a50d lda ad1 -355c : 6144 adc (lo adi2-ad2,x) ;perform add +355c : 6146 adc (lo adi2-ad2,x) ;perform add 355e : 08 php 355f : c50f cmp adrl ;check result trap_ne ;bad result @@ -13595,7 +13597,7 @@ ffff = ram_top = -1 356a : 28 plp 356b : 08 php ;save carry for next add 356c : a50d lda ad1 -356e : e146 sbc (lo sbi2-ad2,x) ;perform subtract +356e : e148 sbc (lo sbi2-ad2,x) ;perform subtract 3570 : 08 php 3571 : c50f cmp adrl ;check result trap_ne ;bad result @@ -13611,7 +13613,7 @@ ffff = ram_top = -1 ; decimal ADC / SBC (abs),y 357d : 08 php ;save carry for subtract 357e : a50d lda ad1 -3580 : 7156 adc (adiy2),y ;perform add +3580 : 7158 adc (adiy2),y ;perform add 3582 : 08 php 3583 : c50f cmp adrl ;check result trap_ne ;bad result @@ -13626,7 +13628,7 @@ ffff = ram_top = -1 358e : 28 plp 358f : 08 php ;save carry for next add 3590 : a50d lda ad1 -3592 : f158 sbc (sbiy2),y ;perform subtract +3592 : f15a sbc (sbiy2),y ;perform subtract 3594 : 08 php 3595 : c50f cmp adrl ;check result trap_ne ;bad result @@ -13724,9 +13726,9 @@ ffff = ram_top = -1 ; binary ADC / SBC # 3604 : 08 php ;save carry for subtract 3605 : a50e lda ad2 -3607 : 8d1202 sta ex_adci+1 ;set ADC # operand +3607 : 8d1302 sta ex_adci+1 ;set ADC # operand 360a : a50d lda ad1 -360c : 201102 jsr ex_adci ;execute ADC # in RAM +360c : 201202 jsr ex_adci ;execute ADC # in RAM 360f : 08 php 3610 : c50f cmp adrl ;check result trap_ne ;bad result @@ -13741,9 +13743,9 @@ ffff = ram_top = -1 361b : 28 plp 361c : 08 php ;save carry for next add 361d : a512 lda sb2 -361f : 8d1502 sta ex_sbci+1 ;set SBC # operand +361f : 8d1602 sta ex_sbci+1 ;set SBC # operand 3622 : a50d lda ad1 -3624 : 201402 jsr ex_sbci ;execute SBC # in RAM +3624 : 201502 jsr ex_sbci ;execute SBC # in RAM 3627 : 08 php 3628 : c50f cmp adrl ;check result trap_ne ;bad result @@ -13852,7 +13854,7 @@ ffff = ram_top = -1 ; binary ADC / SBC (zp,x) 36a4 : 08 php ;save carry for subtract 36a5 : a50d lda ad1 -36a7 : 6144 adc (lo adi2-ad2,x) ;perform add +36a7 : 6146 adc (lo adi2-ad2,x) ;perform add 36a9 : 08 php 36aa : c50f cmp adrl ;check result trap_ne ;bad result @@ -13867,7 +13869,7 @@ ffff = ram_top = -1 36b5 : 28 plp 36b6 : 08 php ;save carry for next add 36b7 : a50d lda ad1 -36b9 : e146 sbc (lo sbi2-ad2,x) ;perform subtract +36b9 : e148 sbc (lo sbi2-ad2,x) ;perform subtract 36bb : 08 php 36bc : c50f cmp adrl ;check result trap_ne ;bad result @@ -13883,7 +13885,7 @@ ffff = ram_top = -1 ; binary ADC / SBC (abs),y 36c8 : 08 php ;save carry for subtract 36c9 : a50d lda ad1 -36cb : 7156 adc (adiy2),y ;perform add +36cb : 7158 adc (adiy2),y ;perform add 36cd : 08 php 36ce : c50f cmp adrl ;check result trap_ne ;bad result @@ -13898,7 +13900,7 @@ ffff = ram_top = -1 36d9 : 28 plp 36da : 08 php ;save carry for next add 36db : a50d lda ad1 -36dd : f158 sbc (sbiy2),y ;perform subtract +36dd : f15a sbc (sbiy2),y ;perform subtract 36df : 08 php 36e0 : c50f cmp adrl ;check result trap_ne ;bad result @@ -14249,6 +14251,7 @@ ffff = ram_top = -1 ;copy of data to initialize BSS segment if load_data_direct != 1 zp_init + zps_ db $80,1 ;additional shift pattern to test zero result & flag zp1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR zp7f_ db $7f ;test pattern for compare ;logical zeropage operands @@ -14300,34 +14303,35 @@ ffff = ram_top = -1 rts ex_sbc_ sbc #0 ;execute immediate opcodes rts + ;zps db $80,1 ;additional shift patterns test zero result & flag abs1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR abs7f_ db $7f ;test pattern for compare ;loads - fLDx_ db fn,fn,0,fz ;expected flags for load + fLDx_ db fn,fn,0,fz ;expected flags for load ;shifts - rASL_ ;expected result ASL & ROL -carry - rROL_ db $86,$04,$82,0 ; " - rROLc_ db $87,$05,$83,1 ;expected result ROL +carry - rLSR_ ;expected result LSR & ROR -carry - rROR_ db $61,$41,$20,0 ; " - rRORc_ db $e1,$c1,$a0,$80 ;expected result ROR +carry - fASL_ ;expected flags for shifts - fROL_ db fnc,fc,fn,fz ;no carry in - fROLc_ db fnc,fc,fn,0 ;carry in + rASL_ ;expected result ASL & ROL -carry + rROL_ db 0,2,$86,$04,$82,0 + rROLc_ db 1,3,$87,$05,$83,1 ;expected result ROL +carry + rLSR_ ;expected result LSR & ROR -carry + rROR_ db $40,0,$61,$41,$20,0 + rRORc_ db $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry + fASL_ ;expected flags for shifts + fROL_ db fzc,0,fnc,fc,fn,fz ;no carry in + fROLc_ db fc,0,fnc,fc,fn,0 ;carry in fLSR_ - fROR_ db fc,0,fc,fz ;no carry in - fRORc_ db fnc,fn,fnc,fn ;carry in + fROR_ db 0,fzc,fc,0,fc,fz ;no carry in + fRORc_ db fn,fnc,fnc,fn,fnc,fn ;carry in ;increments (decrements) - rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC - fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC + rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC + fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC ;logical memory operand - absOR_ db 0,$1f,$71,$80 ;test pattern for OR - absAN_ db $0f,$ff,$7f,$80 ;test pattern for AND - absEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR + absOR_ db 0,$1f,$71,$80 ;test pattern for OR + absAN_ db $0f,$ff,$7f,$80 ;test pattern for AND + absEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR ;logical accu operand - absORa_ db 0,$f1,$1f,0 ;test pattern for OR - absANa_ db $f0,$ff,$ff,$ff ;test pattern for AND - absEOa_ db $ff,$f0,$f0,$0f ;test pattern for EOR + absORa_ db 0,$f1,$1f,0 ;test pattern for OR + absANa_ db $f0,$ff,$ff,$ff ;test pattern for AND + absEOa_ db $ff,$f0,$f0,$0f ;test pattern for EOR ;logical results absrlo_ db 0,$ff,$7f,$80 absflo_ db fz,fn,0,fn @@ -14354,7 +14358,7 @@ fffe : ab37 dw irq_trap fffa = end start No errors in pass 2. -Wrote binary from address $0000 through $ffff. -Total size 65536 bytes. +Wrote binary from address $000a through $ffff. +Total size 65526 bytes. Program start address is at $0400 (1024). \ No newline at end of file diff --git a/src/test/kotlin/6502_functional_tests/bin_files/6502_interrupt_test.bin b/src/test/kotlin/6502_functional_tests/bin_files/6502_interrupt_test.bin new file mode 100644 index 0000000..52a3f6b Binary files /dev/null and b/src/test/kotlin/6502_functional_tests/bin_files/6502_interrupt_test.bin differ diff --git a/src/test/kotlin/6502_functional_tests/bin_files/6502_interrupt_test.lst b/src/test/kotlin/6502_functional_tests/bin_files/6502_interrupt_test.lst new file mode 100644 index 0000000..4f12385 --- /dev/null +++ b/src/test/kotlin/6502_functional_tests/bin_files/6502_interrupt_test.lst @@ -0,0 +1,1375 @@ +AS65 Assembler for R6502 [1.42]. Copyright 1994-2007, Frank A. Kingswood Page 1 +---------------------------------------------------- 6502_interrupt_test.a65 ----------------------------------------------------- + +1025 lines read, no errors in pass 1. + ; + ; 6 5 0 2 I N T E R R U P T T E S T + ; + ; Copyright (C) 2013 Klaus Dormann + ; + ; This program is free software: you can redistribute it and/or modify + ; it under the terms of the GNU General Public License as published by + ; the Free Software Foundation, either version 3 of the License, or + ; (at your option) any later version. + ; + ; This program is distributed in the hope that it will be useful, + ; but WITHOUT ANY WARRANTY; without even the implied warranty of + ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + ; GNU General Public License for more details. + ; + ; You should have received a copy of the GNU General Public License + ; along with this program. If not, see . + + + ; This program is designed to test IRQ and NMI of a 6502 emulator. It requires + ; an internal or external feedback register to the IRQ & NMI inputs + ; + ; version 15-aug-2014 + ; contact info at http://2m5.de or email K@2m5.de + ; + ; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/ + ; command line switches: -l -m -s2 -w -h0 + ; | | | | no page headers in listing + ; | | | wide listing (133 char/col) + ; | | write intel hex file instead of binary + ; | expand macros in listing + ; generate pass2 listing + ; + ; No IO - should be run from a monitor with access to registers. + ; To run load intel hex image with a load command, than alter PC to 400 hex and + ; enter a go command. + ; Loop on program counter determines error or successful completion of test. + ; Check listing for relevant traps (jump/branch *). + ; + ; Debugging hints: + ; Most of the code is written sequentially. if you hit a trap, check the + ; immediately preceeding code for the instruction to be tested. Results are + ; tested first, flags are checked second by pushing them onto the stack and + ; pulling them to the accumulator after the result was checked. The "real" + ; flags are no longer valid for the tested instruction at this time! + ; If the tested instruction was indexed, the relevant index (X or Y) must + ; also be checked. Opposed to the flags, X and Y registers are still valid. + ; + ; versions: + ; 19-jul-2013 1st version distributed for testing + ; 16-aug-2013 added error report to standard output option + ; 15-aug-2014 added filter to feedback (bit 7 will cause diag stop in emu) + + + ; C O N F I G U R A T I O N + ; + ;ROM_vectors MUST be writable & the I_flag MUST be alterable + + ;load_data_direct (0=move from code segment, 1=load directly) + ;loading directly is preferred but may not be supported by your platform + ;0 produces only consecutive object code, 1 is not suitable for a binary image +0001 = load_data_direct = 1 + + ;NMI & IRQ are tested with a feedback register + ;emulators diag register - set i_drive = 0 for a latch (74HC573) +bffc = I_port = $bffc ;feedback port address +0000 = I_ddr = 0 ;feedback DDR address, 0 = no DDR +0001 = I_drive = 1 ;0 = totem pole, 1 = open collector +0000 = IRQ_bit = 0 ;bit number of feedback to IRQ +0001 = NMI_bit = 1 ;bit number of feedback to NMI, -1 if not available +007f = I_filter = $7f ;filtering bit 7 = diag stop + + ;typical IO chip port B - set i_drive = 0 to avoid pullup resistors + ;I_port = $bfb2 ;feedback port address + ;I_ddr = $bfb3 ;feedback DDR address, 0 = no DDR + ;I_drive = 1 ;0 = totem pole, 1 = open collector + ;IRQ_bit = 0 ;bit number of feedback to IRQ + ;NMI_bit = 1 ;bit number of feedback to NMI, -1 if not available + ;I_filter = $ff ;no bits filtered + + ;decimal mode flag during IRQ, NMI & BRK +0000 = D_clear = 0 ;0 = not cleared (NMOS), 1 = cleared (CMOS) + + ;configure memory - try to stay away from memory used by the system + ;zero_page memory start address, 6 consecutive Bytes required +000a = zero_page = $a + + ;data_segment memory start address, 4 consecutive Bytes required +0200 = data_segment = $200 + + ;code_segment memory start address +0400 = code_segment = $400 + + ;report errors through I/O channel (0=use standard self trap loops, 1=include + ;report.i65 as I/O channel) +0000 = report = 0 + + noopt ;do not take shortcuts + + ;macros for error & success traps to allow user modification + ;example: + ;trap macro + ; jsr my_error_handler + ; endm + ;trap_eq macro + ; bne skip\? + ; trap ;failed equal (zero) + ;skip\? + ; endm + ; + ; my_error_handler should pop the calling address from the stack and report it. + ; putting larger portions of code (more than 3 bytes) inside the trap macro + ; may lead to branch range problems for some tests. + if report = 0 + trap macro + jmp * ;failed anyway + endm + trap_eq macro + beq * ;failed equal (zero) + endm + trap_ne macro + bne * ;failed not equal (non zero) + endm + ; please observe that during the test the stack gets invalidated + ; therefore a RTS inside the success macro is not possible + success macro + jmp * ;test passed, no errors + endm + endif + if report = 1 + trap macro + jsr report_error + endm + trap_eq macro + bne skip\? + trap ;failed equal (zero) + skip\? + endm + trap_ne macro + beq skip\? + trap ;failed not equal (non zero) + skip\? + endm + ; please observe that during the test the stack gets invalidated + ; therefore a RTS inside the success macro is not possible + success macro + jsr report_success + endm + endif + + +0001 = carry equ %00000001 ;flag bits in status +0002 = zero equ %00000010 +0004 = intdis equ %00000100 +0008 = decmode equ %00001000 +0010 = break equ %00010000 +0020 = reserv equ %00100000 +0040 = overfl equ %01000000 +0080 = minus equ %10000000 + +0001 = fc equ carry +0002 = fz equ zero +0003 = fzc equ carry+zero +0040 = fv equ overfl +0042 = fvz equ overfl+zero +0080 = fn equ minus +0081 = fnc equ minus+carry +0082 = fnz equ minus+zero +0083 = fnzc equ minus+zero+carry +00c0 = fnv equ minus+overfl + +0030 = fao equ break+reserv ;bits always on after PHP, BRK +0034 = fai equ fao+intdis ;+ forced interrupt disable +00ff = m8 equ $ff ;8 bit mask +00fb = m8i equ $ff&~intdis ;8 bit mask - interrupt disable + + ;macros to set status + push_stat macro ;setting flags in the processor status register + lda #\1 + pha ;use stack to load status + endm + + set_stat macro ;setting flags in the processor status register + lda #\1 + pha ;use stack to load status + plp + endm + + if load_data_direct = 1 + data + else + bss ;uninitialized segment, copy of data at end of code! + endif +000a = org zero_page + ;BRK, IRQ, NMI test interrupt save +000a : zpt +000a : 00 irq_a ds 1 ;a register +000b : 00 irq_x ds 1 ;x register +000c : 00 irq_f ds 1 ;flags +000d : 00 nmi_a ds 1 ;a register +000e : 00 nmi_x ds 1 ;x register +000f : 00 nmi_f ds 1 ;flags +0010 : zp_bss + + ;fixed stack locations +01fe = lst_f equ $1fe ;last flags before interrupt +01ff = lst_a equ $1ff ;last accumulator before interrupt + +0200 = org data_segment + ;concurrent NMI, IRQ & BRK test result +0200 : 00 nmi_count ds 1 ;lowest number handled first, $ff = never +0201 : 00 irq_count ds 1 ;separation-1 = instructions between interrupts +0202 : 00 brk_count ds 1 + ;expected interrupt mask +0203 : 00 I_src ds 1 ;bit: 0=BRK, 1=IRQ, 2=NMI +0204 : data_bss + + code +0400 = org code_segment +0400 : d8 start cld +0401 : a900 lda #0 ;clear expected interrupts for 2nd run +0403 : 8d0302 sta I_src +0406 : a2ff ldx #$ff +0408 : 9a txs + + ;initialize I/O for report channel + if report = 1 + jsr report_init + endif + + ; load system vectors + if load_data_direct != 1 + ldx #5 + ld_vect lda vec_init,x + sta vec_bss,x + dex + bpl ld_vect + endif + + ; IRQ & NMI test - requires a feedback register + if I_drive > 1 + ERROR ;invalid interrupt drive! + endif + if NMI_bit < 0 + if I_drive = 0 ;totem pole (push/pull, 0 -> I_port to force interrupt) + I_set macro ibit ;ibit = interrupt bit + lda I_port ;turn on interrupt by bit + and #I_filter-(1<<\1) + plp ;set flags + pha ;save to verify + php + sta I_port ;interrupt next instruction plus outbound delay + endm + I_clr macro ibit ;ibit = interrupt bit + lda I_port ;turn off interrupt by bit + and #I_filter + ora #(1< I_DDR or I_port to force interrupt + if I_ddr != 0 ;with DDR + I_set macro ibit ;ibit = interrupt bit + lda I_ddr ;turn on interrupt by bit + and #I_filter + ora #(1<<\1) + plp ;set flags + pha ;save to verify + php + sta I_ddr ;interrupt next instruction plus outbound delay + endm + I_clr macro ibit ;ibit = interrupt bit + lda I_ddr ;turn off interrupt by bit + and #I_filter-(1< I_port to force interrupt) + I_set macro ibit ;ibit = interrupt bit + lda I_port ;turn on interrupt by bit + if ibit > 7 ;set both NMI & IRQ + and #I_filter-(1< I_DDR or I_port to force interrupt + if I_ddr != 0 ;with DDR + I_set macro ibit ;ibit = interrupt bit + lda I_ddr ;turn on interrupt by bit + and #I_filter + if ibit > 7 ;set both NMI & IRQ + ora #(1< 7 ;set both NMI & IRQ + ora #(1< lda I_port ;turn off interrupt by bit +040c : 297e > and #I_filter-(1< sta I_port + + I_clr NMI_bit +0411 : adfcbf > lda I_port ;turn off interrupt by bit +0414 : 297d > and #I_filter-(1< sta I_port + + endif + endif + endif + + ; IRQ integrity test + ; test for clear flags seen in IRQ vector +0419 : a902 lda #2 ;set expected interrupt source IRQ +041b : 8d0302 sta I_src + push_stat 0 +041e : a900 > lda #0 +0420 : 48 > pha ;use stack to load status + + I_set IRQ_bit +0421 : adfcbf > lda I_port ;turn on interrupt by bit +0424 : 297f > and #I_filter + > if IRQ_bit > 7 ;set both NMI & IRQ + > ora #(1< else +0426 : 0901 > ora #(1< endif +0428 : 28 > plp ;set flags +0429 : 48 > pha ;save to verify +042a : 08 > php +042b : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +042e : ea nop ;allow 6 cycles for interrupt to trip +042f : ea nop +0430 : ea nop +0431 : ad0302 lda I_src + trap_ne ;IRQ timeout +0434 : d0fe > bne * ;failed not equal (non zero) + +0436 : ba tsx +0437 : e0fd cpx #$ff-2 ;original accu & flags remain on stack + trap_ne ;returned SP +0439 : d0fe > bne * ;failed not equal (non zero) + +043b : a50c lda irq_f ;flags seen in IRQ vector + if D_clear = 1 + and #decmode + trap_ne ;D-flag not cleared + lda irq_f + eor lst_f ;turn off unchanged bits + and #m8-fai-decmode ;mask untested other flags + trap_ne ;other flags (N,V,Z,C) changed + else +043d : 4dfe01 eor lst_f ;turn off unchanged bits +0440 : 29cb and #m8-fai ;mask untested other flags + trap_ne ;other flags (N,V,Z,C,D) changed +0442 : d0fe > bne * ;failed not equal (non zero) + + endif +0444 : a2ff ldx #$ff ;reset stack pointer +0446 : 9a txs + ; test all other registers +0447 : a249 ldx #'I' +0449 : a052 ldy #'R' +044b : a902 lda #2 ;set expected interrupt source IRQ +044d : 8d0302 sta I_src + push_stat 0 +0450 : a900 > lda #0 +0452 : 48 > pha ;use stack to load status + + I_set IRQ_bit +0453 : adfcbf > lda I_port ;turn on interrupt by bit +0456 : 297f > and #I_filter + > if IRQ_bit > 7 ;set both NMI & IRQ + > ora #(1< else +0458 : 0901 > ora #(1< endif +045a : 28 > plp ;set flags +045b : 48 > pha ;save to verify +045c : 08 > php +045d : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +0460 : 88 dey ;Y count will fail, if instructions are skipped +0461 : 88 dey +0462 : 88 dey +0463 : 88 dey +0464 : 08 php ;check processor status later +0465 : e04a cpx #('I'+1) ;returned registers OK? + trap_ne ;returned X +0467 : d0fe > bne * ;failed not equal (non zero) + +0469 : c04b cpy #('R'-7) + trap_ne ;returned Y +046b : d0fe > bne * ;failed not equal (non zero) + +046d : c951 cmp #'Q' + trap_ne ;returned A +046f : d0fe > bne * ;failed not equal (non zero) + +0471 : ba tsx +0472 : e0fc cpx #$ff-3 + trap_ne ;returned SP +0474 : d0fe > bne * ;failed not equal (non zero) + +0476 : 68 pla ;flags +0477 : 4dfe01 eor lst_f +047a : 297d and #$ff-fnz ;ignore flags changed by dey + trap_ne ;returned flags +047c : d0fe > bne * ;failed not equal (non zero) + +047e : a50a lda irq_a ;accu seen in IRQ vector +0480 : cdff01 cmp lst_a + trap_ne ;IRQ A received +0483 : d0fe > bne * ;failed not equal (non zero) + +0485 : a2ff ldx #$ff ;reset stack pointer +0487 : 9a txs + ; repeat with reversed registers +0488 : a2b6 ldx #$ff-'I' +048a : a0ad ldy #$ff-'R' +048c : a902 lda #2 ;set expected interrupt source IRQ +048e : 8d0302 sta I_src + push_stat $ff-intdis +0491 : a9fb > lda #$ff-intdis +0493 : 48 > pha ;use stack to load status + + I_set IRQ_bit +0494 : adfcbf > lda I_port ;turn on interrupt by bit +0497 : 297f > and #I_filter + > if IRQ_bit > 7 ;set both NMI & IRQ + > ora #(1< else +0499 : 0901 > ora #(1< endif +049b : 28 > plp ;set flags +049c : 48 > pha ;save to verify +049d : 08 > php +049e : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +04a1 : 88 dey ;Y count will fail, if instructions are skipped +04a2 : 88 dey +04a3 : 88 dey +04a4 : 88 dey +04a5 : 08 php ;check processor status later +04a6 : e0b7 cpx #($ff-'I'+1) ;returned registers OK? + trap_ne ;returned X +04a8 : d0fe > bne * ;failed not equal (non zero) + +04aa : c0a6 cpy #($ff-'R'-7) + trap_ne ;returned Y +04ac : d0fe > bne * ;failed not equal (non zero) + +04ae : c951 cmp #'Q' + trap_ne ;returned A +04b0 : d0fe > bne * ;failed not equal (non zero) + +04b2 : ba tsx +04b3 : e0fc cpx #$ff-3 + trap_ne ;returned SP +04b5 : d0fe > bne * ;failed not equal (non zero) + +04b7 : 68 pla ;flags +04b8 : 4dfe01 eor lst_f +04bb : 297d and #$ff-fnz ;ignore flags changed by dey + trap_ne ;returned flags +04bd : d0fe > bne * ;failed not equal (non zero) + +04bf : a50a lda irq_a ;accu seen in IRQ vector +04c1 : cdff01 cmp lst_a + trap_ne ;IRQ A received +04c4 : d0fe > bne * ;failed not equal (non zero) + +04c6 : a2ff ldx #$ff ;reset stack pointer +04c8 : 9a txs + ; retest for set flags seen in IRQ vector +04c9 : a902 lda #2 ;set expected interrupt source IRQ +04cb : 8d0302 sta I_src + push_stat $ff-intdis +04ce : a9fb > lda #$ff-intdis +04d0 : 48 > pha ;use stack to load status + + I_set IRQ_bit +04d1 : adfcbf > lda I_port ;turn on interrupt by bit +04d4 : 297f > and #I_filter + > if IRQ_bit > 7 ;set both NMI & IRQ + > ora #(1< else +04d6 : 0901 > ora #(1< endif +04d8 : 28 > plp ;set flags +04d9 : 48 > pha ;save to verify +04da : 08 > php +04db : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +04de : ea nop ;allow 6 cycles for interrupt to trip +04df : ea nop +04e0 : ea nop +04e1 : ad0302 lda I_src + trap_ne ;IRQ timeout +04e4 : d0fe > bne * ;failed not equal (non zero) + +04e6 : ba tsx +04e7 : e0fd cpx #$ff-2 ;original accu & flags remain on stack + trap_ne ;returned SP +04e9 : d0fe > bne * ;failed not equal (non zero) + +04eb : a50c lda irq_f ;flags seen in IRQ vector + if D_clear = 1 + and #decmode + trap_ne ;D-flag not cleared + lda irq_f + eor lst_f ;turn off unchanged bits + and #m8-fai-decmode ;mask untested other flags + trap_ne ;other flags (N,V,Z,C) changed + else +04ed : 4dfe01 eor lst_f ;turn off unchanged bits +04f0 : 29cb and #m8-fai ;mask untested other flags + trap_ne ;other flags (N,V,Z,C,D) changed +04f2 : d0fe > bne * ;failed not equal (non zero) + + endif +04f4 : a2ff ldx #$ff ;reset stack pointer +04f6 : 9a txs + + ; BRK integrity test + ; test for clear flags seen in IRQ vector +04f7 : a901 lda #1 ;set expected interrupt source BRK +04f9 : 8d0302 sta I_src + set_stat 0 +04fc : a900 > lda #0 +04fe : 48 > pha ;use stack to load status +04ff : 28 > plp + +0500 : 48 pha ;save entry registers +0501 : 08 php +0502 : 00 brk +0503 : ea nop ;should not be executed +0504 : ea nop ;allow 6 cycles for interrupt to trip +0505 : ea nop +0506 : ea nop +0507 : ad0302 lda I_src + trap_ne ;IRQ timeout +050a : d0fe > bne * ;failed not equal (non zero) + +050c : ba tsx +050d : e0fd cpx #$ff-2 ;original accu & flags remain on stack + trap_ne ;returned SP +050f : d0fe > bne * ;failed not equal (non zero) + +0511 : a50c lda irq_f ;flags seen in IRQ vector + if D_clear = 1 + and #decmode + trap_ne ;D-flag not cleared + lda irq_f + eor lst_f ;turn off unchanged bits + and #m8-fai-decmode ;mask untested other flags + trap_ne ;other flags (N,V,Z,C) changed + else +0513 : 4dfe01 eor lst_f ;turn off unchanged bits +0516 : 29cb and #m8-fai ;mask untested other flags + trap_ne ;other flags (N,V,Z,C,D) changed +0518 : d0fe > bne * ;failed not equal (non zero) + + endif +051a : a2ff ldx #$ff ;reset stack pointer +051c : 9a txs + ; test all other registers +051d : a242 ldx #'B' +051f : a052 ldy #'R' +0521 : a901 lda #1 ;set expected interrupt source BRK +0523 : 8d0302 sta I_src + set_stat 0 +0526 : a900 > lda #0 +0528 : 48 > pha ;use stack to load status +0529 : 28 > plp + +052a : 48 pha ;save entry +052b : 08 php +052c : 00 brk +052d : 88 dey ;should not be executed +052e : 88 dey ;Y count will fail, if return address is wrong +052f : 88 dey +0530 : 88 dey +0531 : 88 dey +0532 : 08 php ;check processor status later +0533 : e043 cpx #('B'+1) ;returned registers OK? + trap_ne ;returned X +0535 : d0fe > bne * ;failed not equal (non zero) + +0537 : c04b cpy #('R'-7) + trap_ne ;returned Y +0539 : d0fe > bne * ;failed not equal (non zero) + +053b : c94b cmp #'K' + trap_ne ;returned A +053d : d0fe > bne * ;failed not equal (non zero) + +053f : ba tsx +0540 : e0fc cpx #$ff-3 + trap_ne ;returned SP +0542 : d0fe > bne * ;failed not equal (non zero) + +0544 : 68 pla ;flags +0545 : 4dfe01 eor lst_f +0548 : 297d and #$ff-fnz ;ignore flags changed by dey + trap_ne ;returned flags +054a : d0fe > bne * ;failed not equal (non zero) + +054c : a50a lda irq_a ;accu seen in IRQ vector +054e : cdff01 cmp lst_a + trap_ne ;IRQ A received +0551 : d0fe > bne * ;failed not equal (non zero) + +0553 : a2ff ldx #$ff ;reset stack pointer +0555 : 9a txs + ; repeat with reversed registers +0556 : a2bd ldx #$ff-'B' +0558 : a0ad ldy #$ff-'R' +055a : a901 lda #1 ;set expected interrupt source BRK +055c : 8d0302 sta I_src + set_stat $ff +055f : a9ff > lda #$ff +0561 : 48 > pha ;use stack to load status +0562 : 28 > plp + +0563 : 48 pha ;save entry registers +0564 : 08 php +0565 : 00 brk +0566 : 88 dey ;should not be executed +0567 : 88 dey ;Y count will fail, if return address is wrong +0568 : 88 dey +0569 : 88 dey +056a : 88 dey +056b : 08 php ;check processor status later +056c : e0be cpx #($ff-'B'+1) ;returned registers OK? + trap_ne ;returned X +056e : d0fe > bne * ;failed not equal (non zero) + +0570 : c0a6 cpy #($ff-'R'-7) + trap_ne ;returned Y +0572 : d0fe > bne * ;failed not equal (non zero) + +0574 : c94b cmp #'K' + trap_ne ;returned A +0576 : d0fe > bne * ;failed not equal (non zero) + +0578 : ba tsx +0579 : e0fc cpx #$ff-3 + trap_ne ;returned SP +057b : d0fe > bne * ;failed not equal (non zero) + +057d : 68 pla ;flags +057e : 4dfe01 eor lst_f +0581 : 297d and #$ff-fnz ;ignore flags changed by dey + trap_ne ;returned flags +0583 : d0fe > bne * ;failed not equal (non zero) + +0585 : a50a lda irq_a ;accu seen in IRQ vector +0587 : cdff01 cmp lst_a + trap_ne ;IRQ A received +058a : d0fe > bne * ;failed not equal (non zero) + +058c : a2ff ldx #$ff ;reset stack pointer +058e : 9a txs + ; retest for set flags seen in IRQ vector +058f : a901 lda #1 ;set expected interrupt source BRK +0591 : 8d0302 sta I_src + set_stat $ff +0594 : a9ff > lda #$ff +0596 : 48 > pha ;use stack to load status +0597 : 28 > plp + +0598 : 48 pha ;save entry registers +0599 : 08 php +059a : 00 brk +059b : ea nop ;should not be executed +059c : ea nop ;allow 6 cycles for interrupt to trip +059d : ea nop +059e : ea nop +059f : ad0302 lda I_src + trap_ne ;IRQ timeout +05a2 : d0fe > bne * ;failed not equal (non zero) + +05a4 : ba tsx +05a5 : e0fd cpx #$ff-2 ;original accu & flags remain on stack + trap_ne ;returned SP +05a7 : d0fe > bne * ;failed not equal (non zero) + +05a9 : a50c lda irq_f ;flags seen in IRQ vector + if D_clear = 1 + and #decmode + trap_ne ;D-flag not cleared + lda irq_f + eor lst_f ;turn off unchanged bits + and #m8-fai-decmode ;mask untested other flags + trap_ne ;other flags (N,V,Z,C) changed + else +05ab : 4dfe01 eor lst_f ;turn off unchanged bits +05ae : 29cb and #m8-fai ;mask untested other flags + trap_ne ;other flags (N,V,Z,C,D) changed +05b0 : d0fe > bne * ;failed not equal (non zero) + + endif +05b2 : a2ff ldx #$ff ;reset stack pointer +05b4 : 9a txs + + if NMI_bit < 0 + ; test IRQ with interrupts disabled + ldx #0 + lda #0 + sta I_src + push_stat intdis + I_set IRQ_bit ;IRQ pending + inx + inx + inx + ldx #0 + lda #2 ;now re-enable IRQ + sta I_src + cli + inx + inx + inx + lda I_src ;test IRQ done? + trap_ne + ldx #$ff ;purge stack + txs + + ldx #0 ;now overlap IRQ & BRK + lda #3 + sta I_src + lda #$ff ;measure timing + sta nmi_count + sta irq_count + sta brk_count + push_stat 0 + I_set IRQ_bit ;trigger IRQ + else + ; NMI integrity test + ; test for clear flags seen in NMI vector +05b5 : a904 lda #4 ;set expected interrupt source NMI +05b7 : 8d0302 sta I_src + push_stat 0 +05ba : a900 > lda #0 +05bc : 48 > pha ;use stack to load status + + I_set NMI_bit +05bd : adfcbf > lda I_port ;turn on interrupt by bit +05c0 : 297f > and #I_filter + > if NMI_bit > 7 ;set both NMI & IRQ + > ora #(1< else +05c2 : 0902 > ora #(1< endif +05c4 : 28 > plp ;set flags +05c5 : 48 > pha ;save to verify +05c6 : 08 > php +05c7 : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +05ca : ea nop ;allow 6 cycles for interrupt to trip +05cb : ea nop +05cc : ea nop +05cd : ad0302 lda I_src + trap_ne ;NMI timeout +05d0 : d0fe > bne * ;failed not equal (non zero) + +05d2 : ba tsx +05d3 : e0fd cpx #$ff-2 ;original accu & flags remain on stack + trap_ne ;returned SP +05d5 : d0fe > bne * ;failed not equal (non zero) + +05d7 : a50f lda nmi_f ;flags seen in NMI vector + if D_clear = 1 + and #decmode + trap_ne ;D-flag not cleared + lda nmi_f + eor lst_f ;turn off unchanged bits + and #m8-fai-decmode ;mask untested other flags + trap_ne ;other flags (N,V,Z,C) changed + else +05d9 : 4dfe01 eor lst_f ;turn off unchanged bits +05dc : 29cb and #m8-fai ;mask untested other flags + trap_ne ;other flags (N,V,Z,C,D) changed +05de : d0fe > bne * ;failed not equal (non zero) + + endif +05e0 : a2ff ldx #$ff ;reset stack pointer +05e2 : 9a txs + ; test all other registers +05e3 : a24e ldx #'N' +05e5 : a04d ldy #'M' +05e7 : a904 lda #4 ;set expected interrupt source NMI +05e9 : 8d0302 sta I_src + push_stat 0 +05ec : a900 > lda #0 +05ee : 48 > pha ;use stack to load status + + I_set NMI_bit +05ef : adfcbf > lda I_port ;turn on interrupt by bit +05f2 : 297f > and #I_filter + > if NMI_bit > 7 ;set both NMI & IRQ + > ora #(1< else +05f4 : 0902 > ora #(1< endif +05f6 : 28 > plp ;set flags +05f7 : 48 > pha ;save to verify +05f8 : 08 > php +05f9 : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +05fc : 88 dey ;Y count will fail, if instructions are skipped +05fd : 88 dey +05fe : 88 dey +05ff : 88 dey +0600 : 08 php ;check processor status later +0601 : e04f cpx #('N'+1) ;returned registers OK? + trap_ne ;returned X +0603 : d0fe > bne * ;failed not equal (non zero) + +0605 : c046 cpy #('M'-7) + trap_ne ;returned Y +0607 : d0fe > bne * ;failed not equal (non zero) + +0609 : c949 cmp #'I' + trap_ne ;returned A +060b : d0fe > bne * ;failed not equal (non zero) + +060d : ba tsx +060e : e0fc cpx #$ff-3 + trap_ne ;returned SP +0610 : d0fe > bne * ;failed not equal (non zero) + +0612 : 68 pla ;flags +0613 : 4dfe01 eor lst_f +0616 : 297d and #$ff-fnz ;ignore flags changed by dey + trap_ne ;returned flags +0618 : d0fe > bne * ;failed not equal (non zero) + +061a : a50d lda nmi_a ;accu seen in NMI vector +061c : cdff01 cmp lst_a + trap_ne ;NMI A received +061f : d0fe > bne * ;failed not equal (non zero) + +0621 : a2ff ldx #$ff ;reset stack pointer +0623 : 9a txs + ; repeat with reversed registers +0624 : a2b1 ldx #$ff-'N' +0626 : a0b2 ldy #$ff-'M' +0628 : a904 lda #4 ;set expected interrupt source NMI +062a : 8d0302 sta I_src + push_stat $ff-intdis +062d : a9fb > lda #$ff-intdis +062f : 48 > pha ;use stack to load status + + I_set NMI_bit +0630 : adfcbf > lda I_port ;turn on interrupt by bit +0633 : 297f > and #I_filter + > if NMI_bit > 7 ;set both NMI & IRQ + > ora #(1< else +0635 : 0902 > ora #(1< endif +0637 : 28 > plp ;set flags +0638 : 48 > pha ;save to verify +0639 : 08 > php +063a : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +063d : 88 dey ;Y count will fail, if instructions are skipped +063e : 88 dey +063f : 88 dey +0640 : 88 dey +0641 : 08 php ;check processor status later +0642 : e0b2 cpx #($ff-'N'+1) ;returned registers OK? + trap_ne ;returned X +0644 : d0fe > bne * ;failed not equal (non zero) + +0646 : c0ab cpy #($ff-'M'-7) + trap_ne ;returned Y +0648 : d0fe > bne * ;failed not equal (non zero) + +064a : c949 cmp #'I' + trap_ne ;returned A +064c : d0fe > bne * ;failed not equal (non zero) + +064e : ba tsx +064f : e0fc cpx #$ff-3 + trap_ne ;returned SP +0651 : d0fe > bne * ;failed not equal (non zero) + +0653 : 68 pla ;flags +0654 : 4dfe01 eor lst_f +0657 : 297d and #$ff-fnz ;ignore flags changed by dey + trap_ne ;returned flags +0659 : d0fe > bne * ;failed not equal (non zero) + +065b : a50d lda nmi_a ;accu seen in NMI vector +065d : cdff01 cmp lst_a + trap_ne ;NMI A received +0660 : d0fe > bne * ;failed not equal (non zero) + +0662 : a2ff ldx #$ff ;reset stack pointer +0664 : 9a txs + ; retest for set flags seen in NMI vector +0665 : a904 lda #4 ;set expected interrupt source NMI +0667 : 8d0302 sta I_src + push_stat $ff-intdis +066a : a9fb > lda #$ff-intdis +066c : 48 > pha ;use stack to load status + + I_set NMI_bit +066d : adfcbf > lda I_port ;turn on interrupt by bit +0670 : 297f > and #I_filter + > if NMI_bit > 7 ;set both NMI & IRQ + > ora #(1< else +0672 : 0902 > ora #(1< endif +0674 : 28 > plp ;set flags +0675 : 48 > pha ;save to verify +0676 : 08 > php +0677 : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +067a : ea nop ;allow 6 cycles for interrupt to trip +067b : ea nop +067c : ea nop +067d : ad0302 lda I_src + trap_ne ;NMI timeout +0680 : d0fe > bne * ;failed not equal (non zero) + +0682 : ba tsx +0683 : e0fd cpx #$ff-2 ;original accu & flags remain on stack + trap_ne ;returned SP +0685 : d0fe > bne * ;failed not equal (non zero) + +0687 : a50f lda nmi_f ;flags seen in NMI vector + if D_clear = 1 + and #decmode + trap_ne ;D-flag not cleared + lda nmi_f + eor lst_f ;turn off unchanged bits + and #m8-fai-decmode ;mask untested other flags + trap_ne ;other flags (N,V,Z,C) changed + else +0689 : 4dfe01 eor lst_f ;turn off unchanged bits +068c : 29cb and #m8-fai ;mask untested other flags + trap_ne ;other flags (N,V,Z,C,D) changed +068e : d0fe > bne * ;failed not equal (non zero) + + endif +0690 : a2ff ldx #$ff ;reset stack pointer +0692 : 9a txs + + ; test IRQ & NMI with interrupts disabled +0693 : a200 ldx #0 +0695 : a904 lda #4 ;set expected interrupt NMI only +0697 : 8d0302 sta I_src + push_stat intdis +069a : a904 > lda #intdis +069c : 48 > pha ;use stack to load status + + I_set 8 ;both interrupts pending +069d : adfcbf > lda I_port ;turn on interrupt by bit +06a0 : 297f > and #I_filter + > if 8 > 7 ;set both NMI & IRQ +06a2 : 0903 > ora #(1< else + > ora #(1<<8 ) + > endif +06a4 : 28 > plp ;set flags +06a5 : 48 > pha ;save to verify +06a6 : 08 > php +06a7 : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +06aa : e8 inx +06ab : e8 inx +06ac : e8 inx +06ad : ad0302 lda I_src ;test NMI done? + trap_ne +06b0 : d0fe > bne * ;failed not equal (non zero) + +06b2 : a200 ldx #0 +06b4 : a902 lda #2 ;now re-enable IRQ +06b6 : 8d0302 sta I_src +06b9 : 58 cli +06ba : e8 inx +06bb : e8 inx +06bc : e8 inx +06bd : ad0302 lda I_src ;test IRQ done? + trap_ne +06c0 : d0fe > bne * ;failed not equal (non zero) + +06c2 : a2ff ldx #$ff ;purge stack +06c4 : 9a txs + + ;test overlapping NMI, IRQ & BRK +06c5 : a200 ldx #0 +06c7 : a907 lda #7 +06c9 : 8d0302 sta I_src +06cc : a9ff lda #$ff ;measure timing +06ce : 8d0002 sta nmi_count +06d1 : 8d0102 sta irq_count +06d4 : 8d0202 sta brk_count + push_stat 0 +06d7 : a900 > lda #0 +06d9 : 48 > pha ;use stack to load status + + I_set 8 ;trigger NMI + IRQ +06da : adfcbf > lda I_port ;turn on interrupt by bit +06dd : 297f > and #I_filter + > if 8 > 7 ;set both NMI & IRQ +06df : 0903 > ora #(1< else + > ora #(1<<8 ) + > endif +06e1 : 28 > plp ;set flags +06e2 : 48 > pha ;save to verify +06e3 : 08 > php +06e4 : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + + endif +06e7 : 00 brk +06e8 : e8 inx +06e9 : e8 inx +06ea : e8 inx +06eb : e8 inx +06ec : e8 inx +06ed : e8 inx +06ee : e8 inx +06ef : e8 inx +06f0 : ad0302 lda I_src ;test all done? + ;may fail due to a bug on a real NMOS 6502 - NMI could mask BRK + trap_ne ;lost an interrupt +06f3 : d0fe > bne * ;failed not equal (non zero) + + + ; S U C C E S S ************************************************ + ; ------------- + success ;if you get here everything went well +06f5 : 4cf506 > jmp * ;test passed, no errors + + ; ------------- + ; S U C C E S S ************************************************ + ; check data_segment +0 to +2 for sequence of concurrent interrupts + ; e.g. 0x200 = NMI, 0x201 = IRQ, 0x202 = BRK, lower values = earlier +06f8 : 4c0004 jmp start ;run again + + ; manual tests for the WAI opcode of the 65c02 + + wai macro + db $cb ;WAI opcode + endm + + ; requires single step operation, report = 0 + ; set PC to the 1st instruction of the test + ; step to the WAI opcode, then manually tie the IRQ input low + ; continue to step until you see the PC advance, then remove IRQ + ; allow the routine to complete. + + ; WAI with interrupts disabled +06fb : a2ff ldx #$ff +06fd : 9a txs +06fe : a003 ldy #3 +0700 : a900 lda #0 ;IRQ not expected +0702 : 8d0302 sta I_src + set_stat intdis +0705 : a904 > lda #intdis +0707 : 48 > pha ;use stack to load status +0708 : 28 > plp + + wai +0709 : cb > db $cb ;WAI opcode + +070a : 88 dey +070b : 88 dey +070c : 88 dey + trap_ne ;skipped opcodes! +070d : d0fe > bne * ;failed not equal (non zero) + + + success +070f : 4c0f07 > jmp * ;test passed, no errors + + + ; WAI with interrupts enabled +0712 : a2ff ldx #$ff +0714 : 9a txs +0715 : a007 ldy #7 +0717 : a902 lda #2 ;IRQ expected +0719 : 8d0302 sta I_src + set_stat 0 +071c : a900 > lda #0 +071e : 48 > pha ;use stack to load status +071f : 28 > plp + + wai +0720 : cb > db $cb ;WAI opcode + +0721 : 88 dey +0722 : 88 dey +0723 : 88 dey +0724 : ad0302 lda I_src + trap_ne ;IRQ vector not called +0727 : d0fe > bne * ;failed not equal (non zero) + +0729 : 88 dey + trap_ne ;skipped opcodes! +072a : d0fe > bne * ;failed not equal (non zero) + + + success +072c : 4c2c07 > jmp * ;test passed, no errors + + + ; manual test for the STP opcode of the 65c02 + + stp macro + db $db ;STP opcode + endm + + ; set PC to the 1st instruction of the test, then run +072f : ea nop +0730 : ea nop + stp ;expected end of operation +0731 : db > db $db ;STP opcode + +0732 : ea nop +0733 : ea nop + trap ;overran STP +0734 : 4c3407 > jmp * ;failed anyway + + + ;end of manual tests + + ;--------------------------------------------------------------------------- + ;trap in case of unexpected IRQ, NMI, BRK, RESET - IRQ, NMI, BRK test target +0737 : 88 dey +0738 : 88 dey +0739 : nmi_trap + if NMI_bit < 0 + dey + dey + dey + trap ;unexpected NMI + else +0739 : 08 php ;either SP or Y count will fail, if we do not hit +073a : 88 dey +073b : 88 dey +073c : 88 dey +073d : 850d sta nmi_a ;save regsters during NMI +073f : 860e stx nmi_x +0741 : 68 pla +0742 : 48 pha +0743 : 850f sta nmi_f +0745 : ad0302 lda I_src ;NMI expected? +0748 : 2904 and #4 + trap_eq ;unexpexted NMI - check stack for conditions +074a : f0fe > beq * ;failed equal (zero) + +074c : 68 pla ;test I-flag was set +074d : 48 pha +074e : 2904 and #intdis + trap_eq ;I-flag not set +0750 : f0fe > beq * ;failed equal (zero) + +0752 : 68 pla ;return with other flags reversed +0753 : 49c3 eor #m8-fai-decmode +0755 : 48 pha +0756 : ba tsx +0757 : bd0201 lda $102,x ;test break on stack +075a : 2910 and #break + trap_ne ;unexpected B-flag! - this may fail on a real 6502 +075c : d0fe > bne * ;failed not equal (non zero) + + ;due to a hardware bug on concurrent BRK & NMI +075e : ad0302 lda I_src ;mark expected NMI has occured +0761 : 29fb and #$ff-4 +0763 : 8d0302 sta I_src + I_clr NMI_bit +0766 : adfcbf > lda I_port ;turn off interrupt by bit +0769 : 297d > and #I_filter-(1< sta I_port + +076e : a60e ldx nmi_x +0770 : e8 inx +0771 : 8e0002 stx nmi_count +0774 : a949 lda #'I' ;mark (NM)I +0776 : 28 plp ;should be reversed by rti +0777 : 40 rti + endif + +0778 : res_trap + trap ;unexpected RESET +0778 : 4c7807 > jmp * ;failed anyway + + +077b : 88 dey +077c : 88 dey +077d : irq_trap ;BRK & IRQ test +077d : 08 php ;either SP or Y count will fail, if we do not hit +077e : 88 dey +077f : 88 dey +0780 : 88 dey +0781 : 850a sta irq_a ;save registers during IRQ/BRK +0783 : 860b stx irq_x +0785 : 68 pla +0786 : 48 pha +0787 : 850c sta irq_f +0789 : ad0302 lda I_src ;IRQ expected? +078c : 2903 and #3 + trap_eq ;unexpexted IRQ/BRK - check stack for conditions +078e : f0fe > beq * ;failed equal (zero) + +0790 : 68 pla ;test I-flag was set +0791 : 48 pha +0792 : 2904 and #intdis + trap_eq ;I-flag not set +0794 : f0fe > beq * ;failed equal (zero) + +0796 : 68 pla ;return with other flags reversed +0797 : 49c3 eor #m8-fai-decmode +0799 : 48 pha +079a : ba tsx +079b : bd0201 lda $102,x ;test break on stack +079e : 2910 and #break +07a0 : d021 bne brk_trap + +07a2 : ad0302 lda I_src ;IRQ expected? +07a5 : 2902 and #2 + trap_eq ;unexpexted IRQ - check stack for conditions +07a7 : f0fe > beq * ;failed equal (zero) + +07a9 : ad0302 lda I_src ;mark expected IRQ has occured +07ac : 29fd and #$ff-2 +07ae : 8d0302 sta I_src + I_clr IRQ_bit +07b1 : adfcbf > lda I_port ;turn off interrupt by bit +07b4 : 297e > and #I_filter-(1< sta I_port + +07b9 : a60b ldx irq_x +07bb : e8 inx +07bc : 8e0102 stx irq_count +07bf : a951 lda #'Q' ;mark (IR)Q +07c1 : 28 plp ;should be reversed by rti +07c2 : 40 rti + +07c3 : brk_trap +07c3 : ad0302 lda I_src ;break expected? +07c6 : 2901 and #1 + trap_eq ;unexpected BRK - check stack for conditions +07c8 : f0fe > beq * ;failed equal (zero) + +07ca : ad0302 lda I_src ;mark expected BRK has occured +07cd : 29fe and #$ff-1 +07cf : 8d0302 sta I_src +07d2 : a60b ldx irq_x +07d4 : e8 inx +07d5 : 8e0202 stx brk_count +07d8 : a50a lda irq_a +07da : a94b lda #'K' ;mark (BR)K +07dc : 28 plp ;should be reversed by rti +07dd : 40 rti + + if report = 1 + rep_int = 1 + include "report.i65" + endif + + + ;system vectors + if (load_data_direct = 1) +fffa = org $fffa +fffa : 3907 dw nmi_trap +fffc : 7807 dw res_trap +fffe : 7d07 dw irq_trap + else + vec_init + vec_bss equ $fffa + dw nmi_trap + dw res_trap + dw irq_trap + endif + +fffa = end start + + +No errors in pass 2. +Wrote binary from address $000a through $ffff. +Total size 65526 bytes. +Program start address is at $0400 (1024). + \ No newline at end of file diff --git a/src/test/kotlin/6502_functional_tests/bin_files/65C02_decimal_test.bin b/src/test/kotlin/6502_functional_tests/bin_files/65C02_decimal_test.bin new file mode 100644 index 0000000..4393baa Binary files /dev/null and b/src/test/kotlin/6502_functional_tests/bin_files/65C02_decimal_test.bin differ diff --git a/src/test/kotlin/6502_functional_tests/bin_files/65C02_decimal_test.lst b/src/test/kotlin/6502_functional_tests/bin_files/65C02_decimal_test.lst new file mode 100644 index 0000000..2a2c08d --- /dev/null +++ b/src/test/kotlin/6502_functional_tests/bin_files/65C02_decimal_test.lst @@ -0,0 +1,9 @@ +AS65 Assembler for R6502 [1.42]. Page 1 +--------------------------- 65C02_decimal_test.a65 --------------------------- + +356 lines read, no errors in pass 1. +No errors in pass 2. +Wrote binary from address $0200 through $02f1. +Total size 242 bytes. +Program start address is at $0200 (512). + \ No newline at end of file diff --git a/src/test/kotlin/6502_functional_tests/readme.txt b/src/test/kotlin/6502_functional_tests/readme.txt index a3e30cf..12aacac 100644 --- a/src/test/kotlin/6502_functional_tests/readme.txt +++ b/src/test/kotlin/6502_functional_tests/readme.txt @@ -10,14 +10,18 @@ The 6502_interrupt_test.a65 is a simple test to check the interrupt system of both processors. A feedback register is required to inject IRQ and NMI requests. +The 6502_decimal_test.a65 is Bruce Clark's code to accurately test decimal mode +of the various 6502 cores (6502, 65c02 & 65816 in 8-bit mode) with added +configuration options (invalid bcd or not, which flags to ignore). + Detailed information about how to configure, assemble and run the tests is included in each source file. -The tests have primarily been written to test my own ATMega16 6502 emulator -project. You can find it here: http://2m5.de/6502_Emu/index.htm +The assembler used is no longer available on the author's website. as65_142.zip +is now included in this repository. -A discussion about the tests can be found here: -http://forum.6502.org/viewtopic.php?f=2&t=2241 +And no, I will not switch to another assembler. However, GitHub user amb5l has +a CA65 compatible version in his repository. Good luck debugging your emulator, simulator, fpga core, discrete logic implementation or whatever you have! diff --git a/src/test/kotlin/Test6502CpuBasics.kt b/src/test/kotlin/Test6502CpuBasics.kt index d6481bc..d705cef 100644 --- a/src/test/kotlin/Test6502CpuBasics.kt +++ b/src/test/kotlin/Test6502CpuBasics.kt @@ -111,13 +111,14 @@ class Test6502CpuBasics { @Test fun testBCD6502() { + // this test only works on 6502, not on the 65c02 val cpu = Cpu6502() val bus = Bus() bus.add(cpu) val ram = Ram(0, 0xffff) ram[Cpu6502.RESET_vector] = 0x00 ram[Cpu6502.RESET_vector +1] = 0x10 - val bytes = javaClass.getResource("bcdtest6502.bin").readBytes() // only works on 6502, not on the 65c02 + val bytes = javaClass.getResource("bcdtest6502.bin").readBytes() ram.load(bytes, 0x1000) bus.add(ram) bus.reset() diff --git a/src/test/kotlin/Test6502Functional.kt b/src/test/kotlin/Test6502Functional.kt deleted file mode 100644 index 1f08bfd..0000000 --- a/src/test/kotlin/Test6502Functional.kt +++ /dev/null @@ -1,77 +0,0 @@ -import razorvine.ksim65.Bus -import razorvine.ksim65.components.Ram -import razorvine.ksim65.Cpu6502 -import razorvine.ksim65.Cpu65C02 -import java.lang.Exception -import kotlin.test.* - - -class Test6502Functional { - - private class SuccessfulTestResult: Exception() - - @Test - fun testFunctional6502() { - val cpu = Cpu6502() - val bus = Bus() - val ram = Ram(0, 0xffff) - ram.load("src/test/kotlin/6502_functional_tests/bin_files/6502_functional_test.bin", 0) - bus.add(cpu) - bus.add(ram) - cpu.reset() - cpu.regPC = 0x0400 - cpu.addBreakpoint(0x3469) { _, _ -> - // reaching this address means successful test result - if(cpu.currentOpcode==0x4c) - throw SuccessfulTestResult() - Cpu6502.BreakpointResultAction(null, null) - } - - try { - while (cpu.totalCycles < 100000000) { - cpu.clock() - } - } catch (sx: SuccessfulTestResult) { - println("test successful ${cpu.totalCycles}") - return - } - - println(cpu.snapshot()) - val d = cpu.disassemble(ram, cpu.regPC-20, cpu.regPC+20) - println(d.first.joinToString ("\n")) - fail("test failed") - } - - @Test - fun testFunctional65C02() { - val cpu = Cpu65C02() - val bus = Bus() - val ram = Ram(0, 0xffff) - ram.load("src/test/kotlin/6502_functional_tests/bin_files/65C02_extended_opcodes_test.bin", 0) - bus.add(cpu) - bus.add(ram) - cpu.reset() - cpu.regPC = 0x0400 - cpu.addBreakpoint(0x24f1) { _, _ -> - // reaching this address means successful test result - if(cpu.currentOpcode==0x4c) - throw SuccessfulTestResult() - Cpu6502.BreakpointResultAction(null, null) - } - - try { - while (cpu.totalCycles < 100000000) { - cpu.clock() - } - } catch (sx: SuccessfulTestResult) { - println("test successful") - return - } - - println(cpu.snapshot()) - val d = cpu.disassemble(ram, cpu.regPC-20, cpu.regPC+20) - println(d.first.joinToString ("\n")) - fail("test failed") - } - -} diff --git a/src/test/kotlin/Test6502Klaus2m5Functional.kt b/src/test/kotlin/Test6502Klaus2m5Functional.kt new file mode 100644 index 0000000..5409339 --- /dev/null +++ b/src/test/kotlin/Test6502Klaus2m5Functional.kt @@ -0,0 +1,192 @@ +import razorvine.ksim65.Bus +import razorvine.ksim65.components.Ram +import razorvine.ksim65.Cpu6502 +import razorvine.ksim65.Cpu65C02 +import razorvine.ksim65.hexW +import java.lang.Exception +import kotlin.math.max +import kotlin.math.min +import kotlin.test.* + + +/** + * This runs the 'functional 6502/65c02' tests from Klaus2m5 + * (Klaus Dormann, sourced from here https://github.com/Klaus2m5/6502_65C02_functional_tests) + */ +class Test6502Klaus2m5Functional { + + private class SuccessfulTestResult: Exception() + + @Test + fun testFunctional6502() { + val cpu = Cpu6502() + val bus = Bus() + val ram = Ram(0, 0xffff) + ram.load("src/test/kotlin/6502_functional_tests/bin_files/6502_functional_test.bin", 0) + bus.add(cpu) + bus.add(ram) + cpu.reset() + cpu.regPC = 0x0400 + cpu.addBreakpoint(0x3469) { _, _ -> + // reaching this address means successful test result + if(cpu.currentOpcode==0x4c) + throw SuccessfulTestResult() + Cpu6502.BreakpointResultAction(null, null) + } + + try { + while (cpu.totalCycles < 100000000) { + cpu.clock() + } + } catch (sx: SuccessfulTestResult) { + println("test successful ${cpu.totalCycles}") + return + } catch(nx: NotImplementedError) { + println("encountered a not yet implemented feature: ${nx.message}") + } + + println(cpu.snapshot()) + val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20)) + println(d.first.joinToString ("\n")) + fail("test failed") + } + + @Test + fun testFunctional65C02() { + val cpu = Cpu65C02() + val bus = Bus() + val ram = Ram(0, 0xffff) + ram.load("src/test/kotlin/6502_functional_tests/bin_files/65C02_extended_opcodes_test.bin", 0) + bus.add(cpu) + bus.add(ram) + cpu.reset() + cpu.regPC = 0x0400 + cpu.addBreakpoint(0x24f1) { _, _ -> + // reaching this address means successful test result + if(cpu.currentOpcode==0x4c) + throw SuccessfulTestResult() + Cpu6502.BreakpointResultAction(null, null) + } + + try { + while (cpu.totalCycles < 100000000) { + cpu.clock() + } + } catch (sx: SuccessfulTestResult) { + println("test successful") + return + } catch(nx: NotImplementedError) { + println("encountered a not yet implemented feature: ${nx.message}") + } + + println(cpu.snapshot()) + val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20)) + println(d.first.joinToString ("\n")) + fail("test failed") + } + + @Test + //@Ignore("todo: fix the interrupt tests") // TODO the test code is not correct + fun testInterrupts6502() { + val cpu = Cpu6502() + val bus = Bus() + val ram = Ram(0, 0xffff) + ram.load("src/test/kotlin/6502_functional_tests/bin_files/6502_interrupt_test.bin", 0) + bus.add(cpu) + bus.add(ram) + cpu.reset() + cpu.regPC = 0x0400 +// cpu.addBreakpoint(0x3469) { _, _ -> +// // reaching this address means successful test result +// if(cpu.currentOpcode==0x4c) +// throw SuccessfulTestResult() +// Cpu6502.BreakpointResultAction(null, null) +// } + + try { + while (cpu.totalCycles < 100000000) { + cpu.clock() + } + } catch (sx: SuccessfulTestResult) { + println("test successful ${cpu.totalCycles}") + return + } catch(nx: NotImplementedError) { + println("encountered a not yet implemented feature: ${nx.message}") + } + + println(cpu.snapshot()) + val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20)) + println(d.first.joinToString ("\n")) + fail("test failed") + } + + @Test + fun testDecimal6502() { + val cpu = Cpu6502() + val bus = Bus() + val ram = Ram(0, 0xffff) + ram.load("src/test/kotlin/6502_functional_tests/bin_files/6502_decimal_test.bin", 0x0200) + bus.add(cpu) + bus.add(ram) + cpu.reset() + cpu.regPC = 0x0200 + cpu.breakpointForBRK = { cpu, address -> + if(address in 513..2047) { + val error=bus.read(0x000b) // the 'ERROR' variable is stored here + if(error==0.toShort()) + throw SuccessfulTestResult() + } + Cpu6502.BreakpointResultAction(null, null) + } + try { + while (cpu.totalCycles < 100000000) { + cpu.clock() + } + } catch (sx: SuccessfulTestResult) { + println("test successful ${cpu.totalCycles}") + return + } catch(nx: NotImplementedError) { + println("encountered a not yet implemented feature: ${nx.message}") + } + + println(cpu.snapshot()) + val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20)) + println(d.first.joinToString ("\n")) + fail("test failed") + } + + @Test + fun testDecimal65C02() { + val cpu = Cpu65C02() + val bus = Bus() + val ram = Ram(0, 0xffff) + ram.load("src/test/kotlin/6502_functional_tests/bin_files/65C02_decimal_test.bin", 0x0200) + bus.add(cpu) + bus.add(ram) + cpu.reset() + cpu.regPC = 0x0200 + cpu.breakpointForBRK = { cpu, address -> + if(address in 513..2047) { + val error=bus.read(0x000b) // the 'ERROR' variable is stored here + if(error==0.toShort()) + throw SuccessfulTestResult() + } + Cpu6502.BreakpointResultAction(null, null) + } + try { + while (cpu.totalCycles < 100000000) { + cpu.clock() + } + } catch (sx: SuccessfulTestResult) { + println("test successful ${cpu.totalCycles}") + return + } catch(nx: NotImplementedError) { + println("encountered a not yet implemented feature: ${nx.message}") + } + + println(cpu.snapshot()) + val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20)) + println(d.first.joinToString ("\n")) + fail("test failed") + } +}