From b7ebf6c922455ddf69f96e52175ade1e646fff9d Mon Sep 17 00:00:00 2001 From: Irmen de Jong Date: Sun, 9 Feb 2020 11:55:02 +0100 Subject: [PATCH] updating Klaus Dormann's functional tests --- src/main/resources/version.properties | 2 +- .../6502_decimal_test.a65 | 65 +- .../6502_functional_test.a65 | 348 +-- .../65C02_decimal_test.a65 | 356 +++ .../kotlin/6502_functional_tests/as65_142.zip | Bin 0 -> 110316 bytes .../bin_files/6502_decimal_test.bin | Bin 0 -> 234 bytes .../bin_files/6502_decimal_test.lst | 9 + .../bin_files/6502_functional_test.bin | Bin 65536 -> 65526 bytes .../bin_files/6502_functional_test.lst | 2042 +++++++++-------- .../bin_files/6502_interrupt_test.bin | Bin 0 -> 65526 bytes .../bin_files/6502_interrupt_test.lst | 1375 +++++++++++ .../bin_files/65C02_decimal_test.bin | Bin 0 -> 242 bytes .../bin_files/65C02_decimal_test.lst | 9 + .../kotlin/6502_functional_tests/readme.txt | 12 +- src/test/kotlin/Test6502CpuBasics.kt | 3 +- src/test/kotlin/Test6502Functional.kt | 77 - src/test/kotlin/Test6502Klaus2m5Functional.kt | 192 ++ 17 files changed, 3185 insertions(+), 1305 deletions(-) create mode 100644 src/test/kotlin/6502_functional_tests/65C02_decimal_test.a65 create mode 100644 src/test/kotlin/6502_functional_tests/as65_142.zip create mode 100644 src/test/kotlin/6502_functional_tests/bin_files/6502_decimal_test.bin create mode 100644 src/test/kotlin/6502_functional_tests/bin_files/6502_decimal_test.lst create mode 100644 src/test/kotlin/6502_functional_tests/bin_files/6502_interrupt_test.bin create mode 100644 src/test/kotlin/6502_functional_tests/bin_files/6502_interrupt_test.lst create mode 100644 src/test/kotlin/6502_functional_tests/bin_files/65C02_decimal_test.bin create mode 100644 src/test/kotlin/6502_functional_tests/bin_files/65C02_decimal_test.lst delete mode 100644 src/test/kotlin/Test6502Functional.kt create mode 100644 src/test/kotlin/Test6502Klaus2m5Functional.kt diff --git a/src/main/resources/version.properties b/src/main/resources/version.properties index 010d7cc..0ff015d 100644 --- a/src/main/resources/version.properties +++ b/src/main/resources/version.properties @@ -1 +1 @@ -version=1.6 +version=1.7-SNAPSHOT diff --git a/src/test/kotlin/6502_functional_tests/6502_decimal_test.a65 b/src/test/kotlin/6502_functional_tests/6502_decimal_test.a65 index 7a76ad1..1145106 100644 --- a/src/test/kotlin/6502_functional_tests/6502_decimal_test.a65 +++ b/src/test/kotlin/6502_functional_tests/6502_decimal_test.a65 @@ -34,7 +34,8 @@ chk_z = 0 ; check zero flag chk_c = 1 ; check carry flag end_of_test macro - db $db ;execute 65C02 stop instruction + brk + ; db $db ;execute 65C02 stop instruction endm bss @@ -117,14 +118,14 @@ NEXT2 inc N2 ; [6] see text bpl LOOP1 ; loop through both values of the carry flag lda #0 ; test passed, so store 0 in ERROR sta ERROR -DONE +DONE end_of_test - + ; Calculate the actual decimal mode accumulator and flags, the accumulator ; and flag results when N1 is added to N2 using binary arithmetic, the ; predicted accumulator result, the predicted carry flag, and the predicted -; V flag -; +; V flag +; ADD sed ; decimal mode cpy #1 ; set carry if Y = 1, clear carry if Y = 0 lda N1 @@ -138,7 +139,7 @@ ADD sed ; decimal mode lda N1 adc N2 sta HA ; accumulator result of N1+N2 using binary arithmetic - + php pla sta HNVZC ; flags result of N1+N2 using binary arithmetic @@ -153,10 +154,10 @@ ADD sed ; decimal mode and #$0F sec A1 ora N1H -; +; ; if N1L + N2L < $0A, then add N2 & $F0 ; if N1L + N2L >= $0A, then add (N2 & $F0) + $0F + 1 (carry is set) -; +; adc N2H,x php bcs A2 @@ -169,16 +170,16 @@ A3 sta AR ; predicted accumulator result pla sta CF ; predicted carry result pla -; +; ; note that all 8 bits of the P register are stored in VF -; +; sta VF ; predicted V flags rts - + ; Calculate the actual decimal mode accumulator and flags, and the ; accumulator and flag results when N2 is subtracted from N1 using binary ; arithmetic -; +; SUB sed ; decimal mode cpy #1 ; set carry if Y = 1, clear carry if Y = 0 lda N1 @@ -192,15 +193,15 @@ SUB sed ; decimal mode lda N1 sbc N2 sta HA ; accumulator result of N1-N2 using binary arithmetic - + php pla sta HNVZC ; flags result of N1-N2 using binary arithmetic rts - + if cputype != 1 ; Calculate the predicted SBC accumulator result for the 6502 and 65816 -; +; SUB1 cpy #1 ; set carry if Y = 1, clear carry if Y = 0 lda N1L sbc N2L @@ -211,17 +212,17 @@ SUB1 cpy #1 ; set carry if Y = 1, clear carry if Y = 0 and #$0F clc S11 ora N1H -; +; ; if N1L - N2L >= 0, then subtract N2 & $F0 ; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear) -; +; sbc N2H,x bcs S12 sbc #$5F ; subtract $60 (carry is clear) S12 sta AR rts endif - + if cputype = 1 ; Calculate the predicted SBC accumulator result for the 6502 and 65C02 ; @@ -234,10 +235,10 @@ SUB2 cpy #1 ; set carry if Y = 1, clear carry if Y = 0 and #$0F clc S21 ora N1H -; +; ; if N1L - N2L >= 0, then subtract N2 & $F0 ; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear) -; +; sbc N2H,x bcs S22 sbc #$5F ; subtract $60 (carry is clear) @@ -247,14 +248,14 @@ S22 cpx #0 S23 sta AR ; predicted accumulator result rts endif - + ; Compare accumulator actual results to predicted results -; -; Return: +; +; Return: ; Z flag = 1 (BEQ branch) if same ; Z flag = 0 (BNE branch) if different -; -COMPARE +; +COMPARE if chk_a = 1 lda DA cmp AR @@ -284,22 +285,22 @@ COMPARE and #1 ; mask off C flag endif C1 rts - + ; These routines store the predicted values for ADC and SBC for the 6502, ; 65C02, and 65816 in AR, CF, NF, VF, and ZF if cputype = 0 A6502 lda VF ; 6502 -; +; ; since all 8 bits of the P register were stored in VF, bit 7 of VF contains ; the N flag for NF -; +; sta NF lda HNVZC sta ZF rts - + S6502 jsr SUB1 lda HNVZC sta NF @@ -317,7 +318,7 @@ A6502 lda AR ; 65C02 sta NF sta ZF rts - + S6502 jsr SUB2 lda AR php @@ -330,7 +331,7 @@ S6502 jsr SUB2 rts endif - if cputype = 2 + if cputype = 2 A6502 lda AR ; 65C816 php @@ -338,7 +339,7 @@ A6502 lda AR ; 65C816 sta NF sta ZF rts - + S6502 jsr SUB1 lda AR php diff --git a/src/test/kotlin/6502_functional_tests/6502_functional_test.a65 b/src/test/kotlin/6502_functional_tests/6502_functional_test.a65 index 2c4031c..9a2ecba 100644 --- a/src/test/kotlin/6502_functional_tests/6502_functional_test.a65 +++ b/src/test/kotlin/6502_functional_tests/6502_functional_test.a65 @@ -1,7 +1,7 @@ ; ; 6 5 0 2 F U N C T I O N A L T E S T ; -; Copyright (C) 2012-2015 Klaus Dormann +; Copyright (C) 2012-2020 Klaus Dormann ; ; This program is free software: you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by @@ -21,10 +21,11 @@ ; addressing modes with focus on propper setting of the processor status ; register bits. ; -; version 04-dec-2017 +; version 05-jan-2020 ; contact info at http://2m5.de or email K@2m5.de ; -; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/ +; assembled with AS65 written by Frank A. Kingswood +; The assembler as65_142.zip can be obtained from my GitHub repository ; command line switches: -l -m -s2 -w -h0 ; | | | | no page headers in listing ; | | | wide listing (133 char/col) @@ -76,7 +77,8 @@ ; 04-dec-2017 fixed BRK only tested with interrupts enabled ; added option to skip the remainder of a failing test ; in report.i65 - +; 05-jan-2020 fixed shifts not testing zero result and flag when last 1-bit +; is shifted out ; C O N F I G U R A T I O N @@ -96,17 +98,17 @@ load_data_direct = 1 I_flag = 3 ;configure memory - try to stay away from memory used by the system -;zero_page memory start address, $50 (80) consecutive Bytes required +;zero_page memory start address, $52 (82) consecutive Bytes required ; add 2 if I_flag = 2 zero_page = $a -;data_segment memory start address, $6A (106) consecutive Bytes required +;data_segment memory start address, $7B (123) consecutive Bytes required data_segment = $200 if (data_segment & $ff) != 0 ERROR ERROR ERROR low byte of data_segment MUST be $00 !! endif -;code_segment memory start address, 13kB of consecutive space required +;code_segment memory start address, 13.1kB of consecutive space required ; add 2.5 kB if I_flag = 2 code_segment = $400 @@ -621,7 +623,7 @@ irq_x ds 1 ;x register flag_I_on ds 1 ;or mask to load flags flag_I_off ds 1 ;and mask to load flags endif -zpt ;5 bytes store/modify test area +zpt ;6 bytes store/modify test area ;add/subtract operand generation and result/flag prediction adfc ds 1 ;carry flag before op ad1 ds 1 ;operand 1 - accumulator @@ -631,6 +633,7 @@ adrh ds 1 ;expected result bit 8 (carry) adrf ds 1 ;expected flags NV0000ZC (only binary mode) sb2 ds 1 ;operand 2 complemented for subtract zp_bss +zps db $80,1 ;additional shift pattern to test zero result & flag zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR zp7f db $7f ;test pattern for compare ;logical zeropage operands @@ -672,10 +675,10 @@ zp_bss_end test_case ds 1 ;current test number ram_chksm ds 2 ;checksum for RAM integrity test ;add/subtract operand copy - abs tests write area -abst ;5 bytes store/modify test area +abst ;6 bytes store/modify test area ada2 ds 1 ;operand 2 sba2 ds 1 ;operand 2 complemented for subtract - ds 3 ;fill remaining bytes + ds 4 ;fill remaining bytes data_bss if load_data_direct = 1 ex_andi and #0 ;execute immediate opcodes @@ -695,34 +698,35 @@ ex_orai ds 3 ex_adci ds 3 ex_sbci ds 3 endif +;zps db $80,1 ;additional shift patterns test zero result & flag abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR abs7f db $7f ;test pattern for compare ;loads -fLDx db fn,fn,0,fz ;expected flags for load +fLDx db fn,fn,0,fz ;expected flags for load ;shifts -rASL ;expected result ASL & ROL -carry -rROL db $86,$04,$82,0 ; " -rROLc db $87,$05,$83,1 ;expected result ROL +carry -rLSR ;expected result LSR & ROR -carry -rROR db $61,$41,$20,0 ; " -rRORc db $e1,$c1,$a0,$80 ;expected result ROR +carry -fASL ;expected flags for shifts -fROL db fnc,fc,fn,fz ;no carry in -fROLc db fnc,fc,fn,0 ;carry in -fLSR -fROR db fc,0,fc,fz ;no carry in -fRORc db fnc,fn,fnc,fn ;carry in +rASL ;expected result ASL & ROL -carry +rROL db 0,2,$86,$04,$82,0 +rROLc db 1,3,$87,$05,$83,1 ;expected result ROL +carry +rLSR ;expected result LSR & ROR -carry +rROR db $40,0,$61,$41,$20,0 +rRORc db $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry +fASL ;expected flags for shifts +fROL db fzc,0,fnc,fc,fn,fz ;no carry in +fROLc db fc,0,fnc,fc,fn,0 ;carry in +fLSR +fROR db 0,fzc,fc,0,fc,fz ;no carry in +fRORc db fn,fnc,fnc,fn,fnc,fn ;carry in ;increments (decrements) -rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC -fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC +rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC +fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC ;logical memory operand -absOR db 0,$1f,$71,$80 ;test pattern for OR -absAN db $0f,$ff,$7f,$80 ;test pattern for AND -absEO db $ff,$0f,$8f,$8f ;test pattern for EOR +absOR db 0,$1f,$71,$80 ;test pattern for OR +absAN db $0f,$ff,$7f,$80 ;test pattern for AND +absEO db $ff,$0f,$8f,$8f ;test pattern for EOR ;logical accu operand -absORa db 0,$f1,$1f,0 ;test pattern for OR -absANa db $f0,$ff,$ff,$ff ;test pattern for AND -absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR +absORa db 0,$f1,$1f,0 ;test pattern for OR +absANa db $f0,$ff,$ff,$ff ;test pattern for AND +absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR ;logical results absrlo db 0,$ff,$7f,$80 absflo db fz,fn,0,fn @@ -4070,91 +4074,91 @@ tstay6 lda abst,y ; testing shifts - ASL LSR ROL ROR all addressing modes ; shifts - accumulator - ldx #3 + ldx #5 tasl - set_ax zp1,0 + set_ax zps,0 asl a tst_ax rASL,fASL,0 dex bpl tasl - ldx #3 + ldx #5 tasl1 - set_ax zp1,$ff + set_ax zps,$ff asl a tst_ax rASL,fASL,$ff-fnzc dex bpl tasl1 - ldx #3 + ldx #5 tlsr - set_ax zp1,0 + set_ax zps,0 lsr a tst_ax rLSR,fLSR,0 dex bpl tlsr - ldx #3 + ldx #5 tlsr1 - set_ax zp1,$ff + set_ax zps,$ff lsr a tst_ax rLSR,fLSR,$ff-fnzc dex bpl tlsr1 - ldx #3 + ldx #5 trol - set_ax zp1,0 + set_ax zps,0 rol a tst_ax rROL,fROL,0 dex bpl trol - ldx #3 + ldx #5 trol1 - set_ax zp1,$ff-fc + set_ax zps,$ff-fc rol a tst_ax rROL,fROL,$ff-fnzc dex bpl trol1 - ldx #3 + ldx #5 trolc - set_ax zp1,fc + set_ax zps,fc rol a tst_ax rROLc,fROLc,0 dex bpl trolc - ldx #3 + ldx #5 trolc1 - set_ax zp1,$ff + set_ax zps,$ff rol a tst_ax rROLc,fROLc,$ff-fnzc dex bpl trolc1 - ldx #3 + ldx #5 tror - set_ax zp1,0 + set_ax zps,0 ror a tst_ax rROR,fROR,0 dex bpl tror - ldx #3 + ldx #5 tror1 - set_ax zp1,$ff-fc + set_ax zps,$ff-fc ror a tst_ax rROR,fROR,$ff-fnzc dex bpl tror1 - ldx #3 + ldx #5 trorc - set_ax zp1,fc + set_ax zps,fc ror a tst_ax rRORc,fRORc,0 dex bpl trorc - ldx #3 + ldx #5 trorc1 - set_ax zp1,$ff + set_ax zps,$ff ror a tst_ax rRORc,fRORc,$ff-fnzc dex @@ -4162,91 +4166,91 @@ trorc1 next_test ; shifts - zeropage - ldx #3 + ldx #5 tasl2 - set_z zp1,0 + set_z zps,0 asl zpt tst_z rASL,fASL,0 dex bpl tasl2 - ldx #3 + ldx #5 tasl3 - set_z zp1,$ff + set_z zps,$ff asl zpt tst_z rASL,fASL,$ff-fnzc dex bpl tasl3 - ldx #3 + ldx #5 tlsr2 - set_z zp1,0 + set_z zps,0 lsr zpt tst_z rLSR,fLSR,0 dex bpl tlsr2 - ldx #3 + ldx #5 tlsr3 - set_z zp1,$ff + set_z zps,$ff lsr zpt tst_z rLSR,fLSR,$ff-fnzc dex bpl tlsr3 - ldx #3 + ldx #5 trol2 - set_z zp1,0 + set_z zps,0 rol zpt tst_z rROL,fROL,0 dex bpl trol2 - ldx #3 + ldx #5 trol3 - set_z zp1,$ff-fc + set_z zps,$ff-fc rol zpt tst_z rROL,fROL,$ff-fnzc dex bpl trol3 - ldx #3 + ldx #5 trolc2 - set_z zp1,fc + set_z zps,fc rol zpt tst_z rROLc,fROLc,0 dex bpl trolc2 - ldx #3 + ldx #5 trolc3 - set_z zp1,$ff + set_z zps,$ff rol zpt tst_z rROLc,fROLc,$ff-fnzc dex bpl trolc3 - ldx #3 + ldx #5 tror2 - set_z zp1,0 + set_z zps,0 ror zpt tst_z rROR,fROR,0 dex bpl tror2 - ldx #3 + ldx #5 tror3 - set_z zp1,$ff-fc + set_z zps,$ff-fc ror zpt tst_z rROR,fROR,$ff-fnzc dex bpl tror3 - ldx #3 + ldx #5 trorc2 - set_z zp1,fc + set_z zps,fc ror zpt tst_z rRORc,fRORc,0 dex bpl trorc2 - ldx #3 + ldx #5 trorc3 - set_z zp1,$ff + set_z zps,$ff ror zpt tst_z rRORc,fRORc,$ff-fnzc dex @@ -4254,91 +4258,91 @@ trorc3 next_test ; shifts - absolute - ldx #3 + ldx #5 tasl4 - set_abs zp1,0 + set_abs zps,0 asl abst tst_abs rASL,fASL,0 dex bpl tasl4 - ldx #3 + ldx #5 tasl5 - set_abs zp1,$ff + set_abs zps,$ff asl abst tst_abs rASL,fASL,$ff-fnzc dex bpl tasl5 - ldx #3 + ldx #5 tlsr4 - set_abs zp1,0 + set_abs zps,0 lsr abst tst_abs rLSR,fLSR,0 dex bpl tlsr4 - ldx #3 + ldx #5 tlsr5 - set_abs zp1,$ff + set_abs zps,$ff lsr abst tst_abs rLSR,fLSR,$ff-fnzc dex bpl tlsr5 - ldx #3 + ldx #5 trol4 - set_abs zp1,0 + set_abs zps,0 rol abst tst_abs rROL,fROL,0 dex bpl trol4 - ldx #3 + ldx #5 trol5 - set_abs zp1,$ff-fc + set_abs zps,$ff-fc rol abst tst_abs rROL,fROL,$ff-fnzc dex bpl trol5 - ldx #3 + ldx #5 trolc4 - set_abs zp1,fc + set_abs zps,fc rol abst tst_abs rROLc,fROLc,0 dex bpl trolc4 - ldx #3 + ldx #5 trolc5 - set_abs zp1,$ff + set_abs zps,$ff rol abst tst_abs rROLc,fROLc,$ff-fnzc dex bpl trolc5 - ldx #3 + ldx #5 tror4 - set_abs zp1,0 + set_abs zps,0 ror abst tst_abs rROR,fROR,0 dex bpl tror4 - ldx #3 + ldx #5 tror5 - set_abs zp1,$ff-fc + set_abs zps,$ff-fc ror abst tst_abs rROR,fROR,$ff-fnzc dex bpl tror5 - ldx #3 + ldx #5 trorc4 - set_abs zp1,fc + set_abs zps,fc ror abst tst_abs rRORc,fRORc,0 dex bpl trorc4 - ldx #3 + ldx #5 trorc5 - set_abs zp1,$ff + set_abs zps,$ff ror abst tst_abs rRORc,fRORc,$ff-fnzc dex @@ -4346,91 +4350,91 @@ trorc5 next_test ; shifts - zp indexed - ldx #3 + ldx #5 tasl6 - set_zx zp1,0 + set_zx zps,0 asl zpt,x tst_zx rASL,fASL,0 dex bpl tasl6 - ldx #3 + ldx #5 tasl7 - set_zx zp1,$ff + set_zx zps,$ff asl zpt,x tst_zx rASL,fASL,$ff-fnzc dex bpl tasl7 - ldx #3 + ldx #5 tlsr6 - set_zx zp1,0 + set_zx zps,0 lsr zpt,x tst_zx rLSR,fLSR,0 dex bpl tlsr6 - ldx #3 + ldx #5 tlsr7 - set_zx zp1,$ff + set_zx zps,$ff lsr zpt,x tst_zx rLSR,fLSR,$ff-fnzc dex bpl tlsr7 - ldx #3 + ldx #5 trol6 - set_zx zp1,0 + set_zx zps,0 rol zpt,x tst_zx rROL,fROL,0 dex bpl trol6 - ldx #3 + ldx #5 trol7 - set_zx zp1,$ff-fc + set_zx zps,$ff-fc rol zpt,x tst_zx rROL,fROL,$ff-fnzc dex bpl trol7 - ldx #3 + ldx #5 trolc6 - set_zx zp1,fc + set_zx zps,fc rol zpt,x tst_zx rROLc,fROLc,0 dex bpl trolc6 - ldx #3 + ldx #5 trolc7 - set_zx zp1,$ff + set_zx zps,$ff rol zpt,x tst_zx rROLc,fROLc,$ff-fnzc dex bpl trolc7 - ldx #3 + ldx #5 tror6 - set_zx zp1,0 + set_zx zps,0 ror zpt,x tst_zx rROR,fROR,0 dex bpl tror6 - ldx #3 + ldx #5 tror7 - set_zx zp1,$ff-fc + set_zx zps,$ff-fc ror zpt,x tst_zx rROR,fROR,$ff-fnzc dex bpl tror7 - ldx #3 + ldx #5 trorc6 - set_zx zp1,fc + set_zx zps,fc ror zpt,x tst_zx rRORc,fRORc,0 dex bpl trorc6 - ldx #3 + ldx #5 trorc7 - set_zx zp1,$ff + set_zx zps,$ff ror zpt,x tst_zx rRORc,fRORc,$ff-fnzc dex @@ -4438,91 +4442,91 @@ trorc7 next_test ; shifts - abs indexed - ldx #3 + ldx #5 tasl8 - set_absx zp1,0 + set_absx zps,0 asl abst,x tst_absx rASL,fASL,0 dex bpl tasl8 - ldx #3 + ldx #5 tasl9 - set_absx zp1,$ff + set_absx zps,$ff asl abst,x tst_absx rASL,fASL,$ff-fnzc dex bpl tasl9 - ldx #3 + ldx #5 tlsr8 - set_absx zp1,0 + set_absx zps,0 lsr abst,x tst_absx rLSR,fLSR,0 dex bpl tlsr8 - ldx #3 + ldx #5 tlsr9 - set_absx zp1,$ff + set_absx zps,$ff lsr abst,x tst_absx rLSR,fLSR,$ff-fnzc dex bpl tlsr9 - ldx #3 + ldx #5 trol8 - set_absx zp1,0 + set_absx zps,0 rol abst,x tst_absx rROL,fROL,0 dex bpl trol8 - ldx #3 + ldx #5 trol9 - set_absx zp1,$ff-fc + set_absx zps,$ff-fc rol abst,x tst_absx rROL,fROL,$ff-fnzc dex bpl trol9 - ldx #3 + ldx #5 trolc8 - set_absx zp1,fc + set_absx zps,fc rol abst,x tst_absx rROLc,fROLc,0 dex bpl trolc8 - ldx #3 + ldx #5 trolc9 - set_absx zp1,$ff + set_absx zps,$ff rol abst,x tst_absx rROLc,fROLc,$ff-fnzc dex bpl trolc9 - ldx #3 + ldx #5 tror8 - set_absx zp1,0 + set_absx zps,0 ror abst,x tst_absx rROR,fROR,0 dex bpl tror8 - ldx #3 + ldx #5 tror9 - set_absx zp1,$ff-fc + set_absx zps,$ff-fc ror abst,x tst_absx rROR,fROR,$ff-fnzc dex bpl tror9 - ldx #3 + ldx #5 trorc8 - set_absx zp1,fc + set_absx zps,fc ror abst,x tst_absx rRORc,fRORc,0 dex bpl trorc8 - ldx #3 + ldx #5 trorc9 - set_absx zp1,$ff + set_absx zps,$ff ror abst,x tst_absx rRORc,fRORc,$ff-fnzc dex @@ -5997,6 +6001,7 @@ break2 ;BRK pass 2 ;copy of data to initialize BSS segment if load_data_direct != 1 zp_init +zps_ db $80,1 ;additional shift pattern to test zero result & flag zp1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR zp7f_ db $7f ;test pattern for compare ;logical zeropage operands @@ -6048,34 +6053,35 @@ ex_adc_ adc #0 ;execute immediate opcodes rts ex_sbc_ sbc #0 ;execute immediate opcodes rts +;zps db $80,1 ;additional shift patterns test zero result & flag abs1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR abs7f_ db $7f ;test pattern for compare ;loads -fLDx_ db fn,fn,0,fz ;expected flags for load +fLDx_ db fn,fn,0,fz ;expected flags for load ;shifts -rASL_ ;expected result ASL & ROL -carry -rROL_ db $86,$04,$82,0 ; " -rROLc_ db $87,$05,$83,1 ;expected result ROL +carry -rLSR_ ;expected result LSR & ROR -carry -rROR_ db $61,$41,$20,0 ; " -rRORc_ db $e1,$c1,$a0,$80 ;expected result ROR +carry -fASL_ ;expected flags for shifts -fROL_ db fnc,fc,fn,fz ;no carry in -fROLc_ db fnc,fc,fn,0 ;carry in +rASL_ ;expected result ASL & ROL -carry +rROL_ db 0,2,$86,$04,$82,0 +rROLc_ db 1,3,$87,$05,$83,1 ;expected result ROL +carry +rLSR_ ;expected result LSR & ROR -carry +rROR_ db $40,0,$61,$41,$20,0 +rRORc_ db $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry +fASL_ ;expected flags for shifts +fROL_ db fzc,0,fnc,fc,fn,fz ;no carry in +fROLc_ db fc,0,fnc,fc,fn,0 ;carry in fLSR_ -fROR_ db fc,0,fc,fz ;no carry in -fRORc_ db fnc,fn,fnc,fn ;carry in +fROR_ db 0,fzc,fc,0,fc,fz ;no carry in +fRORc_ db fn,fnc,fnc,fn,fnc,fn ;carry in ;increments (decrements) -rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC -fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC +rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC +fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC ;logical memory operand -absOR_ db 0,$1f,$71,$80 ;test pattern for OR -absAN_ db $0f,$ff,$7f,$80 ;test pattern for AND -absEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR +absOR_ db 0,$1f,$71,$80 ;test pattern for OR +absAN_ db $0f,$ff,$7f,$80 ;test pattern for AND +absEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR ;logical accu operand -absORa_ db 0,$f1,$1f,0 ;test pattern for OR -absANa_ db $f0,$ff,$ff,$ff ;test pattern for AND -absEOa_ db $ff,$f0,$f0,$0f ;test pattern for EOR +absORa_ db 0,$f1,$1f,0 ;test pattern for OR +absANa_ db $f0,$ff,$ff,$ff ;test pattern for AND +absEOa_ db $ff,$f0,$f0,$0f ;test pattern for EOR ;logical results absrlo_ db 0,$ff,$7f,$80 absflo_ db fz,fn,0,fn diff --git a/src/test/kotlin/6502_functional_tests/65C02_decimal_test.a65 b/src/test/kotlin/6502_functional_tests/65C02_decimal_test.a65 new file mode 100644 index 0000000..5fcc0c6 --- /dev/null +++ b/src/test/kotlin/6502_functional_tests/65C02_decimal_test.a65 @@ -0,0 +1,356 @@ +; Verify decimal mode behavior +; Written by Bruce Clark. This code is public domain. +; see http://www.6502.org/tutorials/decimal_mode.html +; +; Returns: +; ERROR = 0 if the test passed +; ERROR = 1 if the test failed +; modify the code at the DONE label for desired program end +; +; This routine requires 17 bytes of RAM -- 1 byte each for: +; AR, CF, DA, DNVZC, ERROR, HA, HNVZC, N1, N1H, N1L, N2, N2L, NF, VF, and ZF +; and 2 bytes for N2H +; +; Variables: +; N1 and N2 are the two numbers to be added or subtracted +; N1H, N1L, N2H, and N2L are the upper 4 bits and lower 4 bits of N1 and N2 +; DA and DNVZC are the actual accumulator and flag results in decimal mode +; HA and HNVZC are the accumulator and flag results when N1 and N2 are +; added or subtracted using binary arithmetic +; AR, NF, VF, ZF, and CF are the predicted decimal mode accumulator and +; flag results, calculated using binary arithmetic +; +; This program takes approximately 1 minute at 1 MHz (a few seconds more on +; a 65C02 than a 6502 or 65816) +; + +; Configuration: +cputype = 1 ; 0 = 6502, 1 = 65C02, 2 = 65C816 +vld_bcd = 0 ; 0 = allow invalid bcd, 1 = valid bcd only +chk_a = 1 ; check accumulator +chk_n = 0 ; check sign (negative) flag +chk_v = 0 ; check overflow flag +chk_z = 0 ; check zero flag +chk_c = 1 ; check carry flag + +end_of_test macro + brk + ; db $db ;execute 65C02 stop instruction + endm + + bss + org 0 +; operands - register Y = carry in +N1 ds 1 +N2 ds 1 +; binary result +HA ds 1 +HNVZC ds 1 + ;04 +; decimal result +DA ds 1 +DNVZC ds 1 +; predicted results +AR ds 1 +NF ds 1 + ;08 +VF ds 1 +ZF ds 1 +CF ds 1 +ERROR ds 1 + ;0C +; workspace +N1L ds 1 +N1H ds 1 +N2L ds 1 +N2H ds 2 + + code + org $200 +TEST ldy #1 ; initialize Y (used to loop through carry flag values) + sty ERROR ; store 1 in ERROR until the test passes + lda #0 ; initialize N1 and N2 + sta N1 + sta N2 +LOOP1 lda N2 ; N2L = N2 & $0F + and #$0F ; [1] see text + if vld_bcd = 1 + cmp #$0a + bcs NEXT2 + endif + sta N2L + lda N2 ; N2H = N2 & $F0 + and #$F0 ; [2] see text + if vld_bcd = 1 + cmp #$a0 + bcs NEXT2 + endif + sta N2H + ora #$0F ; N2H+1 = (N2 & $F0) + $0F + sta N2H+1 +LOOP2 lda N1 ; N1L = N1 & $0F + and #$0F ; [3] see text + if vld_bcd = 1 + cmp #$0a + bcs NEXT1 + endif + sta N1L + lda N1 ; N1H = N1 & $F0 + and #$F0 ; [4] see text + if vld_bcd = 1 + cmp #$a0 + bcs NEXT1 + endif + sta N1H + jsr ADD + jsr A6502 + jsr COMPARE + bne DONE + jsr SUB + jsr S6502 + jsr COMPARE + bne DONE +NEXT1 inc N1 ; [5] see text + bne LOOP2 ; loop through all 256 values of N1 +NEXT2 inc N2 ; [6] see text + bne LOOP1 ; loop through all 256 values of N2 + dey + bpl LOOP1 ; loop through both values of the carry flag + lda #0 ; test passed, so store 0 in ERROR + sta ERROR +DONE + end_of_test + +; Calculate the actual decimal mode accumulator and flags, the accumulator +; and flag results when N1 is added to N2 using binary arithmetic, the +; predicted accumulator result, the predicted carry flag, and the predicted +; V flag +; +ADD sed ; decimal mode + cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1 + adc N2 + sta DA ; actual accumulator result in decimal mode + php + pla + sta DNVZC ; actual flags result in decimal mode + cld ; binary mode + cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1 + adc N2 + sta HA ; accumulator result of N1+N2 using binary arithmetic + + php + pla + sta HNVZC ; flags result of N1+N2 using binary arithmetic + cpy #1 + lda N1L + adc N2L + cmp #$0A + ldx #0 + bcc A1 + inx + adc #5 ; add 6 (carry is set) + and #$0F + sec +A1 ora N1H +; +; if N1L + N2L < $0A, then add N2 & $F0 +; if N1L + N2L >= $0A, then add (N2 & $F0) + $0F + 1 (carry is set) +; + adc N2H,x + php + bcs A2 + cmp #$A0 + bcc A3 +A2 adc #$5F ; add $60 (carry is set) + sec +A3 sta AR ; predicted accumulator result + php + pla + sta CF ; predicted carry result + pla +; +; note that all 8 bits of the P register are stored in VF +; + sta VF ; predicted V flags + rts + +; Calculate the actual decimal mode accumulator and flags, and the +; accumulator and flag results when N2 is subtracted from N1 using binary +; arithmetic +; +SUB sed ; decimal mode + cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1 + sbc N2 + sta DA ; actual accumulator result in decimal mode + php + pla + sta DNVZC ; actual flags result in decimal mode + cld ; binary mode + cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1 + sbc N2 + sta HA ; accumulator result of N1-N2 using binary arithmetic + + php + pla + sta HNVZC ; flags result of N1-N2 using binary arithmetic + rts + + if cputype != 1 +; Calculate the predicted SBC accumulator result for the 6502 and 65816 +; +SUB1 cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1L + sbc N2L + ldx #0 + bcs S11 + inx + sbc #5 ; subtract 6 (carry is clear) + and #$0F + clc +S11 ora N1H +; +; if N1L - N2L >= 0, then subtract N2 & $F0 +; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear) +; + sbc N2H,x + bcs S12 + sbc #$5F ; subtract $60 (carry is clear) +S12 sta AR + rts + endif + + if cputype = 1 +; Calculate the predicted SBC accumulator result for the 6502 and 65C02 +; +SUB2 cpy #1 ; set carry if Y = 1, clear carry if Y = 0 + lda N1L + sbc N2L + ldx #0 + bcs S21 + inx + and #$0F + clc +S21 ora N1H +; +; if N1L - N2L >= 0, then subtract N2 & $F0 +; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear) +; + sbc N2H,x + bcs S22 + sbc #$5F ; subtract $60 (carry is clear) +S22 cpx #0 + beq S23 + sbc #6 +S23 sta AR ; predicted accumulator result + rts + endif + +; Compare accumulator actual results to predicted results +; +; Return: +; Z flag = 1 (BEQ branch) if same +; Z flag = 0 (BNE branch) if different +; +COMPARE + if chk_a = 1 + lda DA + cmp AR + bne C1 + endif + if chk_n = 1 + lda DNVZC ; [7] see text + eor NF + and #$80 ; mask off N flag + bne C1 + endif + if chk_v = 1 + lda DNVZC ; [8] see text + eor VF + and #$40 ; mask off V flag + bne C1 ; [9] see text + endif + if chk_z = 1 + lda DNVZC + eor ZF ; mask off Z flag + and #2 + bne C1 ; [10] see text + endif + if chk_c = 1 + lda DNVZC + eor CF + and #1 ; mask off C flag + endif +C1 rts + +; These routines store the predicted values for ADC and SBC for the 6502, +; 65C02, and 65816 in AR, CF, NF, VF, and ZF + + if cputype = 0 + +A6502 lda VF ; 6502 +; +; since all 8 bits of the P register were stored in VF, bit 7 of VF contains +; the N flag for NF +; + sta NF + lda HNVZC + sta ZF + rts + +S6502 jsr SUB1 + lda HNVZC + sta NF + sta VF + sta ZF + sta CF + rts + + endif + if cputype = 1 + +A6502 lda AR ; 65C02 + php + pla + sta NF + sta ZF + rts + +S6502 jsr SUB2 + lda AR + php + pla + sta NF + sta ZF + lda HNVZC + sta VF + sta CF + rts + + endif + if cputype = 2 + +A6502 lda AR ; 65C816 + php + pla + sta NF + sta ZF + rts + +S6502 jsr SUB1 + lda AR + php + pla + sta NF + sta ZF + lda HNVZC + sta VF + sta CF + rts + + endif + + end TEST diff --git a/src/test/kotlin/6502_functional_tests/as65_142.zip b/src/test/kotlin/6502_functional_tests/as65_142.zip new file mode 100644 index 0000000000000000000000000000000000000000..5bf94922a08bc4ea8739d91ddb98b6fce3cbf434 GIT binary patch literal 110316 zcmafabC4(9vhA;J+xE0=+uhT)ZQHhO+tao^ZBN^_yWf20oqO-Q=bu**JEAJ~&Rkg$ zt15P`%&i~|0*VR%03ZP!MeyvBUSmAbzyJUR7ytkbKm$0M7#Q1_&^fz1tNerlfYbvI zi2XBE+(7{+ASWO-Kc%g37!i9g?g+rw6G2^9Vo^E~h0380<|*I`!jvLavAsfC=80n( z|9rj0Hv0w(c}3n1&rdz4zZxT<-|JzhHJ!Cy`SVXA*4My!s&gVly*jgLOc7j_GQT(| z>P-9QW_Rt`y$TV8YV!R!;oc!<(cih}rQ}_gK-rhti@fAUdn1 zNb0$+iurZ^o4ZWv)H*!$#f?k{jUA=o7&-~*5+6)7Zr8sFIl$jj%~czw^Q~ZAFKpFi zM%iCeYc~v7=v0xb4!GXk21<5q2VJ|E4!PQS{?wa>5|=?+d|ks}3SiZI0%iaRanWY( zQ=fWnfBr2TBOdI3j!xT@Cs|exAd^5<2(!;Md%m13YeWY^yZODW+blk_AiyWZ6#@s( zJ30MGInXyW51B_5ceoz=C>e%JniWr{x#z^dbr66LjvlkCRrPRk#=v~S%4+}oh}3L2 z=gDf1vryAKOtPSZWv=hN>Dm<<{}Yw4cqo?8BS1q%B`pfrP~vhdJv+G-tP99sDIAz# ztI8mbW)};(xg3jsQYdIg;kSJkPD7g}ItT+N zEntUj16-C$dfWMj_n^$t&*frBZnZdFy6m7$rw=+n&$_E{KWJX+{h}pd%+j3-I0SW9 z67FbBpIBg`l2-}1_k*P(!@PeGvtGQwYWY5{WY;`@`)(c6ztcZLDEv2(-*a`DA$igL z7hnN^E?ocs_Aim0O`M#K44h2p4A@xzMP(^66X6iE&VN(c7_g*m3jF-K*XfmWv%^ zj1m4SGsOci-w+wKcGlkO)NW9Y$fm5*cUBS?&4QaeB>uQN8H`w(?oaHR(&lZHzy&`f z&(?4%BMX*aDp2yExk(&-r<6T%eh5Ho!HfscUcV=gaU0;#ksc!vABthjZ^}q< zCdOL!K8$eM(nE9kr`LH8b)~WyI8|%6_%G0kpYnekx)NXNPY`j@#7g<3$&_9jn!iV4TY_Wl~-ET;qTF zMg#Dnhwz~}y&vkI#r+UOKbF0g#R0D0YfZu;xq0%hN{oK9ek+(tyrIFpi&q03&P&f+~wXnZG>;t;)V7KmFuNlD&YX& zkSO6uBe0+a@$DMa0-vy*?SxAa8;!+}4S$Bg@!1^eEBveq*_8{Vd~t;xg-?Y9UVOvC zWRZ0ijK%gHyG)q`63oCl(HSOe;hU@5A^3FMH0!~7IfE?t;Py!7w(%Mo9dE}Ncdc<*39`<==F(Ni! z;dqNe!-?vP_Q!4u8_evK$OMGfJ=^orEp!x7zlLQ}yk!`Tp$fNZz;kNB?Je zQ8)aS{MVsFpF>kfLx4jfZY>r!p-dG%xs3?jfnacQvRiR+#UPy+HOER`apXP!_a~tzI z#o*M;F=-Jf6kwfr^wKfER={*AcV`3}sY3*e;V=Stk}az{c~Mq#TbSypre$4JGXnCD zUalB;`FyY+=;gV$buOhtqnM8lk_w?vW1wM@Y(XB|{o zU>~nv{JRd@q?J-3lnl~9T?jFhOk~g=44k=o9W=2_(*)dd+J5Olmgz?eyRo|t$1vvq z*V`^7o4$JBUq7IK-Lb%`=`##g$`X21s+i_4!>Y+{lMX6*35Tu?5vKkBT}9+w<{;jY zf)dS^e=8wyrT_F2koy_6bJ$WtQR13R0cDxFN_W?ZXKt7kR6oQPhH0;q*M7*APgnk? zh!C_=C-c@m|LoKf;9DE-YsyrV4yq;x!bb)v>)7mFscGqm5yEc$OXx1(Eg^tw(BBzK zD5ro-XGtl^H|5cv5X5W|fnW%0n5tpn6LKbe@S^|CC9#6t&RE*j0m5mGgIoT#HP8oG*V zf|9NO5q+4NS)pntNi!3D_)5J3r&1eNcmUbqoV;{z8k`YZ%=qCd+FRtofad@a4C#}>K{8tHolaGpRvsgt=CNwI7A&td!!=5+F;=C z0++BS@=N~!B@nl;v4QxKr{UUdR5@hRJ0= z&JS%K4$v%8Mhg5D7a{{zL9jiB6$%l=9Z9pCTP(N|2NbgU2J-hqtpd$6FyO z;&S@=+80~D+(wMN1yV}XisI~(rWB)y6_SVz_PEt5xaD&jKP5V{)1Iik2Q?SgbBve< zb$oDH;ZyH~kMG7)D2s7C9ZU9FMYxNkAXO#gqxV{YtEh@8z;CPmVl!FR`m}V<_nIQj zBHPT#2`Mo77vhC4s1B2Y+Q5}Zwz%jIkaH!G7V9GiM?OXxqKN)@EmbBZDo>iwv;?=( zkk6sm5_k^|4A!5`2L+!+E%(e!J-|ahxrj$>=1CLGe^l=7DwR-WE1GEnTIi4!s#jvF z@^cmJ?jj$A=z>2)OIYqi4kVjW>~>q4+$E)Ay0@+NvnF5W_eLR+4=qnyNw+%ExsYY! z%)coEa*F?DT-|pjH4>S|h}e;=f-@v==LCRDV~Vr9?vaKR`UM?8Lgj7(0@l;dokR|RbjLC zn|n@av*iNlfh{%px!RV%vs-ThfwmK7xFh+Q_Jj*zbukm0>-%g@;+i8&7iolml^gj~s*>*%t_x_;_k?6l)XJ4z(S}=Zf$pHWU45mw` zmKtK8c$!Ejy4Dnm=yV*WpeQmiHrhWtV({7R`5|xZhhQlBp!K9;5Bf}o3;*;)?s+4t0 z(8Oq#UTNa+Iz^+j$-^Gnd7#`JEFSmv2F{dDrwW3(jXRigFX1~AMVO+;GWRFuzfrad z`B$N{A9Y34n>1+d9NVSFPx~I&#)KlYkKNCA$DTXi;Z~vw`#&}}%~_~zq9@U9wqe3- zL3^ct>0#SWWf)Mtr_u!3U->Ps4rZ-TYvbOrz>+tBSco-BbI{jHR;^YGs%GOvNp2&M z-iG=}gAXwYVE@jzB{fp7iY0mWx-2%Bne(!iOC+N$1~3-Uh;BJG!`3TC?<4Lm+Ab3Lp?6{V55% z!GUX!tIS`iJ$s-B)cRip`a`0QHp= z)mBjFo&#J$>Z6e7V1U1KIGO{Yx%B~vYzzZpK!Cq`7# zYArR<>^K-iFaNgbMm+!MrHL zBi#@Z#$Gy%!(xa4P_oZ|7@QKNdt&T`!#GTZaGVL{1EdK07dsKfwZo0*h7>V?!4%*T zWx8P;hC(=wgm7Jm6aa^Ckfr}C1}1_3fGEIMKGBgNq$6d(KrV*~0H!4Q2NT$VD4;!F z;GZBlMgCflB4Qw?!$AEjs5C^G15+H=R=Do1&}};uuzcKqqCyUbftm^d{U@pk+5d3S z9-@Etzc8+|Vos|QN>WnpX{tH^o?*!0!cbEMLqi45VP2n0V2%y}I$9SX0=-5gIBdW4 zj%`=w&$&)bE*dT=_!ulplp-Y9lgIs%&-~?m9FK)RDs&Ym2U?W0WyhyXOAi}86Y_Q^SHQ7CgP4f_uoK4fV1VE^L_+X* zGRpJh5a&05LUbxA?>nKK_w-=KbFVS$JL8o1{DIMhn5g@(m$vD?Ag%Xwr`C0+Qs+Bu zrT6S9;W>!2{czOU^=M<~H_E;Jc=g=%>~kGfjNpAEOhD&*P(<+lLc#Z1A&`}LXUV{JuYyF8Trmd)WRa^0HEdfA6y=5a{QyjkE)N8r0HOPk(f z$r!+S>@Iik^5;jEI5K1G;w^86BSnJ2JJWk&=9VqtVEnpVvnT|wg2`H_UDlaTiXa6Y z^GUQc9G7IfobLGTOro-q6R~-kyeS^$2v8IR=dldo9m6OLaep>-hOGx<*W6RIdeSe0 zG}Fz-2pLv;yYjX{@=Q$gxFh%M&8OJ1Q(DJy=di?JVVdY{^YUji5?UJ>DX%YAMb;Eg zrm@qIhpW@Ikl~bjZ*GcQrcCOM!<^Ha+fJn~Y^-#k2VK(rchn_5nf3{+GIS>8MvG$6)&1uu3kCWqN$>@Qj|wC4$@!DK{n4>XJsb*ycpK> ztQ!QL8YA4L(f9JEa;I2=_m-RF(P(Rv=JUBZSqYoC>AD>Iy2(zyYk#t%&p&g;J9=2k z3w#F!g(e_<%h8NZqMoMpX<8{+)f*J)Fsha;6C6fjtP^ju&7vLUVjyFsE(tZtUX@A? zx!)_dJhrhMq)237p}4x@_E%Q*nY4S`r^&M$e^FJ%)5NLa#nFOB^nYI zE;C+4D1O`(6Fl^b5bBVy%V5^%Kr~h?s5ch1>^-%AL26oN*?UHNGvUG-*Yh{?(n>98 z4LxttI!;qDIcle=C#G9j&8rTY+awG(!C>qhWM~{(+4k|efTC-49v)FmFU>3`L=tS`tFseba!vv@a z+C*jY5@nV0a(=a>N5-9dg}tDMC|I46Zc&$lB3;ExA_kuEsQt5?TaX^M>~7LgAUKoKGx2dprq&Ad4ApY0cbC)g zKAAF>i)7Ii#f=hv*b7j5J{lR*lj8emWqVc#uWM(L77P?(jO%}6kqVVISjU`XoIGa53Q+AFXWz{l7@ zA~~`$u-h;>GCOY_H3XZnF*|@b0sn*I@)reJ8ofp2FM`B>qBt>f!mzP8GXa2=jYu$* zN&dnZF|#|7Frzpbk^BpqaC>cYacXD^_5VTQ%D8s~%fiM4X~FK`ymbWnFSNh4q1C^V zdWl-AiYXBQ0A~MBwFnJh;KasCXJcUduk9n`UpYO`{D0*1EnX|94Y9=SI?L}t5jn$g zA`_)lRDROyiNr*6Bk5Sm8ur#1od5tOF*p!7h*Tj>OYi3!D}8)^ardImR)47o5Hs)J z>oYUAKTgA;#BPE~G05@fwunk)?EE-{Q9;~a|*F%}#`IjO_U*LBc z#C7a0Mqk{+RqWXSeU4nHhh~MMM#WanpVY`m&>mR$-E-2YDo4!}he{WXQ(17}zyHv@ z+-`zwSRVE7lacWyj>#y;x2)PaJ6rzmLNSfpbuRJIpuzj3XABCnGVM#lY>SlSTi9{r zB@GSAwg7jAzON(K?=)FDFLk+N6<5|;mG9vwUAL;0jnne$%JP?Dc($du(7nKd-w6Gp zqD66!9NkTMXT_>2*kqXoCd1CERf;Ndh@1U8HwPk1r#7;m=jt!m`od8fifNXKaub$+ z3dHh=up3&+?m(6JU08cJ@3-7{kkd$Xaq0|(B?>022snC ziNmWdudr}GpU&%&I5rFbm?Os7b|K8 z)}6?QI}!Iu0=E2}Y~hhUF!cUD`z?ppo8xy?P83bE811Mt;Q!4wNsXJsqjs*GGn42D z;#qQTiH_nX#0subqQ>Cs&sh+8fK&QA00)~e<|omgo(O-C`YO|AW?4TuDIFXEMPwkj z{E@Zf^%GN$5lDpcM8Xrv2P&N%U_vl`({Q3q$9NDq(O@@63r?Cn?^Hm3R8y-NLF_D= z{i_O^Y-Y@mi9?QRAes}}&(WYj;t&6&Gmg?E==aB*ex3*H*gEV)# zy^GNcBW4{5YE=kGs<1Gh-u{2``kxCE?C?hz}V281Vy-IwNNz`h;dL@crVX&}1 z%{&0Wo*+UtnIL6$YxVQ3Glc zG1_lFI+XZxctslg9DNc+_`q()*)-^o~K;HgD z0zF|9q#}IJX28h8HX35kFjqwP^jQyfqRZ+&rsSo51QG%ZAh)HaZ&56E&D#y+G8~Aq zf+i`sI6U0-IMyjAj)6n|P;l`^HY^?qfw^G`Cvpb3J8DLh*mn>>uf~0&=4_~Vset|y zHbT*+4iOLJpq`v68X^w4a`0&|=Du)5&15SeA!?~a*fNjgeT6dz&dCIZXpD^Dc>$2f zvf^P>hP_2+gp0$_b(#F1o1_VKw*|1j+awC96%VVyxtWX$B9L`BBKknVo^r(clJc2^ zx1M8j8%2c3Lp9hZY!|?r;=?`Q2JR~%wWxMR6-y)36u{*gXGzB{%U5!pAH*@;39X6C z;n)mfvEfQ>fWS2(AG#R_;Z*|-Nh)yyAyK=2VGl5yDJlfxQEr%KCVb8WF6%UlRf@oL zV;t$j@P}SN$`miHll$uwQJL*9OSCoos(7bA(GYfG&7ufId`o8&`V`;T*)HL?rExELuYo{0lu)&pM()G4L3&MFn}O zSZ9gr>=)b~c_9k7Vckh6L?@#|U#_@U!%;g78$G7!PrMfZYPP9lSdGbWbT;vAh7gAl zgFvQ=o`DxUxFgsC4mNS`iY{c3QV?P`OrUc{#*gtpkag@^UI% zR$1h8iFLU6C38bv;gtHDCJYA@)@DUb>739OeZ(LNsnn=FzND&yI`;{45D>Zg=9u8;kK<$IM*EQPGHYf#Hr`3%#sivCfnr&o(fY8*nt% z0v8yRX1#PQ1cJmNlPX!nyjq6R2FN?vb32SC0moQ>_X2w$9PDgWYq=W1Mhfhi_1_m6 z!^m7X3{W>=s9J}v`j@y>++2L8r30#UE12tAFAf#TD6@?nVmM0`m~IYjAx~aO8h&8s64GNe5gNY(W^eYnN#!U>C7*ocs+7EB2B}#s zF^)6JuDQVX>|;ktuFu1>#Umqk;QL>cv@hsT5ABnF18YoOaMO^MGX;p7E3*IYAAkA! zxWIemBY{F@!m}$3v?opdunxb#%7BxjLi6<9p)k!;1}6;;q$o!ffFZP0HOc%Fre7Sp zvqP>#`>Pg8tHU4+3d1SAq`7iycu9Js)7!fJg(B`t=~1JwLu23^Vrj8JrO>GpHH;~0OnA^C^NF{h{zQMG0=~*o zed>Hxw%A(6W)QeS#PmREeo2j!Y!8NJ2+(t8Lf`=;(DYBjcOwM?4&M3PzsqlCnq(eFYjb!y=y%%65hMcqWI_`}zM zze_c@Z!i-ELU6^pE2S8)9<5J^b}e}o_1>H;RSl{^hLoqAq<`3{`HDGSH%3o-Uvh6&2g7O+z3Q0dDYI}-vgrJ5T4m_lk3vvE_NQq zQeNUr$i94CucSVDs)O}*&hycj-34iSzk8~~5sb6@ZM1+jQdtO@2H|{Q$m2(eEI*^* z;^*~Clvu#iF&^t0q-ufeW=0 zn?ZaT3H73TT)NfH_58X8YqE2y9=H9r?eACiqE0k{U?>p;lY?Y_FUUGy-JwQXyHZxt zXu3Rj_Cs312e6R_fyv*NU4Ja@S|3Jq( zUe1RaZCn8b&e|))I=m^|Y7Ran{n6px7CA0N0MhtkvS5ifD)YC@v)W7L5B@NQEMMpf z8$o)+3LK@mv?h{jn#sXLnqalqS>Ih_m&>ztr&T@KxHiPp#wHQaNM*1R`7zS*@Q4%3 z;7TG%Ipjv%Pw|t3jrFE^imP~Ljuz-(&jiZ$7b(<+)DLBB5f zTZg|5qu!0#OY-;w{NA~JFsi=hQ}u9FqE@f|F7Ms)YOu0;3e|qh4S%$iy$xe)emoI` zv+3MpNZz^>yS=2ivGa4=Nd0E}@oiJ|(JH^Q{nd17_G_R?r6eavK)M4AynQbf^t@BnGXK8-!gm5asL(qA=OwP9w;En6Zwj zvIhlyI!X&-{TjSgZ;h~V?za4?>b+zs{0@Q!ko+(cifHZ-wMX&SN1W_<-hJW7m!eW(7y?wX>xQ6 zPD9|?O1^fCB7k2KXv&nld7B|e$;~Y~De={e^Q3|$E}$V|;i6^tFV;fwon9wuuv1Z(6Kvef@cG}-=-Ed*eoC#g z2!9;ZcB3*Fb_3IdIiS>eo5`q(H5ptL$!S0z+oT*A@h+dZbQngOvl2NztG6`CD{#QS zq2MZspolMdoAXUW!WFJYPwx<4{k(^iRehcauZa| zM7cca3M7U8C!2&w)9^Xkv!!%?dUNYAXq0GjF1rE~LniDBw$$7-Xox9J_sFH1ELETK zGR0FC)=^)Zt`oRJ9_*|aTpv#I?v+L^;*vzNo9zbSM`gvh+x@kv=%%W<(^8Pi;Bu)# zB9R;XE-JU#xlfLdXVrbzNmFz=^C9$O_JAx73?{JDk|k(Co<6Nb+!eB@5eM=Xo3-KG zUNT(2h`KW5c@&YWfCA9%>ULbMUK&h%QQM)bWnT9It7GS^FRcl5FnAW{)s>}m; zMYDNXgWKK7-T7ndnLqpEakTYXZuZZ&GhbWV$3|H1_s6xB;iq9PBj?4*d481>|I60b z{A=_IjRBbIHCWy7xhSGlcZ*z|uwhBl*4pWXYtJRmb(cQk&Te6;fl#<`STY&La@Zj# zk<=c`wz^1t|r$CeLh%_VvmjY#lj6$ky zLsZMZvl|UwYSi%cxZR}9|L5yS1;Mx$MWq1mkS7Vlsl7!6X)$|VkPK6fY$H$Qg_J2z z@ram1*A%|i^zya4Ul5+NqNEi;kc^oP5TQOPvfqS45yK&-(5%)_hmQPWchztr z#ZGTaPhGK^w44^7bxq^R)iri+m#W*&o9jX-Q@x%XYg>qUW_Sro?onpw6IS!2xg6vw55qSu<@=C*sLqf&=vmZM>7RPW%A@ zAPMTh?NuPSv|=0PP>ETB#{l;%iNaVz&%Sx6ehU~yx`w-CwLVjncp?xn;`XJ)lR1VUpSYAXa~ZC1Y3U}ak&%jfN33eOi*#B{l!Q#;u z4@iW}2?@?NaPymW&(sr^WLYVCJi19-R~*&YagQOKt$3>R-T0Lk!9EL`HRBL~RpX>F z)Ls(A&a}n_I`ARI#CmTuIM|x|qrx(elXg-`HI+jY&#l-FFzGWTZDQa+l?P64ozX#? z9DAyZKv`ni(E}}ow&$M&9W17iZY%m#vk+B8utmqsF4i!^{8=7p7l)tl6qRx+kX|cpyyHiAduIc z^|$3RUhJQ4IN_E#U6h8i<@)p%MkPxp?zoajnejOgYf%Ww?{HoYEwz5}?cvFR=NoLV z0pwKLR>sn`EosD*pJq9}^v$ddU-(+f&-f7M8?-pE;vC#~Q~H>8k3A&2rhc7Z-{R51 z1w%g8W8}0qMuU22{p+3lP#u3vJjzgb61o5f&4+3L*!J5IQ$%Uv-+Q&}s z4O?QD`n44MTKOAsXE5NQ%akOv6tK9SJ%+L-y`p z4HVbCg|K_k#cFJBP_^WWxB-UCG7yXa0 z(o~e$fs5c0m%uylXa56}52y$VE%6!>qB2L8U|UkHk&A{O&G7;iM=+C3Jo&!YJUfIh zwlazCC#^l~YgN-|dS>(bQa!T7E`>SV?n-U^ya?HP7k#sSCj4GHW5UfK*S~CFg3?1N{%n~sdb?}u z7GlN};9Z6GvWHkE$ilhETJ^rz#@LP1vU(P8ae%s9@s$uXu6B9TnpI8Rv`mJj+Hqi~ z)|7D>A7(x-!ZNm6uO9QaxWt!(F7Sw@yA&LLFpoQAo=&1kFoI|lQ@!SRBp)Mg6?<7C zC;j5elHvC5lhRF9Mvwo!SynA^!skw2evVY9pVA^l744shI$6Xnpz%_h2VO-Q)8ArY z{M=yzIzoc@(fH0LqeMpC*+bMqB7V-0;%IPZ z%Sv81X?0I-SCt`_qXxnhx(;145u1S3j4co^*e|-(^bQ$P;nLUfe2arZO96?s?Fout7sx6!krJ<*t%YRl_wx-CWgfdCE%W! zE0!5L(sIOwY;F>W^?k>Yf=*6afocRUSTyiF9hv;V0QBKnC=A-{-WmU@VPw$=? z$*D=T;lL72=mJdYV2vPGq)iyw%yOVXy@7?C)UN&v&i(|r?mq+YBfoy$_pQS!&FJwF zE^Rur^-}cFqnTbK7@I7a+OW$L-B58cz4HAbqUn!EB58?P0|BeXkg^hsIB5gGCt|G) z>~lZLIlz$&_GrVA*Nui=GMI1=Qznn0%iX6B7Z=Y&H?9jXIdBR6E>ma4`uZMgmU@^k zvB_DMPE43y_)I~;J?FD-*^uR-@VL^x6r2Cr)_dUV;^F6i8aR>QX;U>>Y&}ldzCEZF zJA7jI$s=(Gr1(`^+gCLuqO~1xednr7-VNvF|3OYgR9vo|%9CD!`&?>7i`7G1@__P{h2SxH@xP`FOPs6anRN#lAAE%jJ>jm+hhrg<-<9jP&Zl93x-0D3w?-v%cQ;!9Jq0isvwsxNZ z-NKJ3)ZpdpY+&kEf@s>p>sBM(TCu`!>vfb|2NjWU)t^6jJzia$sQ;LvUUVHWpN1`O|Yyv)m`E90u+F*#}RY}=uo@8afWv^G6+IlqAe z3jEc}i=|!ObiLTWyLr(&=rLvY!X;T@1eEGdssd+?^+d}jK&RYdAnVb_hUf?awxjozGHMgr>s3tL#TtA zNr{9X<%^|v#oq4dCDevW#HPLm6WFG&s0}(IvyoaaQ%iNfzv|YzphzPq3&`YGbyV7G zNf#%8l%N}SuaV!v3SjPN%Jw1olwURn#KlZ92d8mukL*!k2_BHDnAF@M88O4#_61H2 zqBl-ZZSv)rm40VlXtk*osZRsrXsxu~0Od7&MdQ%yFtekyU{`AHLtOn4y9u!1ar0`P z5i=}$9nmODPzaeh$( z_gFpTpE5(C!w{{Qrqd3@@j_tw7Cho@dm_-@fEfFACHT39{Gxw417`OWb#OaQ|(pRUDhY@6u`|NdsE#Fk2rV})OFCd{kIBt)eOUYI7_E*zZf^l@5jN- zpVLxqf-IL<0tO}^1Zu2^jqhJN5xW}7}yJ1en7an?`aU^_6E1x zkMa>FN9dV55BXVMCb(0@DQd!v!Y&54RCq~mpF051@l0JXebbN|9ETJ))@@1tBWLj9 zve8`^wB((BXScJF&cIR3vi_p{sU95PcuR%CU4gY5r=n#C@u#U;H&mUzt@%rf9&zuC-6-i#^5}iVJTFMD$aRVJu#QU@Oe!_WHmnYHd=#Ma*%e zvNO}n4HVLBu$xi$7*2eg9dABQ*LL;}6eOO6p)Cde$c0#j6U+8jgd_wqE_B6^Rr0yG zTg5PmA&6sc`g+;h>7S%-|v!0`H!H){OF|H>gfGuD8YC4m6_4qXy%$ zX@58xifRnKeR9L)3SgV1QY#2c<%pEc^Z*jHR&_T~#@(#is z#c%%|_&B|jgt8!{)CV3TRD@Xs4uvcXdmx5F8h{D=DCfh-{_Jbk(rQ zr&UT`n(i{C2OXP$J(s@u-RA53swx-O{~+zwaE*up1d3UWS+ebQ8=_K|gpaEz`Uz>i z)OxicEs}vjk-8TBCqGhvy~N#OG1KufykJwc**uly{l)(BM)@H3`As5&J-$9-Rax4M z7pI&zMclgm1mnjRqSx0(5R-~CF!K)zicbRxG-mtaov|&k;`dTz%u1wlf=r-4Z9(DR zra67C%e@nQ@?fJAyg9Z~JsxmxMMYQv?C7qjz3CV1uAE>^1v?C`ODWXstUjB>Q4(bA z2Q(QrA5Nf1Uf{9!3$P!?3}>q~xZ`qT23&3+3`au(Ip$XiyyEDSqci26E#i5Ti& znj^;|6(Yh)X~&WgNf=jP2s!?|0wW$R&Lv$LW`+KF6+t6HoaU|tO$G;vQUW0yDB@WW zNQ4_P;s36~#X{8p!&HD-524pWnE^_sasO&x?9)vC{V15}LD0#k__ZH;{~)@8;=^ ze`~siURCnb=>evEWFIv=%bQ%zI$F(rOEcm&XQt!|!wv%e;19X;>3n65c38&vjZ=!K zkeuSHXRb@J?J+o!r|bs_8-)7|@iwGfvF z^zU!rZ%dNK-vjJxH7LCT4T$|S{_E)aWjCDn&*4XQU-q@W zKqz*Bz;Z$wa%kWLLdt;r_;~*=%84j-(XmOPLL$i~HzG>NstBPcpzOyaFU&yYNtJW0@qJ6;Vw`gr-V zLBdzt1P>qr9s|xcdv)8yDTt5ij+SkL(bz7xA?5pTjWpLWZo@-)e9XD5KW+#2mPz@S zqw~BP^KZei#C0#Z;K|Dna=#1G~L@0&v5gXNmoYm-I4P+yNp`3@mJ)58SRYd%~Ab}*!|BGp=Y)# zSQ0O)!Y{avd2OTC8pQiF#q3foflOL*e9a>wCWl=vGD$zsi+s)|M2nv}-wK+RBv(T`L0UZB1U@N;_PsaOKGe zS6@rm`Gv(R9d=v3vU+uq!(O1+wX(d@4T`P2P*d!sWrfAsYQ`*eXnD%&l2ThS~6vU+`4p=P5*1QkEDmy~HruHBYXmPd5jv~{@-qHSe46Q|2tVIwN!CB;vCEmKuJ$43!bZeOVO$)7?=9 zUo+{MD251LZyfQ@B-1eQKcRQ6cor7ML36E@a%rOX)iNBv!5ki=tTze2q3kv*mC`NZ zM}^~?uZywt>n~(1=3*g>F(l*(MP>#Wql;?OnNoh~S zlhT`vCv_%M@uZF;9Z%|jX5vZ8d^Vm$$y_{1DKEg2I+I0s5}`}*BxSc8PZIQ-@gxPl z3Qy{|^6?}^Uw|id21R&MM^=g_b!r-()G3wYNu9$+JgGCQz>~DN3s35-s_>+a?_NBq z)2qgl82uog)Nwq7Cv^so;7Lkq8=lnpE%kijY`6H`#2Wtr{8@94qU>!{LQ`T1Ba|FZ zf5G2SGB{a)*Fal{e#ziy0m1?;>;`8GP&I)%c7wwO=#~Rdvm2Z)K-CAfu^SvOK=%}= zW;ZxrFcIzwcB2LgrovsyZq!7m zm!I8`kb+h&Kf56*1#Mh@c0*zc{9Jx^Lvji_xcuyf1Qm30`A@?AAlJVMo&l zu=^3Nf4J+|y^ZT1?x)EO!Abr67SBh{gB^>OTwhQ(1k}=>>y{O4yU%R#&!38PIG_f?udbPq^BU{uqzrgx6v5tmyPi zPVy%bmF_xEgX6LtmL)NkaWQR_PxI^~^B<_M^UO}N)I36&dCW;%9`A}yuj9ntM&ENV z#grN#zleAqEh!eUo}^e~TYSq;I{i_ehWgJ&nHoHM-tHRPLP^DYTI>CzOs#Ksj;;4B zFr@s|Nkhupk+AP&n8nIsFA?A!PJd&)7IoKRle%k`X>5b1#W6_TMUJ6(*9IJIy{WO< zr(L8_s-V&Wo{<;e@Rt8wvj?Cbppe@oml3}JVK$dVUGNRu)I^Ae4boXM?X9v>PU6}f|CAs z^;ApPI*9{y5(g29&fV6VZrR(Yla|nvwBi1N6p`FkN`7pk|HN@gXe>N*f_<4^BhzO^ zrt#rSQz&j=9!d507YUIT$pzB;ka7=PPU-cK2j7AuGc~u+4^L3d-mq-(bGI68x2o%TYz=zb?%J$(kKMzdL zEVHxT?5P*UX%S4e42uWG2Fph=1ELs;y1$nwql?AeqgVco(*) z+hblMPI_-NtJ_KLRTm7<)H?S*^}#yIKI?$$I-7iuoUAZ&oe+YzD4Kso7i5$Pb~<7# zO)(YpcfzZc^mpf-^vC1a?cVQc)uvOaV>7}9)~pp%Cpf-Tcg>~dHYb!;ul+NlN}Us7 zNSkj?lpW11jr4L#W64v;Q*y8o-qkl7DU zcPjKC>YY)A@`O}(^I72ntFBFCmQo!rC#Fr~3RB$&V%h6P_NrvB zz2sE`Yq=H*#XBV*NgZ)yuzr~ygAi>BH3fR^$RZWEll9=K%|@d%-TT$q4baT~kyJ_E zI7D*q)snr5NqH1~a{^WSn^#Q|p{F4iXo-sSfb0#h;pO zTw&T^VAnh(wdlR`h;+`QPTkr-nQyIgk=FnHz=*f|{(+GSdQ()8dlkv4U!}&;98;bv zg*L{Tr@xtB6y2Wa0EJ)M4*6!r0A2AvL#DcaBUy+3{#jH3iGp{)Cp+bW>50s?b83oY zr*#YpJ|PM9>7PVpttpV?9qMnO6?8G%sieat>*Eo9^iomaqu&slmUR+qXRPAR7UZ)+ zrMmw~|42zczMPe8qw3BiU-uEOqZJ%FqCUnPI+r}1Gf*d_A6nI{k$7#686IXqeE4mI zeB-9j9FvfDD!+{zIDYfY#1-Ym4v?%O%dhRZ!0g?aw^~BhbT=DzK^i#?7_r^Ua zBxP%UKQ@Ns01weInqA6004@t?yQhoYYe;qL%!uHMEU$e5ptepQFAhfMK zUH5lhAPG9!{5()1{T^gf_IrWoW1Lz$6#5*bCVBwXHG$N4>XB?@N#REj{_De>nCv4C z1_lyJQ-39}{}?oWhROE>lZ#?LM&3^URq4~$4o$7Jpk9W2x7Mf6fC{L0eBs)wy044oP9YXU zLQsTRkE}O^6#L~+nc}Lu-ewGKr#I_O@4`1T>)WDz=DEHlQ7xXOZ+a4eYCvp2Rkt zZC^3A<8PH+7y$b+L+V`@hZEc*^PVoqLH~gPy*~|9Y(LAZFx#1m;e=9gY>ImS-%J?O zv}AH`gUH=90;ssd1m3A`dMcr;*1&4&)k16;Fbm#4$r(WF>E&%EFP+`-LLa-0><;vc zu>0pC`n?8rRS7Sb^zz^J$Z%Ha95mPDTW$*U zXJ3qAS!6yVkqPYUluDkukl;bjFY4`J>h_n(8)xEjWO1Li+&2)4}Z#ari{MKL>HxK<|N7WYWnY z%OmhSNbCw+`Hf7)Eo7ZI=YJ{4G5P)eAV%U_=(Vy79_n2_mf;F`rKdQC1vg=SXPyXM zXU8ZkMJr6d)X^SXZ6J>;C|4xR@0WAJkGYXBJk+~XZqOC*qJ&2VPLQC_(*qBg5J+jO zu7mVS=^qSyNH0(klGKBrQR)?VP07z)(^TPtafq3oC5bGjv5Ks~blH$LCPvCUZUz`! z3mZ^%Cmj|{K?ot3sVDSr|184Vdx9c-S5`zptosbY$0Hln)hKd^#rgxQ6qzI2t|Y?0 zVPw_Sc}S=%tXuTP3(w$el*n%!VhVnMx_eSk14RFc&w2;~Q_~p`RfzXD16+j;u0r~| zZa%8d!CXE&IK5i0KLkw_^>-21--XNrM}!B@1|mGTi*l9BM<#0m%zS!HDY9$Cd<+Z& z{;xO!CcFGMuI3iUBwziRRJDDW5kEp7^0N+3otv$f4AqrATkp>(w?HW+uFsz?!-Qml zS4)cZ-kcNl#7t zQV_HxDIs;g=WV#zEY;%EZ`Kkss!U`uM9m_@w!_m($*-XFsq1t$L{&^JhaIkv9iDy; zjE{^^CJ_^?zk2?>S((9|6pciqjr44KNOgU})>4PFTUGDJ8g+)}8%Edx1WzYWb~8$+ zGejtu6mt(A$mt7DsQ_^4maq%i_0KdYjH~=h0g# zzgg(*Vt(sSZzDsn>M}yU(iS6)+BD95z?MlqGq0*=_{^og$^Coa43jv6dg6FGQ1n0} z>HO5sJ$`m<@7AX^!Ea`?&i_OVJ$JxFrZL-iZyZLR6YIzVvii(hfl>dl8Pi+NoloXq zO60*h&z*QntvlRE)mX!Iw~rJ=-K*4}CDpW(yCVIyy64FvqLF37YrE-ft|zf*De!6$ z>}hHA#-S^tQRoEdG}6i(+IvH@q!=9iOxRh zA6f(QY1|g;%LvsX1Z2*wEwu>&TgT<6MxdRe-uDc}adt*&Bb=Slstd+a>OLY(7^nQI zmv3htk2tjyZ=5LJpSgGr)ocDUhO1B@(j44K5H-mK@Ert znXlgWh%Dq9DkQfj7na9h4kZFpo3eSWvnxtl?(B-L7U7jhg=>eJ^mLx1SRYHlJFu-s zi#ps$jI65XxfG%B3(V?SUNHq@Lba;1c^FZPKd5Y$_td)Pn2BjQ;{|dU&qcyF2k0a4* z{ws)kW>Ab$p(ry#TTIIOn@GI9BmNqZv~m_O#}JrTh2s_F$Zpe%*y7|!<*ICsLF?oJ z`$(|TGxCY&#T-rJS84!i&7rBB5Id_{qdv4N~#mJSq_a+*~OE<5Aq#hx1W4)Wu zbuAi2UE8pOWVxC?>0=eh@=pr+7X`aR>V4QCmAXGTFw=Q_rs~?sBh$-Z32Yz7Bx|2~ zv?R8?%PG~={b5TX<6~+ZV_BYL2IYDNzosBhtFujYcBmhmK*^>;y_Qp38c3a_sPx9Fify}MEHh`o4AlHam*ZftRrDg%&i^di`9f;v zgJoah^jFNFCa$bs-m5oBt%Dda;4w8Zo%GNrl6#_oVpVM@G-NWga| zsSbtHT^EP&L3+679q$aJ?hb99*qqhD;MceL>O{0+XWmSu}m_gA*RDMuw}evpEne}Hv4xRhr1+>qFD5xms-3f>2Z zi8YK1UWu{1#B)pYsEFRJ2=&a~`c#I8U-dP@dTOCF{L!Qn>b0@d{c1_hV=>gFxc5`n zL5B2`)8h^PtLnPb%(}6`f6os%lPXf*{#!p_7P_aR*sgn`F`KW!NNsL*r%U=g zkIu$4OP*CM%)mnRas=N`c@z@kzaho~8ID1cX$|V#8JrHho0*|VrDD3Gt?>Wg0F}q$ z=_VCjH7wi1IO_JH>aGU$1@o*UyRD9Yx%R29t|%y0v+6#^J&M4JP9H6di_EHiGOFjO z$c7Sk)cT*fk+R(iVy7pf5ULBc*wkO~|CBHKVli?& zO1%?WN_Ce2KdXcMSql#yBUDNKdQxQF!>~hcJFyWSU97 z{i({+>Kz>-+0E04lBR6aRYZ!HV^>VII+9cOhS)JnB;b+tYbCjM9*gE_cgF{wqY>f* z$4-h-{LWEg6i+1TwuM?@dxRW8@1q=pq`a2A zypPV+(T8|vKl&8o-Xn3pNZsdkbIXe1mgOEs1hOF=N#qtzr0+a4B6;?aOOl?;POebs zd(V-GJ;SCe_vCAY1?!C4Ln_ov!?{_c(T01?A3#ZGBB_(tkqR0Kq>afH=^wED?f6j6 zS7!P@3 z&F6J*Q!=6p+}o(nmF7|GV4c{%C5lmz&V3+_4ey3d6&;)V2x$X#dk4msYot*LS1IXMU8CMj}T2Kh0ws zJ%0kC-K_XPXAv5|3;XU{ku;HK_7`jzJ$*jHTIAL&Bz zi>Wee%IcHAdbB5lghv^(h2=%rsxsTTGrG5s5m(S_pjM6aRo4WemN<{kW<>J%C@@s? z9`3Vx%a65Q4uDM9%a#u8lD&4yq^KP+4Pl0uD(gpz6*%Knep!rU71E-8|x9TX-EoxN)5AHo; zWRFdSX0*A$Q#9g|8~k3?$Fr%SWs57@Uq&Mr1eVGLnL8*uk9#?)Vk`bKsm<u9i!aA>paJgep!Ef zl&8h>c712e*j7(N{l{jX`A(m?BCT0<{gi~=JB62%j;QWic{PEvs5mxVyLZcIGDrR_I+4%qJ<#tkpmV1>phc~M zDM8Vqw{nkLH3RvX&#nKb#q^G;!}t6~^f=sGdEA%|^0_zhdl7o?SGYQ;yK)0z9M_I1 z#t*SzE5Nh0fGZG%pnBp-2=Ak)IWO1We5#cDUS_8D^ZJU6#F}(M-yTq}R{gr0i8K+t zkH8%BA@(?5KBvw(`Idz93r-VKCR$4hFY@#YC!8HlxqiUgYSqF>${F-(;zEYFBxHR- z5)&s=$M`6ccl_RWjmg9Gdjz#Y7C`;;aK98X7NMV>QPY6GmG?uPj)*5|P+j|A^dFn1 zy0P>8=%b~guJA}}R9%o7yDQ4rdsOTV#e+{PTo_5PQzsrSm0;Zpf-F^N_dVi7?3 z0z=rWSuV|*7ycquLLe3e+1jfhw<5vM>5uGhD9F)+q;&?8h(~Hw-3ca%WuG+973$r8 zIKfG-?-8%OcTuWDJR$mbh$tI+M7g~$(ZB9Q57Ey!!J_YZ9%2=40Gm!}0Gq=NAkcLJ zfnZYL=*e(FBl`D-SF!vA6*nRt3^*G@xcwxN6w${x8)>ikI6yV~&j*nb*p1-JWoIXo?6cOwLEA9wgs=98%vSqYV@d{ECGp*jq ztbbM4Tx8=zz)RSM(D$m+7?M|PO*#%yI~0tk{y;7+sjd&vnB)S}XM$iXGm*FjV#S`( z(ae}{D8Tn9mj~;Sf2QWtD99{}4XV}iCCM=r(^DLWYFbuO=YND0@!0`1*VWZnuZAZQ z#Cc79&3e&W(B6(Vv5S+2@NVp^k&H7Zg%X~hJqnW0$NW8+rXRl<3RUg~`+4Dt`cx57 z@_SC;Pv~-q7x$qMo>tH6b9uF_)8shfTX1eD0CS)z`qIn*G>?Igyk96xg+GN%05(&Y zjF-?|okGj9-n4k*c)#ji)jc7kC&qKIOXW6ytDGcznPLV8gif8$vKyD)4sYZp0> znWe3CuJKkYYPttb>&-FUP$SjS^C zb$eZK`_Y!*v+DNU!QUstP9*sV)}A8o&i3IRN2i#Hl!Q49#{4}!%s_n+fZ3zX_1)g> z>>lhL!94Tu%-Fi|zB#6_VR31bS*&e&1Wsz5n0e%RN1`W`^!()W*bv^F3O4EGnLHQM zorXEeh&>-p`yH8fbhDY$MtG0(2fV?nA=stckh-60Y-{5M?*vvrlf1{nl2$&)g##wP zWV8HdM~`{l38YKEABFuI17o0V{`elB;~M)$;2ds1Vy`q<3V;jLyimH2>cd{lWzoS>9GTIJG{q@ z*Po2?#H&6T5#br0j3Ib03Bn|_&g8#jv(Pm5luw?o9pRl~Fs8|ls=61_memF%@6xtl zl8`@`@;i70p}OjM%UTSEB+R@zcq&Yuy_>F0Adg7Fk?g*hNdM|KqJWnielP=5--hK5o^JZlSHihIe z^75X`$g|a5byH;70N3hq#MwK|Wh zTkIJT@2afB6`Kx|K2%+UxP)1UJz4F}P3y(-Ec$BuqdE6}5SDQ>?VDnZ}U-_L<-K$21t2;CJV|CY+i2LIvsp7*U9`%0Q zIuKS)=}e`RA!-roE;0m{nd;jtzV!Iu%RTo)^fN^^J9H^xFL19K=u};I^s0eQ_5Om8 ztbu<~4RjI@#a0MxkNBip-yX5QTi+h>cDKGgqPbh&9`Q=IzCGek-TL;3-*oHSBOdFP za$SBVxjreywcNYupsD!`a&18Lo0>hK7)CvB5(!+U3&Mj!j98;=%D{Tc2u#6H4W&Z$ zy6(Vs=4njXFm)G9`D>!x#%p0a`do7h$zv$qtd1TlWiL=7{$b7Fm9giWW0EUpV>{%ES@4nOm~FBb<1Q$o z-^b86JIoIM<{iF#3wilwSN%aq8d=zCdN1g^tW1muR7!TPX&#(0++_}dljdB<@v=kj8YeGfP5 zR6a9EpZvR8Os&2?vxlDJLf7gGu;DGpFpaVQe~4ITITw!3`cUXaEXN3bdiF3!c>|1T zB$7$p>#p1UabHz=vR<#sbwm580wJ-dt`b91u@yF!SBQ1_?NQCq4OGp!yThx*dxTPqEGefPFnDKu!F?+lD_Zm@>LVjhoQ+8M*^YDN5; z8pHGB%X%ab+vt+sQ1qCJH^VC_s*#@_O3d)mC{PJGBr;I_sB>`wZDp!rX13QD7=weUnOM5 zk7)Heb!;0Y>~T&c7bn|fo_MYyStGQUt&Y_#nrh33VN&dy@ zyjg~K{$SE{xe3)Gh@wob$nfI-LHG%)iV142a|1ghHwJ zv)R(wt-2mH^|8-4J;{IFD?BUfX;NKS6pD!Z))Va3*)oM%BWD{}CGF9rhJ|F0UhUVs@?C^v z=B{rcB#{jt-o$P4Faf4~c)t#nd)zBxSRPG@@$pOYYw=v@6twU+U#at1%$Y;39O6g(`jOJh)K6NNzLJW z1i~Kd9j5PYzJmhTm#_E;?|&KZoq{|tkiwNGo(?e3+~M2-29izLOrFjiEVbSpsHEns zcJ7O_I=aNbOSlfgrMetEL8@XVJEh{-xneJT#j#Q9V+|F@2JrSf)s0INTzl23{q&q8 zupRq69lje(AwCi*Nbpo6yHG_sH;VQqWnj}xlj5AgU644gydXxQ%xm$7XX3HoQV78{ zXqQJ?kN{859}RjwtnUs_&vzK7=Nq*N;vgw?L#||)_B>&F=#&Z5M%CR<9IXz|m4<6H z?7> zy)OZ0zCisPP)Bm#fR==uUX#5c4TO-_-7ivxuMrz>R$W*k-<;Kp<1QT9 zqIh$vETM%5XHrffPga}b4arkugLt`x3Bpxdd~i@il!*GEY|Al{$TA*hjh801r^6cu zp=DLj;n@>?CmI%}m(Rwk$DL?_o;zh(xK(==7<-BG7sVzc)%8(W^ZfhPox2lSk~Ijo z@h0=MbA>>&AQO8*h3D^q0=~pze56^-@n8NT20g0rJQ*%lbAC3_v(&G;o6(3PNqHaa zfEre}4;1a2nB%%Y$~G@?(qL;KHkvfTXKS6S(eb%!zvGTjmOuE8Yj3q$wUPKWC$NN1 z*$u2#-F%pb(?>=7%ni5;fo0yiv`vV;6cjJ-5hh)7-@QDxX=btKwp@*)dB?6&UAu4; zZfRRn)Xf>5rEP)F$q9-An5j1w;}KbmvqB5~j())lGWiSw?~h@!8;IMKNvHozzL97GjL%b#>?!d+deY#)xjF ztPF?DbMNzr4M*mg73Z0uNv&BvG6{pDed;?g+^hF((Qfkqzy5WOl86xXRdYt8IKB~&vm`taf4U9or$gPoN8R2Z<8pGQ)jKZpba>wJbh+vr z1A~`(Ix=y7tmm*JfEA5N@sEB!6e7wO zT53TUZ(EW0t33-Ab!Sv|;U+c5A$Q$gF|*ugurp_E%ppgqnAeWj>9!`h3|B4;%wv*2e&UH!Bb|bg$JzIp`MIb7_k}g#_`9xL%!u^ z?@V*>cc|k8QOCGF)qmxm*y2HSEw(uZDZ)Sah;F&mPmG+)dgeKO{()7wZuELb;>Hys z+q)^&yWiqn?h^4M5K*dV4xL z^1j0ywz7=(3CaD^G!9*1k@G<$W0KhQZoP<7kT$TKZG@0FQgID0tv0#ROn)iXLqyuh$9 z24PB+$cv2gtix;^oa0Y(2d~>D549 z5#b5FdG^NoDX_%dJgVyp9#P;JQZow>Ffg|Gm1sv}h-Ci{P;*&->f;#03F5AQTsVZv zI$r5+d? z-%FT$vQFyvy^W`?e;b?nCRXdX`Bjd$GQ)$iS;u617h66>o7aX$+B=P1(8&b*(@QjS zc0nFr7BCJ)8E()`kN<&n(<1bWE?gtq9J4^`C+`&Y-M%zF#L<1(!x@iMVAZmCPj&(Z zj)(q8GM`OYSqaVAy!p8*doYa#qO_~&Z?v|O{+hI_BjZoGbw5xTg6zki<(MZ1#jJ&> znUSRxJAHA&(?hg3!W!!`deg1&DPWGlZ8t|8pcM)_Gofm6JV>g_9GqGgbcN5qjx(Hp z{bR5D(<19{Jyq>k{l2n@zO6qh_&;7-#chT4jpIYIpKQEwazryOuf}vd@52&nCf@U? zQSA)A@6T)}mQ7AFZWa&A%+Zr#sb!!Z4Xv&}8oj>C*89Ff=;wISa9LsuUES2PYz z&{!p+4dqs`M=ua^yXf~k4r$Wf_ht>>iBThK4{_gJg)kBmJgrARuKz5?!_$@ZH2yMI z(-?AWBe;7r>uZbuU%wMOxhaZ2_!Oy)g$cfgD$&30HDPRNsj7ynYQD+Y80GngXGKTq zzRE8*BZp4k%I^Bkeq=E}?qavI?J79jd?3!ffAfW@dsFLt2}-?Rb+(xXG^pDvk4_%A1qz(+mSZ-;wU zbaMZ8!t03jv{wET7EygC?&mYJZ9!2y6taTk;e>ZZ=ib0aPxXwy=>)Y@oGJp=*Pc$# z@%ql;^~d973L-`S?~slrHfTJC_b#~9?M=w!K6rFeHdJZ6TR_wtcXee?=_W2;_ZWvA z=U$#m4Sm$N{uu9_lK%?d5|Y9egtNP!n#Cufnq%_it!caijo)v94P_dnOUomquDS};{&bp}d0qR|k!HhIwh+T=;%_4k5)J;=c-i4j=A{yQTmxOp*r?~7$A_D|B z8_p4GEW@Lp4v_)npYKA)BRIoTY`FS0Q|34l&4R0rG&14`FH(2yaUL76{ad_`dwI;g-=1sg{yj|*0S8cKu)(=S#+K3BcM$8{vhk5{mhM_MT0+;r3WRA)m} zFrM3E<*~;o+;_c68zEMq1wUqqRaO~c-Fr|YCs z!*xMkt{hK8L!Q5>Zd_RHoA*~@+xj8g+TLmV&8yg<>Bdb~o^r=BJnCLoy#bIKv!G=KaN+=2Y$ zolt0(Dcp{@t38MEujopmwo3K_SRc60H-Cc+@T*o3PVf+JYo%mXvLBisis zGKAxD!)M8Rk13KExAy_R%@DA62Nv5 zE*}-ln+T?Ov)Y{vW=~WN5+Snd($F9)W=@Z>9Nk~vMoqLTAGg7J1ojZhb{mCxmbQBm zC8MlYLh18k`UoEitf}6)W@nvQIvrnm;(!~d;UV6uSl>cw(-Tn{wNH=-AL^@p5*Kb{ z`ZCP5k~B|-*)x)(Vneyt>{h7ATwdO^rC)IKn^C7O_3&nw>fQl-2BNp8V_;-xpdYPU z)*I;*`5I3)u6HRS~-gCRxgA)8f5L zJFsgDcNF2SfKR-e+OFMT37&neGZfMW)36Eh_iF#l0&xc_pv z%rahHl!;-9|5y#C+dI;hwrNYk!w0fn2iI`BdV()miZWw@WR;-aJ%F-J+tjfo$?ND? zUF{tS9J0K#{gt2b#0YM_^4C!OwC>Fx>6ebp)640{;#`AXQj4Sog`CMF_Z{0JMbr{d zG<`CGQ2Y-glrzk-$mOX(_BIx!*>fno3*j>*3*xrPeNp-iQYhHeZH9u4jW$;JEm5+< z{c>93zR#e2vfANH)z?EwtTCq(;96B(Lm?$A+PO2%r2hO!<0$RCv=wcehatCOfu;?} z&UAKL9Urf*c5XUolKZWewv!{umoUt;^ng$o?jxHgr|zdLOs#x6@luLzYUaTL%FvlD zCnuheC4A{I;__j~TQtt-Jo-LTJKEy;yPDPM%{o9j!qdrfl*AZLqDRyUiWhl)G)8|0Jj+h-HE$ec%pC5MUMEWZ-#kiz?+XhB5&Q=ql?Dy4 zy-N>DL{i4@&XN6SJy5oUi6tsYv|s|wipG8L$l}~N(CsZCyW!}*%8!}qB?hki9%Qw~XC@RD&nOH`?+2WJ4Z}sP9i7?RCBm z^Y^&G#p#c7cAC~*C@+K2mdJfUH8=|u&F37E!6l#KhC}MpLwraIm%zwdeum47VECpV zb#@H4A=ly$Z%E$D`-gfZcJh-@XeVaA&^Tu&0?)&LgLj7aE6Mra)khnZkan$+)UlFO zaV3|h6|!|I!5eU|44>!XYl>&O_tnDXSi|%flC$b1ztxz+&0@~svQPL@$Vj>Ok={rI zM%hqVZf#&Qml?&Ed$2KAJDsuCZ`H91BUr(TUbKFG@HG73nK`Tn^~8VWwD@0iV}BvA z#l<7l;rR-4?NhIY?@JRGeVerY-1jzC2fW?A?ngp+R3!Yip5aS(iuDj|YLaP@*f`E| z&cHES)3YPBI9v$Sa+93@2hn37*zyjO1ir(hqRZq+@s8ljO8CAmpR+>I_gcT|nD(hd^$Pa_kJDHDx^O*wAA>aH^<;M!OMGu$5ljTo_E3JVKE!3I#G_!s~OI6lk zT+mXP&b0E)B6lA|-m&cA%j_1#Ti8zgcunvlT6MimDBZ6+206uM?EdQA`0$y&89no) z*jkCYq!w^LZkMS4SAU!!JM8?6I-m=BZx_axn+`|wXI9j#toCs${8R%z`$=cxCcknb zeACHK8!9&aE1K8ZHH|a{Ojmy!jURUK*M$BSzW+_X*(+P}BdufI2=|fl;g#Kd?^=9i zH_lk7_q{8{MDUmQor=A&nJ48fZhRA$OeI){?6n~thb2-WfmK*n&a!}(pg*!+E6%6O z14HWe$>N~yq3+kUvL4%JJ+ah2Fr19zI(uJM*q%OW%F{Y_k8f_bvu^VY)~_AJkaWq8 z)x?f&u;cA6UN2>iMD{nbN+4x$xy(E5{dL3L`^yt5k26DJiNVZ}0RYw zqDt2Wc^1mE$${K1En@!WAX=EA#1YW)gp*(ZFs<^lK4`_8`+mA+PY$FA5MxZ*X0}#_qjj`iny^{ny{( zP0)|mb7gtsSdjOs_uKj4A_Up_M*jitLyV6e!}g{0Xl=GY*`lUz3!78g-b$(oAjO9BKoJvJJ$EHo)y=^F6(*MtphzByfMM_vpAO zwk9c0IAG0U`iH5(tjQn@OAfJ`tmln)+{9bQw)jfJt$2N$6mHe^m0;llG~x@o;1q;`(v85Hiy$t%du=Fk zWGVGXxHa(YqC($Q{u6(B9WU)2GRlw`-?4#dAw=uK?Z*xaf1#~Lw<~N1LZM`FmBs?q zg%g6#x(d~GAyMof`!>#;GU`m=rX9dF4B@Dkz9_!szh-eBmj(wVVNvi$Fdg|y4XwmpY+Q<(a_lt`OTq&7cTw)p|F&2K(m zd?tG=mNd!utB}^x7Gp+51+a|Ec!QjScT0_YL}MvH}OR; zp(OW1By>*ZbCk0&0mFQJqeC)7x3^5adNU1^3&v|bbwleu+@I0gbo6D)9L)0AN|uF{ z!j*^dH3wF)&c^tllQRuT<1kia4Ry8Z46cNOkuk zKi^_=<#Fuv*^$pS9)EnL>5ypCZ($Zd5Eh7*7asifkbW~vK=u;6>+B7R~a_G z)w^#q@gZZ+8@dS|*uV-GiHeoXhN#NpxKYc)e%jE9b{IUeQSZjAt9J&9k3-gzBlpI*L!=`3BSz?Lz%gb=vq@)%YZ^$+903Nr_7%SQf)R*l zV3U*TyDfh8E5Vi*B8HFX*xdL$qc3x?tShA8{OVL0QQg-^g)Q*PF79Nmnd^C57#1r; zDY0+{c2J+;tc%h|0^)?8r;~;gZmiVGlKJk6TyJz)U-mM0aW&xXLQBv6RDoF?M6*2K z=gS-pqTj-|5^w@L(k*u?VbMxEv~C;O>W@fU{XyMU_mIj6-sKZJiM$=mqu@_^v0vs; zgy2rts;gBs)~q>3 zty#6+cRu8s3OMo;c0iW-M?-;>EzJskF`20tu}LZXm1(k6hLH-UL1~uZw@Q?nQB;Gc zGD$wGG-9iO^SFDDa~Zz)K0ukil3mXy(T2e0y++l)7DYJafh!I9n_{c}&D|TF#~Wm5 zU{m&AuwK5gNs2_)EwiGIV9JM1+IOpP4V=+QLzc`DOx&)KK>6}tWesKx!A#80>yoX* z^m2r15(0e6=l+^80-z(EUR&GWlx-*fd!!9z%n_2B_4|xI_@5GCFmEq>8&W5v2cZ}v zhMp3ZP3$YHtMOrX$IxsSmaFTMdu8Vb@Op0!`c_(J#vU8zr%2Dg#&~MrpAmbB(pnru z%8dXD-D80A>n7$65WSgX{JA%wCLehTY)+}xTwiqhVDF5;>Dtnciul;$ z;YxTnKaJNw-uZapY!^$xi(_@XIoT0a;6FINSxC%dK0NCPtl)-YwoiT>@Ja|MB?;dA zihm-S6+|-Q8ca88*UowR3565qmwopv^2*4ZVnB%16m5lkD1cLf2*w^00_G_J0UXN7 z_|+>y_MA^3^)a*a;hj&ocsxs`g?#Lz6jUnlR3cC@^P2PgA)0To6VF(f z9X5L|u*}+>QPenwNfagq-5*r+bpLnLnWwM+k=Fz_b9()fUl z%P<2Sn;>G+U;GL6&J)TW!xCRX9jZ2>Ld}_}%BBkLu6^h8%opCLu|MB~P&WFy7*_uv zSbWd4{>6@3n4QANK&xtbNTNqlj&3Y*0vxfk0LL@bq&AJ2FAnpeL@5M33aK`qF+OMb zwgV?2gc9Q&X^I6qdRuDjMW6?FzoG&P>90e>aQbXPKCfeIKVUC7{@Y9EeH)*7{b3X1 zY$f@wjW-mJ3FV}VukOe~zBFM$_8NgnI9?1|wFG;UN2?52eB_Z-6wV2IuY9A%@{K5w3)X*|d>7 zY404kj?Kg9t{8m9)RL)u5ca$LiGgAOxeWXITQio|guZ&-`V>rhIA8u1Qr*Rw8i`wG zcdn390>P&;XE&a+oWX}r-e*+Gb$6YRB+e|YM#8Dh;;&VFZ_wWDPr3~6m!FGno%-MP zP~Il}w9cL9eyPDwA6WKS`RT*fB%}~=>XL$P!YP}8mtpFO%Jx8dM;xMyPsR1jXKdp# zWP*Js&@sf_w0$KESHroM?rWhd7`An3e?8N#ZO}v$%Qcu;W3UY$uD^a!2R<AU>wn3o5<69!P{yn9 zSjf5;H}7aUJ8WS!6Y;s2#>5_vQJRC?$s9Cg9r-yE(ajcw5BBWsJsr|b5wwYTwVjL1 zV;dd#*-iG~ocn1m{9_|%$Tn>j2V>Tu+q;9Ws}zonuVu{t`ACtf+Qb<&vcIh=uB1~F z<$;!C?`A4eug&(a#@JG?vXS!3%N*A`jli%{rzd9D6|Wr%M{Q1{hEEY_)cot*h^RJb zlH-!W=@xK);{J9qG_DYy^R!V!3!p)Z4Y~1XoXAcB6iozjMa*8u<4WT$G&T{Q7vqbc z1ac_k5HyO6*ldet#OI&z^$tJxa<4CRM~*uY3=YoRx-7M3cB5YmFPCsb~O5 zkzdpq4f`0{6}wo=qpz>*w8Xjh55{=~U`$ow#0$*E+N=#@974YP!6W%FQ+=Lk&ZwG+ zF||$#tX_=A0!LG{LQ=>?lxoPc-Kk#m`o9N8iqUSv+SZWx9rgyxU7vQb6%NEDHG&a+ zr*API{YrVqlcQ4M5at~DYn-N|lunFhesm@3x%3rPFpiUN@Z}n#Lu6NE9|B`rM11-0 znQAkwgL^`I!PgA6X9niuz<0}!`1=>?o6f6I_*B~@b@eJe)(*zgeU}>-lVon zOrF(*Mb-E*GyEa@ z3)}6Qt<3HsFNK4@vIe(v2&DV`mmsQUKong=Xs?eayREPM7pKCW8NvZD7q)_h7P2F)h3^-`+?Qw~Gq*HU%H|bX28oSD^)UvjWjFj{3TA80llv_;=VDvu5#T ziaUqj>eI%t<8KE5s(B5xnGzl!$ZA{SjqWFS5Xr=MVc@e~;$VQcI z4^sC1H_Xt9!B&kW`z@9@{sNG%qv_Gt*|ZpIvTTaLzvLh!!<`@;@-rk?GNKX z;#Zv#e%rf;Y3Cxofr{ICT;q?vPv0x#x=6@V9j7v&rsJ7!^4EXPV#k5hwkMwue}Ppc zehW$(j!KcPn5na}?SIH(q>%H6``>h7-(Hih##OSbb0jqL+nNKTX$t4H5`+#7lZKfLe6DFxUt>~y~Do^#R~BxZqz5TX>bX1gv3b8$;!5o#|P>{x1PDY6N6 zb(Q+I@Xq>Wvn|(qHCM})vaHr5)Ed*O3ofq>tUGh&ntIFICDIFo%2?4Z+YGrO**2q} ze?>c8xLI38dB{sEHH?o_L3O67lmy-=@A5IJQ@f#2qejg~J1?!(G|4wIP&KiFwi$(% zvh0Sd-)5V4Pb>XesIr#18*|rNanG!#YaO&h{aVJrw5>}+TdxWoDn^haOHNm@nQGR$ zENP|^B51AUzkm^ z`Ym@Je2lwvl!m6ob};?QHNc5v-#x}P`&G_V9Mj0}>ucl}@0H-GIc7kMWiQuFr-lh2 zmZ1a1dwz0wTMZQxQENdbejE-lM;MB>U7*v>B$aCdoQb_nU#Mz)*Bq zwYVVTQM{z=@C9+e=#zV-?WBXpBiWGOptM1=qo5(t5od@nWg41yuR6T~jWeFvw)wTNrg=MCIy1L9SZ zDdgzN`&M{N*X7-j!fw~(oY_J*p&!?(eK(wQib{yscL9T5$n;-=6*tI8@tGSk8P;d9 z`v^&q89UQaQS>;s6|;_(k@nX#U#5`H@_GGdd8#oznUTxqz7=GRq1S7=dPlh7Gf|;C z((!nRYp2j{GmdV#V4=%K%W6Hnc#o;?y}4J+@y+9oO6Br&x7lcV-J?fOb?4T*>b$DC z+t}}3cHjP76nMJ@L$v!GQy_d>{VU*qFlWHqQhjv0M(OujX&~^Lz5R7nz75=sR}i?r z$j|fkdxz!G-*}y$sJ-xNuIVXoe72UG@_y?18qW6jJ7=V~zxF=f?ESjDuD1@=J^ zeidF8#sfWXk`;i5h&~uLz>jD~o*r(Omvj3#yi49C*N?%mE5*B_NH=2_Zd^AF1aJjL zr6LOy=9)6yx}UDbO8khm141g)R2SWvD|#|3S2!6tjFaY_=*?35^yIiDdJVq3T1KWn zRbGCc&l?*F%jgnxJys}ZRxEbVm5v%M_*x{#wy>A}`rW{vKCH63oR+ThGE>A$>O} z6^HKl(`XQ&@|~ zx^H~=CsrkucD_BTMs+?kR*um)2b6IAjijP!be+tLezFza8cS7L6=!lzh5-BV;Wx5$ z=2RT<4=yK;U+kI>4;?*4bOt^1E8v8)v;xjoPK7(Qv*3PH)*ubeN@_(=? zu;x^lG*Z$HPIF@8SY}l$^4PVy6-A}Ar>rTor@+*4dTDv3-7I5r0fR9EM7AO{v?LN` z@W}Du*zu!0mZ0R;jBvczTkw9>pr1jj;94k0$aLhIVh*?P}6hvt(l{Q&&O6}xAS zpkA52$!%}nzIX79i@%eE4AFfprg*VYl$_y)Kl?d@#=u#j8(?b4HRTgT9B2c-d8Z&t z6n?S+uz%`F-l1UHV8C?d^+|sbuP}mOy88&;5cdl}^OL-U08m$if@WZP$X=p$nEE-u zbHPUxz$nRb$WAEwO4Vng{&Z0EP1PTx#*nlH>Z<6-3JRN#oQqyw@MnQQrE z$62P~^dIPNTsN+huH5@`Z}4v!$tB4%L>;jEO@pX`LT^2=R}c1)&$bRd)!V@8j~*E= z*3^ir35xHRSo)5Y*h&8@IA>>l!VXT5HH<^UDR=kxC2kaU!5exbhT8yq8{krb zAh1+?_VXr3at4*9W>rwYCSn5KEQ@Y}SFGc)X(rVJsN<&u3Ec3_~8jAp2#-9x6{1=Is9{=u%98Y;x$Q zLD}jOZfl#qCZyLi3Q?{Rxu{hI9tqvyA1;oBb-%CK>-1dTcM2kZLT#aX9ftDbzkz#! zy?NpYardW!Yakoe`iG%ltDLrk+qq-e!kzG+h&;F+=a6d!Xp@vjOm$Zy8kIMI0Yqo_xGWgR!N2QG}Ap5DB@Wy1Y#jXlw~6u$Bf zuFvOG`4lF2r{-IqYV~~byPmj~ZR@_jwzyfa%>x0(am8oTqxSyPQU4sbv0S%pp|fJw z;nru>InytA)-#`Ifovr2xq`djPboD1160yQ{lKt|J6$$_+0FfsRWdhjfi5*@;zA?D z!4q~s!wa#3fyct)re#Otkc2;_#-?3-@Q2cj>ul zaInn9Bg4WyV1R#tzg`C`BNxETYu_LUf6o;BEs>rb(FQ!g&!)D6lcO+U^kYFgA7iZ> zcI_qK+yDV5&iCRTUp&J2{paAvL1-YR-upWrSYldPCZUMTFcscuRXi9L3 z_(Ju~QA7SLt~U@h2=hbp-CMavenz1_-e%i+xkjcu^d1bXhV%w^Tl;s7EO6;PnEAxF zSL848fxV4v(AsY<{Y>{d`9je2wc|b59=UULjm&t=vvcGp)751km<+TZu(g2J@x=kM zmEJO*{H?7+?A3X{>8wWV{iA=?+`Tar_Kfn^yWHnXk$>U0SLf zyE926MIu2#QBqO7PQHH${!K(tTfR$Eh`V{50S613dbiYf6%K*J4L0S(5OqT;y~~`rp^c91t|wP1;I;O zBDY76>WN;{t6& zUboH~twxD+sL>itVqMUo^N*4by+!aJbgMzAYC4U%3&0)y3~?RpS{Pn2FQr6#K~+L) z6Xp64|NGq7(;PKe>QMO@DkZ%_9;atJi=2Npr&51qgU9&b#7>yWZx-7lACf35HTGkbm(~!eUQ_!F}G1fVy z-7u}*(ots0hrkfY$t89`mbsX$uVbU5qpX`zO1HDqjL;d@D6kS?M!Q4;l{aYKw}%oN zK}Qr+@~dC;Ep2Sy;5Jr}epQ zi}BWmMPv9F9W|}4h^t7obYnGykyepZA3(>^Z`X>yQE6|sDzq}Sl9T}0Ff=*HDo#**e}3USRwTlE?)F zx!It&@L2Ga6TJq?VQ(NR$jM>o+5rzV=jP7J$&b|bpaN!$ zN%)!SpE^CK2&t-@mPg)#7;RHNtD6%C!#=gkWJg}i@s+i%hWe`{*H0~3gSzxbZp_bb zgPZ2CTi3;uM{f0TL7sY4VONS}ro6AHr{odqLNiO9@&cItB?be3B5Jrq&7$rU{lE)h zD3DE&bQKb06vZ7V`{Q8dZZ9Apq3bA1vo~;7+LbMtLam#+Wz@dzS4ZLV+h|bU7uY*uWg|t) zgt#kg^CwUyKC_h)DWH%P)$$mB!Co?7d5xzrl2XxX;bPYzsJi$wH)SOex*w5f1L0w( zn;6!Y6%6v4;1USHW};$I!`)F{2IKse%pO9w89w}9!e4U}Ep}#XF^4rTz;R(Vz@Jfh zWpAv5N@4VgR^)ClgPvg!P{6-yy&SR#`KWq0B1ITT)c;mVEO`fl{&sLu7;$7D+t_+t z!5LVXwB#JhzwvKVWL|_K*O;if!b~AM#M0iNe3U4<;&qhY;fLluYB8ssK6K>_KWWT6 zV+djN2WyOI9?d)R3px139BPF0W^C0`YG#pLshw7Sm`mFyNJTb?4{0(n#_`Sy(9UGO zR^nh_>)#fy26a=`L;6e>58)0l+vgB%;zym#gv+?gq`Zg^LAQ;CM8wC{8zRh0U-eUv z53dowwUY(ozQz-Cbc?$Cn6(%(9(n}h9(z&XY`i$^nr3d3j3e5bR1o8}$aeH^3SVVH za@ZuT4pa~NliuaaTyZAP_g*>+ZG*O*wx6V%Gi;NH_*`Ua89SIFdqaWdiiJl+1`<@c*B-pk3KpF@~%0H1|7Z{C{p88Wyt zZX+A+P{@|D8Z8Ic^>kMd!&PNGxhMi;FUMrgK_Q?e=zR- zhyZ(Ay*-B0Bn%(rUFUoP{{|wfFGcYm^)|xup;|3v{d3bcv%J3i*ARzmJo0f3>D>&} zuhc+;x=6q1w?9!A9?CmFp}RttS_gr2@{_sO`rwUv$mabM)%!jO$GmB8~ z)<6Tz&aL1FA}Gel8w{{sNA(Lm5zqSRO)H0M;%AV+nY*YLTj8&_@0ICUXmv}vyn9zz zwzuGe?Z9q%9d_=Xvz_PRN#@FS$D-w61ocmk!R63QKJLj7K~*jMCEE{dXn~a~xSY?Zey|JRBl(pITX|L);VqsIb_B(v9iuQ*Euc6Z;^UZo1W@x(A{e2U+k3uSIC3=&pF^A)A1 zZ=fIek#&~(ZJJ9W9*gBOwRy%%xBSXaz-Tc$*!LHN9*p>)%6Y zf94$B)I<>%OTLa-D8-tg+uHe^VSnPFH~n|&4pLy|!>wWvSr9e2Nm*}(!b~yvD>y|_Jlc~2?M@Ga@C+LD7 zFFf`z+4_ifX(UL*6=iNC2BktyN^R$Wz-Am9b?FtzXZ+WZskwY(T&DBXeErfGbvbpq z7V|^4$7|8g^Ne{Goy_XdG?UiY=D1AT3HnKD^BgHuWk%fh?F?Y->wl+JR`aOtzM51^ zu6F4k7~SL2sVT;1oXX~Ax_m+tT7^Yb)NVy+2P?2CDIf4dPw>`5DzvD?=Qd`Vf|t9R zQbsA{H-j>kiDCa>PZ=4y6qV~dq=d-3rbvd=>zrJ%ueM~y7No~7QUX0TvNVP>53A@W z3*n@HevvApGS}CVlGmEjGgA146JE%k*sf&4q?*G%+cw{`_}brdiA_Qc7cVs2i#zY zJr07UVBJu7O{GN+PL``7cX_#+GLoI4yj65>%Tl*Q_Bn}t{tYrC?2)#x^SKd#so-%-?|a-Smxk`4sUbzwg>YKB zPyD%!HP31w(XzT;S_1VFoX9`W*tL1DTN(Ep1X3G!a|Uhi=>x8CyiLpEzoX?mmR1z# zu^y#zi<1&zvk%o}4F{eDH}eZ@>r4Ut5dKiL>)Tc*0|t)v4W)txV7Sw=&QV)E9cBOk zse~W^xNl64kP15+y{Li;gP5k+|HJjT#qT>8`q<&BC*8D%K<}72BL)A z%d9;uN^}eyQEF^g9<&6f+K?AZtg+puiCj=r=D%+rgn$kvfKJq&ANDJ z{2$Fa1NAcNIc@93=E(ZA3Ng{cp5w_4Tu>|b=htrF^Cxf%D8p-hH2EK^XL>T{b@H!F z9x=M;2%ped1ler?`T=@+eMkbdFto(hVn&QNKo{T-RR+Qd=K#K=5?}%t0m%Z$gXKW9 z0d^qU;AY_*@C_ZPi2X0cN5hFj&_KVrl!Gvec4S4i48%%^$WFZACx9GCPFM$!K6nT0 z-`G3cg0y|MfcYuYe}EG}44?pD1n>nw0x|$$pfLa}FeG>;5F!F17$OKFcteUlJOFE- zaKI2i1|$zK3aJT`fT##g1V{m-fT{v`!RlZPS^L-njzL<$y5MeT`pyBJfGtoDOhd!~ zSV4PGf^dL602QDNI0Dc?jzUs_QbDYM-|+TT0_;J)d75B&V4U#ZK_Cbc0I&fMAXq<; z;1j@^Pz{OuPyw$1a=;A02FwH75VMaU04G4@OC zKLVxz>md429+*4V00}^pL`KXxU>v{>PzAApc!BNn2D}5rW5C}4B823oBgVpO{na>T zELI?C08>B?wlzy0SR1qh%+8NKwE&C&_5e448d?#^ELaHO0RRnk0)+&^1Wtrvh$e_8 zNGFKbM;2fjP!8bjvk7nsunP^Dq$M&PvJ%$5gQ<@N!+U_MW){4+6efs(SOo(8frRhg zqFonlRgHAqIR%kunB^oxf~Cb%W32?!vtm)s{Q{$zTUV29-H!>43=K4~>sM9VUbCKI z+!C!nxGk*B!(L`atPw4m#ML2$Pj}t#M2i&4?jgC9muJ_;EsTy>QAMG{{E5y86_;gE;e(fOhiDR ztVZK-IdUJj_!;1L&uG>;z%_f3&p(9EUMYm}ln38_S$O{)3X4v46(lZ{+RMh7=E%YH zZ?sQon`0YqS3La3i5rCQLnw}W3NFIH>&&2d5n z31^kXzww_H^Ondp7EMQgvDYLm;e&?p;B6_N64pGSIUv_m z04UO+mochW`QQevtB&JSDeR|z@#Z+n?!}8OLBwrh;~36{fkQVc*`$dl3a~F&S~}h> zBO*prWw0#qlQdXC{$ubT_dIbJcGXUY${j&L{IOZ_qJko7lEMxlJeRR@j)h%%7?Lb- zH8FbN9NS}&rrORlF_+tD(@i_EnM>+GdKTBgIvGyI}>+_tP<9-=-_P~3<;QYDxa3CJ`R@Mk5aon$@0n`De_$hR zv{-z=_z(!Bgykcv>fc8z6pQ(c+LHr=3K8~Ax}pEDY*h7;qH&WMqAc3mztRvxv!}IC zaL9~&)dLI3ON>%z9GB0uck@pLAa{Kp&Su~^N41kW_=7I|Q$_z(aePe!)KtDjFMnxx zCy&`%Ew5Ns7cA#pS8MtxV{4|zHNdGwz7rHVYi5!~)?$$se3(XQ&`_}RP;4(F7<((` zKPlr<*PAEr`OHZ1n@ofY5maTSaS2VW;QOm4$s6NAqN;o=R{j#yS%Zf*x&WWys%n4C ztF0z>hanuI&oBV8a9p(4h+H%Eo31;kpqO-CLqDw7q=+v-_ry!SoY<(&nt^$NW}xi% z@KtK=pPosn59%3M-R>t#v>^e+O@rZ}C$vi^Zk|aSnmoP<4uT>(P zk?i%mTd+#F_}S02^ZGZA3I_@4mWfY|_ZE%mv~lcxx?A9KwtfNiA9+qV_ze)Fs8~VD z%mqL36}8vWz4L5?2b(A?leZ*z)7Do&@CZbCI@p{h&gbv^i&MtuxW%Adn)u0O@6I%N z2v(0~1OWWzKI4WE8|T20@lz!f{zT{8BSg zES;pTRk#_+qW3w;2l>Y_-bY%sxtZW|q~?@rWar8e-J%SzPc*Pg%GAG|6=23$nZyz) z@5*JQs^|$OUaB%s%$E0l@8Uc7w=92%#88n_ai4yok`_J3#~Tj9$~fG})%?!A{bqcV z>e7}5_Q9|gPIP-AGrzfTtZ}#N8^?(5_sTQZjY)h%KsSxtp6e{v^+7NLu z*`rJIMy;szaVf`auIGlSSty~#C?{mK^k829a1%&)r zy1saS@>qopCt2L{VR+&xf{WXnX&ss}QN!F5MeV8W$f;hVb;EfHHG}mWzolRxB)4J? zGXVhG!D-!wbkazuOOW@Himo$XY8t#3caawd*)r3gjWXi58Awyj0o@rk_EA;@GDj27 zawkh7X!#S+k7lAnSFL|kKPf-9D5s2l(eGVnkBR^uNUL6=rg%AQWS zJq3x_*H)nupXr*=G{)cT+@CEKsqEwBeL{&0X6HHx!CFiULt5}9SpKEV#^dY@BQk^g zD7qU?^H|wY5@^jV8mk4hmoy9OX~9ssl)USs&$eQ|;mZ@n#v3&mfF>B}{-~E6(k|EB*Owhz5~Ad%8fcd1(T>JzLwHU62aqxu z-f!+(KjD^`!ne>H+;Uw@!7oH)Yl`D%iJ$9ln%1t5Gwx5b6YkM-^)vli{~-p!VuLP8 zT7oMUt$ttx8O>@uB3EOBRs&YR#^r(0My3xXGXGsHqWI&M9wHG-#u)-3eG3{71hM-2 z47Oq_g?7wMeQEjiobRT@y-5=Z8UsKnL}dXlzC9uuJLTk2k6kA! zJP#5sLy2_7N#c7xB;F@<3n{hUPh&m7i#X0fssQnyA zun2Cn8#8v*Q+N??^5XepmCl*H*c@OY`uE^*sYUHqOem5kdDLGl*Lyo1pg}hPe>_7sU?h4+TAm0zh#M(KFg!8Ko$gpF!WAC-cJI^xT)d7md~hHwMB!S2R&sbnB7Nm>tO`dKUTMSz z*8HKcwXsi*qE8N9`|U6@HfxH})0w1*j>tlL%Ly!VtdpXm*cHBVCT#3R?P*nyn9MBm zpV7lv9SpS)I;mY_tDG(hps@I;OF@1D%35_^ z^mz)8XeU=iX={2F>gAz;aUq;QDE5%JxD3%6l)9fqpt-M&#i)$WKA|!jZvbtddsIO^ zhPlC*N^Ug~k0)-0t%eD78fNFBo7F9c?wr2YIvNFRl|r2euCw7ul~D#=nw!IKI&az> zL*&@c;svB+zivfLj0y5#JU(P7qajB_G^SRuXqNoGC7VdEenSyt)`JBxc>iOewQECJl^3IW`s-N}y! zw8r<0$g9*}7a%oP2e;b!bLI7P+=9v^x)4IvHW3~MA@_RY&*bR}QNf!! z!lLtM;NQw7O&w=EkhJ+>ueXs2B>zs#j1ylo4!!0X?3?lQmaV&{Vv;LA!mT+sKqyzP zxIZ$pMUF`SjI6c>>pz$b!4CF_&`N$h0bxl^&nGqHwXc&VEA|tKB$Il?U6N`mwSGiD z-!YM{*QZL#!Tmu74C>Y(le$KitodP#u-#Cg3c5gqdK80&k0Xvt3Bu)xF9m+QWwS94 zZ-q9n;^M|c0^CU7yD*yfJ}-jS=pY~ypc%g42YIWl1^u&*2rbmtYE#k+XWr3b4D_Og zhkFAgPT8yY< z*A|ss>VluDpQb$SxQDn98GW5QYG5-i{M?lT0=cUz1mM`ZPlB%%=^2I+C ztYgTYhu)qm+MO^%#)WMFIzyi9hscpIU8H~TG`pM3hh2uPA-CB*>ztqXZ3S`G=(YU8 zdNh=ygB)@R3g$ z;kvM*_q@>Mi~HnN4qcy(l)sLzgL5#eZ#rs2b5}k2{^cNJ6qGIBNmX=}WE6@QmxAge}sS-4aMUl*G|8&mT2&GX}VjMvg`g&Z!dk!40h zL~;!4LDo1OD=ZbDu!WAAkn(6Ur|P`kltu*Us|N}4ksCgD7!5va4Cud?U2e#bLl?o( zwpull+~Fm(Zm??(f=T&`yiD-M3i-o6 zt^HCLlzZK8n7Ys!IrVcxuyQ&6&x%60Sy-(y?7_fh=I~6Rg?_k!Ik`)zu2O7O%B5lz zKJOTjWV;hi-57yF(gF88Ej;bg3U4z#iL2>1+CQe7eQ>$)b9ANg}hkvXovZWKd*?h0ZG!gLsP9iE$Ms*Ulk875>R% znXv_txmrbRxBfLAaQl~PjlUR$as8Wt*9I@y5I}H&1Ff@Dddhd|=A_z)-|K_etpz+|cl+6B62= z4y9xGk!w_LduTtx1<&ReUv((+<^_STb0MBne(*s7pBHW?l-~nI}J~PAKu>kHk)?lfaO7Q@Tlv!a)gDV?oR*XrruxGOAc(Hz4vJt!GO6 zM@f6V?#_`7}`ABiN&+mK|+msYZ{fh5G9aMH7DqJ7$Yc7YT;6t|@5L|AB2 z2Ny!vE~jNsrw{Xw=BpNzDZe>)z~Amm;^mS&^Jjfnq~aF-ya%TqCPEvUMsQvJ@ynRS z{Ym6_<`4DDJTy_npC8incUJ*&eElnq-RL3jqnzj)KI5s0dvN~qs@?Nwq>(yP%7;P& zDWB5lI=Xn^&09EtNk(NMHc|1mFErB+np=%bf+{dRs`g%jpJFc$h6rc<(U;JS*ZC&P=pf`+HE0-v0n-K$pLmTz(jQ`Vp_nf9)2R zJ!0-_QQT|cWpN6gzFV9^$j-$n)%&L2&ytQzs2-X?8{ce#dp)icdQ=n=?U-+t;vy5I zxSV7%yUCYN{{j*q8&heL0@Ri+~=~>^@CJ5+ab%A?v_? zD(){vfIDIxsoR*5qDRj(#Ybp)$I)~Vj^uoLmSt~{SM53w1U&7V8sVx5>ey^G!)VjP zJF;{1uQB?0?BFi=MI8oFL*311aSZI>^fKL)}cn3D^exQ@;FEfMC6203BJ6=U5X+k+|%BLq@}4?-#6Mvp5Wpj;pDqE3Yfuv&*Z>X zV)J_0(#Paz!?)i_OUt;gQQ4W?T{Fa(n#AU^p18RhvX3LqAHO)~44*Ix5&%jtI-7Sm zVB(>|gM#&7un|J7M36*SWxGVmdW&@!p}bqECaA_13TDpZ^A= z?Edylr&9x;=Q$2*-JhO`soB9+iW4kan5VVEJS~COtie@l*GRo`x;>`FS$rKD4agu; zY*&}Hi0LhkgDKARwngswdS;ae*7Mh)FV)USENd%uJIb!3y|9T$#Vzvn4MjaSKnv2x zw1{X;L_DX=gXk^dt#K%~`4M3b&H>?}k+YJvdb%dHAw0$Ln@{aZt>l>X4 zdJ*yN^ItpomK2Ajm9Q1?L|WS6Qn@aX*TAfFpwubRpJ}4Ezh-?CJKr$CvIs1ypqi49 zy?tb}|E(lkgj7s22$e&`-@KM2zW-{H({j;Se4(DdoRP9QQ?&8%g5E*OQou=R53>AmJ?mx9=GKAUuZeRxr2{H3*O4 zyOotFCCFZ1#W!oB4`*DK_{%tsze(jGh{y37t&!02$nS?Bz+gCl2~v)KvqbZ&e#$upS)p?ShNlv~A=DfW1W6j18& zXMZ=azbgrPoa+);Wb78e2WC7)tRW-oIsP&d_y_T2z0`Ar+{Fhr?&ky2(memIVn?s< z%MoDd^3%q*lkTG8d6uyHO){<5B?So@UCr7#fB_Ef7RI#ySQy?IAmlZ;meE#v-N|2- zwaL-C6z^-?p~l4!$Ncxl%$MSiK=>S?o^I=VpU>z+{B#|CI%2wqU9oPU|+CX z@ZhEt7dKIgn=r8>Z|VKFlH7B;Q)>=1R2X+SV!}jq6R_H^BT^*@pO_p_4Me7lZ2&~R zguAPNT}W^4k(TC
DE|K%k2FCN091|hL}2#fhB@!;CN&X6bc2_a9CGA%0w-Bak? z0BJjeQr{sljq|1VcLS+iNi>(WJ@ACz{R_AXj4NG7$vhvBe_sQ@_Pbk`yzBmbC5Zda zm0&`!sN$n{_j;?|#8+3I<)8*cTWsUksa1H`V6^COLH4rIj%SI(;WmZL`ik4Bl!?&+XA z=J}GAYL8rOJjL@02=C=2ES+3^i=7+aQmV2Zb(qv|1RW+m)Z6HJLN95b(EFu%7t)OL z^ZzAD)_U`N8Hu^Es$$msWaaGV1mC%0#_MadkXQG_Wiaw6g<7FEE3w>WXa~lhQQW@- zcT!y6i2_zZA+&-jAEZ*mi2%*BD(z?G12xh~Jf9{@+E0^rbSm3!h`B4NvzQbQv_a`E z`B?NKue*nMq~Z{%*yz47jk464oi`xH>q%(Nc4^{*#?_zrkYY&eI8^JuBqbgxQ&-~x z++E$tm>IYWRc(V8Ka~d|!NIB{?{XF21~#6J)CFRyP6?oIt2*B)_NRMj z>vrl_iopCv_B4V)1*2^@BvzQ*nuU*pwAjRNoX z%#1-`*Kt4pXBs@@fuX}9hmROJYV??~QRA|6a#yU(dvaC&>Vm?er>r(1I(9-_{G_Dh zl&NX_%-M6&&GQ#p7B5+v@x(HF@tTsg>te<~I58n{@|4tR(`U?j=;68Z7Cf@((Z?Ro z%v%17()DHK6_rmrp82m08#g(t#LZi_KD+Ig&;9E8U%&91?K@t4>E++P^1D}ezE=JE z@89^tu0QU6^Q}L<{m#38{>xwY{O!H>U3>R^@b~}Tf1u{zq1wYA*3}>R=;Kd5{p{%H z#~K>HIR1|lUpAdQ_0{RG&wO+C+jHkH{PW^>ZqFs}kK0;YzQ7t3PBD; zNz@j@X;8pXbhmkuQWLy;mI9uk;Jb6 zwDL3@sQpq`&FCI|!R&reNhRkM*)pSh1s>98G3T4z8v{T~y#4&sD#dfB2Ke%1H{Sn@ z#}=qe7s*0ZXLge61wW|<+f5zJ{BLFU-0C_J>z}$D81-VMDGagB=t}l zB5zp_h;RiMI#~DzRHsh90Q2I}2v?xN?B4o0E-GvWUzlIaH!-HW7_i}f*k4oZ6M&uO zhb^br*++e>KGsgJHY81qa837%w+Q0t-9wHl2a82$PCMJD_#JT4!63uhHEVD33lz5% z$;yrRtDD%l;PIL$*00g$Dmus>U!hn=Q7^P_)lrjv}OARumXBA2hQc6!4kkS)|ol6Z4?NURC2$6kqE!K$P zOAI>~8<+s=`P+*Pn={(!ixiL2E_H@3vDwxaJ1tiJPEUS#BYkm-hhZH0mVq3N3634b zrssZzK<`_u4}MVUs4ylhy2RmJqZ8AiSDdRC(?N=JjsITPD9+F)YEvfKgCoVc#>9~1 ziJ;tj2t^H3P^JCF@Z^b(L*?|-Se-l(nXgX4FJ1N2iT({f zP@aB{Ud8I9ZkCJ5#=h-qL@Y}?vgla+7s)_hQp-sMrD24MDgQ> zZ^c8yNClprywPMhQWX$=L4Cye@eDrkOgRL}Td7hpHX2A@b$GkkUHu51lgKFSqkoAQ zIi?;$z6|cj`3*BV5Z2%82hB?>nrBN?;F+soBA{ zDtbu8p(1bGn@z?y-uQ7oIPu%eNJqGG3^0tPfe^n=b{r04&J1h>0n;Zc%a(XPh7S?> z5GaQ4W(YMJWH+?Y57H)%u65L?!0OnmC112^qFTC>>|fA!Y;+Tj1{TAdD6Cex=Y;zAsTeo^BfKU|j<}vybbFd!{f$H{wH(U%LLY z!Gml8)uplhVWP7q#e05p6RXPzFl$};Pl1Ip{-b>yx%t^(Ter#Nshjp7@x-3VRlE)o zW@dPm%Tc^;=(ENYJR#2OK?p!x{po1K-2Yik!g^|8YX76SDq&UmA6QMop+hZ zP49$3lQ|+pO;(dNBUvbC4}gx)dtrQym~p%Ed0( z0X2}7ZgIyk|5w+=CaKqJp(pjslxUg741LA`i8s022$8q~$3{Hi9M_vd03!1LQigXvVj=QZZCd zLp6I+DapreYD!ZkiA^P4SH@1Zdij`c%4cx9`o3At^hI!=tT6d8N}AY zaad#hE>i<}lUJ^paLXb`vTG`?B*B+M(&CNk3px%g48RhxzM4;xAARcB8QlSv$B+ch z9#O9yl7ME&1$tXsL%6O(&UY1 zM-K)?OBDw;8AyrR)2_lz+q=-;sl4BH3aHw+$*|p7@4V&kwmWVG6{|f5GHQtu{q4 zg2MQatVSMSeDuS&FXo%+1#9~eyjR>QCeGa+gX!QEneD6}sln!G*W00kcLkf>J!5dg zupE--;911>V0&NXD%dbePm+A}q~d0&_zK-m48kyPq919kkF*egWV$J2&eUVnP`|{V zA_foc`^wp+wy)sHqGm#<+0t>VvECs`0`HLY>r+Kbv&dihKu=;ma=#X1o-fw3`*w@j zb-QLKf2E72`3M96fzku=ahX4tOgacPzRW&IXbMdG{J1NMg!dfw2RB)6;w z@R&NmaK=IB$=EUF2qoKlzg9{YU4}ex9_U3N9<&U7DJviIYVeIxO#P@yE_yF;~6g9 z1Fs{VZuh_|EjUJEjQ6HzsH-%SjtQxUp?m8Z7+9A@#Q#DsRetneZBnxQVTxST7MV zgimtZ>?eddZUzY595*>Z@3^VLJJ-GJLB2ddAw9eAI3$zsq@(^rrSZ@r;eqk0XJ0lt z({D$A&zeu*_QWHCwxaAdu|JH#6$f565+PKyfZcydIiltbW`5aA$!z?sG5UhD-jxX4 ztvC3MG9&AuYP{SG77H@t+acm1tcH#!;~>X&V*kp!nXQPaz<{o)PK)1s>Vt*x&hYej zXT+R%M{Tw|eVh|K*-9A=s=@0gl4pVBs8h|5 z*?SgPySZNNSuH92whjs*H;f`T@$tXlrZ45DON2?F-3e3aWCy5#5y`bGLW=1i#vcQ z$3b=;*WohYgSZSB&Gvoz>^!AYYnP^&-9tR=zynxCXLNlC*iXKo6Kuq4OdR< z2D5X_G(}&s^NeC@jY2hrt{9*GbCl_DAtz1~;d*YQVxMn`^u5;e0$2S!XYZ$ME#Y%L zlVX(DPI`~P)97^jk41pF276bj$4Ke@(2)_Y=SP~|dWdhN8J=?TO-}wqg2f2hvqFVu zM)Ygcp2t+3tupFy-%I^Mx^V|NaX=SS3PyIYrIYFUT!K3yTQRXaSqEV;^9>6 zdhHn}e_BjGC1x}^YB@&(!Go$eRTu<=XwXS0X*FJFhRH-?x)D_S*Q8XJ$m^~6+zrFC zXAs5W)9T_T(Q-=Un;bPJMHBDO?l>kf`T+Z`g_jQ)NeJ3ir~e-y?eJr84l zqUB8K5iIg)>p{_S1`5RSP2DZ0Km}FyUZUlk$e;CHpQa3l%1C-m8ZqFBzF=mvV_ycV zF$0M|!ODwiI z+Z-#E9}nlmjI#<4jv5Z?%_j$cX3j>qzVc(nJ{DiOGy`4Sbes8~moDy{F2Z%mkKzMJ zQKlzfaSX-{zT^>RcN&E0d@=ut4-0vmDi$d`!qo~5{jFj21*Lv5X7}0$*vbWK^U&Z+ zqsjxIwHFV^=4-jY+E72G`TDA^^ek%=CmBX&*J2cTy`x5QG)jyhn4u%fH97r|tzb-y%!fg$|M?~nOHS|dx*WpphqTbG8e8NhIKtgkA zzseqLtJiKKPrOjCts>lfZwBHx;{PNpbO0b2=XrcI7NTa!QC(k-QU)aN2u!6Su8Y3R zFy=BP=8wLZou8Ve*JGp4Q;92Udvs}3X9k+Ba4gZ2p!&^r=v>B-yx}K{uyMJ**dGU&(k=#l^bsRw5^8Sc~D$RBnc`K5X zn|QyIZ{kI1$^(PGg8p=vhF-*r(3A#M-l9(q^wiw@=xp+dDFkB9&^XGjtHJWmPVz@rO)O)un-nbzl_4t7+k5)KK^uU}A*2^9vDufW65avKPYG3sfstBk!p0cZ8R% zSg@xB?Y*VAQ#$wbZ_?7DFNoo-nxu!k0{A$Qi6J~b5dyUoZN7p*l?jRaI!0g`E zLBQhPeOL0Qu3@EazSarfXYvl>s*vwas7MRG@BQp1HUD=TcBO`PhV7=<8_J3c=n1E+@V= z*oHkKY9TOvaVAETnb^mgKv|arqK!pb~~<_c-jbM=N=l?jv6-nK9_&Hu`8ZB?`8Y4 zw%3EUy>Cup+nf9fv1fQe^V-$+c)8{E+xrTc=U&p>(YxAPVOCCi5&`dcHnaBjXtRu^ z&8?5?6T{Jlm1uDxjs%wY{a_J z+EY45O*^igSCj@g+RMv&V+{!1UF{$%4pO;7<+Bc0F(DLv>542bi~AeJ`M*nH>Ftpb zSJIdw1*3MPw)ohMYx&=eT{WrBNTqkj)Hvj!)&;O*XH!x2O1)O>vb4mN59NC5d%0X8 zwBfA$NiGfR+$KW>U)U?*Wtv#5UGEr*hh}Z$WFne39@T9?}M zCSmU_mQh@nKJMeb4R%JqoIBy@InY~BSrMWY1C=DbXI|n z3D8RupU@eG%3Ii_>-*XEK)K;AEApm#f7PqVTWKt;nVj-=l)~cv)E5g=#?rd&#e@?= z3;pM7ik#;_;@?7aTBa8jw4b~*C@;{4^725&d>BoW=fyrOuOmU%f>7?KA!TU$iQW#S z$LsVbrud$l(&Fwe(p7u1xqCE*wtr!f2XV4RPB>~Y-XyX`-b^}MCHH(DuD#Qfl)9J} zjN+Zs_1%j|Kg!)HWyP{;4g6P@Rm?{TAt$DkbzCnKEt8lm3F;< zi3UTN-`PP~yk|hX=M7&}d>lC6-QA7N`L@#YxqT);ySumBZ(#5n*|Ghc`c5`J=}XTEs(jt~-0ytd zdD?d!Me4%&=Ii$^QT$K-X12;_X8Y{Vze=6$&uYov+Mx>_UX|lkz?vxf5bkJVh zix({Ur@Bzck~-T<;g&@^SDHS^NEu!0U%85w3Tm%+B;?_XB-!#ZO+*OYX9w7bT`Q&$CFy zm+3`pycpu2+_y0JT5reUF!$=}D*m#Vab?rSj1=z^N($dC5lr;=D6{)7z5U*7Pw0~2 z$onPpyUdnPI(;D5aPPQ($(}F4cfFuI?!WBx zrn5AzRD8hwV$=e+KHRUKqPx_S$uG9+q948A^up>{w$tzZ>0IKv9@S}!9*;bwB@z2j zF+;;P-X=v!@5e{E`{Vg-=zI0{AbO5>wGp-dU!TGnfKS_9A!KLi5QBEz5FvE`x*?7_ zqr_ifKS_2irl#5zU!6O(dPu@vNpeCbQGG^Not9MXnp(XqwR&j^SeZMI>*za;)k{)3 zp2_KZDlN@f*X8Dse8kBWU)fF{PdN>uzOvT{5dzi?@vWN1k5krF9nk&sz+FwW5x-L7 zV?hC)FVv3q0Q&>3O@(G$FPDn1M7Y)skx%R-#^4zydYRO#ujen|!tg~Dn>K|A!$kg~ zfxjRO?D{B^(bWrBcDARbdH$;I5@_$kQUSY(YI>u%T#I&K6tV#+@i!0VV#>8@nhON| zhEQhMi=5BUtE4Cr?MW0#V%!FU-9QmPH6cQl#W6LOR_(d23Tjzvq^tL>cYy2#Rbt$p zV0$;VXe{58{g7js<1wp7jJ02NZ+VQ4_Q}Jujic2QzJ+(op^eAbGaw*c8%OVB<4YiF zPcG*>fPs6o_55`_=+c7s`!CA}Fp^AyCMn3?U1C2%M-kVOf`lK?$6f*Q5=1A0>syk9 zdl;t(i@N>5q;W8c$}eQTM5G*}qwF%li=>zF$VGF>Uk3_``JgjuJgeb6w)E z<1_DtG%3g5BWNKF3J7W`vKw7GoE;!a!?A>#?a(3}t-e!~46EH<9XAdtHIN7q zwDHJC4gzph#)#Jo+|MJG3ORn@cAPZQW0`^O{$Il^X9Wh(GAz=evI2X39mz{m=uT)x zDj|t+XLN$r;+}I$d8uxK1SoeB_`M^kg2tdTf@-|_1QKz%)rrk`qE2o1BsN3wkK<3X zq!Rl?R^(_YZb=GW=!FT|j+jRI)i&jc+wVV;-v_~$ZOra3+Aw2W{28fSU@=h+k zgzHa!w1begr;5b1__Ii#bqB=>swv}L?~YRjEIErJB@1?1L8f#7f1#1T7nQ`i@(&&D zI@>VU-+TjJmp4$J#@pJ!pRV*GtNd!izg79H*5>ZaNM+s0a-p|(RD{drSHj^)+B+t~ zwciifgCcuNaT%!*uETx-H}RJq@2w%OPyFIF7}1J(c{|nQecwiVhO63cyZRZoHf`3H z#72q{V~8_?#E4C!BT8bO5n0iIQjyV3mA6Q!RsDg~O+2RlVk%CpwjLADS9)uvR!AzF zc3(-f=WFiPp6Jg8SFejrLd=`do=-UKpzy%`73B6?u@}T62WqBXdp)*h_vV_dO*0(d zwL6m^jox1~^#cugD`~P_??@gJ2WEtO5~r^b7Va|zO*$l8oKz>Aqc3v}w+B=mt7_&e zZ&i?D?Y_Eb&uT8+`F_K=&A3S*75i7-20+h$P&u%cg7ZP`(sv>z^tlHXttCqx!mtt$c+`E1C?YHf>X3TIVgB-M9 zjH^AMC*wbQ3uG_|M*IFS+V>t4T@tcAvECN+%NyTWHR>a_Z})AD_QpCxhQ!rkN#iP~ z?0&>PNIX2cwzzL1Fu0~??UK=Fi-S7?RnobAInjH9J{wGjh(8C(GvEDTG2X})jl&+{ zY+zVH9sVm4_55vp%;t=C*X&ql9sW4X?Z}oH zdIxS3wJ&h@#9v5q@V7%@Ku)Z)e%t9sN#x68+5?j0`8A1==;f=q`j&$ZVNlCKjU8W( zSm1t!&}WF18(&vHOG^u?hxzDOeazladSbq|;k@|%fTW-nq0e4DnMdz1Tin_B%W(6} z?#rLiLo>KNrujf0GrG1Tm9yEoaX^xM*yGkf{C#Jbh0Fex@sM7u?|5}+k$k0XSR}z; zMOcVe!y*kcw8CuV>RmnFTLZLqbgR&J5xq@nbRYZ#=p@z)I(k`kuHMAR;A3wZCBAY8 zIS9k*XK2{31A!b(0uCSaWj1+nHwVo``<-T1~E#X2Xi_dHF1SxKA- zcILP)Oxgy>OoIMhAI)o&G~T&$fo1Phpq9{Hta7$n*pS8Yq?Z_-anKi|pPPu}M@}4h zgDbx7g$Y84$QymvDe23WWs=D2eRhY}L{DqUZ}FSmKMs_ckk_QxFD{|+{w0k_?}mOV zM`HGkZ+%zvUFT!JS`rDRgO=$Ih`>gH4+BU-L>2parA>kK2)iCKNC#tlkoOC4dHb;R z$}i&JXuTXdpLPc?0D?!#FKdI>)IQU@tn{bMmWvYx4l;)D-tH#Tg3X!hwz40 z?GA5igll1}+5H|~w5+v=SAS`!5mYz6eF45SH_oe@#e?wwiHzE9hDN*Y#x?Pj*igGo zJR%-~`n~o`h8X`*?fJ8h{5MDR-4UG*~8oqhhe(~{IG~^zyHGH)8ts5tAeC0Sv z+^e)+br!J`_<7;a7 zJrT<~=sBMa-o}>u#SE?E7Kg>Q4mP_N6Y-yhMxoat7?N6XPJ0c=8oLcFyjV#% z&aTfvz5!}7w0*LMSm#dG66^b7I1ot&A|H!4ww~N34%oU>l{iCF9KZRbcrEc``xR)O zm$qiKRosRl7=KaJ?HvDDilE1z2IslOi@k42;l;6r8vE!moV~pX+r(Sy*3GBH9~|FxYxtgh)c-KwXj0G6Y&{g|oURcA zBb@=_3`jFw5=};HC<#mZJK$3I}^vL zOxD`GDKK`rcem5piZNRj%}2GTl{Tk6GV$T|VvSsP*M2`pZf1ip{gTX##a?wsJ!)xP zYB1;%xo#kXGL3l1P%oHn)N{l>aPC|Y$|^!xp(0d?H>~~l_A~Cc#Cm&rjuOuoWE;%y zRf%VcdqWGk27(gPV6YmHc*y$Q8cpIi#osED+ImVH>s+k?X*vgPJqhB3x;QAFQ7_eW zDemTziHCsVH-d(#gA(ftjCF~9)Q9ML;nqVes(recuZdKz)>ykc!661X;XlYIP31ix z9t@DWZEZq-q&N^z&H;|^n<3ifCSU`+6YA46&60S;`#dTSR_Gwl7q`XJ;+JuU%T=^r zx%xKr3CCuNZF28(xJ)PGZ#0a)DK=o&bK@|`?VGD_&lNvz@I-9Q&|mv~L&LS##ag-F zp(=6$E9!8D?ybnGZqp_mv}^S>_G{k$NvYP}NlVtKG^UE1sa9jf%_VEp6$ed|4hkn? zFH~I~eQ=O?6)1?OEsKCBtuOD*r;x?C57%hL`fIOmJ(ZcU`A{v!q5)b6Q2FtB?F~WO zzvic2gka2CH%C5^jd6DrsjWzUe<~4zU(HU9_%Qrf;+|oj4IYHSNh)iQc)5yK?SXDX ziYtMh*8ItVvvHNu*|_2m#}67Yz%X4UG)n`$m%&D*Xgw%R@cHXfgSWYs;x5G5^nhuR z8fMJ!HY=zQmh_r5&{41PUiQ6A4i?*ZG?efby2bsM!)W1rY1e?2(;e_;u)aPy#H=1} zhGIg=H(aaIb;rK#|52)o!&}etbzB;{g*Td&yXtiH_QjXLdc!wr$th$a2T`M%SvGbzoVj&(Npk>N>{V zTwE=Fkr3C8SY^WM(Za-bm@ts#iql_<#%F#F(nF4`IqTynVqAF885TfG@I}h=v|Jom!s?}fMP|bSdP|F z_8FaW-bHiHJzHMS??PkPKj+~hzl&vAOLN?H?;KBxNH`yN!B*nwuQ@`9cOYaP>eW}I zf2*S+GIdT0QmTvH+e2A0t(_>-jSr z@eB*tuP0mh5Inx^PS!dtuR8fxoR-&}{A)pt<^AZ3vtjl8$6Uwd1`P8C01kiJ?qf`M zNDGSLU4yq#!}jY4FsBm?uAQhZUbReL1dcz2ar;z&Okrka`dKq*{@Gm>cA&N^h=AC* z{h^&=za_^O)6cdX)CplhhlJ3U5Ajzas$;!s*Bh9{7XBkAe^KOLH}J2~S7;&eFalC) z?zp;&7!Kc>Dr?3IhWy1X=^w(drLE)Llf0>-<#iGBpf_7bv{ckaZ_032l(`eix;x5R zaGfL&*GYyG!n;{4jBa_|efuZi4LGa}v+(W|NB zKZ@SMe>|GM2sPv~5vaT}H7FR=A5`7?NzS^_#b-pz*~)W70~4b3i$RS-Hy^X|fy8LS zvSPoPa*EYGM8Y2f!g}@0SJ&|u2-OgjtCoNY=wua$6X&*psAPt3wF6O5eSn?BW?OgfnJ!d80uVE(2B=~T>)DF33q&v?Sv!m#b2a$; zGF#Gjk3NX);!W;n@^eCOIr-f!{L3c0zA|_BH{Vp|zV*#FRnNQ-3q9r;zwXLg8onjt z;|1{FxdmeSuGD#*Bpx{0CvlNK=V-lyw_kRZ1v>bb+db=`8$CCY-{l!|r)zIZf7b#E z94d4d`4@NKL#%A6#B&|Gkr$~y(Bmc%Qt@&3<)7%Xt@B59`WY_$MX~IS(KjJ&iZBe1 zKj6r@-8Xc?_@egwlSokVjN|mTFTM_v$`*5FFJe7&_H_IWy%aJx=A(qqOHx_tpcWxu zUo^DweI_!Wk)e;^p2B_r}=)g_Y(ITM`lpNwe{EvH5Pl)R`C!IH_p80?p>=891&wPg_J*U0cwGV{Ar?n2wa7;Xq?CXtiKCiafo@t;+#{!HfOmw%Cy+m zhm803fmplnkWc7%uW^?K96iQEW?|zy_yJr0M!Hv(J~yr+DOzZat5`2Z*}1uBjXr)z zMWndD$4hbh;@uw@aghP-OBsVU-P6Mq6H>P4!v7v$y)WLC^lbJ1_znxu_0Y3s_wz*A z=&#rAi`U0&j`+JTqGFTMh^tt{!x1&{Y-_AuJPfoW;?@=$5%JT$JA8U#aAB&l8umYV?5KN z>J#yJ$TUFG9*&p7_s3U%8t+K{G#*V$L%_}x@s3s#9uy72eHFbu#V;`?#n8(b`W=J{ z=e!0#GGfH1@$5HdE;*7<#1s1;Ja22zH4Ln)Et-1m$MN{EMHhOb>|qrlALDiNP674W zBM{p=c;}ILX8ma)a?P>oBk^4#iV-K`nF)B@kql{Y5A{gAR8EVs679i!Aq4HgQ11}T zNaHo)m(Cl2U!h(3q3jN90bW)1a0jo4{z>m^GU3PKtB=N0%8v;{a0_UlqqRWjb3ZXa z%md-$_x4mw%-^Y{oS{2G;H_hE2Whkr=%t0{{E|x{M`(pa3%G;rUrVjauui7h@wI=j z?Rro`C5T&W?+Lh2|Ja^xDhS^jjlU!YF%n9jkU|c}V~>OH#{hZaP5(DIp;>uqxqmOJ zj(E2Jn^E<|v-;nR8cIAn9NqpP0>(r= ze|y<@oWkAC9lzf|JQv7*knS1BEkm)|^CkV=%%{gIO0O0MEO0*_l$Pc^1aj{<(xa95 z+n(Ko;&e4aXp&7ZR(f;CJ8q#w--ArvgZbs#g#MJ?r}2yJ`gXpZ7Q<^-s(+Wp-VGmP z5d!e39}VwWE74@$1(+mCc!-v2I$n&*5khIqo{m;C_CQ7Up#1@~@ZLxoFx^v4c)5Lt zp(wg3CBRLhjf96bC}y-td|Oj|dA{dr8CEL}wqt1O~s$ z>|T#!`r$aN>NIVnbEziMIR{iA%-ffRKaSz<1%3Rq!*{aV??wH}%NowI=&tc8!``zC zPW~Nw=Z4$ubsO5-$zHT@)X;pN)~cV_0!| z%Y6}jUkp2(863gB;{ZqQB^ALSf{Iq`liG>WQE52PRAt%C64OFQL1B=8->UY8@|fPg z6Rpdrwd~i&c*Dgs{Vs=K+?68eA}nsrdHSPKp_T2kW33nH8|5ydfmxN_!0QBh%mNQX z-nAxX^!<>bQ7n@;i`*{|N4v)UK99K-?VEd6l2GX0H+ZZ?WRWW5u^07>?pbWTdk^1nZk} zD(|@Jga{=GrHEU|&$yLWiC5@v#MJCyxl(d+<^XgN$!UVx-Qy1CyGVx>y+{RP!kQ2$D$w}pP2A4R&_Hzt)s&CHA2bA|3S~S8g9?1( zg$cig?m}m1=x#j}QSLl^rv<=z-+c1J3~iEL2zy+bt0_qpzdSr;w{yzYlVV%!g<87F z9{g^w`<$di1;$c@FWe21yt3|g;*UicY8DGP-aKCGDA!2#y%AeaE-<@y+>u|G#grPP zZxT-&o)}rB;bSj2CyG}oeO*$pa6YM@(0A)eIr%9}?iO%osz#`#b3-f~Ed@rR-QIqJ z%~mg#8O6FC;|~qvi27JiqhQ!O;CFc3tN5xnc<;Gaz$qSW@Ho@2?tFQ|jf+nH`sT(h z8>UK5%LONY4i6Mu#OX?gM%{#u&t+Vpfqbh+t&)nbI*&BCod@x!c%4T^A5tRDUm%}8 zu~0jLZ*!)*aq-a7EM{C8eFk4D%eXXu!926{CH?K2vL5u^9k*0`kv+l&31tVP(7mv_(IOo-{1MyG2;%azfV zi-{kXjbZb7#7))jtP+PUqP| z|W24}HGJYf%% z`1ZrNcWOLb2K{a@?TGPdaE{k;yk@rjBu#fnPr9V63f#m}R?(E3g4uxyiPuS(?6i`M zC^PUZyx+F2TtH#l<}l z$1*Tq@ZfJI8`<^pP$3NuFIv2->v^M|z4kvP+MWqM9qAx@;FSq`HOyd4lXA2W8cNVq zG^!}wXeHfne5Wy~M9?HHw)gk;QqZ9ky$sM(?HUKKQOTyiQ8xV*=J{6nchCf_gKs_N z?I~uoGHY{L#rbbw3gFBD`?@ueH?E(z!%;&j8%c$1`G0>V(Q+MsPCAjlS{xwH46egW zKn@>!hRqCGyUYx5BLIrv`Gq9g7NJUOP#$ili~YfsW!DK9qmHtx1en8lLT|9_6($&+ zdTnVeOj0m@HwZBfp>SkG%dh z?$%}8-rTUIxOH>W)|vyCzSA(c$Wdk_LT*e82!AHc`*uRz8jIMj zZf*F%*?J>41TCKooqwko%6<+esAjD(ND@XlZ_aY2-}Zj!0Qx2k8S^PtQfmLFA3d}Ch`1JjsAVsdG$-|uL-!dc~kg5ZH>n7%@I zCcW+0DmGVMY%aG4xE~~5eZv*@F@{#1t*WoORrPh1r|M|c)!4>{a}5m*Uo;%+`dtfi zxOC<@c5GLuaIJP*dduMo!Pww#_^RP#!>Ni!!dJFSfu(BCIL^^d$~Ecksp^(GwOylc z6tWC0_5er7$_GR7Ka(Rl|3M;{D)GxGq|tAUU3a6NRIH8jhU0fhlsBZMP9+R)sSBVa zA}Z=Mjt1iRg7hN9&?3ZO_CdUof7OYqAFDpA@>YFQ)mn8p_JV>}zC9JB<#3A7#C!kY zxMKL@SxE?0f_Pgq`0dU58v9_wSN6dhPi;KuxDpD^aM>X&)l2rE4YwRubh|?B21O3( z-XEc)>xcgjbSqDlvLB25GI<^+WkXvu4W_#<##!;6}YvE<{&;*IZsHK~+znD0~NY zzYb=|j_p;j!@Q+9QRGA%G&yUpBi z)^Nyh&``U$cH2#_YFn$Nf6F2>%SjlCc?qMy+BEDT<*GfEuPn~Ys5R6={6lulo)qs7 zd&nB^o=Wd`?j4f7$@{(gIZ0^PGu?5K3yNF$p!XQ1h%-q)qKhce$AA;+eUy4L#Mbd; z`jVIgUT^Q8kfF1OC!}lb-4iStyKzs7p$0R4{E&`R9fll%5q-_tOBL5EylL+*_9LYe9PO>; zz4To)+)<~qU)*@~e9s#vp?Rn)K2D(ueWu~mxt5JbYYoQ?Ultb{5 zBhY7{nbA+o=p&|wi6Vg?7U4jMgkenpe zNn-1;ZrF@f#!$y0jy3EsMD+cmi3l_3YCv;&X)K$3nN0JJtS?|!Kxos2pk2O+4NK%`g^63A@_+i*4g;*Z?A^y#?F$RCx1z!9s?swfqBO8vl{lz$*7) zM|!MW&m(C)k72&?eB>lPc1;vkb@ZCySk+N$Ojy-pY<>M@;58^!4N0)JX?6J5cejp8 zEN=D0w_6rD`62fcX$(K4GIt26a3{4v4O-va_WGMSZDthSAJ|83rFA$qyCYh?dSj?! z7>vGAStqGM6~rH_ax>ba+iKYXr805Nq$mV%3^JYbdk?s{yOK7^}PA;f61* zBcb`7z~*=EsNsa+3;i+u39-KA*s-%!&7i(eg(9fgp&K3tx$)&9T!;G{r3n`DkYHej zj)2~k;FFz?Z}YW9XlU5npwaPK@APd@wFZ7jr`nCCRZ2RV?jY;O$Z#KPEjHcm*1u!Z z)qDS@)L~|ZT!Gu}Q-kTPp5oj8UJb5mg&G|Hr<^~%`}WSa|Ni!eZ@&wlhj+L1!FU&$vwKEAjE1RvUM;5b`Ba#yPj^ed?iu)8Atv={nQx)dh!vn4we1n zE!oydZSuDL`+CEoF|~==_CMAerZBzdn_f+xU29q7eofVI5%l7r zcOH2s@151}2=A1>E1w^&2tgBGF|90IArk}UJ3k%{6gD+5OuhDfIye)?~LG`|= z;$nsV;`m1KV=!#wEKxr($FF(SOD8k5k2?-)URt~avn+0*S?+)5$UE2H`R1Jq?|9yE z-?>(Kr9y4^SWr7YQHjUITK90Zcfh`ia&PFq%5tw^Url+1WU_-5!Bt$S&|e>4139&N zA7Ghf z)@1A*L`EMyZ)mvG&~)sZiZ95ypI|CLr!givRhcRl6G!_X!7!Ortce!J-)QoVyKx9c zrD&y)-a&tb$&dur+2<8th#m9pr>V!+?C=Ko6baZh9II@D;p#{4CAOi#5Kf@`&k?}1z4uR!9 zTx_fSt^zFgigNo9vF%2EiqCQ{H?($G?S>lJVuvUYHE?{3djs(XH=L`2hALhazpVJU zqUvhZ@v5`2HMKBh+NN(2x}y+z+fVuy`%fu$^;ECd&}a_=N&)*S$oQ6)LlySGhO-Tg z>E7!&rRoV&syaHAf@JA1XZ37{d3}{9_9OAfhAWlr73DT##kq3B32NMZSxc=%wuzbE zaQ0Xu&=Xp~c6OIWq3s-|uYoG~l&d;iMVUm?`8zP3L%?*d0YfqcvpLs>R`a3pjrzla z=3UOKsybA4QM_84-ckn>O^jhv89AKfl2Vm-i#*4DQQDPa*X)`i%=@`1?u1TL+(>UI zo#IA#b-Pl8KD!PGVF48c)CJ97%q@V&>`)#G#~vcJ)TIcQd9P=D&1_)=v|N@$#64z+ zdOAbY>?<#yDa(i6EyTMCV!FPH*HxWu@LYSdq2b!@&4=i<9;#cLzk(mNq3hB)vV*@X=cJLpM&Qi@4B#Lp)M( zD7vC8p-f$IC~#94=-0*cI?Y)1HSx32M-Riqq<-_EYp)OLxN&L0bNDSY^s)9(N0~+v z^vab>J6^4)`+Hh>i8)f7tBVxZXcHUks>C`$9VvB_&+#9g7`aJvxL6x0rQu3nM#tM} z@{Zo;^irpT94LNJ-ijC0p2?h)qwHp?>hM|i3CfRyU;D6QH}H;!aPr0>KJW1j@o}j3 zG!jRdQB|t;e1upH{_F}?|9DlpJvIOjVD2P@5Quf=H zz7=U@g;BYtOXJ4Wn7cj*T5*|hFVc%| z&tH8GzOQ>T8E=fw!x>koN>FX<4U*NkCtmmGY2=O0(XV!muDP;KWqqrm9n5Ji{R)?U z)jz(gc?xRnC+;)fL#)41c3P@{jn;a;4cWTweY`XMmag=7UGry$>%vZ3*XZ`|ZEwrW zv~cNdotPP#!kC%&y=||fES$4PaAih39B%|EciS6564H(913>T~=Oa$uxc_=QbmNr= zug5#n+r5^`_J9OyK%FMqJG)a|zR}|3FIS~st~eOI$>^V<$X|Ao7Waf7(9rbd{^eEw z0`d4B_EB4PdPUNMrGqNlug62D!-sRcaYmi?dVGx602xAHf^fc_sq_>v!&tZRdOX>D z3M!l}XNSqZOCH^EU!3k2-fO3;j&~E^ZdZU;+s?ZoR!q$%-s9wt;i+`~xRXDziT}>Y zH*MlC?r>VpI{7ooeV221Z0>@x&vi6T-sggT^$?MAwD=rPglm7CvY=ib04*x0Mi_vP zL-_~f$^mLm6{+Ws;oe*${&yVzJJDS3*`>h~D-o_Ez9i#W68!B9jiz%N6HVidVYzf9 zA##%84!k9QS2nHXY|Cu~bon6~&x7)%Z#={~n3MPB0+SYlw+Dy&aP7F2EAPEssp7xG zH^Du-NgeOu#EdI!>rKbD-sIDFSJ+YV$~LJR_Cf8op&&3cOU||7c;IaE4F~M^-{>iQ zzOw8B#Md~=&b8a(M9W!`Khr6h$Y1G_4yy>G_HH%o&U}=NNUJ!f`1id9$aU1Pi@25@A#cM$XIW7)Ev84sULM%Q;Hq)k;tDDEf?Ht4?6jCPRj+k@GV^m-z;V{v)xkMzP`KY<0QGz8l})V zf+lIYeO(=Y)o*XNbKAkqP!vZ@i+4n2JJGH0?`)j)yPFD{ zkAKQ~zKM_+iFV|z#c`W6+PumBDcBEMcj}S9``(|x$l@k3y(#hN`i~mg9ek^92L4b@ z*&^?y&Qxx9rLwaVm4>rHO+iP3j^W{6+(YJyo4gva{l+&)`}4BDBJJBc+-8L~1E0;O zK8TD{)8F9ExQ#iMH2UY~YA$DebK-Y)-8z}3yuUq!R)$eIsexxCy6$*al(`9BeK{d! z92e6YMawZD9w*n^IoYajpB&NFcp7rIs4R@>*lgy?B6RYabN zD}U)^)S0-izNM&_TC@O5ryf!`Q zxV7h`6KlZoH$kZG+?V3PL12oy$N9b+NI`gj=BNLzJC91D%k=gd3-) z?tT}%&0=eCDEW6cUEMF8^X^xcoVIsi-io zK*+I@C52WYXZcFgG}HK~XlslqKW~{e%er=qX>$elviLX%Cgx^F;RL#3JMv%Gx{E}V=;F6U9k~8EvsO-U|J42 z2|1=hyHI2oOu2daIi_JYUua~a(Pn`BzBvT%*5z`lAJ)PG^F zY5Cga`A~o&@Z}ZQ1gm|ykXKlMIp^ouguH?kWNcbeLDuS=WJsHqlMBT)=+j9uZ&az;);juqKvtc}gjDbC4<*vsrIAfwzu>*_4b zl#E@O1dJt9E{k%O=jE<7t<0gi42%|Kt$;!mT08j4^JOq=MM0r8$Fw}lmV=xZ7A-H# z&asiPvyzIkgq6vD^zsUp=i9So>0qD<%1o){-_0(QeMg4*K0(Z3C`Ja6WbEqB5?-CP z+zRzrQj}F-gR`NxJTWrUA?R@-y|SAWUSp60gGx{owK^oy4Ga3VI{22 zDk5WxeGx1<)@6ktct&|m(we;NPE{zgVgkIda*Qcve2k(wObMy(kg@B01o^!De3QMv zZp+D5GG3DhHMK6sT4*EFRQ-(Q0Pg{K0D7zY8500<05$>q9-sl>DnMUNKVuTWd;lB3 z^8jxF{1f1R(&9ThSLjnGjE#+sesGM5w`LWrGNneD9)eQZ))W?Ild=CF`6H&sVxlHQ zKORMte{uX>&YXi3zNWYdTf~OajKPiqMuttHF%Pq1kt`Hk(g0s@^cDS zKn%S)n+{w>WiMONxjH9y)E^9@1vYy=YHbu*xH1nK zug#R@7yk487|otU<=X@@maM_Hm8gpMp9tUCs2#aNj6C%E67Tc zM`n?HvYHf-LQ+JYf>A;sc2W!smymVjr21R+5Abd=kI&I({pdno?&-?HiRwimD8)Z z*X3Tn>Ge@~Q}}n`E#YCkV|&l*UDW&8-f#Eb-}`9quX|tat?BbXpNIOa>T{vb%|6}x zKF~M0uXPzAST%`c0hvU86Y-mf&_PkAEdv)uER3id^4XB%Lmqix>jRBL4MP_W+c0$1 zaNF=-40jBFX?XSUH;4aqI8p&cp+Ts*TH#z41^!P!9WkpecZXR~piR^h)H4M+})jkZB(5*-hd^;pnR zM8OUn79F2oVj30`ou5tP`_K~rP0OzY>B#~%KrN&Ll)j6^qxLD#^~Eh*8_Kia3+qlQJt+8+;wwi&GN2Q>s*D*q9!bgw_6 z4=|{W!J3e6q1}7*RE2TAzh2?J`}9=>s_y&O-rn9%)&4W#{o4n$|G)j07#2RcZ@>Nn z21X1r4W2S=>d5H{WO7f^BeDFcL{3BgqIdl8hpw$ru}4c7n`FZHv-ad;;(pz~=xB0AB!{ z0B8a@1#lYR48U1{a{w0rE&{j#E&+TG&(-{p^)L`^X36@9?Q7AIYEN z2{z?y@(`Ir9wzBzE-{mNWIotY3qdC>WD!|R9=#8Z`JMpulCDeFq^r`8QnU1fbVd4Jx-5C6OOi)Ykyh!3^pn&A@Duock^;yrX%ytx7siK3 zm=WBeAwNlKavi96;ByH+KS}Yx%|sZBd&9uolg1rNhQmNTg67|!3<8b^${!8TMLNva zkNER~+_2AO%9WSWzeKre1sDT8-B=O@ecfo%Cf%e|7)JqwebDuj6iseJsD{$Vc^~F9 z0djtju=xD|M?fYa;2#a+UOd$Z9yH<+m_Zi8=NC}Bo1i8|vIRab{*OO6O0v)2?(?Z3 zACoW0SL7UVlPlyJX(e}viqmp>E*M6_9$Xj~&JE>axD@VT7z^ieOW~8p6?2aN(PtZc ze#`ytKlr=_BW>qTFz7=+sMP@=y$GmV6WC=#WV38IwaM-miniMQ!p7V;B2s~}x$@=j)$(@%{lAd@Uj*@Guj~BH^lz4T2y@Bko91# zmfttD^1dNY-#5f@-;hoB4XL_s$Y$tEcHB4g#ruXRGeQlx0s#!r0`E0rTnJcZBXQ6+ z#zTKM5!yf^=xz%1a5G_yn+rCS3fkcquv??3-KvB9Bnih0)~bz^atK{dL#t95{r
tGmlBq>Zz^$7I7anMdDLF>Zyk_s&aEj}EDaSUc7?`Y`VgP`mkREC2Lm@61YHA!Of zkff0$l8!AHG6?=><01O=@)}Dh9f^AVPZsEZ=1=v1)JF}PF%~|!c*Nm9jTV6ZuT^O^ z8V$j9DYZ(CF*G!a8WGIl``|yd{EbeI(!-c^4F37g-8`w~85im<&bqpObaWnuHW6Ay z25K1@!7f6}2yG*@j?g~pPVFh>)02L}=%<(b3HN<^`#y%AKdkukxJRSjA6F3l+ddD3 z59}4x3tI~6od0^XqQRZlsFgpZY*-ehWh)H@SW?#V?*`@n4p(Qal3q()Og0ko z#NmP&<&pC(oe>G$fP;!w6FD6I)EX&N>Mmih3O%^WCI#swgHZ|&=_V%D0lNf^3pyg>PFvKq1L0v5{rVtN`%6d^rGo=R8H0O8WnAcrg~$|uXL zSpciZG8=>!L%d=eS)RWfAR8bLzzR@IaK#D!1Hiq*@2*kE(8NeE1gLF0!olSsn0m31jyf$VNAgQnx zU>y;FjF7dK2zdg?O|UK_f(-$%C0PJABCO3KC0SX7?d-SE)%AxxVv*C;Pwhap7Xgm@&dSZ z98qU1-$q{ax!)zP_}tCpHJN7m6DIP84SZW-Ta`B`$==dK~mzBnBD3EV-ze@7&vgQFo!UrpK2p!3lDCi?4Iq%L%N@P zKGK1_4nz|2$Y7<6=g6a&7HEECA|z|DB9rqZ$H%jqExXJYO>bH|4y=Ac1L8rMk;0ZJ5Rhy{!1>)J3}~9)V*}Y?gB>ffT3~84PyF}g}thA{&$p^kTgdFhk$&p&Q9)m$X z^>Q7(Geku`Wo1{Z7R)5ad~O{%F1vfKIz^g%?j__jb8A!!R+6(m_Xu)9cK2M>M%+I4 zI&yii(ykvM&EO6N9xmq*a@|+Coo^Llk}Eh)KqeS*0OEnOi+(m6419cQ@!~F6VJ%j7)!a zRwaq{qd&oqe!L(3Byej%w)IhjOq0{Tl=U>3A-g}#svr*y>F5XM`qJ(u3w-WfWYG|& zx9<#5lgC+nE&=+etRYMf6F@vUzWDn{p3hxHR{Pv9lBay`?Zobrn@H^xMGj_b;RM?HenxSv+B-wa~s|CG$n;7ZwUx z`6e9uOvCcCO}JBpCqB{(O*opHR>%j7@RULn5G5qa7Lx$~uY|Fj92(Kjcm&|+2zC;u ztDkW}Y-6oC%L}d9I6ezG`D1C?>k#J_K)}d;#<8{-(^wllHnhl^hsT(d6!bV-PF6Oa z9aGAL=Q76HVwHnNEQOCU+a|wHGBN;iOCQO&TSG7@?xGK~b!@IfK_?B1j$I7mSsWcr z7Q`qXf)4tho-BAUdOYHoZ&GwLjU6KgCin+VTbZ+b6=vechiO@%y&yZwng_DRZR`8+ z0e`6r;vOW#lxnl(tOf(gN>886k9#mWmSjOlmTfg244gNrpYaiZM@O-ejV*~$r1OX^ z$Ar=S_AUKR2-+ZOtZ8hCU(^NDAachk6_O7$e^ z7pyG+tB0i`vkHpA!p%0Z^EzaDNm0&nDnqs_3sPd|2g$7b{G1h#+47ZH)~w}t>UM#U zwS1MSusFw>n_oyz_OLWr`QQbMOd-9xAZK-9LEdsQhX${<+XOs{g!`&F1p-9#JA_z} z!;Z)0=dI2Y@F3~(l|adNXowxPC@2(wU#JL@mRFpI;>AOpt;lYh(O)8vJg59Fy#xDuO#zxXo@^~ED4$hOJ`n* zCoZX2p?t!coE&ywHOJ-?MWHos1>_ICkC3w(3qKvqXB09u)+u|1cEJP|`CKY>)9S3X zlyQ(3Jpq_ylQW}dyl`&NLCmHc@}e;z8(}4|4jq;)X9dk{R!0tOaxfR_ZjIb#pgM~4 z3hlQ1wI=_whG^u|Z-~66J%$V-!6eoiYh7*KWc`D+#`>YvcQ^}AAay>SHO$6%r>BtaKDgBp4E@e> zlX4OXJNOb36~(?yGM<ua%|lH?D*;b%D-Se>)htbom;SeXs|xL z5ZetM^qJ06>{J*XZ8S0+{EMJ>T%7~$g9fI}U0{ldDk-6D*k&&(!ix&oH0WXIf}!ge zA8X38uCOUx63YnhHssn1*x_^ek^_VgosYqQb(|l&xB%tvS8-e?zm`*V@>g)`F7Y*; z{QqbCm90};sl*bCN{Fp1SU)o-s|Za(=yk02B355V%l#5U)PgJ+(&0Y>rdTeZG-~yT z0(*Y`NJ64X^kNbXmf2V`nwZD~fEWca25d;$Fm=Ps4e1*eZWyuEMt3^0Ngmy$vy&pS zn3RxQ!V~C2$qcfB6p);a2R44V@gjVpH$AwC-;}wjXp^vMuXC^S%c?J{u8G&gFE+D0 zh)gFND3wrJHlU7_a)Hte@)%GX2C~r z@2;N0G&8jG-!r~H8Bt09xO@Du@TckDy^aK8sOkSv?YY-qAV_~P)WlSxc~$eO0Y1|T z-^w1LJ)-~ZZ#I9f+xOV8$$z+>cBk9#W5@qt*FPR;nU(N&XVY)~()e=Hq|MRiwyvF? zJa*au@42{sQ+^Tl_Ka`WJu~IS9r(9*3ZvgVCFy{z{Oh^B?6Cu*Z_Zrv^pc-$PVuPc z#y{Mot)rrH#i{!#gRsQle5Yjr3<1-L8VdrD8G zG#xJ7FL)Y4IZ{co{#FE^jelG9-v72`GjZg9SKjiJhQ)di+On{P{jl$ceTg3=en7~n zGGk5p)aYpY09G>rJy=@Z+@+}tqUKJWO-Oi;Z%hoSpSyJW!?PALbW5x;$cN@<&6&>7 zs-(~4zCCE}(ub!%%&^BM9}o0JUO0cc9QpO>f0QE|=Pq5aFm39rbQX|4RVWQxm^yXN^tcC=z+9QJ z5MXyMaONxE$|aFK{Apr{l5A`K%})8zYl5=8HWilX{PUaV&y2PtUd2YwfaOuC3mzsU zc^y_4VsyF7^9yY`QOj|#m~=PNweGKXBlCap%-zW5U(C208DF|o9=HQ@@y;CLo?kzc zbj6)sUv?L6N!er>r)Q^IZLx^nUY4$)SAZ2#P|S*SvFtk;9h48#yp;@lv^-iZW6}JO zi{JiqZ#k|(rp)l+j)Z&S&5qQ2;-7Ow-V^U~jJPNMtm8R_$K}{Y7}omC5~V=PSE7Z* z(4Rh2q?hGc1T=(PEPT?l;X$&TY%mp~xcS>>s1@1e+ifcm_u@-Lk>_$@ZBY)x?Nf5k zEwT%;EEc{j$;uJ_R)tKN&Aa{%X3X+}wYia!>q-JxhJGmswXaghS*A5e6C_Hen=l#FRNNvvYVp{T*`+Rbv7H?;qzHrsDycNsrxeWb!z+DA1)(DD> zGvlMJ?;Ak>SiG-%Y zJby0Cu379wc(1RRdV(^imk6_P`dK3TAthcBv8|Ico|BU+%+1ZU zd-5dR3_Z?fjtLMZ`$%XT=a&Q#&&%O*=G&<^G;>w@bY9xtC9sdciQ~vsSBrv zvJotE9yU&lyOkmWXt{n%Lv@+yIcrerJG!GcFmqZCPN$ZpFb1Zs6>_L<9MdtLr!H8a zEOj*MSm~z~X6Gol<8riVcB^#(TUR+DM@!2RvXp2|Iz>SWP+ykiSWoF#iIf=A*fPrT zL{`xcXIWR}SWoL%9imj(P0m?4@A)|^6e{QBylG{mvgMBpI;Dbe-D9fV zwsvuf5(_a*VPYSDcW)foxHJ?`ghy;ef($h)vZAwLx znYO?jPKWEDOlShji`HfqRQUO`gvUnU@(K%RS8y>{%s%hX)_-|&*Obr(EJ?1ZY{{^%XmQrz{22;Bx=jF zm04D3Eh`7GoNA*$-pS@Msibj7&RN9o9#&76S!fh~RN76;foFKg*Z}LSYfZyg!a5 z0tI7;f@p>?XUPcMzoTh#gokrhF92@dh+*|<#^L!9xev-n>1Y;H>9x;XSq;;3a z#z^lZ$fW^4l^gEL(g=k`)Sr~dyzvk-Z52<=usoy8hm*7D`h zd;T<&`Je`&y9=A8_*NGd`+W9-{JeryF4>o7%MygOkIrH;#sz7#Q;TLWe|DiQ6SI7O zCX)jCDc|WcSRv7(|E=uCh#L&@I9-@uSg^;)dhS%)^1Qr-g|t)7O+{QtChH>Q{_2=) zk#tnLYbsL}9$MCr1m7?rKs#K%64X^I5BIdXAv62x0$y%8`B~7p7p}@F*b~g+q}ptG zD+(y;y@(v$Hx; zTaZ(nQ?R@XZe?Ds@KWcL3xtwSyJFUU-xag2&+<-`7OsSzC1H7|SPRz_W-Mo-nMya@ z@Kg%Qc^XVp+hq4_`|6?}R>+!{BVcvhUcs6eNQ9-s(-(A%&trCY&sB^nN_D}sF{@Z= z^vx?QN?XMko3(m%PIex&6Tn?u)k%neiEqCPH8DKDgZ~n@ z*k)UimgI*>D=f&_n$Osg&G*zoSpzV^RvL^tbQ9Gj4n zJuBB1H;%Oj`tU_x9 zx%;sjFAQ)Zz%UsKemQ4q^v)P{MfI$BO5;M^04zU)I}Ez88=VV8o)DapyiMTq2e ztiE$`4A950jwLg%aM=L4%S3l9+p|DHu|))E5VK>M7Ia{WT9eUzRWpZ@ze11I(fxg{#dc9l(7;tS% z%2+gLcG>o#?Xr(8N||GsQbAW=yv&|E$In|NSof8)xS4aNJ#0?d;Pa);vZP!rQ+y9U zGAG4UF4y!UH1LcZbva$lnp44itEq2nC5vj!pBIm_RlD%Tx&b743tkCjy;%erEDsqD$IS_=v*{X&X=aIkuz z)ptS8E|V^@u|(hlJ+WHL6sZ*2aQ}Q=tdgB=b=H%G*0T=QowB5vxig-T{n>@tVDZ_0 z;TJ!zpwP;Q>oMF$xncwZD56AhLwkPv8OGr9m5{CV8Mzkea^I)VFwy0*Wj?Q*WwGoJ z`Y#rl`6B*{MJ{GutL(Kg@0S0P)5`uv*`Ha&4!>kQD=Ri#Jlygu8xjUIc=Y#wGoh;2V8=V16cum$Dey(|X`u1uT5&GlY0k6}H zv#od}NAp+e$)%o*Kgwy+Qq$5>Rz9e7R5_W;?N)5 z_?!}dRyy@p`K1R`O1l#Ok@N)^UgQ@JsFYolpKjTpbBsY4`tq!sDbwAslPp>eQv@3n zBs2RW6_uV<+VsWKQYOADBOZ~t|DA$B>d5|BmZXFHMM_zp>qGp5)>=R|*7Z~>z<^wI zKmUf@@@TzaZW#}f=qcoiW>aCi8iuVp?R`fxrsVh__|Tpxc% zcH^@6nLR8KTMdu@o80Pfg4y_<>=APE^Pha5kweCd3T-baUK{o9d7n|l?awn-QpR*Npxp8KnQ6k4jm&8vr*2v|@(*{D4fnET~lH&!?CE-(m(~=Uv^~I~fYF4LBXa&Y>URbmR`;Y5*5R4gzif;DX41hY&I!aC(SMfJYU$x^*L@ zC*TaE4RHMdXCOlWw*qiR(u-qhjl|iFl`WXW$hctgMR&$?2zi)e^g>AY9)$b}aNWq0 zfa?LcZe%~;;_yfUDdm`~Ldo@>(4RoO?&Oy;t~=qv@QE>w>p|X-aXm;1;6eb`lYAiK zdXjV*7e7x}FmFPz+zapC06Fnsic<9d@|6~px=?}ss7 z`jEjYCi_0*u$;CpiI;JGNn;q3eLpf+#bn=)v;!^yaQ#V+jO$M(_9A3G;0BOi0Im<< z29Q0y7`=hyS2AuOIV9sE$eS`Qf*b=}H^2=dwK8rH`9_XsB45ck6Zu}o4JOy*dLr9RC@jQeyhhwdB+ylg}J_T?Kb1MMQVzm%zw^#o_FS*5xafge*1s_|BW8r z_qm_vJm)#jInV8#b8DRtA_#&G!0Q!+?E?E5g&+S}0s0Qz*;ja>_nX7EYi7SWY{Bvp zlcA!rd|74wN<%?@Sy{Q+u(ZffX(=<5lo_VY%`vPjFDx1p85thW^T^H=gxQ)!NtZF-uJ*a>QV{njUepVtyqoKcWrLNC<=HR~MK2Q|tSGzyEjs za-}a9<|LhwGxbS_WkD8FAB09-Jtfr%kIMPGkwNCqUm>i}yPkhY5Nvy+Y#kc&osLFx zr0qn+3ca_@_PQ5*okbnep+&dn?a>LTk3drMfz_F*597NH;^q(Z-F^t_jyy+Q*xjA0QSXDp#mu19h`3wXktd!5(o zg*d{BKCW2xn$TYi0+MF58)TT8_*9+$iK^L;N&hxeorgc0yM5?E}&v zr2#5)lN|H=q%>jc5{TzGC_1VkrLFUb`SR>+ij^&=CuX}W4-(QWuC24td|6J89Esuc zL;FDeZ6~5vXuL6X;OqKVH~2PSZJjS)&G`kxwLJXI zi^Ao|mmxsN+b*8l9GMa|9^uJYkCQp)R)^YoJCJl0Wyx;h%AJ(lr1 zM?P;9u8qn5yHRMJ7Oy*c5{R}SUSB^5NF(XuU1K4p3`s5L_bd6;V`L~P0uy`*2}ZR! zXI!wkw9+2w^`_%Pn><4`ZIrL(!?!!6_uoD@s%6vx$s8YrIm?lhbws@D-3L@zGXlNJ z@x6H=a9FGyV*pP;u)qHYpcQJ3NuvSG*6B45sh0}x*1UKbe&kc3loI5Xd=8?mJaw7a<+BdDsIe#FzM4) zUHmQJzsm?Uaor5aj%umH_L4(v%{phDx4XOhY}>Fs(%Usht?)B{E$x%m#Sa3iM1KoZ zX>vu?9J5*lq-zA`Ax_)p%+P{MkJ(BGkbLbY(f^Qez;-xf)Thpk6CfTmWRx67RD!1Z z>qfvcZb=+-wQb}Lck^y)xQPJ`X9n`7Qo@vYmjx5DTHmUh5z-k@t)!O#P zF1mg3{$?o>>7}@SpmCvTdAnk(j%tziHMxdjvuc{4i4RcY`p`ZL{OhrD61oNhE~A=( zI?<4A6jH}&I-^hmOA0wf=tnSwrRaE917zS1fgT6>>L8zRz})p92 zs9ALJLm;N>Ss-3LmbtrrU>cC2C3Fis6FmBKS;uPIXpXf`O0aw@?w$eS=yq@Nhvv^~ z`(}AQW$n=tW@yRMTq~WWT%4=4Ne2TG5429YR!N-YO>R;W->hv36OvDgc2r^!J1ke# zbn%Ft2-wN%T@J742+>lDp`>uRKv!Mo6RGvscFv{F~i40S%xUkpqpWaMhJ1Oj>1w2QPG~=8%RD4dv4x|-p!VNa_S^- zIJ}l#z`$55*>YlM>p#6-$oy?FGZLfL8&NKv5i@g7fZUeIPs;tm^;QPrAUdM@5_Jgs zySQIUsNZkZeIS1y!&mEC?-;Yb#ftA^GU`7D-c34#5?6re63`#}ck6xrq}TH7zK7nJ zCF@?q6plvAyVzD30ph)jGPHoDK`wPo$Ku#{A~vLJoVRN1P{N;pc;fCxo9hN!#}x72 zzd)!r-tqEjqtMdpk}ME$pTYw63m1s^X{QinmrdfF>lu`Vctgl6OmG)Ypf`+atvu*z0p^#*u3Gc<~H0`5ZjhJ5b&s1Hv|B!5|z=+}_Q7CH^uDilJDs*v>% z;*(Ox^-#+k4dtOoD=w)JKi7UJz+K=aoJOiLnFN`5Ls9e))}t8K21sVzYNQwg!Anl{ zG2#u-hSx!1awIjP1{yJ&H{v`!apDYx6UX!rXM+xt&QN$!Cpp)pw@In!p%gLz$}sO$ z^Wx}xAh#y#S`AcmI27W|JVDs5?P6V+Dhu&foH8nvb{&G2c2Dc{dh3~R6YWF0kX|JF zx8q-r&S;$^SUP8rUuCFu(pbwWITgEw^A-){^W0@=B=K$EhJqrbcTEgOiOO9EZhe-=Rw8dd3cY4AX#^86i(Zc6#+Lh_SPp z5vb-A4Ls92p;|guHNovz!H#Y*b6 zY6BtQ=japSA7S=SVk6A%b6&6O<5MUvQ=-@?-WuBId$YzdR%9jv^E1ZrHyzEVxt{C? zf09?jpLcKYDaaEszT=?zY9ASs-!WefoW<4Cy{MK)$Af0Bcg5Mz(wI#Hvgr70FQh%y z4?KlpZ2=i9DZC3|wLjMQt9|f#ray>| zf-nJTjD)hS|3VO-B2pz2`(uO1mM>aE_xT9X=6l=gdwYYw+0J>TiPNZDg>qu%hpnN9 z1}HJ#^}WsJ5u~`6DS@BBGyFuqB&o-PPUCvZg5-+kf{`}5EfcC`ZqZJnCke?dxq$Q80`w5>AVqQ(*K_BViKAOzwB zr|Y8{u1~p}&p;RUH_NB2A+d2V7ql0lYl@klq6LIam008BkxJc7prKcS5%nCB{qmL& zFdaQlF!3{sxY%}XfcPY+)g6vb(LTO|gdc`RbMZL%EU71tp;GV_ScdKaI4sA^V7-o* z45jOo8loYxi)$>ryZ^-0nk|^_ubA!&kfL0B+=iaLYn0yPZXy928^wkK97*1o1}W;8 zexhq+eHP`1YkUo|*H)~ZXwTF!OBE-BNeXg1iJBi;Bg;x%(EdA+do(*hk+nTX9?T(g!(*%Xio%}r{tVb%3=B%ZRuWw)pCEqiJ z1*cRv_YXN881MHOuNLBwGC3=CAI7`qJHe-b?&ArMoeE5N2PTX@6X>}RJ@=j^&j5vr z%mvi5pFV>qff5c?a4lQU^1kQPr3d}bfvE29Ar&ZmDm4qajD|WBhCc$~+~#qAaTZIs zMEQ`i97~Q%VI@bLLakDCw*dvv+Ic{G+DEb!UUSz;@|w+cAa~+v>Q7ae&mY!-j#hMf zJLXMOH!Tq11hfS{XI-Et%~!eGF9gn)%!0bRk91O2G_4X|3LZ;PaB$Hn+802{@VjX zsfZ>+^4n~TT+YYHmmoXWNe|2JCDx0m2Yj=ZiI$fH)RS=3s7FqJ6^9NU2gEca5;MC= z&q|%+ACcZ(i-}b7mPQn`$Y@A$HLX>K9O)3mc$N(}NINmJ1v1sUo?7ciU$kRCQdL2; z--jN)G3D8d#uWD-&nZ;)&B|3p@OemgZqUTm?~tZO@T^n+7Uswc;-h7pExRo~3i11{ zx*r*(=E1d^8#B_tYs0rK8bNAbbbE7g9lYI0erFUvZg}(g=$j$Kb@5SJlQckmO9d#j_8~ziBboo-PEG#lab~DQuT(1)S`)m$K5TO@QgHf70@4=2j0r)Z3w&- z(wiRMZl$+g@Rm(BdL{H}t+TpKRp4e@ckd04Id!k5J5#a(ak(3U#0S>kx&jM!uY~uR zvu;ewaHD9Z`qj4$25teiz;ytlt)pNodTbDDqhB*zj#KHc#lxc+84gz>-6_j~)PeKq zwi9~FMSLj+bv}P416p*HiAIX1T#_31Hv{)!KCaWt1Ytk45u1-sI!rV2gv*5YFs?J* zOPNR~rSGVr%rS&7wBBrW>)EMVe3XG|~ zsH5`PXx6^|cJBr4{>WLQ(&SHwyQgBhosf>|=c}0bKs4m(t6U1NoRV*AW;>PKFj?Gv zufi{*kYD1{rOb9}r0wMI^_u(HyyAukIkO!(M$J*uahKQjZKAaPL?9C5ZQkA+#>kl`(w#c1 zQ#W1842sYnBSZ#8$UFgPnz|L1x`WM4QtJ*Z7Jwjxk+}N`araG{rqA`xls@jifKQSa ztQmVfytxZ0!a$55?yiOsvqGAV=`{zMzScJ#i_&yDQ?%}?Zc<#->tBQ9NaBsW(~_k_ zT7O>7)mu~E#MTILrg_ad@JEh)6I;caLX8w+zQNYn&v|FJ%o=OeC})<&$EWERHKm+) zTDEk^>(B3R_Qr3jI)`n@BggQ_A+0)!j6cttO2y-f!1XFv8Jn8W=4=)lx`zGJ^HA^4 zJR6ff^V~P=GtWKApV91ihZ}n)I5v@^lsTRt$71GqiX8KqgH(TaCUa~i$0U^KAHMUo zdn|kLy03y4&1deR@EG-(dk_kZzje8z;0YGdRZ_=q&UQ(y)cL_Zkhwpg3Blfoh`SO( zw&Um^O~lF)a|OzCRevX{bMlV1b?TfmKv!Yp9p;>;v2_+m)T1{HY0^I`#KqR3H80vQY=(K#^yCk!-Syka1jPiXv?^V>xX#uQ zV);ZF;fH46_>7UJd-luG7f4V&4?4e4)4c&if_QJ8h7?B6yRwc#lg>bomi9M+P~J_)R0)MI4$sw3MOcF*%Ns#>TsDzEcop>_jvzcZ<7+uwq|D1vvSi z8-|Jv(ZsUi?mfu06&uoLmZ5+HC2g+zfM|amIkF2es1qM}7kdfg#_6>- z#4f|L2if{%!owYj(%_)zz~xZD--<1Ck)9b#fv--`D1{rcyt-rwOJ1!?bRIK~#6=-?1l2uk*fi z&-WOo9OJN_W;<@J>107D;3$oIu73jrlLs+4)wCTaMZg5OvL2_K9F3Mi&gl6``q-X^{zXSiW~i^|Ka%@*KY&x?Z@#ohtJrGZ-gBb zc8K0RCyVRU;~y>2Dh44~C-Er45OL%jU{1!Bax_tYaHFj;0<8>M1Bhvd5ZAW}Aatds zomlbh{jdj|16yQIkUU+u8+V#PkBO2q^{5DL?=sRvOm;a=#BN7B)N$A{%#(%n0pZav zP3nW&DMm@{H#r)shodIq^C5EmotS(NM6`T>&UA2+7`E+=T6DXz zYlG>BH78!iIy#m>yCX8Kj$6F!*Xme+e%xk!1eyboMCATa2Dv*>mzH0_zYI;UXnz5x zQ8%HNb2Dzb!F0rUvGKUe!1d=cW&=KivxyUNrrS$pIL=s#w-0rA=E+WUo_!YoHk}(P zebD3$9re#UJ}XS#j9y@OP9(eZjQP5z&X7?DoU!wr5g#Q}D$AAfD+_p`TL4+K-uR}Y zJw~Kc>`Ih1&gCQ^n`)goUS`1CXQIyoS}jVDaM3=Q{3q9mj?Xldq5{JkHkVVv8kCjd z?uYTQ1IZ+{^nSl8tm&A}8KK3A;Cr>0$gzSFy;uT|U2GZ9%2Gax52>~H2P{#n77&p( z--d;DUN7Ez2bJl#gOWQ-DPrF$mz>J1y^bYXNr_%5Qzs%d8F3VAaZe%GOR91OYBD)4QCGx8~5%vF#ao9!n&;IG)^Z*w0-7H{?HU|UF#hy+UII$ zhQj&^h6p=w4oi+>R_!M=a8TZ6^Cjj#HY}=hzKAh!ZUctfvBRY81m)Pv?__BXeLjLmRwLoI+Wgqg#Y^+$7mh67N+8~tJ} z?#0;VB+?@XJ6ExIetBh6r&loj-}!~*qxyYf#W%hU;d(FGz3r?N8Q7e`7iWG(?ngS=Atsu4#qP7Dfr7& z^ea~A>)2r+Kc(Q)6I2ENquW<7ak8o`-9=^9QdyRPyqxFz&Z_C^z5$KPGAv`BQa4t* zYY`|`?m3vNI{pUKl0QWSI=MSQ0oSHp@M2glhQ+DFW~6pg2wH9KkZw+&Tv`IaP3oxs z#UUHW7CrRB5~dsP;OM`{`Cw-EK64>gcbzwSC93KUUdG@1hT?gNR4*6?tM2t2 z$R&h0lM{w2Qs`bM5UE_>3k_plD zxmJ=fhAUS4wP@mi`4pAr&qRvE zjRlq$seF9hiou?pqs(age2rP++t1ngqqIs zDes=1&!{{u#XMtqdL^EDiX6>Ug8PsuYR(~7tR4&FV20}!U%u6C7fnoIgDXY6OV*|5 zxJtg)<6a7!Y{S>ddE&509aS4~iCC`Y2onnHsTN6kt3w81q# z&A$b9B4n28!m|xc<~(2p^DVY>q2eQKtIZ?0f5bixO_f(L=iVTb(dgQY4lfmkHMkO_ zSKeaW^|^UF&vzGPe&{M+=9aCl8?&j{TIfx#?j^Km#gRff=}uf<6zy)>o&N?7_pgk^ zfR1DbK1Ih+2yq>cWZGkYj7BM)Ptt;HX!c7+p$-IED~$|T>rgBuxtY!5SyM3(3fO~~ z;k)!APPuwU25uJ917oK;bAWjL_HKYZ$yZORR{g0R7`KZVYp~7#G&_Q9}Yunui!YK zqUpd1JC|lI#o=G~06X<&!Z<}vRI_$QCjYG{HkmBOV(B{Z#FQ#x@FWj!Gf}K?XQ2Xk3e-${= zW?Hj>(^y##wI= z%n9-<#G(zoybgS+4a?#Yh;>bovXg~tz}Wa$CV7%fxvo!c3A?Q&OLIe#m!+_^XsuHW zmf_A>8YvPzq}QD@HPfwYyatjaHgAadB$`G?SqG(k76}&^F<)i!PVEFzh%oV>{tG(NJIqpZD70<8ZB(Q=eJ6H2_sfuk@rmes7i#0oNrGmnU8wQ3 ziHg{bT?)zE@8atw>Q=zQPyY(A$%t@&+STLw&>%XMB>10K_Q7N^j0hsce`90gBy~Q z+g9hwxq8s@3c!|u$UCtywzqcCcBCj81%S$LqU77pPLYYz_CV)|s6R58P@oMO)lhHO zj{ROQE@6?pYPlQJhPT}PAdVGOgk^KRuY?`Egb1aC<5)stJuBb2N;;7gRaB+AS(nM_7G4ns)M zbL@vv1L+)xRjn>jXxMa1Fb!Ar4XiHJ6L+0cUD^4p9X-;t5i1*udt4)2$&jzhybsyl zwl{iF;Q73yMn4NQv-6N>dKiEJwyqHAL(%@Gpe({UE4}qt3)_ApX6)PKK2f!gU@J8r zPD_Ar_YUMH?oP@B>7XGxfLUIlRQtfqKUQry2J6kZgjh%>%I)6OQ_T+o?}*b{Xm397 zfolq6?^@N$YHuL>CQj9;Ts!>2nFCe|DTpA69>6UC&-G;%pJyLdCH@vZW$)P$d_I)X ziwu0xem@F|jeRuS$bSth9!I_9aCNa#9n7 z3&pY%H?BpAMly(YPT+8G2A;${+ki@La2P%Hv>tpOa4{g(!uWSu%j70ulQ(V?>5NcK;mJE7L+{i)aCkCE7$9xx%B73c&ptD+T8fpe0#n8=T7Y!-wDj5 zGp;CzlH4si|4OKM`Xc=^Y+W~q4?Ktr6MY4W^0j@*ST%oz2RyMM6VEGM89FSCk@qct zxVkG)OwDC+*<2AX{6^hOX!aYSa4bgFwg^>Tt@M%Ym}u)1Mf*DN#4@X2zUa80;-_wAeCFnWQ8+dqh0eHHeYKD<=Vo=CrjE++` zYR?f1=(IRhq@-E32k+Fy;~SfLi9zMrse8y7fqhumJ_P&7j_0lb6-RX7B%WOJ!WGy> z(a@KFQwQ(K?c(fql)B{S`Ys0>jb|fIc2?Va$<@+GmnDX(t_k~$Y^ymY34=F*^w z-kN8yat~t3z|$?$HOi<=>y026ZVIiyb?7r&@gdrmqZQ!WU}o*SL9}0w##wHAi}tp3 zDYsoI^EUI;4gFCSuF=s#VV!8VhW3Q<;{wAN=W~1*-)7lEh9`IoMB{V!0nvdgj&dp) zphLj`oy8AFRgs-~Q2N03Z6c2p$rwihX^yN#Mv*ywxDhjYj@5~ z%&P5^A?3BxPDnYkJ*!slopZuyTYtifyW$*!y}0W*yv3;D*1l8ss=EUP-oT2|7C-!*tP)vt{0h_pp`Dx~12fx`s;cH+6@O`t*+O!sK)2VRGsM zcIL!h3@LDx_aogSoT%7S8=>8s8Cb1OX@qS94 zVwEyoa_j{XFTfs2<{=lizj;N5$IbdzaFA#(MJsE4dq%AYjXIqgb$z?#J>vH8mUL+U zIWDJ8k|w-H%}VEu$P#m$5pRmCpv}J$J>B~Oci=Q)!MUPi725g_K#n?b^&1#5&`7zAm5Hj`HU?P|3FPgwB@Pu5%y6B}gKZY-tBdwS4wbkCcIq>m#BDGKv9^u2s%m<47GAV+3EpvUJWst? z>9H($!sE_}?*;Y9wG5-}z>%w-2Cl!;z||_wZlxJ(tV8k~-?$a=kR1CaF;;B6YuFtB zxRv4?w*o1tKi?xI@7~4-m$+FfN>T@;&c*Ud0ZLv_C>b&fX;^N>FW^hy)*D)-1qu8QOa|`_EM5gVcI) zi%ZzzcdJ?)$j~-J;4%~1J*lxpH}!JgpeUtKx8OP-&fsgHI9I}rbZo1gPRUhMqrbtI zfiKZgvt}qQwICo1u|&^&nU!M#AWL7=T=5({b5} zID-k%NIdk(*RNt9ccy6|mLww|Y^9JnQF3O4^e{3>t8JUY9=2zEZ`99Gwe}8$7Pmnny-cw5|J}HQMHOxb6n$VNh zcibaq*^&c-Egl%u7s4KE_kD zIh$s3#D>OTe2T?}1@U_ECG3cinAG}~rdWzjQ_LI|5`!V)tGe{&9Qih2&e`!1o<3}S z{-D{Akw)98>e_J3Y|w}eR(wm|V?MSBZ>MTrgp+Z8{Mr16MUP7uxHCu&Ln3@mv(i~n zDdD31S@h+SM6^4>l@cl19q>Gx6^-{Wn!~L(^|P`lau(Z9mm%dO_e>mQ&mwgjDbqWTfZfH?=MW?w$zvoC^IE5|&?_wnCB2Niv> z{p^6}l5jEtV@FQngDlO7#NeKxR-y`xfd@rLCOaMaDo+1M&wIVD3I9-LNx00W!`-(- z>$(PGP$aLDezXv9obnBY5w@m7)Nh_w&Rg?L@DT4{%;eqYQN6%QI1XD9w1Jd&~0*X<3`MUr@FAAyu2R7Ejv$?`rc8fN-w!+GxVT*NS{(meA|h0mFtF9k0s{CaLcFioQUms@qm=1 zC=>D!XrmT6H)1=AYiXS4E7=mUoy@f>lsKyK`{spoc~wC9{LC7yF{m+E$uL+iZp1CI zgoWi(${4F4bjZ3ks*kw@ zDl3_A#EPoDB?_~a=d{<(>*smd)*WJb2@FYTvCi{1Y@k7`4-}HVlEyB(Gtb*zNO~9I zjBms!VBJYqxN%2`L?oi~SxjZ!sT0^n@!0Nx6nzv>nhWI zVPpN*6Z{zn5OAJNnXmG(f+fN;vO0^1U1uH=&>o+3V0)}TN=^PHkVBr>Hh}h;C&=p~ zXzOQdFH$R%3;6Qd8X6Tu@J$JRf+tUfdYuWPcLX1y z9KI3i7&d24#FUujke9hidYegY>wc?h9vW3PSzD_InLUvPO|&N05@V;MJdcc4OvoG> zMH0|+ZInDK0zFc1>4%$+umCBh3W>nRq_s3A@y=|Dk|Qx*@>}L3$!|&f#QSO2d*g=W z7V&{%Vna+?(@HzU*XqT4=XsSOX4G5KcfJ9sDn*`LE8^tcgiiHAW7pjq-*t zMgolxuhT)h)9^3HZJorS2fj_M+X)IwK&Mqgl8E%c*~qjx

QF}4d?G4h18 zuc<>{8&-RhMy6ZT*aX=+;!HyFHc*uAN)|wX<+fYGZF@)a5sCPFGU~tJmvoS~9P+PB z<3H{>k+rCkc#rn5Uty&G`Rsh*;sYiz64)rwGM_=I(Li^dwM&^zC zmqTg7X*l0zn2LpJ@XVNQE0(M(m&L-L=THXQ#Nx5nbk)%W`bM3yvCfEXO;Op-Qn6vY zbvGghmd|`(E1Jb>4aLl9K5IDqN!riyk>U)vk2F=WR}_BoafsJr;*;S4HFwCXZd5U`lKa{*6G_y*b=r*2;6Hk zXuEIwkSjKsZPq%3v&9psDfZMHuYkOpI<;t}rQ;Otjqlmc0liT}q;`Dg$e(a}S+q|> zpHLdEu%>i{!X(@oHYMINI_S>CTm367y>MsY2&=%#&Hx0l`b3r8bpI?-!gtYthM&H{ zLw946Pp-cv4YeMMlP3PHTl0amzFlnim6sm~!f3scPp?Ult!Ut zl00?;jMDTB17EQrs$!Eko7*~jZy13y=O1$3a89r~Qz{98G!>qf_kmrl=c>d<_E^s? zRhFgfZ(wP2+VP0mVceZGOQWiT+fH?*X5^+;=Qe%zx9OnCEqodjKCUA$$bLxi{OJ8{+ zrkOlYw4)h@_djwP;hVeUJj0W=c2e#P4|g8z0KAf|D&gF(!okkFx^3R!;=Q=ABE9dP zh!!+)(CYpH+~Wv4Pg8QJ(7BpntR%hPzdwc{fqw2Ua3fZZrnrvreY)6itJk`Vx?9x= z-~C+3P$;_You~*7_Y-KIk}Bj_KzCtcUqkX|p^L--UafYPCVx|+*v&L0xY?8#hschM zGl4D|3K#9)&}?(0==dGqsmIkax+`ttE+Ci|3AToBqg49Yg7J*kpF|^zU8hP{x!wjT z$gE+N#W(laPP8lU9*&Z3EoTAgoULQ>h9XzB1wm8hj z)^#~Bo~?~gbffxp`ar1_4`F#Bff7Vs7~-bxxZCX=I`&%JLHlB1n3z@vInJ*Jc6 zFdFNeGLaed5m~n>>UD@2>qvYT8wi(H(|NiL$7G$eZl4jedt@KZAXX1znLzZ?eHa}j zn=yIMhHoHd`)k->!q!GY=4+Hp(T<9}xTmXXsJQ#Fwq_$vfOw-fCGKTgOzC(KLpToW z2lCctfx~WHWz3i znpGndxna%$YY_KS(KSK1enXdDg1za+gB!pF-cSq&yV1bUi45ZBZRo6sI4u+pLu|!A zbSwhz=cuO~*$Fd1^;yVj2b%e~O=%jPBT^SCF&}@?c@W=Y3$|~`{?HenZ5F)dEIE?S zqq6_vSA_FckaL_k!+0TsIdOI};>6IAy%-;LxMAa?ei7NK6NwlTsVK1S z@~{{}jjX!jI*tWkuoQxDV^}z=#vosv0}&nKLzHf+32Kix*G28Y+JJU>u>GCf-pGxB zc9AoqS~EY!hHxB|=Cn(>C!|c5==g*V(kd6BKFjvR=egEL*WnE0_OA(3OIQZ@t^1es zshsEX4Dg@FdW?sM&MK~3^9`RS{|pDR2dTsQZ;8vBVsVM~A|0MSrCU0|N*P7>D<>YM zMJyvuN4i!g2tvK}AMBEqD{&$cRed@#bJQsKKQk~F;<@hI?7#ZXe5Lvh*nz6ebHCED z+29DT7H}{x#mp9J@RFT&%<0PnS|^O6b;5L=ni_MU7bka1r#6g1HpcpH`-++bk!Vs) zPrritr8Wai{^YLe_mwqXc9#iN{BICL>cYJb$Sb2xLHEXbXOJDFRaIKFpJu~=o{!a7 zZ`TpLQ*|PhYte&YM7!JWU^6kdL0w#PDFVOu583an1pMp^KOeCktDA=#)?8;stE!tr z7csCa6+}lY)?$t;dCteJnMY_i$@~Hz>kVxFH17yz@P{v1lNWh2kI1>M=ZWyQhw&X{B~l|@h6B-cTxRhtW)L@x~;{yZK%{@ zo;W4bwLX#S!&u8f3>kCmbengm_`pKMz;Z;>eYRyN#4v{f?bm(4ka$6(Ab~sXk`5<# zt)Bq7YrxWi-t^Beyk1S_$8<#!Qfz~Ulmb0(Y~Yhmt^sD~TK9%L=VLkVW65&l?1z}$ z*>}Xu*Tsf&5>O4&*)?fwhYPC=p!kPt@T%%B+-=>oYlAY4e3^Z*;yw+V(sBvcLTf!p z3gZz>j#<@fn3*g`M)5iCTdyI4fMxB}g-Mwo(*;3bmUmGjKMU~z7wIjrp$V5-P^#XR zs5yJM=5wr7U{>NaN?W;0yM1$18LqFXmhMUH=Gs-rdxhZT&b#2pKKF#2vPoS7JQy(* zW9_CD8Tz8ZLDAs_SJL6uP%Hngi~Ad#{Y2L2hkAKV2=3gb6DNpyLuXT`Uh~1(4{E;l zvbll?_iUVg%RS;;9D>mfFoLl4I$upPNBM{{Ei447V&GiAiU}6il@P=IN7PW~d|_(} zfyQb&r`P;bT@v2I3@P5zu<4WfC@y4OBXL9O1%}0h$?m^jpjA3OifH%Z^MThs{sqhV zO&9I3;&;OmX|Q}n>Fzbk_kAFKz5*`^mGU~04ojBvyQgdEh@p9Tbpaj)o$9|sv^5m( z243>0Wkqa|BvnK1(4VPlM63dDl{3DBp!~ zsY_7rgov&|U!#GBIpjkQ?mGk4Uwr2~K}0PsMB0Nt|2P@rE&-QShB{2SwvvlGO zU!(l5q3T>Z&Zy=`cd+#yAfj*5hwd1{0}UPe)r-CHj&<5JzVF;iN2A4ti1*lqPv^S9 z604_;YV3j`(H^4no%TrHXBy~etm@CM73xFR3W*ylAvztn=JF6HZlrx=zuPE#t*tp4 zWn{mz$~Jm`fgeJF_PsczQR(HSKv#i8tQr%Q4fSub*#Upn&I~=vUB|sM_2}<@<_tR^ z`1>>d!gRc_L*4rJ(nQ8+ z3SBzr`UZh8bTN))a-KZ~f3(BqwS?jaX^oFLjQfC(M9pxY>G7;B;U zq_pBaSK&gio4#!k?Ro4{`QC(gBQ&2U{$tz^EMJSqtemD;94$Y<>-Fg_1Wg>$(fw5q zrMa)i39O6=tj*Jqfc0(nG+Gv6nO3cGnj+}_1AqAA-TV~0b8RdpJ^V3FcC;mTijL`Q zWreO>=D52B+y)rQ;zwXh{ly=DYd6LBSfRFtg|Psheu8%Xh1&k^5#DB@!}?;m0w zSKSXd+-%s6U5x3|%`+_Dp}fU4TDt#v2o5Fe%M1I>@7Li_1@7RYW6!CO`!ILeu= zpUKV#>Dz0W3cI zPyv3dlYB3n3;I5vjdkJbUhZS((B9%T^R2(I`(@}>n$8gO@aiaAXBaP#pyfMT zBkA4lx!);5QA_Rz&f&#H0sF54@D~Al%K(O=UP1BJbG~-K`w`UfLxGx>-V|$sKUU!Q zxKlO0b%1uj`y$wK=5Y1_KB;YgGi6Kn>abgO!bHbg)Y>F_SrwE^P{iHsD2+A>%9Nx3 zI@hiIs*Z3)Y?@PS-68Ch8#C9Z;+5ejpvJc=U5XFUOTVQdntv3~o%1bV}n?X1cSXi;0VyQ4IBiKRb~=?p|IJ4%opD7uQu? zqagIVZxw_T8QS)ZUxpU3Q^Qnv6&C&#V;fa_Xs|s(czgW*Y|rh%$xnU9tUcAt_$|Z| z>aIN7Q-5Rn9n(udLE(2WTl4`#gL#efRxi8Ghac5Ln!WvvB6_5cYL21clisTN3ZKa* z#Z8T)UU$ywwl!Ca4ecQ`+OR7l#b579I*h}>re?=SY#6ev0=GGrsO=lZ{_!s+f0dgR zhxnA9$}~FNr&^Ktlc(=u%jRo!ryHma~zRd~yM!pB<*3+IDZoqzoi+S|gb1iENYdpi!(T7x)^ zWChl7f~tMLy>p`zV`tHezE0#D*JRTF`sU^yz&H^b2C8VdrKZ*o^s zc-~giLv%C?LSStb1s5;e3+8}&c6)`A7nb>9idz9!niX$fRH{b&qJuxt-NDfk@#niQ(L?D z3o2b*wBh&-m`Mpr1>AToo=*d$`v&Dy!Xzc$b?jZQmn?l-$87U*Tcg#|SB@k49Tpvb z0Hj^n??5rlq%6?wX3xE=bV%rPs0%!$WTDJu@!6U!XeEss;-9V`I7AuGz-Ko4OgK&# zXrPKY>Ugk_S<{!|9^Gg z@9n9snd+MJ^yzbYYNk&2oTu~ypY+jML+^o{?hPS2{>`iJvqq+67_1HcQ=s~S%#)36L#CN-C5nU)4tybhJWxmRjG`pIP1#o`l? zay-5ZWeMn5qA%Hd_ir+P6{q&a z$EjD*8sk13L6`K~4IeD64LrYxUFebq>cqwoW!EZ@vf59q^)Xnj8^y$FYay>bcjgc( z7NYA;rc6G`tNqf9W)}QswtPOc*5P7Jt~gTn4}+oaQQ^9rwu4zeCQg-Z3+(59TVw!= z6W#2W2DZj~cdn}hI+B}E^!jD^8pVx^_*PTsIoXk;iHG$p&^+1p4t+d>b)Q-aec8e{ zxWtY5iSQ=Y6S;wwfC=t^rc7+?ay*ktUq9~k=p;P;P{U*WLnv&fw}i>TvZm47yURrY zwt(bpAN=^|LCC>R2BE@??9ZwAgjX5?-i9vajt^%lcRekRlAN#u3JzQlv4bg5Vbv!a z>2tKM;A*7}Q;x}w*`d0enH;Z-Ushk|)08*Q&FyTx*f9GO9$>ad=Pu8>vt|U6a(?$d ztPw>2jZax~62nA9VDiT*n|;lFQ@g{gb}@V4{BC=l52@_3cw6FemuIyghp|C(n7#eQ zI|^g*(t(l1?v$patP7|8mwtH+n549(kxt}b=^h^~zh=dr(@JHz5)-BB+Zj!&OI4f`29 z!k*6INsI@a>Ry1aC@@)>J+cBdgn9j$j=6PMI47{S|= zRHw{V<$?F(ZBEb+(wyT5I@re_;|r3LZfwb?JsqS46DmkAY=6UI-l&8s2!FquS}yf? zUT|_$Do}&pXFmTNwH(Rm|NRyE;O>>o@=njdJLBq-&tYMa!Kn|vS~?CoLkezuxlg%F zq0up6?A${+baJ_rCK~j@`7L7UKX&Bvu`5R{Wp{O z!NT!rl#crmYH#)@h?ZPsXl>qPX&>lPVx?@WbLV_H&3j72Q8?H0`_Edx!$8DAE^I&G zdffXc|KkcKzD7)@T)d2^!ib{(#h!f4vTf&~o}I9sS%}Mi+{F{q^Zna#e2mvokj)fV zWd!G}PB7v&#e-vfsZ)6csu(zfZG}tz>ZO|d1IKXsSAI!9QvJdlzSWlSYOO6tfqglC z++qLzxZPXw)yN6sHZrV+Ewxk6Z6l-F9c&EuZ73`<>lAr{^jsC2)pafg>Sa_}zC#uXrZFDc4A*Pbn*`lKt z``V{6DVD|aWqI8Io^8YMmxpLH6(;9xhq_bhF<7j>7>3^GhN*uDifvJu%Cw%sW_|8X zecl@dAYfg~qCeBJt_nz#By`gsW+m=yJoI`h($-{6 zA~rF}osR!XMKmuW4dkcng?43L*@N*Tgs^>jHCOSQ-nFJs8?rAXJuR=hQ$zp^#!;s}X2c$%#uSI(|soI@_@?7fpq@Q(3Fe#?8M$segv-00D z^G{#?{5_ODQ{OtY)uu!0cLV$hRYCCW5}FmvZPJ^Ee4b_I^S*=&;f(*Vqs~_$QWW>J z7R+|}9^X@){mk94+JVVYWfo)KJ(`^sKh0P>__i+91~S8en%~TeJaqCTY0W!td&|T6I5J) zkhIfHMSy)^{qFtr!(XXZgO9XZQNO*{*zFV7ypeeyB^(}&iu|s138x=e+VF)(5Cs}a z%zj?TJ;9z)<8@ZBU3z-R-^bz}?$XuKnZRi|2c>-aZ0K@`^e{`{^=&k|0eb^?+sCvt zO6)>FA!5;vNol_&D33ol=b8ZdQ2d~UW7K>5`HFpiwomBlP)A-(^wUL*PY)Q7g~mvq zy3f_Vj~~Y->h9p-((5>?i6Oz{%dG1^UXGW(L3eI_dWhCQPkh}R=3u3sP9GI_A>He! zBVkfpZCmaq=n{I-FVoO75hN3!=6fv8QNnUiIp2u+WUBevhC9T+g0W(!EuWa$B1pr# zO#+D`4yb;tIsK#|=r~cvWY}zAdj}KgvO_g?dLuArk4@t7Y-}Q^zK!vh#dy|e=nHI* zt`JKOPvXyn)8$)jZt{x~bM4MW2tF{!sdM1v?+&@?5GoFB7zj%>?^4HQW(x zBRiE3qPmEie0wJ(*xA2%=v|wV#gViNTRrXJ9U?|C%B+JvPa> zhs4-TAERRMx-_~$A}i+EGETux+-XL~(C}<>*$pi-f|ZACS^6DBK1N{-zxl{|sr@>3 zEFs)E>tE@O|4?r+`EsvA)5}xIp8!L zU6CJ;J|p`-b21$GhDh;um`Qkn*6#Nf33-h9P!aXQKTBQ5;`ew3v6U?auz1ebsR3`&&rC;mbzr-MH^sZ=^6ZtnlU~hS)^&UEAHWwt>N>Soq1EF zu-xSgQ^9uUwcrjywIeRq`J8J9;o=@F6FWQdZDM6M3xN^nWSzA9`J2RrU$k7VZ4%Y7 zKA#<%J7`b@)>ezN4|2ypc|`VA-$Gk~c^> zoHV|URUW@ce#Jm}VcI4SZ5ZcJY)uoIq&hzKps-KSU~IMI+Bun7(eA*uazrZB)apjs zUN|N5$)#ZKb{WqJDqC{ba_($5*1DV%M zUx`(QS5&`;ERaT23s=uDMl>-lH*aY%_3f@}#qazPW>fXW4zYjxe#yGuq_7j+wbqt! z#Wbe2imu$2aU2+la-5@KYJ`jU}=Td4`P;$$>l7f<&LnmFV197r3HGEef~ory*`eU{NER7BL(BLr zn~ps982Ns=WG_$Ovc9z8<-Esd79MGTWq5OM@4gyc1NdzCP^dUTcm&Mz%--C>(vo}8 z$c6h;6<@6wjph&m1%mT~HU04{4*nSf>5heu{s#N8_&K@UyG;XggQqV=04l0P3AbE< zT5hmt#t=Ug^D&5?;m;dMJRZOv;ta$9qv-LsM1M3On?Mrage`?e;xWP9i$)DP12= zn)D|%@9n)Ws%i1@f@jo6J?n<$!A1`-7G)1!NMHrIVlIO=3=)Wr*EnWr9v%)@A3+M5`+@Y8o#qeqcHiU zdK-ChRiU6%MED~r`h4PYi*YrWmGvf8|L&UjZ6b}|e13O2@w!-OFEz&a=eJ z5DTP%Qh`*oRP;sM7igxKbyzR>VF4(DZaIJqb_WmxvINK6um^xHNS3gUaAgd|_jFr* zGa&|(5pZko{Wazn6~uS+!Os`#=d*#(9v~Y1IWEcA4X;3MfwANsRdEN_%1^6gmp_8) zqFYqO8W_z)D*+IVF6Q7mwYWo)*Z!_=l-8#;xip?eP!-qTg^PXZV*Vc7#Y~tx z3e)llJ;R^4zo05c)H6Ndx!CkyZ5Dg?h*Oa=h6ZRs`#`lxKZCY7yc@lp_tH|3>)Tl< z?LAH%KaS;X<~WWUu)+Z80h+5;&|o=7Wxzwg?HSKuKOs5}_FD{?@xeXt1I6v@X3T>N z!x6%MArP}5wE|VDbYr{@CE1g5!t&c&#u#&$qdzAOyN-!%z(VfBfgRTj3GK4U_p8)} zgx%B+W68o9fA?JyBV&%aI$v`u#MAUHBPqu3aU#nBU+X9job~a2E=cYpSE5z=>vHDs zN9-}3^eRO9^w$;np~OOpm_NX8al^ypV0Lma;=6XVpT!PoDPKxXXv)K>mb;0w7;wJ9 zSE&lmRQ+%Kg-zp#8tpnddOCtx+h3FgK(oo)9tM)n(OiZ(iwtv9yI??GT{smTFH#pJ zXS~1&vnQvm6}F^R$c2tE5}cZ}q5tmJ>fPU^8qvb5EkAqIi5sm)ahse_bxhNFc}+96 za+!M@!tLUQum&rL3nIq_n*~~#W#1oRBh~MwyD()BmHn0o-0;g}eu}MwIPpeml;|+G zV}Ec8;W<_H2)j@MqnQF5&QV`~IxJb*VuW_}U-z9fT;tyRo7g!e>a8xC9G_{B!K8rp zT5CoWNm+KDewWqhqnvyNLAHnGeDsrCI3r6v!b}H3jg{mJTskilv?rK3C(%7|f^wz6ULN=DtdjdyUQG@z>5(;9q+8H3P*;pM+9B zVnONbSof5;kMwFd+;CQ%ue#1JZPzD|-AGHlkUil?G!Mvgl;79K=0Zf&eqfW!DbgH4 zPb_{})m-DAK${h~mh&D+uDyF2MG3#Q9a(nLACJGOdtR^n}fhKgmt#d`w(`EH<$hfmm z_j_LVdkYc7GW6&*aBF!?3u(iU;A%X4wPk&md4jZX5B;RwmKxtSW%xc=ZV>ju|1FjJ zilo#r)>L39=l#T3ydYBXX4P4g7+C3NX{Y$Z0^9~rEWP`JyP^-VLYKX8bt1myJbC~p zM(TAPX%H*l;heME<*Hb4mMSrzontrh)U5dB>%6_D{OMlqNw_K%Onjn?zEWbu1?ohH zEqEQHeRKuxG2PH$=x+2VUhG|&6@N-#GH-S4$e&tXKYc%ZTfF_=RN$w=oQeBUFQzdq z#uP}`^Z6ouq9^QFBiqGcIdRR)=r<#WRb%Bi)+4$%#h>m?XA83L-Iem!ufSL3J>yFq zZ zAHsz2XIeog@^e|~VO(K@jDe2h2}7nS1=n}_w);;y<5vN{k`)Yy5rj{kD+FIr9)<@z zfIS3mCH5Z$)dbMNtfW_Ng>z*?3G)e8gkq9F$4@tOLC0;LYM@RG7`mF@gRw546Z47) zIBLFQ1QgPKdE-irt)eMPLZ|@UJXPR1mK!Ea50G6CD8XBcc%eelbYnp1 zj9y@Di_Wdeh9lZ&47jtxLfgja+_X_ZYi0TGyO<1T1~u3rqmh->gu(t~ z?>(kDI&V^Y&|GV>8q-D2=mG>KLKezBBn#v9`@UU|V)(lH4KfZ-jBTCl=XV@qRXDk= zXBk`2#^v?Ez58j4>aZ6jE06oU>mGw8hsyiFl6!>1Ah6wJvz9XiNs$K~(G)4xvb$$Q!49Hs!yOBFgM7yMP3mw?C&Vm2DnPd(K zDS%TsTc^)1BPY9q(H7_Q!4ov{T<;ha^Q1?9RSYqO(mGIhy(*(a$cAK%W1oC{O`eEf zo>zj{_-=(UHGF$=A_B|>B5hq-fTH2|V#F2xdGaR8 z^%m)$7Ux2FlRMjy%pKolgYY+!9_mq)QMJAwn+_|fC@P_c?2!>;aV!>zM zA4hfO?9M|shrwqiwAx#@nx6%a$Ud+vk7!X#!$o2r=b@deV`qHdkLdF8OPUt(1@yGulE;=J6w*uQjK|6#s>67}fci*u2CM*;s8ZZn&`We9kSuy~nkcLL^8#y; zg@UAy^J+^FF)p1%BhGfDgDboOPxmbqve6(7uHZS z()z}5nqI*ZsIaG*nZMop0_J6-$hmZr7qgGjG%_*`-n&}L8$(}dm?>41Br{QWEAG67 z8qH3`x!Z3W-)?Z9zqge*vzgB?ORf`19_2m52M-fIHl{$>ahB)vKx*tdnIBSH3O7hxECm@@Aj~(Vt63&kf6GiWb|f0A$OP_Ld?ZtC z*3#HM^+L6ZJF$-no7dUYtg(Tfy{Iozr$MAkS>1FquCA`!!%lfA{xfy` zB@lXc`XjpdL<3J$xRc$du+bOM@Ey#`VKz z_bfHjy7ovy;ZNKOi%jpZx{W*1K50hs@q?dX@z*u%G@*boGpai9j{1B)fr(nbYjN_h87p1R6LK|4We8PBp z&oE9&XL>)#qH1lKt)D@=eHqBKWDBwk^GiaHkGeF^?Z-Od1x^7Mj5+L(O8-`6;P#h4 z;T%oT{U!X%?5)_9?mFU;5W#Vqc9bo9d(17)=yv!b7h=|yrU3{l_EHxKQLlg@ zCx9v>6F38fV4|K+X+;V}epp~Kr#oLSHZ_qDPCgS1&aVFPs*CDjDC^(oS5z=k=nVrT zjY;D(+rS+`sC-`@@yRv;WT*tqfjEjcYT`8f)*#G?CG2;PQO{$AaW`#v-_j>VYa&Ay z^=aXe!CImC_SU^Uqp1p2x|$~t$%$IkdR9)lpbPY7{?~!5aXF2Qgg==XO;sxen&K;v zQ6sXf+dm^nX;85ju zA?0Sx<~^`=v5;o7YV%WSLhzBPwMcmo<1>ERL)VSGVfa+9BD-DVpr4g=t@%`YwYFYvoK@j5y@>se!Qm!I+q zfh0;Nfc+C4HMPrvBZ%QEGo<>S3b z(9_3r5lRGWc3ZTnmSae|h3lDF;_2}iDck7HfV9JL^+fpjNwgp1L;)OteYe*)1IRSm zF{zlFJP`Sjg?{1$OEQzC!k-Xk5l+(}yj@E=!eO8Pk%m2QJ`(6OMgW}M?VMKSLt|WR zcLLLq74_e&|JvDq8FCp%j;>>Q=ZqWTOZQp<+W;wf<|ZTD<6qe0$jl_cEt zL{WC5inXnmicVcL;0-HD($;y+ZgxJ)cxir1Z9!^6%lWt!Dx}!*fXx!xD!kJ>{}PRQ zh7MCsR;|Yq5B3xiHJ#5EZdK=GVQpq+4GA!=R}gy>j-C)TEBZ=@<`_SY@SRDR6StU9 zoAE#u+Hi`)$c9Kpnv;lnhMBo}BLN%NdL$FyH3y#wo9vrZDJk{#P zZLfOS(LjJT+K_@~ErD6vm@(qeQ<#A%9d8@)TDhX??RS^d@IKf61x-AZg{}$xB>d8# z5z_J6tlGS0#^I3?d=`&B(7+e*vLiu_!inMUnCn19cWz7Q>hK5xD8g1y#m%eB8UNfOS1+7 z5{RXe-s{VW^CXh46P9^=Ze?Un^0MIy0_tmaKg;+ z2L_G8O&i{p#@>dr$_s+}K0C@P)JJNQY!wl*_tpPohnQ(}#;fD;Vz3=X#d`$V#ELxK zND7djNRLkHHD$=wEb?bE9wXd2Dy~i7R{Z7m94cfV5A2OJ!)3$1XWdNoPvrhl9VZZ` zoE$X>#9I>pAq7RKPcc>zT=DSCZ^-@p(QQ-W)tyV8-uaT)OR;vYk=#sqIkxq!lXWtY zSM2e+11;_s3AmF~BN=%@ueNk1yXhQ6d@4$c8D$P5nrRD@m_)5ddWF}?9@J`S zYqo}HPh`MtCPgS6-K{k?O%3h3=j<>s`7Fc91X*~()|3Y3!cQC4QtWKC`gL1f__iF- z91V;z^sH;>4Ha8AuiWD@nfy4kONZX7!E~!VfF}x#)8>c+2=lM`%GHH(EtW zOEvYxl^#!E?u$ORw`Jp)t)eEBPK4)ViV!Gx$nB!MN&D{2_#IMKLpu5)}W zK#f5{oQ#tkE(T-}y5TFbC}P4MLd+p*z*j(4ROt*keEmAI5w5&3B=($l6hk`Q!pstw zz=7Xmp_|eW-%3FOF<0M8lnrD*`${kNXQB{3@+q7(ODvj{Snb)OOlxy~IA_OZW)9tQk4z#A>Z=CYMVO|m>^NCS7kSeK z1nP_gEOA@esF~uZO!zFH8-4v$OxCwHa50zOPpfEM1ZgVeKpxp zj466^fr=VZ0Y6TOQt-%+Hy{@g|NJW+cWI@?rHCTEGQ)KvpDOV;}T!a*vm@Fi}G4EFV8RHh49# z#HXZov8~ZTl$_LsuCbFZs_jcEbY*qExM4{dRibfD)fJN$XZc6WEz13vhipDz=a6_ zcmN@akPHAosG1-4*OiBz^-E_v0WUuGTM()e@l9!B+0ZWzo?+3)c;Ge=HHT@!qWe?+#JesB_>VA_ACH^>Gl^5 z+`r9FPYe7*3g>L?^7nvo{$;iQueMm39|sau7Eos9Mh5_Vlmh=0X4I)e1~p(;Cs$uP z4*^?O=YRKYhH`zL&jOp literal 0 HcmV?d00001 diff --git a/src/test/kotlin/6502_functional_tests/bin_files/6502_decimal_test.bin b/src/test/kotlin/6502_functional_tests/bin_files/6502_decimal_test.bin new file mode 100644 index 0000000000000000000000000000000000000000..7d367a51cf05f95b25cdb20db7fa051836b4fd1b GIT binary patch literal 234 zcmYj}KMKMy7{!ycNz=b^6sN4cffsP|4rUSB19$^JaO@FEA%nQ|2!dE}E4YZbw&>;} zIQm%}T;6*>c>GGb4z~mdP)kz<3FZ@&uV7>ea)kMWSkIY0Gu^Ouq6?;P!&E(KuRU#> z&FFxNki7TQk|hOKX235$UG`NomOzt9U=lDfe-}nViQ+3b|9J50VXgfXX_GNQn!g6+}Men+6|dZ z+jPdV4#H6l0}h_rE_lYB%f*+`s>ma^CKH&*Rz{#fH;_3`Ck+lG`=~)y7+RmFF`;#J z*Z00Z_WRwv)#R^aGLr{mwD*2|KJR_r+r8D^*)YVPOk`sJR%5_e`Hf7nHjt?$zw@1T zbD7y;cACr0?nu;(nGI&#Tp0P1xyO9i{0sBT<|F2#=2y%wm|rv>G#@fCA{J?g)acLe zyaICQ#(HB``HCG)xHk`8B zA2Y9ce|iUw%*0&7xvFJ*Fu(1C%00hr#sD9arD8cxGX+sp@c97|OyhG%gI|!hrKI0VWDCIMUr|cQ}2a3dpAqP0f|6 zeN)5u&+bz7LJf`OTB(XTQOJowj$2FHsg9kUN0*mY^hBK{@x4)}Gd>!1y5p6kvo`M7 zap$(Ub9>ymBW|58R}l;#7>;YC?VgUkoukVuD^gKsSA1vG`P2B(sPn~mDd{{McOHp5 zUyVCoi#t!mt-h%q>^5ze%u3XGDn4pLU^d=krlQW__+E2o)cJ?F8%f(0vlMmyDSp%( zjXDMHKf(R~8h10o{~FIf8&8=%QRh7O|6APMBK&W0|5cuUJ-*Z28+HCW?#>B+mE$)w zviw9N^Dl06tD?THMpoZi?%%-u8ynpL;lHPm)wjKo)$efs{f+MH!v7HWKg#nTZ)E*_ zvk{e#feZ~et=+j{P~VN%X=@5b)0akJZ4lKp&;)}96NqMGR1Hnw*P^sU8KoskEG=wI;U>^V;oe)>OMEPI(Q$Z!1;vmvUn$)Vt_@*AuFI3EX3x zy%CTs&ThLq@>_GeocBI{?OLfiJ6nO1?Pzspb?SPlS_ZW7KQ2{^=gyt$9d_<)k|8}j zWCw(7g^*nw)dJKeiQ1dLFZY?pyEXyn;GhMUQ`5S}x+jufTFsT7HNJuY(1z z4S0+juo(~TfP;2v`4%4B1(pY-bGGE0yXDz&> zK^(3!yx_}&y9h7T`WAH$yihqsEY(B7P4rOkRPa!+6AuMF9t!5E z6*H)N;DyQ=#9|y;v#n-AH{#uoUybz$! zt)fc6Zux7)kz*Xkd>rR&c&%};*M1HN&^QKF0^?w>6$f;YuN|_7WN*9?X3$t>nZZZn z8k!BYvWi+3Z-*ItT)EmYdstr$>l`y^T-*@gVnKRWS{83h!^N567B|Bdx8N2>a8@r^ zBasN6WjF`^0?IB5m!Z4hh32a1E_l(CkGz0cr`hr&Xg`2*1N1Qh*#n*d_(mWHWW_9C zR#`wH3?d5}5eAV3jr3t7E#OE(Be^L0f6!(f>YcEUM@_4D;>~urHR>gQ}1Bu zNhm#qrO*AK^U(38$l&<@j((7vd#x+-d@CN`5GbqwhQT`G2=5|73J?|nLY_7MYMXTo zntzcsKP{S{#^#Huw;=?Y4-4tnLZJB{LGu7JWIv0||Fn(uu7v1443zFcb9Z8748P^-pbu8rMq3Y` z;X*gML5EQ8e$I{VFz)^fj2qoy-2E3AH@d^P`#CrC{j%KAgE*$Md`w>3FE0}te6Sh4 zOZ;8G+#$U!=!G|ASZ_{@$eq%gL@(a!fLHeH=N-Pnh*i&i;^8ZdS@rB^9=^h;RnLCv z;VX<=^_-uuu8XzyI?eC5t}lamV2yIB`K{LV4q=m{%p2DAPGOV1C_L4G!c$c%JXNZ~ z0XyM8qY#C`lGuHcbgIP#&$qyz+ z;%LT_pN^Zj^^0NYJ|edMC3dP0*@xNI4~+-5{-q`S6h6$herSBZU!Rwj3OC#Oq4B`h zztk?=Z0m>E+q|{`q1;NqP;RAVD7TU|lv{1U33+ikfLlLwCb0G=VC~tp>j19((3!yA zpMbsRZruB!Gl9iF0gKPwxcEb70-GP;=BJ$MJHXA)In{T7o1b*5?*KPH>r~&l3F~}t z^K<*H^TEx}ZMDt^H$P`s=YyNC@Kgf|PgSk(RH+J&*O&7)|A4mnu$gl64``bY8!0#c zfVTOE)#e}2Hvcf+{Exuqx54J~x4DyTFrDysxiWv33yF|#PZ$B$xG~rx0C}$dE$%Xh zs1J|`5b$f?;9xD?B~UQGDS2fba)sWLl=;m>NQAtVfC#vi2;4rr$AM4rE}pp)@ZVU+ z&T(-gbD87T2S`{52!YMVIq-K`#rqJ~cN0}C!fg}_f;Xu8AP&xgLgDc$2B)OE6lXbi zvQxbE-^kC6bw!^0wQv2o5A)UU-hO;x1Q^C|j{Z_`Xg5Xg=RQ2u9eL)H=;n7%QPc0v zS6}Jb_el=$K?ner2$u!79ZJMSDX?Wb!Y;E@fvap`3C{HhyT(ohF0qBB%*QUUQ-SMi zp`H2I)s_9eqFr3;`P2zo&!iJZE^?a(odOp>kJ7KXmV!S<&_k`|#i@gi$w+!x9i@gP-P2MuN zhQ;20(I#&h6rQSE;i-BRo~l#f@%n!Aw+!$O<}Tx#43F^Ew98+Y@z+AwZg}{&W~uy* zc(1Z8k+y$Pwl-<2pp88eRCu2jHXRRs@ndmd^YC6*HV+SftHxSt_6FD+@sLp!xB(VT z{LZc_+yI*?jH<*9u*$-yYSb`Qks79|Qo~ebYM59jULBT!rX5_y#JvEBm!E*!|iF_h*z#sX47-?YS_2s4qDvlW{9@oK&0ER1$8L$?tkjn!e zFh69ta99V+-3*lYiTENC@wG@%Gen+O zY7B~FhKk2^up)rriem<>1uNunPmMu-$Z+AX4wkzaDnDePDpIP^32H3oYPcEu>@sUA z!?pnT19yCY*&rD<1If_#6tnsC@#P{bo^N_C(xXk!6@5YO1yH7rm>Gl2%owEB(iOLs zuE@1?#XdDqPmZ=AH`;>KDpxV9Tt%#Mkv9*Y_@$xmpTadIs5jbz%xDWTt6asbauu`6 zRUO0QiF#sY3^FrgkXlPu+*-OK*V2(a7t33`bGXN;uYehY6)_^5vyFq`$h;a+Jd}j3-YR5#jA1^ugXPUyy7i~b9@Dy<9YbN zG<|Zhy}+7Y1;3=jO~Uji;Ab&43!a+K^Q7isIrm!A9}_v-{W+fJ$!Xy6`*04(lDE_ z;|Z&f2nhL(5HjGFU7{N+2KNq@?Uz)`*4?spEqmQO+}JdL>u#MJJNMjvnKf>n?bll4 z{>nU+3vS)5S1!1@+b_Mwt-GcE?8$Q%=)Y3w55L~nE$}N2Jhuvrpe#mEA0d^%2%G{& z+$S*ngU~Vj5was4A0a!^G47eS4wM8j{1JK`sEQupABtXw#PH8Wuj8qC zdy#ecBlKQm9Wuf{AiWNMgq#sOM^?d%R^yBe_o-|Gu0!?=yPkedycvBSe$JN7Qp~Mp z6Xk}|ba947P1Z#fdltaQ_3ya*vWe2PfP-gTI$ZyBC>%uTa6HNfhiCI@sPvX(H`w{8mwhsUDw}Q&ODEe(WzzySvG>roSmx`fuT9F$IsYc|Xl zw14=eI@+sVqUMyDSK0IHQ^5EM$b3_X_9jX)m_lbQ9dPzbr+D^_?p2@ir{WXsE8?-Y z-_Ns|-($WbkUf~1@radA^3LGg;n}@=3!nSyBh5_nufyCEb|#;m^-BJUOms;eLk5d<_^9Gzg*Y4n7iL8 zGsWD&`Dc(BK6k%U>VH+v9o$<#<4^U?-RG~HJ9s}A$oA&$^GRMd_gi4@HlKUPkrbQz zS7GkSy5@1JECMw5M@R)&1fM$uG=$E*gU{XPm-#sN4l#EKXbzt{i{LeA5fVep9n#x6 z=9#)B8jz85mcb~s*?%-V%$oA&$ z^GV*B2k?ZqVeso=@E7wf@J%)&o5(h2TR{D6GMjR1*;e>a$u+Z!+Pm|2&m?A&mesd@ zKYVq0Ce@J2F4_#%$;3=^sSKGZc)y=%L4S79Wb04xIhZf#g;oxyeY5dlYU2 z_)?IIG@HA>e%EB8kStk~Dfc*}wysZ>5|c^&Z#%@yBnr)yHs))d)c!h$HbPo+p{3FT z&i2U`^>?OK{he%?X)PdMfwwu6DrK?8TcO6=pvLx#mb?40-S~C!_M7}LRjOXJnGufo z0eaoL((pBN>n8qm($>W-GK3#M2;$xbxD~*49=ppiVpgH~(H840eBr8ZedH{{f#qsz z(DDQF;87 zrvGWEGd;W`2z5Cfw0z@%pymBP_gVH77Onqwy3oA6rDp;Bn@q*}nzp3-vWs*nC(gn* zxqMQ37A2);Qc_A&P)cbJN-6D1O3&g+=~T z&U=Ve9)avvwCox*-o!rg3+Dd{@?&Y0{|B2P|M%g4jG`V%0aAbzAO%PPQh*d71xNu> zfD|AFNC8rS6d(mi0aAbzAO%PPQh*d71xNu>fD|AFNC8rS6d(mi0aAbzAO%PPQh*d7 z1xNu>fD|AFNC8rS6d(mi0aAbzAO%PPQh*d71xNu>fD|AFNC8rS6d(mi0aAbzAO%PP zQh*d71xNu>fD|AFNC8rS6d(mi0aAbzAO%PPQh*d71xNu>fD|AFNC8rS6d(mi0aAbz zAO%PPQh*d71xNu>fD|AFNC8rS6d(mi0aAbzAO%PPQh*d71xNu>fD|AFNC8rS6d(mi z0aAbzAO%PPQh*d71xNu>fD|AFNC8rS6d(mi0aAbzAO%PPQh*d71xNu>fD|AFNC8rS z6d(mi0aAbzAO%PPQh*d71xNu>fD|AFNC8rS6d(mi0aAbzAO%PPQh*d71xNu>fD|AF eNC8rS6d(mi0aAbzAO(Iy3cR@Kdz=1w)BgkSkj~Hm literal 65536 zcmeHOeQZ_tc|P}C`}!EJ?Th&`-%bk2C1IJAl_4P2c*~Lbt_T zeMQ*p#{Tm?0Z()g-^V2T}&JoAW*ZL3DXBbJV~kJ8GUfTt)P@4x7;&bO{uUu*0z$eFawJhq`p?$}4oQ2o+*Te-OqGYq znesqM8A{5~KcWmH%0TmQ0h0s_jdW*wFwlOf4CFJ1#_kl$onr&^&(31`(li-M)5S97 zB#~2toM5^=n_0Yl$Uy>S1`mL#{CVy4R&!+tQQ~m=f|G|`Zrc@>{ zKnR?`Y0tJT-o0dK>D01J(%+HVp7j4Hbu{V!X{y-dKbi8sobvxX<$o>ZKa=u0$J(gd z_H5CeO8R?JLoNb)Qf+P~=^sw*cDE<}zfT2;_Ux2fO#1(rI_eH3{XXeGA^qP^1>MU3 zhRi>g%D8Pw|DyE&b1K-N{O?Hrb(w!NwcXvF^#3Cj+)@6r#ILOr`RO|0pIaA{Rej6r zM18BIe~t7%R2S@3{zvLWeVgk<{l4@+S{J;j{7*>#S7iRvb)vt&sw3rVAVV!pYiDi% z>IaEzyElf>bheYQS%?}qWWu0ff@oQankEzcR+N>fqpU=YWhI)ZPK|{P5scGWm?YyT z6=Ru9vaYVMt}t;ZtSe01tD>w#Vk}|zMzDm`do6lT(bl2KPiH$ubr}K;wozd-bx=+U zId!Dh%G@T(Ysud5##%ygN-F`ssaVcm$qkcG@00ueP^i)sxQ8Ws9gsZ9o(;C-H|BQu zAAIV@jbeFnatbHg(en24*v(?O1hkRQ7t4hU7cO)R_@AuTA#E~b3qm#`WQRocfLgCn zJM!CdpLu%uI)L`}dbpfsL*)062Go&9th2BlxwCZc*8HQn9j#wl7fmZ6?TbkBt+ZK4 zn=R9VP5B+U&t@G#Ha3aiM-jXk{nP5m(-f)<=Ld7I>!^i@I*BO!?F>)mK}bCtxM{-0 zMWMyRs^N6cuBQXqrpM{vV;p=#TQ1YVf5LKGTYg9fZ^A;?20Eq9zZqvbfST1V|oy&B*8^#}MBUPD3l?|veU#2=IJ-VbJj#e2DK5QRDkQOFabP)<%1bHN)iz<6Ma!2?rFukFDDlhaGZAXZuk7!S<( zfCmzVib10B;DO1>Pm?l-^w~wqc$4(l)FU68l86@p2Hh)|1nO2kHXJ#@aV)}dA&bWr zhj<+2K!C;3YZ3&9cx*V(MSl8FwqN%q8xaPJWl|U-G=XE;NGq>kWyyAgA;OiLK9(J@ zSHrs?3>KF(#JEI|-IbLk+p=(JrnJQk*y2Xo;snj=Wp6N%ptFqTARnOYf^s>w3lA*U zwC%!!wtV7c$~q&KpFq0+Dh=pk5ZQY}1Na7!16e5x%q9yI%Am5)h%%@wG}1|pG{Vt@ zMsi8=|6s0nsADvHJn4EJqi-+7tx0D`+uKX=yEpSLLQqMykS;3(C~quu31%SsQkr1q z(gZ@7cO*>J7>$FNymLD3sN|Q@r<1O#=MZY^&AdmYH=*WA zaL<#Ie6EHzVxY8Nx|eD9eC4i{?v2vDT)P)2cS^eDB3xQQZs<^zyGwGDyBc@bCBaSZ zYTR9y1UI>>ad$~>^nFtA=s_COIXR}V?UOBPgAX>4cV4vXlZ&*sk-YPxO`lw>y-nm@ zAicWhDDS{EL2P=C5)WJx%%qcT=r(*lB*hce4fazzHgq zg*N$(-pxhIrbn4~yqk-aP4{B(OalhbRBiA~sRmEhmv{QG^fZTq=|NihOH?Vgvadl7 z;9$dG4VkG}Y-3-eRQ_P&U@e)c-sfuFz9uR8!KT3!nW^OGQZ8*hpo4j8>t7Y8dVlt? z*!upF*w()~PoBbu#n$(a?2qd6>U`xETi-tt+xk}*D7V=9e(^L9b+u|$xs8BTxs8@p zxs9w_rtcWHJn2l|F>ZO*nZ9$Q-o^Ol=k|LSd$f|`7Bo@LO(rG1g;Rn*du_vSosupRYFt-XaofO$|pE1RZzT|cTZ!21!v_-hwCv*fHsHU77oz4S<*LN34A8I$r~;c$N#JjbiuVz2 zhLb8-NVB|iYLR;Czm>l;ye#qJuYBsyeVi|Ud(H9L z2{4S@9{Q!?ux^Sz%zb=%MdJDO=~2zhu)-eg@CfZSYLJ2G7)K@ML}e z|F;ZypDI`+HyLl?tz4jAF4N0GY&YKgTRC69BHnFm^R(@I#x_^mrpPAV5;S;!sBAVK zUigVP*h0KFjV;8ZSJhO@baoB)M!m^s3S5IlQ?J=gg=?^x%4kYlgH={WQ=^4xinK6I zl@_Kc)54@W>FTfunl6@_=DV}k7Sek|^zKqY9zLWFOM7rVZXX+>?(jZ>jwC)6xi=d5 zKNRUut4Y>-QPLtuF*aB)}xE8PNB9tuzsNtmR@VyLl1 zs*&r?o(;>i%)%I_w$cr^m2Swbbi+Qjx00M}ac;83sZFk7Ho1n_ z1Ub^Bf#W}tV=eT$wacXXMmN(vt7wNc37;nSxLS|CDg0MZ$ zS{|nzo~_<^R^_aZ=7gSS$Bjqi+*ggKOlYCU=1C~eO2xA_%7Yx~d3M}*1kcy1)h2jC zk6oMKfoF~4`E-;g^gKJRJfz_=Xt>;H*ptqt(q3OWCggic$e3GqNp7kb?kyraDyfxi zyLIhW_B}IjQ_}#q-8MIM9=fA4Tih}`s(CL=0oip#BlL_)bdIdRj9Sf%UQA~fq`gx! zog*=~Rz+_b+>eRu=xFq=#N4_UEBjM3aFZCww%s;2DG|D(~ir9V7{1L?i4vNEJIGIuyGOjS-!TUB{jod(m}7BkW#u9XcX9AiIuegr1Q&NAALm z?xqcVYUs{9kEe5I=VMWNm;aX#8*pGuR;Zcs+m zR|eT%nCV8Gbj|SG+yV3n#CYfkEw)t1@? z4<}ty@y}4PihZYgtR%UDs((gRQ!vVj0?UG`0wXpG9L8F}RQ)Pce-BlkJhk*lJyk#a zCvLXYbG`9DQ!D*d{4Qj0e#nUFctqE@6(P@P~Bm65Nz%K!eU*`)yt(2_ccOXpF z8iW)?VMS;Rd5=uahnL2)C&bNN)Ti^vCu#p+TLta)Fwt`A%(gNTJ!HPEM0=Yg z>CKRHx;^IX(oXf>H@WZn{b(w^qkT=i?H%>YY~c@?AB<)9W+p;nr-xwophBj9t@=Pn{-4OWE4 zP;*E6&ej>`9`WfsHFx;Fw4wjI(9qx^rqN$O&NBk9Y zhxZGy>~QW8pXL>FzZY}Q%DJ~3X%cgP40CU+Xr87jBA|IRLMtF54eW>@T)QS%lSrplg;T#_cZi0Lj9hm zo=h;^(~J+50=H*QOKbk&iS$I1=XI{$kFPFIWNI@#bJoLpK0VP;EFm+4=lh99^7qU+ z-~1E$c(tdgc%DdBgXBJt+!iFqLy8~)z6^4SW_{~lu05abYbtu@Gr@7BHm`0frq4Io ze_9YTk?w1lnlF3}=dC~fp@)#x(APNC24~CpM)PN)+59=*IMLike0{RbiA=GFYP=6M z-j5nvE_=bwr*_iU#anL6!%VS!IV+4fk_Y4s*0$qo=H6}k?YDcEH|P*~fDppHAGlM% z^`BbnJ2hTk!&e%;bNIql=jy~cf`jFHbKLR_mOd8rZ}@aCYHB>vj8C>(=fv&JN9L1# zUfkaB*G>$f;iHVLrW-SXbGhZEuoasvP*pxd#Jn{|F>eQJf^?Fjjv<3A8J2S zx`VZ(@8V}WC-H^vrh4bzbziRc?_L+r>%bSMx8aM^_&B*T@9EZc{?2vS^?24+^`&gh zhObc5w=VJB@4<3n>}8xM#5_RUyZnD31pgKB?{^H^*znY*u}uKl0s8i0xo6hF*=L4b z@m0`H`X=?665bxQVBZq3-<>_#H>+bHyTSi}uu6l-e$C3BM&tG3Bfoe)zSSMnw440j zU61_V!v815Ewciw04u->umY?AE5Hh{0;~WlzzVPetN<&(3a|pK04u->umY?AE5Hh{ z0;~WlzzVPetN<&(3a|pK04u->umY?AE5Hh{0;~WlzzVPetN<&(3a|pK04u->umY?A zE5Hh{0;~WlzzVPetN<&(3a|pK04u->umY?AE5Hh{0;~WlzzVPetN<&(3a|pK04u-> zumY?AE5Hh{0;~WlzzVPetN<&(3a|pK04u->umY?AE5Hh{0;~WlzzVPetN<&(3a|pK z04u->umY?AE5Hh{0;~WlzzVPetN<&(3a|pK04u->umY?AE5Hh{0;~WlzzVPetN<&( z3a|pK04u->umY?AE5Hh{0;~WlzzVPetN<&(3a|pK04u->umY?AE5Hh{0;~WlzzVPe ztN<&(3a|pK04u->umY?AE5Hh{0;~WlzzVPetN<&(3a|pK04u->{9h^X%DV5Y`=@pP E3ya{&@Bjb+ diff --git a/src/test/kotlin/6502_functional_tests/bin_files/6502_functional_test.lst b/src/test/kotlin/6502_functional_tests/bin_files/6502_functional_test.lst index d178888..ca5fd45 100644 --- a/src/test/kotlin/6502_functional_tests/bin_files/6502_functional_test.lst +++ b/src/test/kotlin/6502_functional_tests/bin_files/6502_functional_test.lst @@ -1,11 +1,11 @@ AS65 Assembler for R6502 [1.42]. Copyright 1994-2007, Frank A. Kingswood Page 1 ---------------------------------------------------- 6502_functional_test.a65 ---------------------------------------------------- -6104 lines read, no errors in pass 1. +6108 lines read, no errors in pass 1. ; ; 6 5 0 2 F U N C T I O N A L T E S T ; - ; Copyright (C) 2012-2015 Klaus Dormann + ; Copyright (C) 2012-2020 Klaus Dormann ; ; This program is free software: you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by @@ -25,10 +25,11 @@ AS65 Assembler for R6502 [1.42]. Copyright 1994-2007, Frank A. Kingswood ; addressing modes with focus on propper setting of the processor status ; register bits. ; - ; version 04-dec-2017 + ; version 05-jan-2020 ; contact info at http://2m5.de or email K@2m5.de ; - ; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/ + ; assembled with AS65 written by Frank A. Kingswood + ; The assembler as65_142.zip can be obtained from my GitHub repository ; command line switches: -l -m -s2 -w -h0 ; | | | | no page headers in listing ; | | | wide listing (133 char/col) @@ -80,7 +81,8 @@ AS65 Assembler for R6502 [1.42]. Copyright 1994-2007, Frank A. Kingswood ; 04-dec-2017 fixed BRK only tested with interrupts enabled ; added option to skip the remainder of a failing test ; in report.i65 - + ; 05-jan-2020 fixed shifts not testing zero result and flag when last 1-bit + ; is shifted out ; C O N F I G U R A T I O N @@ -100,17 +102,17 @@ AS65 Assembler for R6502 [1.42]. Copyright 1994-2007, Frank A. Kingswood 0003 = I_flag = 3 ;configure memory - try to stay away from memory used by the system - ;zero_page memory start address, $50 (80) consecutive Bytes required + ;zero_page memory start address, $52 (82) consecutive Bytes required ; add 2 if I_flag = 2 000a = zero_page = $a - ;data_segment memory start address, $6A (106) consecutive Bytes required + ;data_segment memory start address, $7B (123) consecutive Bytes required 0200 = data_segment = $200 if (data_segment & $ff) != 0 ERROR ERROR ERROR low byte of data_segment MUST be $00 !! endif - ;code_segment memory start address, 13kB of consecutive space required + ;code_segment memory start address, 13.1kB of consecutive space required ; add 2.5 kB if I_flag = 2 0400 = code_segment = $400 @@ -616,9 +618,7 @@ ffff = ram_top = -1 else bss ;uninitialized segment, copy of data at end of code! endif - ; org zero_page -0000 = org 0 ;edited to provide binaries loading from 0 -0000 : 00000000000000.. ds zero_page +000a = org zero_page ;break test interrupt save 000a : 00 irq_a ds 1 ;a register 000b : 00 irq_x ds 1 ;x register @@ -627,7 +627,7 @@ ffff = ram_top = -1 flag_I_on ds 1 ;or mask to load flags flag_I_off ds 1 ;and mask to load flags endif -000c : zpt ;5 bytes store/modify test area +000c : zpt ;6 bytes store/modify test area ;add/subtract operand generation and result/flag prediction 000c : 00 adfc ds 1 ;carry flag before op 000d : 00 ad1 ds 1 ;operand 1 - accumulator @@ -637,63 +637,64 @@ ffff = ram_top = -1 0011 : 00 adrf ds 1 ;expected flags NV0000ZC (only binary mode) 0012 : 00 sb2 ds 1 ;operand 2 complemented for subtract 0013 : zp_bss -0013 : c3824100 zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR -0017 : 7f zp7f db $7f ;test pattern for compare +0013 : 8001 zps db $80,1 ;additional shift pattern to test zero result & flag +0015 : c3824100 zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +0019 : 7f zp7f db $7f ;test pattern for compare ;logical zeropage operands -0018 : 001f7180 zpOR db 0,$1f,$71,$80 ;test pattern for OR -001c : 0fff7f80 zpAN db $0f,$ff,$7f,$80 ;test pattern for AND -0020 : ff0f8f8f zpEO db $ff,$0f,$8f,$8f ;test pattern for EOR +001a : 001f7180 zpOR db 0,$1f,$71,$80 ;test pattern for OR +001e : 0fff7f80 zpAN db $0f,$ff,$7f,$80 ;test pattern for AND +0022 : ff0f8f8f zpEO db $ff,$0f,$8f,$8f ;test pattern for EOR ;indirect addressing pointers -0024 : 1702 ind1 dw abs1 ;indirect pointer to pattern in absolute memory -0026 : 1802 dw abs1+1 -0028 : 1902 dw abs1+2 -002a : 1a02 dw abs1+3 -002c : 1b02 dw abs7f -002e : 1f01 inw1 dw abs1-$f8 ;indirect pointer for wrap-test pattern -0030 : 0302 indt dw abst ;indirect pointer to store area in absolute memory -0032 : 0402 dw abst+1 -0034 : 0502 dw abst+2 -0036 : 0602 dw abst+3 -0038 : 0b01 inwt dw abst-$f8 ;indirect pointer for wrap-test store -003a : 4e02 indAN dw absAN ;indirect pointer to AND pattern in absolute memory -003c : 4f02 dw absAN+1 -003e : 5002 dw absAN+2 -0040 : 5102 dw absAN+3 -0042 : 5202 indEO dw absEO ;indirect pointer to EOR pattern in absolute memory -0044 : 5302 dw absEO+1 -0046 : 5402 dw absEO+2 -0048 : 5502 dw absEO+3 -004a : 4a02 indOR dw absOR ;indirect pointer to OR pattern in absolute memory -004c : 4b02 dw absOR+1 -004e : 4c02 dw absOR+2 -0050 : 4d02 dw absOR+3 +0026 : 1802 ind1 dw abs1 ;indirect pointer to pattern in absolute memory +0028 : 1902 dw abs1+1 +002a : 1a02 dw abs1+2 +002c : 1b02 dw abs1+3 +002e : 1c02 dw abs7f +0030 : 2001 inw1 dw abs1-$f8 ;indirect pointer for wrap-test pattern +0032 : 0302 indt dw abst ;indirect pointer to store area in absolute memory +0034 : 0402 dw abst+1 +0036 : 0502 dw abst+2 +0038 : 0602 dw abst+3 +003a : 0b01 inwt dw abst-$f8 ;indirect pointer for wrap-test store +003c : 5f02 indAN dw absAN ;indirect pointer to AND pattern in absolute memory +003e : 6002 dw absAN+1 +0040 : 6102 dw absAN+2 +0042 : 6202 dw absAN+3 +0044 : 6302 indEO dw absEO ;indirect pointer to EOR pattern in absolute memory +0046 : 6402 dw absEO+1 +0048 : 6502 dw absEO+2 +004a : 6602 dw absEO+3 +004c : 5b02 indOR dw absOR ;indirect pointer to OR pattern in absolute memory +004e : 5c02 dw absOR+1 +0050 : 5d02 dw absOR+2 +0052 : 5e02 dw absOR+3 ;add/subtract indirect pointers -0052 : 0302 adi2 dw ada2 ;indirect pointer to operand 2 in absolute memory -0054 : 0402 sbi2 dw sba2 ;indirect pointer to complemented operand 2 (SBC) -0056 : 0401 adiy2 dw ada2-$ff ;with offset for indirect indexed -0058 : 0501 sbiy2 dw sba2-$ff -005a : zp_bss_end +0054 : 0302 adi2 dw ada2 ;indirect pointer to operand 2 in absolute memory +0056 : 0402 sbi2 dw sba2 ;indirect pointer to complemented operand 2 (SBC) +0058 : 0401 adiy2 dw ada2-$ff ;with offset for indirect indexed +005a : 0501 sbiy2 dw sba2-$ff +005c : zp_bss_end 0200 = org data_segment 0200 : 00 test_case ds 1 ;current test number 0201 : 0000 ram_chksm ds 2 ;checksum for RAM integrity test ;add/subtract operand copy - abs tests write area -0203 : abst ;5 bytes store/modify test area +0203 : abst ;6 bytes store/modify test area 0203 : 00 ada2 ds 1 ;operand 2 0204 : 00 sba2 ds 1 ;operand 2 complemented for subtract -0205 : 000000 ds 3 ;fill remaining bytes -0208 : data_bss +0205 : 00000000 ds 4 ;fill remaining bytes +0209 : data_bss if load_data_direct = 1 -0208 : 2900 ex_andi and #0 ;execute immediate opcodes -020a : 60 rts -020b : 4900 ex_eori eor #0 ;execute immediate opcodes -020d : 60 rts -020e : 0900 ex_orai ora #0 ;execute immediate opcodes -0210 : 60 rts -0211 : 6900 ex_adci adc #0 ;execute immediate opcodes -0213 : 60 rts -0214 : e900 ex_sbci sbc #0 ;execute immediate opcodes -0216 : 60 rts +0209 : 2900 ex_andi and #0 ;execute immediate opcodes +020b : 60 rts +020c : 4900 ex_eori eor #0 ;execute immediate opcodes +020e : 60 rts +020f : 0900 ex_orai ora #0 ;execute immediate opcodes +0211 : 60 rts +0212 : 6900 ex_adci adc #0 ;execute immediate opcodes +0214 : 60 rts +0215 : e900 ex_sbci sbc #0 ;execute immediate opcodes +0217 : 60 rts else ex_andi ds 3 ex_eori ds 3 @@ -701,38 +702,39 @@ ffff = ram_top = -1 ex_adci ds 3 ex_sbci ds 3 endif -0217 : c3824100 abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR -021b : 7f abs7f db $7f ;test pattern for compare + ;zps db $80,1 ;additional shift patterns test zero result & flag +0218 : c3824100 abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +021c : 7f abs7f db $7f ;test pattern for compare ;loads -021c : 80800002 fLDx db fn,fn,0,fz ;expected flags for load +021d : 80800002 fLDx db fn,fn,0,fz ;expected flags for load ;shifts -0220 : rASL ;expected result ASL & ROL -carry -0220 : 86048200 rROL db $86,$04,$82,0 ; " -0224 : 87058301 rROLc db $87,$05,$83,1 ;expected result ROL +carry -0228 : rLSR ;expected result LSR & ROR -carry -0228 : 61412000 rROR db $61,$41,$20,0 ; " -022c : e1c1a080 rRORc db $e1,$c1,$a0,$80 ;expected result ROR +carry -0230 : fASL ;expected flags for shifts -0230 : 81018002 fROL db fnc,fc,fn,fz ;no carry in -0234 : 81018000 fROLc db fnc,fc,fn,0 ;carry in -0238 : fLSR -0238 : 01000102 fROR db fc,0,fc,fz ;no carry in -023c : 81808180 fRORc db fnc,fn,fnc,fn ;carry in +0221 : rASL ;expected result ASL & ROL -carry +0221 : 000286048200 rROL db 0,2,$86,$04,$82,0 +0227 : 010387058301 rROLc db 1,3,$87,$05,$83,1 ;expected result ROL +carry +022d : rLSR ;expected result LSR & ROR -carry +022d : 400061412000 rROR db $40,0,$61,$41,$20,0 +0233 : c080e1c1a080 rRORc db $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry +0239 : fASL ;expected flags for shifts +0239 : 030081018002 fROL db fzc,0,fnc,fc,fn,fz ;no carry in +023f : 010081018000 fROLc db fc,0,fnc,fc,fn,0 ;carry in +0245 : fLSR +0245 : 000301000102 fROR db 0,fzc,fc,0,fc,fz ;no carry in +024b : 808181808180 fRORc db fn,fnc,fnc,fn,fnc,fn ;carry in ;increments (decrements) -0240 : 7f80ff0001 rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC -0245 : 0080800200 fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC +0251 : 7f80ff0001 rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC +0256 : 0080800200 fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC ;logical memory operand -024a : 001f7180 absOR db 0,$1f,$71,$80 ;test pattern for OR -024e : 0fff7f80 absAN db $0f,$ff,$7f,$80 ;test pattern for AND -0252 : ff0f8f8f absEO db $ff,$0f,$8f,$8f ;test pattern for EOR +025b : 001f7180 absOR db 0,$1f,$71,$80 ;test pattern for OR +025f : 0fff7f80 absAN db $0f,$ff,$7f,$80 ;test pattern for AND +0263 : ff0f8f8f absEO db $ff,$0f,$8f,$8f ;test pattern for EOR ;logical accu operand -0256 : 00f11f00 absORa db 0,$f1,$1f,0 ;test pattern for OR -025a : f0ffffff absANa db $f0,$ff,$ff,$ff ;test pattern for AND -025e : fff0f00f absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR +0267 : 00f11f00 absORa db 0,$f1,$1f,0 ;test pattern for OR +026b : f0ffffff absANa db $f0,$ff,$ff,$ff ;test pattern for AND +026f : fff0f00f absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR ;logical results -0262 : 00ff7f80 absrlo db 0,$ff,$7f,$80 -0266 : 02800080 absflo db fz,fn,0,fn -026a : data_bss_end +0273 : 00ff7f80 absrlo db 0,$ff,$7f,$80 +0277 : 02800080 absflo db fz,fn,0,fn +027b : data_bss_end code @@ -3930,7 +3932,7 @@ ffff = ram_top = -1 0e56 : 48 > pha ;use stack to load status 0e57 : 28 > plp -0e58 : b613 ldx zp1,y +0e58 : b615 ldx zp1,y 0e5a : 08 php ;test stores do not alter flags 0e5b : 8a txa 0e5c : 49c3 eor #$c3 @@ -3938,7 +3940,7 @@ ffff = ram_top = -1 0e5f : 990302 sta abst,y 0e62 : 08 php ;flags after load/store sequence 0e63 : 49c3 eor #$c3 -0e65 : d91702 cmp abs1,y ;test result +0e65 : d91802 cmp abs1,y ;test result trap_ne 0e68 : d0fe > bne * ;failed not equal (non zero) @@ -3946,7 +3948,7 @@ ffff = ram_top = -1 eor_flag 0 0e6b : 4930 > eor #0|fao ;invert expected flags + always on bits -0e6d : d91c02 cmp fLDx,y ;test flags +0e6d : d91d02 cmp fLDx,y ;test flags trap_ne 0e70 : d0fe > bne * ;failed not equal (non zero) @@ -3962,7 +3964,7 @@ ffff = ram_top = -1 0e79 : 48 > pha ;use stack to load status 0e7a : 28 > plp -0e7b : b613 ldx zp1,y +0e7b : b615 ldx zp1,y 0e7d : 08 php ;test stores do not alter flags 0e7e : 8a txa 0e7f : 49c3 eor #$c3 @@ -3970,7 +3972,7 @@ ffff = ram_top = -1 0e82 : 990302 sta abst,y 0e85 : 08 php ;flags after load/store sequence 0e86 : 49c3 eor #$c3 -0e88 : d91702 cmp abs1,y ;test result +0e88 : d91802 cmp abs1,y ;test result trap_ne 0e8b : d0fe > bne * ;failed not equal (non zero) @@ -3978,7 +3980,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 0e8e : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -0e90 : d91c02 cmp fLDx,y ;test flags +0e90 : d91d02 cmp fLDx,y ;test flags trap_ne 0e93 : d0fe > bne * ;failed not equal (non zero) @@ -3994,7 +3996,7 @@ ffff = ram_top = -1 0e9c : 48 > pha ;use stack to load status 0e9d : 28 > plp -0e9e : be1702 ldx abs1,y +0e9e : be1802 ldx abs1,y 0ea1 : 08 php ;test stores do not alter flags 0ea2 : 8a txa 0ea3 : 49c3 eor #$c3 @@ -4003,7 +4005,7 @@ ffff = ram_top = -1 0ea7 : 960c stx zpt,y 0ea9 : 08 php ;flags after load/store sequence 0eaa : 49c3 eor #$c3 -0eac : d91300 cmp zp1,y ;test result +0eac : d91500 cmp zp1,y ;test result trap_ne 0eaf : d0fe > bne * ;failed not equal (non zero) @@ -4011,7 +4013,7 @@ ffff = ram_top = -1 eor_flag 0 0eb2 : 4930 > eor #0|fao ;invert expected flags + always on bits -0eb4 : d91c02 cmp fLDx,y ;test flags +0eb4 : d91d02 cmp fLDx,y ;test flags trap_ne 0eb7 : d0fe > bne * ;failed not equal (non zero) @@ -4027,7 +4029,7 @@ ffff = ram_top = -1 0ec0 : 48 > pha ;use stack to load status 0ec1 : 28 > plp -0ec2 : be1702 ldx abs1,y +0ec2 : be1802 ldx abs1,y 0ec5 : 08 php ;test stores do not alter flags 0ec6 : 8a txa 0ec7 : 49c3 eor #$c3 @@ -4036,7 +4038,7 @@ ffff = ram_top = -1 0ecb : 960c stx zpt,y 0ecd : 08 php ;flags after load/store sequence 0ece : 49c3 eor #$c3 -0ed0 : d91300 cmp zp1,y ;test result +0ed0 : d91500 cmp zp1,y ;test result trap_ne 0ed3 : d0fe > bne * ;failed not equal (non zero) @@ -4044,7 +4046,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 0ed6 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -0ed8 : d91c02 cmp fLDx,y ;test flags +0ed8 : d91d02 cmp fLDx,y ;test flags trap_ne 0edb : d0fe > bne * ;failed not equal (non zero) @@ -4055,14 +4057,14 @@ ffff = ram_top = -1 0ee2 : a200 ldx #0 0ee4 : b90c00 tstx lda zpt,y 0ee7 : 49c3 eor #$c3 -0ee9 : d91300 cmp zp1,y +0ee9 : d91500 cmp zp1,y trap_ne ;store to zp data 0eec : d0fe > bne * ;failed not equal (non zero) 0eee : 960c stx zpt,y ;clear 0ef0 : b90302 lda abst,y 0ef3 : 49c3 eor #$c3 -0ef5 : d91702 cmp abs1,y +0ef5 : d91802 cmp abs1,y trap_ne ;store to abs data 0ef8 : d0fe > bne * ;failed not equal (non zero) @@ -4084,14 +4086,14 @@ ffff = ram_top = -1 ; indexed wraparound test (only zp should wrap) 0f0d : a0fd ldy #3+$fa -0f0f : b619 tldx4 ldx zp1-$fa&$ff,y ;wrap on indexed zp +0f0f : b61b tldx4 ldx zp1-$fa&$ff,y ;wrap on indexed zp 0f11 : 8a txa 0f12 : 990901 sta abst-$fa,y ;no STX abs,y! 0f15 : 88 dey 0f16 : c0fa cpy #$fa 0f18 : b0f5 bcs tldx4 0f1a : a0fd ldy #3+$fa -0f1c : be1d01 tldx5 ldx abs1-$fa,y ;no wrap on indexed abs +0f1c : be1e01 tldx5 ldx abs1-$fa,y ;no wrap on indexed abs 0f1f : 9612 stx zpt-$fa&$ff,y 0f21 : 88 dey 0f22 : c0fa cpy #$fa @@ -4099,13 +4101,13 @@ ffff = ram_top = -1 0f26 : a003 ldy #3 ;testing wraparound result 0f28 : a200 ldx #0 0f2a : b90c00 tstx1 lda zpt,y -0f2d : d91300 cmp zp1,y +0f2d : d91500 cmp zp1,y trap_ne ;store to zp data 0f30 : d0fe > bne * ;failed not equal (non zero) 0f32 : 960c stx zpt,y ;clear 0f34 : b90302 lda abst,y -0f37 : d91702 cmp abs1,y +0f37 : d91802 cmp abs1,y trap_ne ;store to abs data 0f3a : d0fe > bne * ;failed not equal (non zero) @@ -4135,7 +4137,7 @@ ffff = ram_top = -1 0f53 : 48 > pha ;use stack to load status 0f54 : 28 > plp -0f55 : b413 ldy zp1,x +0f55 : b415 ldy zp1,x 0f57 : 08 php ;test stores do not alter flags 0f58 : 98 tya 0f59 : 49c3 eor #$c3 @@ -4143,7 +4145,7 @@ ffff = ram_top = -1 0f5c : 9d0302 sta abst,x 0f5f : 08 php ;flags after load/store sequence 0f60 : 49c3 eor #$c3 -0f62 : dd1702 cmp abs1,x ;test result +0f62 : dd1802 cmp abs1,x ;test result trap_ne 0f65 : d0fe > bne * ;failed not equal (non zero) @@ -4151,7 +4153,7 @@ ffff = ram_top = -1 eor_flag 0 0f68 : 4930 > eor #0|fao ;invert expected flags + always on bits -0f6a : dd1c02 cmp fLDx,x ;test flags +0f6a : dd1d02 cmp fLDx,x ;test flags trap_ne 0f6d : d0fe > bne * ;failed not equal (non zero) @@ -4167,7 +4169,7 @@ ffff = ram_top = -1 0f76 : 48 > pha ;use stack to load status 0f77 : 28 > plp -0f78 : b413 ldy zp1,x +0f78 : b415 ldy zp1,x 0f7a : 08 php ;test stores do not alter flags 0f7b : 98 tya 0f7c : 49c3 eor #$c3 @@ -4175,7 +4177,7 @@ ffff = ram_top = -1 0f7f : 9d0302 sta abst,x 0f82 : 08 php ;flags after load/store sequence 0f83 : 49c3 eor #$c3 -0f85 : dd1702 cmp abs1,x ;test result +0f85 : dd1802 cmp abs1,x ;test result trap_ne 0f88 : d0fe > bne * ;failed not equal (non zero) @@ -4183,7 +4185,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 0f8b : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -0f8d : dd1c02 cmp fLDx,x ;test flags +0f8d : dd1d02 cmp fLDx,x ;test flags trap_ne 0f90 : d0fe > bne * ;failed not equal (non zero) @@ -4199,7 +4201,7 @@ ffff = ram_top = -1 0f99 : 48 > pha ;use stack to load status 0f9a : 28 > plp -0f9b : bc1702 ldy abs1,x +0f9b : bc1802 ldy abs1,x 0f9e : 08 php ;test stores do not alter flags 0f9f : 98 tya 0fa0 : 49c3 eor #$c3 @@ -4208,7 +4210,7 @@ ffff = ram_top = -1 0fa4 : 940c sty zpt,x 0fa6 : 08 php ;flags after load/store sequence 0fa7 : 49c3 eor #$c3 -0fa9 : d513 cmp zp1,x ;test result +0fa9 : d515 cmp zp1,x ;test result trap_ne 0fab : d0fe > bne * ;failed not equal (non zero) @@ -4216,7 +4218,7 @@ ffff = ram_top = -1 eor_flag 0 0fae : 4930 > eor #0|fao ;invert expected flags + always on bits -0fb0 : dd1c02 cmp fLDx,x ;test flags +0fb0 : dd1d02 cmp fLDx,x ;test flags trap_ne 0fb3 : d0fe > bne * ;failed not equal (non zero) @@ -4232,7 +4234,7 @@ ffff = ram_top = -1 0fbc : 48 > pha ;use stack to load status 0fbd : 28 > plp -0fbe : bc1702 ldy abs1,x +0fbe : bc1802 ldy abs1,x 0fc1 : 08 php ;test stores do not alter flags 0fc2 : 98 tya 0fc3 : 49c3 eor #$c3 @@ -4241,7 +4243,7 @@ ffff = ram_top = -1 0fc7 : 940c sty zpt,x 0fc9 : 08 php ;flags after load/store sequence 0fca : 49c3 eor #$c3 -0fcc : d513 cmp zp1,x ;test result +0fcc : d515 cmp zp1,x ;test result trap_ne 0fce : d0fe > bne * ;failed not equal (non zero) @@ -4249,7 +4251,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 0fd1 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -0fd3 : dd1c02 cmp fLDx,x ;test flags +0fd3 : dd1d02 cmp fLDx,x ;test flags trap_ne 0fd6 : d0fe > bne * ;failed not equal (non zero) @@ -4260,14 +4262,14 @@ ffff = ram_top = -1 0fdd : a000 ldy #0 0fdf : b50c tsty lda zpt,x 0fe1 : 49c3 eor #$c3 -0fe3 : d513 cmp zp1,x +0fe3 : d515 cmp zp1,x trap_ne ;store to zp,x data 0fe5 : d0fe > bne * ;failed not equal (non zero) 0fe7 : 940c sty zpt,x ;clear 0fe9 : bd0302 lda abst,x 0fec : 49c3 eor #$c3 -0fee : dd1702 cmp abs1,x +0fee : dd1802 cmp abs1,x trap_ne ;store to abs,x data 0ff1 : d0fe > bne * ;failed not equal (non zero) @@ -4289,14 +4291,14 @@ ffff = ram_top = -1 ; indexed wraparound test (only zp should wrap) 1006 : a2fd ldx #3+$fa -1008 : b419 tldy4 ldy zp1-$fa&$ff,x ;wrap on indexed zp +1008 : b41b tldy4 ldy zp1-$fa&$ff,x ;wrap on indexed zp 100a : 98 tya 100b : 9d0901 sta abst-$fa,x ;no STX abs,x! 100e : ca dex 100f : e0fa cpx #$fa 1011 : b0f5 bcs tldy4 1013 : a2fd ldx #3+$fa -1015 : bc1d01 tldy5 ldy abs1-$fa,x ;no wrap on indexed abs +1015 : bc1e01 tldy5 ldy abs1-$fa,x ;no wrap on indexed abs 1018 : 9412 sty zpt-$fa&$ff,x 101a : ca dex 101b : e0fa cpx #$fa @@ -4304,13 +4306,13 @@ ffff = ram_top = -1 101f : a203 ldx #3 ;testing wraparound result 1021 : a000 ldy #0 1023 : b50c tsty1 lda zpt,x -1025 : d513 cmp zp1,x +1025 : d515 cmp zp1,x trap_ne ;store to zp,x data 1027 : d0fe > bne * ;failed not equal (non zero) 1029 : 940c sty zpt,x ;clear 102b : bd0302 lda abst,x -102e : dd1702 cmp abs1,x +102e : dd1802 cmp abs1,x trap_ne ;store to abs,x data 1031 : d0fe > bne * ;failed not equal (non zero) @@ -4338,7 +4340,7 @@ ffff = ram_top = -1 1048 : 48 > pha ;use stack to load status 1049 : 28 > plp -104a : a613 ldx zp1 +104a : a615 ldx zp1 104c : 08 php ;test stores do not alter flags 104d : 8a txa 104e : 49c3 eor #$c3 @@ -4356,7 +4358,7 @@ ffff = ram_top = -1 eor_flag 0 105e : 4930 > eor #0|fao ;invert expected flags + always on bits -1060 : cd1c02 cmp fLDx ;test flags +1060 : cd1d02 cmp fLDx ;test flags trap_ne 1063 : d0fe > bne * ;failed not equal (non zero) @@ -4367,7 +4369,7 @@ ffff = ram_top = -1 1067 : 48 > pha ;use stack to load status 1068 : 28 > plp -1069 : a614 ldx zp1+1 +1069 : a616 ldx zp1+1 106b : 08 php ;test stores do not alter flags 106c : 8a txa 106d : 49c3 eor #$c3 @@ -4385,7 +4387,7 @@ ffff = ram_top = -1 eor_flag 0 107d : 4930 > eor #0|fao ;invert expected flags + always on bits -107f : cd1d02 cmp fLDx+1 ;test flags +107f : cd1e02 cmp fLDx+1 ;test flags trap_ne 1082 : d0fe > bne * ;failed not equal (non zero) @@ -4396,7 +4398,7 @@ ffff = ram_top = -1 1086 : 48 > pha ;use stack to load status 1087 : 28 > plp -1088 : a615 ldx zp1+2 +1088 : a617 ldx zp1+2 108a : 08 php ;test stores do not alter flags 108b : 8a txa 108c : 49c3 eor #$c3 @@ -4414,7 +4416,7 @@ ffff = ram_top = -1 eor_flag 0 109c : 4930 > eor #0|fao ;invert expected flags + always on bits -109e : cd1e02 cmp fLDx+2 ;test flags +109e : cd1f02 cmp fLDx+2 ;test flags trap_ne 10a1 : d0fe > bne * ;failed not equal (non zero) @@ -4425,7 +4427,7 @@ ffff = ram_top = -1 10a5 : 48 > pha ;use stack to load status 10a6 : 28 > plp -10a7 : a616 ldx zp1+3 +10a7 : a618 ldx zp1+3 10a9 : 08 php ;test stores do not alter flags 10aa : 8a txa 10ab : 49c3 eor #$c3 @@ -4443,7 +4445,7 @@ ffff = ram_top = -1 eor_flag 0 10bb : 4930 > eor #0|fao ;invert expected flags + always on bits -10bd : cd1f02 cmp fLDx+3 ;test flags +10bd : cd2002 cmp fLDx+3 ;test flags trap_ne 10c0 : d0fe > bne * ;failed not equal (non zero) @@ -4455,7 +4457,7 @@ ffff = ram_top = -1 10c4 : 48 > pha ;use stack to load status 10c5 : 28 > plp -10c6 : a613 ldx zp1 +10c6 : a615 ldx zp1 10c8 : 08 php ;test stores do not alter flags 10c9 : 8a txa 10ca : 49c3 eor #$c3 @@ -4473,7 +4475,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 10da : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -10dc : cd1c02 cmp fLDx ;test flags +10dc : cd1d02 cmp fLDx ;test flags trap_ne 10df : d0fe > bne * ;failed not equal (non zero) @@ -4484,7 +4486,7 @@ ffff = ram_top = -1 10e3 : 48 > pha ;use stack to load status 10e4 : 28 > plp -10e5 : a614 ldx zp1+1 +10e5 : a616 ldx zp1+1 10e7 : 08 php ;test stores do not alter flags 10e8 : 8a txa 10e9 : 49c3 eor #$c3 @@ -4502,7 +4504,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 10f9 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -10fb : cd1d02 cmp fLDx+1 ;test flags +10fb : cd1e02 cmp fLDx+1 ;test flags trap_ne 10fe : d0fe > bne * ;failed not equal (non zero) @@ -4513,7 +4515,7 @@ ffff = ram_top = -1 1102 : 48 > pha ;use stack to load status 1103 : 28 > plp -1104 : a615 ldx zp1+2 +1104 : a617 ldx zp1+2 1106 : 08 php ;test stores do not alter flags 1107 : 8a txa 1108 : 49c3 eor #$c3 @@ -4531,7 +4533,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1118 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -111a : cd1e02 cmp fLDx+2 ;test flags +111a : cd1f02 cmp fLDx+2 ;test flags trap_ne 111d : d0fe > bne * ;failed not equal (non zero) @@ -4542,7 +4544,7 @@ ffff = ram_top = -1 1121 : 48 > pha ;use stack to load status 1122 : 28 > plp -1123 : a616 ldx zp1+3 +1123 : a618 ldx zp1+3 1125 : 08 php ;test stores do not alter flags 1126 : 8a txa 1127 : 49c3 eor #$c3 @@ -4560,7 +4562,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1137 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1139 : cd1f02 cmp fLDx+3 ;test flags +1139 : cd2002 cmp fLDx+3 ;test flags trap_ne 113c : d0fe > bne * ;failed not equal (non zero) @@ -4572,7 +4574,7 @@ ffff = ram_top = -1 1140 : 48 > pha ;use stack to load status 1141 : 28 > plp -1142 : ae1702 ldx abs1 +1142 : ae1802 ldx abs1 1145 : 08 php ;test stores do not alter flags 1146 : 8a txa 1147 : 49c3 eor #$c3 @@ -4581,7 +4583,7 @@ ffff = ram_top = -1 114b : 860c stx zpt 114d : 08 php ;flags after load/store sequence 114e : 49c3 eor #$c3 -1150 : c513 cmp zp1 ;test result +1150 : c515 cmp zp1 ;test result trap_ne 1152 : d0fe > bne * ;failed not equal (non zero) @@ -4589,7 +4591,7 @@ ffff = ram_top = -1 eor_flag 0 1155 : 4930 > eor #0|fao ;invert expected flags + always on bits -1157 : cd1c02 cmp fLDx ;test flags +1157 : cd1d02 cmp fLDx ;test flags trap_ne 115a : d0fe > bne * ;failed not equal (non zero) @@ -4600,7 +4602,7 @@ ffff = ram_top = -1 115e : 48 > pha ;use stack to load status 115f : 28 > plp -1160 : ae1802 ldx abs1+1 +1160 : ae1902 ldx abs1+1 1163 : 08 php ;test stores do not alter flags 1164 : 8a txa 1165 : 49c3 eor #$c3 @@ -4609,7 +4611,7 @@ ffff = ram_top = -1 1169 : 860d stx zpt+1 116b : 08 php ;flags after load/store sequence 116c : 49c3 eor #$c3 -116e : c514 cmp zp1+1 ;test result +116e : c516 cmp zp1+1 ;test result trap_ne 1170 : d0fe > bne * ;failed not equal (non zero) @@ -4617,7 +4619,7 @@ ffff = ram_top = -1 eor_flag 0 1173 : 4930 > eor #0|fao ;invert expected flags + always on bits -1175 : cd1d02 cmp fLDx+1 ;test flags +1175 : cd1e02 cmp fLDx+1 ;test flags trap_ne 1178 : d0fe > bne * ;failed not equal (non zero) @@ -4628,7 +4630,7 @@ ffff = ram_top = -1 117c : 48 > pha ;use stack to load status 117d : 28 > plp -117e : ae1902 ldx abs1+2 +117e : ae1a02 ldx abs1+2 1181 : 08 php ;test stores do not alter flags 1182 : 8a txa 1183 : 49c3 eor #$c3 @@ -4637,7 +4639,7 @@ ffff = ram_top = -1 1187 : 860e stx zpt+2 1189 : 08 php ;flags after load/store sequence 118a : 49c3 eor #$c3 -118c : c515 cmp zp1+2 ;test result +118c : c517 cmp zp1+2 ;test result trap_ne 118e : d0fe > bne * ;failed not equal (non zero) @@ -4645,7 +4647,7 @@ ffff = ram_top = -1 eor_flag 0 1191 : 4930 > eor #0|fao ;invert expected flags + always on bits -1193 : cd1e02 cmp fLDx+2 ;test flags +1193 : cd1f02 cmp fLDx+2 ;test flags trap_ne 1196 : d0fe > bne * ;failed not equal (non zero) @@ -4656,7 +4658,7 @@ ffff = ram_top = -1 119a : 48 > pha ;use stack to load status 119b : 28 > plp -119c : ae1a02 ldx abs1+3 +119c : ae1b02 ldx abs1+3 119f : 08 php ;test stores do not alter flags 11a0 : 8a txa 11a1 : 49c3 eor #$c3 @@ -4665,7 +4667,7 @@ ffff = ram_top = -1 11a5 : 860f stx zpt+3 11a7 : 08 php ;flags after load/store sequence 11a8 : 49c3 eor #$c3 -11aa : c516 cmp zp1+3 ;test result +11aa : c518 cmp zp1+3 ;test result trap_ne 11ac : d0fe > bne * ;failed not equal (non zero) @@ -4673,7 +4675,7 @@ ffff = ram_top = -1 eor_flag 0 11af : 4930 > eor #0|fao ;invert expected flags + always on bits -11b1 : cd1f02 cmp fLDx+3 ;test flags +11b1 : cd2002 cmp fLDx+3 ;test flags trap_ne 11b4 : d0fe > bne * ;failed not equal (non zero) @@ -4685,7 +4687,7 @@ ffff = ram_top = -1 11b8 : 48 > pha ;use stack to load status 11b9 : 28 > plp -11ba : ae1702 ldx abs1 +11ba : ae1802 ldx abs1 11bd : 08 php ;test stores do not alter flags 11be : 8a txa 11bf : 49c3 eor #$c3 @@ -4695,7 +4697,7 @@ ffff = ram_top = -1 11c5 : 08 php ;flags after load/store sequence 11c6 : 49c3 eor #$c3 11c8 : aa tax -11c9 : e413 cpx zp1 ;test result +11c9 : e415 cpx zp1 ;test result trap_ne 11cb : d0fe > bne * ;failed not equal (non zero) @@ -4703,7 +4705,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 11ce : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -11d0 : cd1c02 cmp fLDx ;test flags +11d0 : cd1d02 cmp fLDx ;test flags trap_ne 11d3 : d0fe > bne * ;failed not equal (non zero) @@ -4714,7 +4716,7 @@ ffff = ram_top = -1 11d7 : 48 > pha ;use stack to load status 11d8 : 28 > plp -11d9 : ae1802 ldx abs1+1 +11d9 : ae1902 ldx abs1+1 11dc : 08 php ;test stores do not alter flags 11dd : 8a txa 11de : 49c3 eor #$c3 @@ -4724,7 +4726,7 @@ ffff = ram_top = -1 11e4 : 08 php ;flags after load/store sequence 11e5 : 49c3 eor #$c3 11e7 : aa tax -11e8 : e414 cpx zp1+1 ;test result +11e8 : e416 cpx zp1+1 ;test result trap_ne 11ea : d0fe > bne * ;failed not equal (non zero) @@ -4732,7 +4734,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 11ed : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -11ef : cd1d02 cmp fLDx+1 ;test flags +11ef : cd1e02 cmp fLDx+1 ;test flags trap_ne 11f2 : d0fe > bne * ;failed not equal (non zero) @@ -4743,7 +4745,7 @@ ffff = ram_top = -1 11f6 : 48 > pha ;use stack to load status 11f7 : 28 > plp -11f8 : ae1902 ldx abs1+2 +11f8 : ae1a02 ldx abs1+2 11fb : 08 php ;test stores do not alter flags 11fc : 8a txa 11fd : 49c3 eor #$c3 @@ -4753,7 +4755,7 @@ ffff = ram_top = -1 1203 : 08 php ;flags after load/store sequence 1204 : 49c3 eor #$c3 1206 : aa tax -1207 : e415 cpx zp1+2 ;test result +1207 : e417 cpx zp1+2 ;test result trap_ne 1209 : d0fe > bne * ;failed not equal (non zero) @@ -4761,7 +4763,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 120c : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -120e : cd1e02 cmp fLDx+2 ;test flags +120e : cd1f02 cmp fLDx+2 ;test flags trap_ne 1211 : d0fe > bne * ;failed not equal (non zero) @@ -4772,7 +4774,7 @@ ffff = ram_top = -1 1215 : 48 > pha ;use stack to load status 1216 : 28 > plp -1217 : ae1a02 ldx abs1+3 +1217 : ae1b02 ldx abs1+3 121a : 08 php ;test stores do not alter flags 121b : 8a txa 121c : 49c3 eor #$c3 @@ -4782,7 +4784,7 @@ ffff = ram_top = -1 1222 : 08 php ;flags after load/store sequence 1223 : 49c3 eor #$c3 1225 : aa tax -1226 : e416 cpx zp1+3 ;test result +1226 : e418 cpx zp1+3 ;test result trap_ne 1228 : d0fe > bne * ;failed not equal (non zero) @@ -4790,7 +4792,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 122b : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -122d : cd1f02 cmp fLDx+3 ;test flags +122d : cd2002 cmp fLDx+3 ;test flags trap_ne 1230 : d0fe > bne * ;failed not equal (non zero) @@ -4804,7 +4806,7 @@ ffff = ram_top = -1 1236 : a2c3 ldx #$c3 1238 : 08 php -1239 : ec1702 cpx abs1 ;test result +1239 : ec1802 cpx abs1 ;test result trap_ne 123c : d0fe > bne * ;failed not equal (non zero) @@ -4812,7 +4814,7 @@ ffff = ram_top = -1 eor_flag 0 123f : 4930 > eor #0|fao ;invert expected flags + always on bits -1241 : cd1c02 cmp fLDx ;test flags +1241 : cd1d02 cmp fLDx ;test flags trap_ne 1244 : d0fe > bne * ;failed not equal (non zero) @@ -4825,7 +4827,7 @@ ffff = ram_top = -1 124a : a282 ldx #$82 124c : 08 php -124d : ec1802 cpx abs1+1 ;test result +124d : ec1902 cpx abs1+1 ;test result trap_ne 1250 : d0fe > bne * ;failed not equal (non zero) @@ -4833,7 +4835,7 @@ ffff = ram_top = -1 eor_flag 0 1253 : 4930 > eor #0|fao ;invert expected flags + always on bits -1255 : cd1d02 cmp fLDx+1 ;test flags +1255 : cd1e02 cmp fLDx+1 ;test flags trap_ne 1258 : d0fe > bne * ;failed not equal (non zero) @@ -4846,7 +4848,7 @@ ffff = ram_top = -1 125e : a241 ldx #$41 1260 : 08 php -1261 : ec1902 cpx abs1+2 ;test result +1261 : ec1a02 cpx abs1+2 ;test result trap_ne 1264 : d0fe > bne * ;failed not equal (non zero) @@ -4854,7 +4856,7 @@ ffff = ram_top = -1 eor_flag 0 1267 : 4930 > eor #0|fao ;invert expected flags + always on bits -1269 : cd1e02 cmp fLDx+2 ;test flags +1269 : cd1f02 cmp fLDx+2 ;test flags trap_ne 126c : d0fe > bne * ;failed not equal (non zero) @@ -4867,7 +4869,7 @@ ffff = ram_top = -1 1272 : a200 ldx #0 1274 : 08 php -1275 : ec1a02 cpx abs1+3 ;test result +1275 : ec1b02 cpx abs1+3 ;test result trap_ne 1278 : d0fe > bne * ;failed not equal (non zero) @@ -4875,7 +4877,7 @@ ffff = ram_top = -1 eor_flag 0 127b : 4930 > eor #0|fao ;invert expected flags + always on bits -127d : cd1f02 cmp fLDx+3 ;test flags +127d : cd2002 cmp fLDx+3 ;test flags trap_ne 1280 : d0fe > bne * ;failed not equal (non zero) @@ -4889,7 +4891,7 @@ ffff = ram_top = -1 1286 : a2c3 ldx #$c3 1288 : 08 php -1289 : ec1702 cpx abs1 ;test result +1289 : ec1802 cpx abs1 ;test result trap_ne 128c : d0fe > bne * ;failed not equal (non zero) @@ -4897,7 +4899,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 128f : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1291 : cd1c02 cmp fLDx ;test flags +1291 : cd1d02 cmp fLDx ;test flags trap_ne 1294 : d0fe > bne * ;failed not equal (non zero) @@ -4910,7 +4912,7 @@ ffff = ram_top = -1 129a : a282 ldx #$82 129c : 08 php -129d : ec1802 cpx abs1+1 ;test result +129d : ec1902 cpx abs1+1 ;test result trap_ne 12a0 : d0fe > bne * ;failed not equal (non zero) @@ -4918,7 +4920,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 12a3 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -12a5 : cd1d02 cmp fLDx+1 ;test flags +12a5 : cd1e02 cmp fLDx+1 ;test flags trap_ne 12a8 : d0fe > bne * ;failed not equal (non zero) @@ -4931,7 +4933,7 @@ ffff = ram_top = -1 12ae : a241 ldx #$41 12b0 : 08 php -12b1 : ec1902 cpx abs1+2 ;test result +12b1 : ec1a02 cpx abs1+2 ;test result trap_ne 12b4 : d0fe > bne * ;failed not equal (non zero) @@ -4939,7 +4941,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 12b7 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -12b9 : cd1e02 cmp fLDx+2 ;test flags +12b9 : cd1f02 cmp fLDx+2 ;test flags trap_ne 12bc : d0fe > bne * ;failed not equal (non zero) @@ -4952,7 +4954,7 @@ ffff = ram_top = -1 12c2 : a200 ldx #0 12c4 : 08 php -12c5 : ec1a02 cpx abs1+3 ;test result +12c5 : ec1b02 cpx abs1+3 ;test result trap_ne 12c8 : d0fe > bne * ;failed not equal (non zero) @@ -4960,7 +4962,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 12cb : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -12cd : cd1f02 cmp fLDx+3 ;test flags +12cd : cd2002 cmp fLDx+3 ;test flags trap_ne 12d0 : d0fe > bne * ;failed not equal (non zero) @@ -4968,56 +4970,56 @@ ffff = ram_top = -1 12d2 : a200 ldx #0 12d4 : a50c lda zpt 12d6 : 49c3 eor #$c3 -12d8 : c513 cmp zp1 +12d8 : c515 cmp zp1 trap_ne ;store to zp data 12da : d0fe > bne * ;failed not equal (non zero) 12dc : 860c stx zpt ;clear 12de : ad0302 lda abst 12e1 : 49c3 eor #$c3 -12e3 : cd1702 cmp abs1 +12e3 : cd1802 cmp abs1 trap_ne ;store to abs data 12e6 : d0fe > bne * ;failed not equal (non zero) 12e8 : 8e0302 stx abst ;clear 12eb : a50d lda zpt+1 12ed : 49c3 eor #$c3 -12ef : c514 cmp zp1+1 +12ef : c516 cmp zp1+1 trap_ne ;store to zp data 12f1 : d0fe > bne * ;failed not equal (non zero) 12f3 : 860d stx zpt+1 ;clear 12f5 : ad0402 lda abst+1 12f8 : 49c3 eor #$c3 -12fa : cd1802 cmp abs1+1 +12fa : cd1902 cmp abs1+1 trap_ne ;store to abs data 12fd : d0fe > bne * ;failed not equal (non zero) 12ff : 8e0402 stx abst+1 ;clear 1302 : a50e lda zpt+2 1304 : 49c3 eor #$c3 -1306 : c515 cmp zp1+2 +1306 : c517 cmp zp1+2 trap_ne ;store to zp data 1308 : d0fe > bne * ;failed not equal (non zero) 130a : 860e stx zpt+2 ;clear 130c : ad0502 lda abst+2 130f : 49c3 eor #$c3 -1311 : cd1902 cmp abs1+2 +1311 : cd1a02 cmp abs1+2 trap_ne ;store to abs data 1314 : d0fe > bne * ;failed not equal (non zero) 1316 : 8e0502 stx abst+2 ;clear 1319 : a50f lda zpt+3 131b : 49c3 eor #$c3 -131d : c516 cmp zp1+3 +131d : c518 cmp zp1+3 trap_ne ;store to zp data 131f : d0fe > bne * ;failed not equal (non zero) 1321 : 860f stx zpt+3 ;clear 1323 : ad0602 lda abst+3 1326 : 49c3 eor #$c3 -1328 : cd1a02 cmp abs1+3 +1328 : cd1b02 cmp abs1+3 trap_ne ;store to abs data 132b : d0fe > bne * ;failed not equal (non zero) @@ -5042,7 +5044,7 @@ ffff = ram_top = -1 133e : 48 > pha ;use stack to load status 133f : 28 > plp -1340 : a413 ldy zp1 +1340 : a415 ldy zp1 1342 : 08 php ;test stores do not alter flags 1343 : 98 tya 1344 : 49c3 eor #$c3 @@ -5060,7 +5062,7 @@ ffff = ram_top = -1 eor_flag 0 1354 : 4930 > eor #0|fao ;invert expected flags + always on bits -1356 : cd1c02 cmp fLDx ;test flags +1356 : cd1d02 cmp fLDx ;test flags trap_ne 1359 : d0fe > bne * ;failed not equal (non zero) @@ -5071,7 +5073,7 @@ ffff = ram_top = -1 135d : 48 > pha ;use stack to load status 135e : 28 > plp -135f : a414 ldy zp1+1 +135f : a416 ldy zp1+1 1361 : 08 php ;test stores do not alter flags 1362 : 98 tya 1363 : 49c3 eor #$c3 @@ -5089,7 +5091,7 @@ ffff = ram_top = -1 eor_flag 0 1373 : 4930 > eor #0|fao ;invert expected flags + always on bits -1375 : cd1d02 cmp fLDx+1 ;test flags +1375 : cd1e02 cmp fLDx+1 ;test flags trap_ne 1378 : d0fe > bne * ;failed not equal (non zero) @@ -5100,7 +5102,7 @@ ffff = ram_top = -1 137c : 48 > pha ;use stack to load status 137d : 28 > plp -137e : a415 ldy zp1+2 +137e : a417 ldy zp1+2 1380 : 08 php ;test stores do not alter flags 1381 : 98 tya 1382 : 49c3 eor #$c3 @@ -5118,7 +5120,7 @@ ffff = ram_top = -1 eor_flag 0 1392 : 4930 > eor #0|fao ;invert expected flags + always on bits -1394 : cd1e02 cmp fLDx+2 ;test flags +1394 : cd1f02 cmp fLDx+2 ;test flags trap_ne 1397 : d0fe > bne * ;failed not equal (non zero) @@ -5129,7 +5131,7 @@ ffff = ram_top = -1 139b : 48 > pha ;use stack to load status 139c : 28 > plp -139d : a416 ldy zp1+3 +139d : a418 ldy zp1+3 139f : 08 php ;test stores do not alter flags 13a0 : 98 tya 13a1 : 49c3 eor #$c3 @@ -5147,7 +5149,7 @@ ffff = ram_top = -1 eor_flag 0 13b1 : 4930 > eor #0|fao ;invert expected flags + always on bits -13b3 : cd1f02 cmp fLDx+3 ;test flags +13b3 : cd2002 cmp fLDx+3 ;test flags trap_ne 13b6 : d0fe > bne * ;failed not equal (non zero) @@ -5159,7 +5161,7 @@ ffff = ram_top = -1 13ba : 48 > pha ;use stack to load status 13bb : 28 > plp -13bc : a413 ldy zp1 +13bc : a415 ldy zp1 13be : 08 php ;test stores do not alter flags 13bf : 98 tya 13c0 : 49c3 eor #$c3 @@ -5177,7 +5179,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 13d0 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -13d2 : cd1c02 cmp fLDx ;test flags +13d2 : cd1d02 cmp fLDx ;test flags trap_ne 13d5 : d0fe > bne * ;failed not equal (non zero) @@ -5188,7 +5190,7 @@ ffff = ram_top = -1 13d9 : 48 > pha ;use stack to load status 13da : 28 > plp -13db : a414 ldy zp1+1 +13db : a416 ldy zp1+1 13dd : 08 php ;test stores do not alter flags 13de : 98 tya 13df : 49c3 eor #$c3 @@ -5206,7 +5208,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 13ef : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -13f1 : cd1d02 cmp fLDx+1 ;test flags +13f1 : cd1e02 cmp fLDx+1 ;test flags trap_ne 13f4 : d0fe > bne * ;failed not equal (non zero) @@ -5217,7 +5219,7 @@ ffff = ram_top = -1 13f8 : 48 > pha ;use stack to load status 13f9 : 28 > plp -13fa : a415 ldy zp1+2 +13fa : a417 ldy zp1+2 13fc : 08 php ;test stores do not alter flags 13fd : 98 tya 13fe : 49c3 eor #$c3 @@ -5235,7 +5237,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 140e : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1410 : cd1e02 cmp fLDx+2 ;test flags +1410 : cd1f02 cmp fLDx+2 ;test flags trap_ne 1413 : d0fe > bne * ;failed not equal (non zero) @@ -5246,7 +5248,7 @@ ffff = ram_top = -1 1417 : 48 > pha ;use stack to load status 1418 : 28 > plp -1419 : a416 ldy zp1+3 +1419 : a418 ldy zp1+3 141b : 08 php ;test stores do not alter flags 141c : 98 tya 141d : 49c3 eor #$c3 @@ -5264,7 +5266,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 142d : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -142f : cd1f02 cmp fLDx+3 ;test flags +142f : cd2002 cmp fLDx+3 ;test flags trap_ne 1432 : d0fe > bne * ;failed not equal (non zero) @@ -5276,7 +5278,7 @@ ffff = ram_top = -1 1436 : 48 > pha ;use stack to load status 1437 : 28 > plp -1438 : ac1702 ldy abs1 +1438 : ac1802 ldy abs1 143b : 08 php ;test stores do not alter flags 143c : 98 tya 143d : 49c3 eor #$c3 @@ -5286,7 +5288,7 @@ ffff = ram_top = -1 1443 : 08 php ;flags after load/store sequence 1444 : 49c3 eor #$c3 1446 : a8 tay -1447 : c413 cpy zp1 ;test result +1447 : c415 cpy zp1 ;test result trap_ne 1449 : d0fe > bne * ;failed not equal (non zero) @@ -5294,7 +5296,7 @@ ffff = ram_top = -1 eor_flag 0 144c : 4930 > eor #0|fao ;invert expected flags + always on bits -144e : cd1c02 cmp fLDx ;test flags +144e : cd1d02 cmp fLDx ;test flags trap_ne 1451 : d0fe > bne * ;failed not equal (non zero) @@ -5305,7 +5307,7 @@ ffff = ram_top = -1 1455 : 48 > pha ;use stack to load status 1456 : 28 > plp -1457 : ac1802 ldy abs1+1 +1457 : ac1902 ldy abs1+1 145a : 08 php ;test stores do not alter flags 145b : 98 tya 145c : 49c3 eor #$c3 @@ -5315,7 +5317,7 @@ ffff = ram_top = -1 1462 : 08 php ;flags after load/store sequence 1463 : 49c3 eor #$c3 1465 : a8 tay -1466 : c414 cpy zp1+1 ;test result +1466 : c416 cpy zp1+1 ;test result trap_ne 1468 : d0fe > bne * ;failed not equal (non zero) @@ -5323,7 +5325,7 @@ ffff = ram_top = -1 eor_flag 0 146b : 4930 > eor #0|fao ;invert expected flags + always on bits -146d : cd1d02 cmp fLDx+1 ;test flags +146d : cd1e02 cmp fLDx+1 ;test flags trap_ne 1470 : d0fe > bne * ;failed not equal (non zero) @@ -5334,7 +5336,7 @@ ffff = ram_top = -1 1474 : 48 > pha ;use stack to load status 1475 : 28 > plp -1476 : ac1902 ldy abs1+2 +1476 : ac1a02 ldy abs1+2 1479 : 08 php ;test stores do not alter flags 147a : 98 tya 147b : 49c3 eor #$c3 @@ -5344,7 +5346,7 @@ ffff = ram_top = -1 1481 : 08 php ;flags after load/store sequence 1482 : 49c3 eor #$c3 1484 : a8 tay -1485 : c415 cpy zp1+2 ;test result +1485 : c417 cpy zp1+2 ;test result trap_ne 1487 : d0fe > bne * ;failed not equal (non zero) @@ -5352,7 +5354,7 @@ ffff = ram_top = -1 eor_flag 0 148a : 4930 > eor #0|fao ;invert expected flags + always on bits -148c : cd1e02 cmp fLDx+2 ;test flags +148c : cd1f02 cmp fLDx+2 ;test flags trap_ne 148f : d0fe > bne * ;failed not equal (non zero) @@ -5363,7 +5365,7 @@ ffff = ram_top = -1 1493 : 48 > pha ;use stack to load status 1494 : 28 > plp -1495 : ac1a02 ldy abs1+3 +1495 : ac1b02 ldy abs1+3 1498 : 08 php ;test stores do not alter flags 1499 : 98 tya 149a : 49c3 eor #$c3 @@ -5373,7 +5375,7 @@ ffff = ram_top = -1 14a0 : 08 php ;flags after load/store sequence 14a1 : 49c3 eor #$c3 14a3 : a8 tay -14a4 : c416 cpy zp1+3 ;test result +14a4 : c418 cpy zp1+3 ;test result trap_ne 14a6 : d0fe > bne * ;failed not equal (non zero) @@ -5381,7 +5383,7 @@ ffff = ram_top = -1 eor_flag 0 14a9 : 4930 > eor #0|fao ;invert expected flags + always on bits -14ab : cd1f02 cmp fLDx+3 ;test flags +14ab : cd2002 cmp fLDx+3 ;test flags trap_ne 14ae : d0fe > bne * ;failed not equal (non zero) @@ -5393,7 +5395,7 @@ ffff = ram_top = -1 14b2 : 48 > pha ;use stack to load status 14b3 : 28 > plp -14b4 : ac1702 ldy abs1 +14b4 : ac1802 ldy abs1 14b7 : 08 php ;test stores do not alter flags 14b8 : 98 tya 14b9 : 49c3 eor #$c3 @@ -5403,7 +5405,7 @@ ffff = ram_top = -1 14bf : 08 php ;flags after load/store sequence 14c0 : 49c3 eor #$c3 14c2 : a8 tay -14c3 : c513 cmp zp1 ;test result +14c3 : c515 cmp zp1 ;test result trap_ne 14c5 : d0fe > bne * ;failed not equal (non zero) @@ -5411,7 +5413,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 14c8 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -14ca : cd1c02 cmp fLDx ;test flags +14ca : cd1d02 cmp fLDx ;test flags trap_ne 14cd : d0fe > bne * ;failed not equal (non zero) @@ -5422,7 +5424,7 @@ ffff = ram_top = -1 14d1 : 48 > pha ;use stack to load status 14d2 : 28 > plp -14d3 : ac1802 ldy abs1+1 +14d3 : ac1902 ldy abs1+1 14d6 : 08 php ;test stores do not alter flags 14d7 : 98 tya 14d8 : 49c3 eor #$c3 @@ -5432,7 +5434,7 @@ ffff = ram_top = -1 14de : 08 php ;flags after load/store sequence 14df : 49c3 eor #$c3 14e1 : a8 tay -14e2 : c514 cmp zp1+1 ;test result +14e2 : c516 cmp zp1+1 ;test result trap_ne 14e4 : d0fe > bne * ;failed not equal (non zero) @@ -5440,7 +5442,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 14e7 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -14e9 : cd1d02 cmp fLDx+1 ;test flags +14e9 : cd1e02 cmp fLDx+1 ;test flags trap_ne 14ec : d0fe > bne * ;failed not equal (non zero) @@ -5451,7 +5453,7 @@ ffff = ram_top = -1 14f0 : 48 > pha ;use stack to load status 14f1 : 28 > plp -14f2 : ac1902 ldy abs1+2 +14f2 : ac1a02 ldy abs1+2 14f5 : 08 php ;test stores do not alter flags 14f6 : 98 tya 14f7 : 49c3 eor #$c3 @@ -5461,7 +5463,7 @@ ffff = ram_top = -1 14fd : 08 php ;flags after load/store sequence 14fe : 49c3 eor #$c3 1500 : a8 tay -1501 : c515 cmp zp1+2 ;test result +1501 : c517 cmp zp1+2 ;test result trap_ne 1503 : d0fe > bne * ;failed not equal (non zero) @@ -5469,7 +5471,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1506 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1508 : cd1e02 cmp fLDx+2 ;test flags +1508 : cd1f02 cmp fLDx+2 ;test flags trap_ne 150b : d0fe > bne * ;failed not equal (non zero) @@ -5480,7 +5482,7 @@ ffff = ram_top = -1 150f : 48 > pha ;use stack to load status 1510 : 28 > plp -1511 : ac1a02 ldy abs1+3 +1511 : ac1b02 ldy abs1+3 1514 : 08 php ;test stores do not alter flags 1515 : 98 tya 1516 : 49c3 eor #$c3 @@ -5490,7 +5492,7 @@ ffff = ram_top = -1 151c : 08 php ;flags after load/store sequence 151d : 49c3 eor #$c3 151f : a8 tay -1520 : c516 cmp zp1+3 ;test result +1520 : c518 cmp zp1+3 ;test result trap_ne 1522 : d0fe > bne * ;failed not equal (non zero) @@ -5498,7 +5500,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1525 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1527 : cd1f02 cmp fLDx+3 ;test flags +1527 : cd2002 cmp fLDx+3 ;test flags trap_ne 152a : d0fe > bne * ;failed not equal (non zero) @@ -5513,7 +5515,7 @@ ffff = ram_top = -1 1530 : a0c3 ldy #$c3 1532 : 08 php -1533 : cc1702 cpy abs1 ;test result +1533 : cc1802 cpy abs1 ;test result trap_ne 1536 : d0fe > bne * ;failed not equal (non zero) @@ -5521,7 +5523,7 @@ ffff = ram_top = -1 eor_flag 0 1539 : 4930 > eor #0|fao ;invert expected flags + always on bits -153b : cd1c02 cmp fLDx ;test flags +153b : cd1d02 cmp fLDx ;test flags trap_ne 153e : d0fe > bne * ;failed not equal (non zero) @@ -5534,7 +5536,7 @@ ffff = ram_top = -1 1544 : a082 ldy #$82 1546 : 08 php -1547 : cc1802 cpy abs1+1 ;test result +1547 : cc1902 cpy abs1+1 ;test result trap_ne 154a : d0fe > bne * ;failed not equal (non zero) @@ -5542,7 +5544,7 @@ ffff = ram_top = -1 eor_flag 0 154d : 4930 > eor #0|fao ;invert expected flags + always on bits -154f : cd1d02 cmp fLDx+1 ;test flags +154f : cd1e02 cmp fLDx+1 ;test flags trap_ne 1552 : d0fe > bne * ;failed not equal (non zero) @@ -5555,7 +5557,7 @@ ffff = ram_top = -1 1558 : a041 ldy #$41 155a : 08 php -155b : cc1902 cpy abs1+2 ;test result +155b : cc1a02 cpy abs1+2 ;test result trap_ne 155e : d0fe > bne * ;failed not equal (non zero) @@ -5563,7 +5565,7 @@ ffff = ram_top = -1 eor_flag 0 1561 : 4930 > eor #0|fao ;invert expected flags + always on bits -1563 : cd1e02 cmp fLDx+2 ;test flags +1563 : cd1f02 cmp fLDx+2 ;test flags trap_ne 1566 : d0fe > bne * ;failed not equal (non zero) @@ -5576,7 +5578,7 @@ ffff = ram_top = -1 156c : a000 ldy #0 156e : 08 php -156f : cc1a02 cpy abs1+3 ;test result +156f : cc1b02 cpy abs1+3 ;test result trap_ne 1572 : d0fe > bne * ;failed not equal (non zero) @@ -5584,7 +5586,7 @@ ffff = ram_top = -1 eor_flag 0 1575 : 4930 > eor #0|fao ;invert expected flags + always on bits -1577 : cd1f02 cmp fLDx+3 ;test flags +1577 : cd2002 cmp fLDx+3 ;test flags trap_ne 157a : d0fe > bne * ;failed not equal (non zero) @@ -5598,7 +5600,7 @@ ffff = ram_top = -1 1580 : a0c3 ldy #$c3 1582 : 08 php -1583 : cc1702 cpy abs1 ;test result +1583 : cc1802 cpy abs1 ;test result trap_ne 1586 : d0fe > bne * ;failed not equal (non zero) @@ -5606,7 +5608,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1589 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -158b : cd1c02 cmp fLDx ;test flags +158b : cd1d02 cmp fLDx ;test flags trap_ne 158e : d0fe > bne * ;failed not equal (non zero) @@ -5619,7 +5621,7 @@ ffff = ram_top = -1 1594 : a082 ldy #$82 1596 : 08 php -1597 : cc1802 cpy abs1+1 ;test result +1597 : cc1902 cpy abs1+1 ;test result trap_ne 159a : d0fe > bne * ;failed not equal (non zero) @@ -5627,7 +5629,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 159d : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -159f : cd1d02 cmp fLDx+1 ;test flags +159f : cd1e02 cmp fLDx+1 ;test flags trap_ne 15a2 : d0fe > bne * ;failed not equal (non zero) @@ -5640,7 +5642,7 @@ ffff = ram_top = -1 15a8 : a041 ldy #$41 15aa : 08 php -15ab : cc1902 cpy abs1+2 ;test result +15ab : cc1a02 cpy abs1+2 ;test result trap_ne 15ae : d0fe > bne * ;failed not equal (non zero) @@ -5648,7 +5650,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 15b1 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -15b3 : cd1e02 cmp fLDx+2 ;test flags +15b3 : cd1f02 cmp fLDx+2 ;test flags trap_ne 15b6 : d0fe > bne * ;failed not equal (non zero) @@ -5661,7 +5663,7 @@ ffff = ram_top = -1 15bc : a000 ldy #0 15be : 08 php -15bf : cc1a02 cpy abs1+3 ;test result +15bf : cc1b02 cpy abs1+3 ;test result trap_ne 15c2 : d0fe > bne * ;failed not equal (non zero) @@ -5669,7 +5671,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 15c5 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -15c7 : cd1f02 cmp fLDx+3 ;test flags +15c7 : cd2002 cmp fLDx+3 ;test flags trap_ne 15ca : d0fe > bne * ;failed not equal (non zero) @@ -5677,56 +5679,56 @@ ffff = ram_top = -1 15cc : a000 ldy #0 15ce : a50c lda zpt 15d0 : 49c3 eor #$c3 -15d2 : c513 cmp zp1 +15d2 : c515 cmp zp1 trap_ne ;store to zp data 15d4 : d0fe > bne * ;failed not equal (non zero) 15d6 : 840c sty zpt ;clear 15d8 : ad0302 lda abst 15db : 49c3 eor #$c3 -15dd : cd1702 cmp abs1 +15dd : cd1802 cmp abs1 trap_ne ;store to abs data 15e0 : d0fe > bne * ;failed not equal (non zero) 15e2 : 8c0302 sty abst ;clear 15e5 : a50d lda zpt+1 15e7 : 49c3 eor #$c3 -15e9 : c514 cmp zp1+1 +15e9 : c516 cmp zp1+1 trap_ne ;store to zp+1 data 15eb : d0fe > bne * ;failed not equal (non zero) 15ed : 840d sty zpt+1 ;clear 15ef : ad0402 lda abst+1 15f2 : 49c3 eor #$c3 -15f4 : cd1802 cmp abs1+1 +15f4 : cd1902 cmp abs1+1 trap_ne ;store to abs+1 data 15f7 : d0fe > bne * ;failed not equal (non zero) 15f9 : 8c0402 sty abst+1 ;clear 15fc : a50e lda zpt+2 15fe : 49c3 eor #$c3 -1600 : c515 cmp zp1+2 +1600 : c517 cmp zp1+2 trap_ne ;store to zp+2 data 1602 : d0fe > bne * ;failed not equal (non zero) 1604 : 840e sty zpt+2 ;clear 1606 : ad0502 lda abst+2 1609 : 49c3 eor #$c3 -160b : cd1902 cmp abs1+2 +160b : cd1a02 cmp abs1+2 trap_ne ;store to abs+2 data 160e : d0fe > bne * ;failed not equal (non zero) 1610 : 8c0502 sty abst+2 ;clear 1613 : a50f lda zpt+3 1615 : 49c3 eor #$c3 -1617 : c516 cmp zp1+3 +1617 : c518 cmp zp1+3 trap_ne ;store to zp+3 data 1619 : d0fe > bne * ;failed not equal (non zero) 161b : 840f sty zpt+3 ;clear 161d : ad0602 lda abst+3 1620 : 49c3 eor #$c3 -1622 : cd1a02 cmp abs1+3 +1622 : cd1b02 cmp abs1+3 trap_ne ;store to abs+3 data 1625 : d0fe > bne * ;failed not equal (non zero) @@ -5754,14 +5756,14 @@ ffff = ram_top = -1 163a : 48 > pha ;use stack to load status 163b : 28 > plp -163c : b513 lda zp1,x +163c : b515 lda zp1,x 163e : 08 php ;test stores do not alter flags 163f : 49c3 eor #$c3 1641 : 28 plp 1642 : 9d0302 sta abst,x 1645 : 08 php ;flags after load/store sequence 1646 : 49c3 eor #$c3 -1648 : dd1702 cmp abs1,x ;test result +1648 : dd1802 cmp abs1,x ;test result trap_ne 164b : d0fe > bne * ;failed not equal (non zero) @@ -5769,7 +5771,7 @@ ffff = ram_top = -1 eor_flag 0 164e : 4930 > eor #0|fao ;invert expected flags + always on bits -1650 : dd1c02 cmp fLDx,x ;test flags +1650 : dd1d02 cmp fLDx,x ;test flags trap_ne 1653 : d0fe > bne * ;failed not equal (non zero) @@ -5785,14 +5787,14 @@ ffff = ram_top = -1 165c : 48 > pha ;use stack to load status 165d : 28 > plp -165e : b513 lda zp1,x +165e : b515 lda zp1,x 1660 : 08 php ;test stores do not alter flags 1661 : 49c3 eor #$c3 1663 : 28 plp 1664 : 9d0302 sta abst,x 1667 : 08 php ;flags after load/store sequence 1668 : 49c3 eor #$c3 -166a : dd1702 cmp abs1,x ;test result +166a : dd1802 cmp abs1,x ;test result trap_ne 166d : d0fe > bne * ;failed not equal (non zero) @@ -5800,7 +5802,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1670 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1672 : dd1c02 cmp fLDx,x ;test flags +1672 : dd1d02 cmp fLDx,x ;test flags trap_ne 1675 : d0fe > bne * ;failed not equal (non zero) @@ -5816,14 +5818,14 @@ ffff = ram_top = -1 167e : 48 > pha ;use stack to load status 167f : 28 > plp -1680 : bd1702 lda abs1,x +1680 : bd1802 lda abs1,x 1683 : 08 php ;test stores do not alter flags 1684 : 49c3 eor #$c3 1686 : 28 plp 1687 : 950c sta zpt,x 1689 : 08 php ;flags after load/store sequence 168a : 49c3 eor #$c3 -168c : d513 cmp zp1,x ;test result +168c : d515 cmp zp1,x ;test result trap_ne 168e : d0fe > bne * ;failed not equal (non zero) @@ -5831,7 +5833,7 @@ ffff = ram_top = -1 eor_flag 0 1691 : 4930 > eor #0|fao ;invert expected flags + always on bits -1693 : dd1c02 cmp fLDx,x ;test flags +1693 : dd1d02 cmp fLDx,x ;test flags trap_ne 1696 : d0fe > bne * ;failed not equal (non zero) @@ -5847,14 +5849,14 @@ ffff = ram_top = -1 169f : 48 > pha ;use stack to load status 16a0 : 28 > plp -16a1 : bd1702 lda abs1,x +16a1 : bd1802 lda abs1,x 16a4 : 08 php ;test stores do not alter flags 16a5 : 49c3 eor #$c3 16a7 : 28 plp 16a8 : 950c sta zpt,x 16aa : 08 php ;flags after load/store sequence 16ab : 49c3 eor #$c3 -16ad : d513 cmp zp1,x ;test result +16ad : d515 cmp zp1,x ;test result trap_ne 16af : d0fe > bne * ;failed not equal (non zero) @@ -5862,7 +5864,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 16b2 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -16b4 : dd1c02 cmp fLDx,x ;test flags +16b4 : dd1d02 cmp fLDx,x ;test flags trap_ne 16b7 : d0fe > bne * ;failed not equal (non zero) @@ -5873,14 +5875,14 @@ ffff = ram_top = -1 16be : a000 ldy #0 16c0 : b50c tstax lda zpt,x 16c2 : 49c3 eor #$c3 -16c4 : d513 cmp zp1,x +16c4 : d515 cmp zp1,x trap_ne ;store to zp,x data 16c6 : d0fe > bne * ;failed not equal (non zero) 16c8 : 940c sty zpt,x ;clear 16ca : bd0302 lda abst,x 16cd : 49c3 eor #$c3 -16cf : dd1702 cmp abs1,x +16cf : dd1802 cmp abs1,x trap_ne ;store to abs,x data 16d2 : d0fe > bne * ;failed not equal (non zero) @@ -5910,14 +5912,14 @@ ffff = ram_top = -1 16eb : 48 > pha ;use stack to load status 16ec : 28 > plp -16ed : b124 lda (ind1),y +16ed : b126 lda (ind1),y 16ef : 08 php ;test stores do not alter flags 16f0 : 49c3 eor #$c3 16f2 : 28 plp 16f3 : 990302 sta abst,y 16f6 : 08 php ;flags after load/store sequence 16f7 : 49c3 eor #$c3 -16f9 : d91702 cmp abs1,y ;test result +16f9 : d91802 cmp abs1,y ;test result trap_ne 16fc : d0fe > bne * ;failed not equal (non zero) @@ -5925,7 +5927,7 @@ ffff = ram_top = -1 eor_flag 0 16ff : 4930 > eor #0|fao ;invert expected flags + always on bits -1701 : d91c02 cmp fLDx,y ;test flags +1701 : d91d02 cmp fLDx,y ;test flags trap_ne 1704 : d0fe > bne * ;failed not equal (non zero) @@ -5941,14 +5943,14 @@ ffff = ram_top = -1 170d : 48 > pha ;use stack to load status 170e : 28 > plp -170f : b124 lda (ind1),y +170f : b126 lda (ind1),y 1711 : 08 php ;test stores do not alter flags 1712 : 49c3 eor #$c3 1714 : 28 plp 1715 : 990302 sta abst,y 1718 : 08 php ;flags after load/store sequence 1719 : 49c3 eor #$c3 -171b : d91702 cmp abs1,y ;test result +171b : d91802 cmp abs1,y ;test result trap_ne 171e : d0fe > bne * ;failed not equal (non zero) @@ -5956,7 +5958,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1721 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1723 : d91c02 cmp fLDx,y ;test flags +1723 : d91d02 cmp fLDx,y ;test flags trap_ne 1726 : d0fe > bne * ;failed not equal (non zero) @@ -5967,7 +5969,7 @@ ffff = ram_top = -1 172d : a200 ldx #0 172f : b90302 tstay lda abst,y 1732 : 49c3 eor #$c3 -1734 : d91702 cmp abs1,y +1734 : d91802 cmp abs1,y trap_ne ;store to abs data 1737 : d0fe > bne * ;failed not equal (non zero) @@ -5985,14 +5987,14 @@ ffff = ram_top = -1 1744 : 48 > pha ;use stack to load status 1745 : 28 > plp -1746 : b91702 lda abs1,y +1746 : b91802 lda abs1,y 1749 : 08 php ;test stores do not alter flags 174a : 49c3 eor #$c3 174c : 28 plp -174d : 9130 sta (indt),y +174d : 9132 sta (indt),y 174f : 08 php ;flags after load/store sequence 1750 : 49c3 eor #$c3 -1752 : d124 cmp (ind1),y ;test result +1752 : d126 cmp (ind1),y ;test result trap_ne 1754 : d0fe > bne * ;failed not equal (non zero) @@ -6000,7 +6002,7 @@ ffff = ram_top = -1 eor_flag 0 1757 : 4930 > eor #0|fao ;invert expected flags + always on bits -1759 : d91c02 cmp fLDx,y ;test flags +1759 : d91d02 cmp fLDx,y ;test flags trap_ne 175c : d0fe > bne * ;failed not equal (non zero) @@ -6016,14 +6018,14 @@ ffff = ram_top = -1 1765 : 48 > pha ;use stack to load status 1766 : 28 > plp -1767 : b91702 lda abs1,y +1767 : b91802 lda abs1,y 176a : 08 php ;test stores do not alter flags 176b : 49c3 eor #$c3 176d : 28 plp -176e : 9130 sta (indt),y +176e : 9132 sta (indt),y 1770 : 08 php ;flags after load/store sequence 1771 : 49c3 eor #$c3 -1773 : d124 cmp (ind1),y ;test result +1773 : d126 cmp (ind1),y ;test result trap_ne 1775 : d0fe > bne * ;failed not equal (non zero) @@ -6031,7 +6033,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1778 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -177a : d91c02 cmp fLDx,y ;test flags +177a : d91d02 cmp fLDx,y ;test flags trap_ne 177d : d0fe > bne * ;failed not equal (non zero) @@ -6042,7 +6044,7 @@ ffff = ram_top = -1 1784 : a200 ldx #0 1786 : b90302 tstay1 lda abst,y 1789 : 49c3 eor #$c3 -178b : d91702 cmp abs1,y +178b : d91802 cmp abs1,y trap_ne ;store to abs data 178e : d0fe > bne * ;failed not equal (non zero) @@ -6061,14 +6063,14 @@ ffff = ram_top = -1 179d : 48 > pha ;use stack to load status 179e : 28 > plp -179f : a124 lda (ind1,x) +179f : a126 lda (ind1,x) 17a1 : 08 php ;test stores do not alter flags 17a2 : 49c3 eor #$c3 17a4 : 28 plp -17a5 : 8130 sta (indt,x) +17a5 : 8132 sta (indt,x) 17a7 : 08 php ;flags after load/store sequence 17a8 : 49c3 eor #$c3 -17aa : d91702 cmp abs1,y ;test result +17aa : d91802 cmp abs1,y ;test result trap_ne 17ad : d0fe > bne * ;failed not equal (non zero) @@ -6076,7 +6078,7 @@ ffff = ram_top = -1 eor_flag 0 17b0 : 4930 > eor #0|fao ;invert expected flags + always on bits -17b2 : d91c02 cmp fLDx,y ;test flags +17b2 : d91d02 cmp fLDx,y ;test flags trap_ne 17b5 : d0fe > bne * ;failed not equal (non zero) @@ -6095,14 +6097,14 @@ ffff = ram_top = -1 17c2 : 48 > pha ;use stack to load status 17c3 : 28 > plp -17c4 : a124 lda (ind1,x) +17c4 : a126 lda (ind1,x) 17c6 : 08 php ;test stores do not alter flags 17c7 : 49c3 eor #$c3 17c9 : 28 plp -17ca : 8130 sta (indt,x) +17ca : 8132 sta (indt,x) 17cc : 08 php ;flags after load/store sequence 17cd : 49c3 eor #$c3 -17cf : d91702 cmp abs1,y ;test result +17cf : d91802 cmp abs1,y ;test result trap_ne 17d2 : d0fe > bne * ;failed not equal (non zero) @@ -6110,7 +6112,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 17d5 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -17d7 : d91c02 cmp fLDx,y ;test flags +17d7 : d91d02 cmp fLDx,y ;test flags trap_ne 17da : d0fe > bne * ;failed not equal (non zero) @@ -6123,7 +6125,7 @@ ffff = ram_top = -1 17e3 : a200 ldx #0 17e5 : b90302 tstay2 lda abst,y 17e8 : 49c3 eor #$c3 -17ea : d91702 cmp abs1,y +17ea : d91802 cmp abs1,y trap_ne ;store to abs data 17ed : d0fe > bne * ;failed not equal (non zero) @@ -6145,13 +6147,13 @@ ffff = ram_top = -1 ; indexed wraparound test (only zp should wrap) 1802 : a2fd ldx #3+$fa -1804 : b519 tldax6 lda zp1-$fa&$ff,x ;wrap on indexed zp +1804 : b51b tldax6 lda zp1-$fa&$ff,x ;wrap on indexed zp 1806 : 9d0901 sta abst-$fa,x ;no STX abs,x! 1809 : ca dex 180a : e0fa cpx #$fa 180c : b0f6 bcs tldax6 180e : a2fd ldx #3+$fa -1810 : bd1d01 tldax7 lda abs1-$fa,x ;no wrap on indexed abs +1810 : bd1e01 tldax7 lda abs1-$fa,x ;no wrap on indexed abs 1813 : 9512 sta zpt-$fa&$ff,x 1815 : ca dex 1816 : e0fa cpx #$fa @@ -6160,13 +6162,13 @@ ffff = ram_top = -1 181a : a203 ldx #3 ;testing wraparound result 181c : a000 ldy #0 181e : b50c tstax1 lda zpt,x -1820 : d513 cmp zp1,x +1820 : d515 cmp zp1,x trap_ne ;store to zp,x data 1822 : d0fe > bne * ;failed not equal (non zero) 1824 : 940c sty zpt,x ;clear 1826 : bd0302 lda abst,x -1829 : dd1702 cmp abs1,x +1829 : dd1802 cmp abs1,x trap_ne ;store to abs,x data 182c : d0fe > bne * ;failed not equal (non zero) @@ -6177,7 +6179,7 @@ ffff = ram_top = -1 1835 : a0fb ldy #3+$f8 1837 : a2fe ldx #6+$f8 -1839 : a12c tlday4 lda (ind1-$f8&$ff,x) ;wrap on indexed zp indirect +1839 : a12e tlday4 lda (ind1-$f8&$ff,x) ;wrap on indexed zp indirect 183b : 990b01 sta abst-$f8,y 183e : ca dex 183f : ca dex @@ -6187,7 +6189,7 @@ ffff = ram_top = -1 1845 : a003 ldy #3 ;testing wraparound result 1847 : a200 ldx #0 1849 : b90302 tstay4 lda abst,y -184c : d91702 cmp abs1,y +184c : d91802 cmp abs1,y trap_ne ;store to abs data 184f : d0fe > bne * ;failed not equal (non zero) @@ -6197,15 +6199,15 @@ ffff = ram_top = -1 1856 : 10f1 bpl tstay4 1858 : a0fb ldy #3+$f8 -185a : b91f01 tlday5 lda abs1-$f8,y ;no wrap on indexed abs -185d : 9138 sta (inwt),y +185a : b92001 tlday5 lda abs1-$f8,y ;no wrap on indexed abs +185d : 913a sta (inwt),y 185f : 88 dey 1860 : c0f8 cpy #$f8 1862 : b0f6 bcs tlday5 1864 : a003 ldy #3 ;testing wraparound result 1866 : a200 ldx #0 1868 : b90302 tstay5 lda abst,y -186b : d91702 cmp abs1,y +186b : d91802 cmp abs1,y trap_ne ;store to abs data 186e : d0fe > bne * ;failed not equal (non zero) @@ -6216,8 +6218,8 @@ ffff = ram_top = -1 1877 : a0fb ldy #3+$f8 1879 : a2fe ldx #6+$f8 -187b : b12e tlday6 lda (inw1),y ;no wrap on zp indirect indexed -187d : 8138 sta (indt-$f8&$ff,x) +187b : b130 tlday6 lda (inw1),y ;no wrap on zp indirect indexed +187d : 813a sta (indt-$f8&$ff,x) 187f : ca dex 1880 : ca dex 1881 : 88 dey @@ -6226,7 +6228,7 @@ ffff = ram_top = -1 1886 : a003 ldy #3 ;testing wraparound result 1888 : a200 ldx #0 188a : b90302 tstay6 lda abst,y -188d : d91702 cmp abs1,y +188d : d91802 cmp abs1,y trap_ne ;store to abs data 1890 : d0fe > bne * ;failed not equal (non zero) @@ -6254,7 +6256,7 @@ ffff = ram_top = -1 18a7 : 48 > pha ;use stack to load status 18a8 : 28 > plp -18a9 : a513 lda zp1 +18a9 : a515 lda zp1 18ab : 08 php ;test stores do not alter flags 18ac : 49c3 eor #$c3 18ae : 28 plp @@ -6269,7 +6271,7 @@ ffff = ram_top = -1 eor_flag 0 18ba : 4930 > eor #0|fao ;invert expected flags + always on bits -18bc : cd1c02 cmp fLDx ;test flags +18bc : cd1d02 cmp fLDx ;test flags trap_ne 18bf : d0fe > bne * ;failed not equal (non zero) @@ -6280,7 +6282,7 @@ ffff = ram_top = -1 18c3 : 48 > pha ;use stack to load status 18c4 : 28 > plp -18c5 : a514 lda zp1+1 +18c5 : a516 lda zp1+1 18c7 : 08 php ;test stores do not alter flags 18c8 : 49c3 eor #$c3 18ca : 28 plp @@ -6295,7 +6297,7 @@ ffff = ram_top = -1 eor_flag 0 18d6 : 4930 > eor #0|fao ;invert expected flags + always on bits -18d8 : cd1d02 cmp fLDx+1 ;test flags +18d8 : cd1e02 cmp fLDx+1 ;test flags trap_ne 18db : d0fe > bne * ;failed not equal (non zero) @@ -6306,7 +6308,7 @@ ffff = ram_top = -1 18df : 48 > pha ;use stack to load status 18e0 : 28 > plp -18e1 : a515 lda zp1+2 +18e1 : a517 lda zp1+2 18e3 : 08 php ;test stores do not alter flags 18e4 : 49c3 eor #$c3 18e6 : 28 plp @@ -6321,7 +6323,7 @@ ffff = ram_top = -1 eor_flag 0 18f2 : 4930 > eor #0|fao ;invert expected flags + always on bits -18f4 : cd1e02 cmp fLDx+2 ;test flags +18f4 : cd1f02 cmp fLDx+2 ;test flags trap_ne 18f7 : d0fe > bne * ;failed not equal (non zero) @@ -6332,7 +6334,7 @@ ffff = ram_top = -1 18fb : 48 > pha ;use stack to load status 18fc : 28 > plp -18fd : a516 lda zp1+3 +18fd : a518 lda zp1+3 18ff : 08 php ;test stores do not alter flags 1900 : 49c3 eor #$c3 1902 : 28 plp @@ -6347,7 +6349,7 @@ ffff = ram_top = -1 eor_flag 0 190e : 4930 > eor #0|fao ;invert expected flags + always on bits -1910 : cd1f02 cmp fLDx+3 ;test flags +1910 : cd2002 cmp fLDx+3 ;test flags trap_ne 1913 : d0fe > bne * ;failed not equal (non zero) @@ -6358,7 +6360,7 @@ ffff = ram_top = -1 1917 : 48 > pha ;use stack to load status 1918 : 28 > plp -1919 : a513 lda zp1 +1919 : a515 lda zp1 191b : 08 php ;test stores do not alter flags 191c : 49c3 eor #$c3 191e : 28 plp @@ -6373,7 +6375,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 192a : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -192c : cd1c02 cmp fLDx ;test flags +192c : cd1d02 cmp fLDx ;test flags trap_ne 192f : d0fe > bne * ;failed not equal (non zero) @@ -6384,7 +6386,7 @@ ffff = ram_top = -1 1933 : 48 > pha ;use stack to load status 1934 : 28 > plp -1935 : a514 lda zp1+1 +1935 : a516 lda zp1+1 1937 : 08 php ;test stores do not alter flags 1938 : 49c3 eor #$c3 193a : 28 plp @@ -6399,7 +6401,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1946 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1948 : cd1d02 cmp fLDx+1 ;test flags +1948 : cd1e02 cmp fLDx+1 ;test flags trap_ne 194b : d0fe > bne * ;failed not equal (non zero) @@ -6410,7 +6412,7 @@ ffff = ram_top = -1 194f : 48 > pha ;use stack to load status 1950 : 28 > plp -1951 : a515 lda zp1+2 +1951 : a517 lda zp1+2 1953 : 08 php ;test stores do not alter flags 1954 : 49c3 eor #$c3 1956 : 28 plp @@ -6425,7 +6427,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1962 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1964 : cd1e02 cmp fLDx+2 ;test flags +1964 : cd1f02 cmp fLDx+2 ;test flags trap_ne 1967 : d0fe > bne * ;failed not equal (non zero) @@ -6436,7 +6438,7 @@ ffff = ram_top = -1 196b : 48 > pha ;use stack to load status 196c : 28 > plp -196d : a516 lda zp1+3 +196d : a518 lda zp1+3 196f : 08 php ;test stores do not alter flags 1970 : 49c3 eor #$c3 1972 : 28 plp @@ -6451,7 +6453,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 197e : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1980 : cd1f02 cmp fLDx+3 ;test flags +1980 : cd2002 cmp fLDx+3 ;test flags trap_ne 1983 : d0fe > bne * ;failed not equal (non zero) @@ -6462,14 +6464,14 @@ ffff = ram_top = -1 1987 : 48 > pha ;use stack to load status 1988 : 28 > plp -1989 : ad1702 lda abs1 +1989 : ad1802 lda abs1 198c : 08 php ;test stores do not alter flags 198d : 49c3 eor #$c3 198f : 28 plp 1990 : 850c sta zpt 1992 : 08 php ;flags after load/store sequence 1993 : 49c3 eor #$c3 -1995 : c513 cmp zp1 ;test result +1995 : c515 cmp zp1 ;test result trap_ne 1997 : d0fe > bne * ;failed not equal (non zero) @@ -6477,7 +6479,7 @@ ffff = ram_top = -1 eor_flag 0 199a : 4930 > eor #0|fao ;invert expected flags + always on bits -199c : cd1c02 cmp fLDx ;test flags +199c : cd1d02 cmp fLDx ;test flags trap_ne 199f : d0fe > bne * ;failed not equal (non zero) @@ -6488,14 +6490,14 @@ ffff = ram_top = -1 19a3 : 48 > pha ;use stack to load status 19a4 : 28 > plp -19a5 : ad1802 lda abs1+1 +19a5 : ad1902 lda abs1+1 19a8 : 08 php ;test stores do not alter flags 19a9 : 49c3 eor #$c3 19ab : 28 plp 19ac : 850d sta zpt+1 19ae : 08 php ;flags after load/store sequence 19af : 49c3 eor #$c3 -19b1 : c514 cmp zp1+1 ;test result +19b1 : c516 cmp zp1+1 ;test result trap_ne 19b3 : d0fe > bne * ;failed not equal (non zero) @@ -6503,7 +6505,7 @@ ffff = ram_top = -1 eor_flag 0 19b6 : 4930 > eor #0|fao ;invert expected flags + always on bits -19b8 : cd1d02 cmp fLDx+1 ;test flags +19b8 : cd1e02 cmp fLDx+1 ;test flags trap_ne 19bb : d0fe > bne * ;failed not equal (non zero) @@ -6514,14 +6516,14 @@ ffff = ram_top = -1 19bf : 48 > pha ;use stack to load status 19c0 : 28 > plp -19c1 : ad1902 lda abs1+2 +19c1 : ad1a02 lda abs1+2 19c4 : 08 php ;test stores do not alter flags 19c5 : 49c3 eor #$c3 19c7 : 28 plp 19c8 : 850e sta zpt+2 19ca : 08 php ;flags after load/store sequence 19cb : 49c3 eor #$c3 -19cd : c515 cmp zp1+2 ;test result +19cd : c517 cmp zp1+2 ;test result trap_ne 19cf : d0fe > bne * ;failed not equal (non zero) @@ -6529,7 +6531,7 @@ ffff = ram_top = -1 eor_flag 0 19d2 : 4930 > eor #0|fao ;invert expected flags + always on bits -19d4 : cd1e02 cmp fLDx+2 ;test flags +19d4 : cd1f02 cmp fLDx+2 ;test flags trap_ne 19d7 : d0fe > bne * ;failed not equal (non zero) @@ -6540,14 +6542,14 @@ ffff = ram_top = -1 19db : 48 > pha ;use stack to load status 19dc : 28 > plp -19dd : ad1a02 lda abs1+3 +19dd : ad1b02 lda abs1+3 19e0 : 08 php ;test stores do not alter flags 19e1 : 49c3 eor #$c3 19e3 : 28 plp 19e4 : 850f sta zpt+3 19e6 : 08 php ;flags after load/store sequence 19e7 : 49c3 eor #$c3 -19e9 : c516 cmp zp1+3 ;test result +19e9 : c518 cmp zp1+3 ;test result trap_ne 19eb : d0fe > bne * ;failed not equal (non zero) @@ -6555,7 +6557,7 @@ ffff = ram_top = -1 eor_flag 0 19ee : 4930 > eor #0|fao ;invert expected flags + always on bits -19f0 : cd1f02 cmp fLDx+3 ;test flags +19f0 : cd2002 cmp fLDx+3 ;test flags trap_ne 19f3 : d0fe > bne * ;failed not equal (non zero) @@ -6566,14 +6568,14 @@ ffff = ram_top = -1 19f7 : 48 > pha ;use stack to load status 19f8 : 28 > plp -19f9 : ad1702 lda abs1 +19f9 : ad1802 lda abs1 19fc : 08 php ;test stores do not alter flags 19fd : 49c3 eor #$c3 19ff : 28 plp 1a00 : 850c sta zpt 1a02 : 08 php ;flags after load/store sequence 1a03 : 49c3 eor #$c3 -1a05 : c513 cmp zp1 ;test result +1a05 : c515 cmp zp1 ;test result trap_ne 1a07 : d0fe > bne * ;failed not equal (non zero) @@ -6581,7 +6583,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1a0a : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1a0c : cd1c02 cmp fLDx ;test flags +1a0c : cd1d02 cmp fLDx ;test flags trap_ne 1a0f : d0fe > bne * ;failed not equal (non zero) @@ -6592,14 +6594,14 @@ ffff = ram_top = -1 1a13 : 48 > pha ;use stack to load status 1a14 : 28 > plp -1a15 : ad1802 lda abs1+1 +1a15 : ad1902 lda abs1+1 1a18 : 08 php ;test stores do not alter flags 1a19 : 49c3 eor #$c3 1a1b : 28 plp 1a1c : 850d sta zpt+1 1a1e : 08 php ;flags after load/store sequence 1a1f : 49c3 eor #$c3 -1a21 : c514 cmp zp1+1 ;test result +1a21 : c516 cmp zp1+1 ;test result trap_ne 1a23 : d0fe > bne * ;failed not equal (non zero) @@ -6607,7 +6609,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1a26 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1a28 : cd1d02 cmp fLDx+1 ;test flags +1a28 : cd1e02 cmp fLDx+1 ;test flags trap_ne 1a2b : d0fe > bne * ;failed not equal (non zero) @@ -6618,14 +6620,14 @@ ffff = ram_top = -1 1a2f : 48 > pha ;use stack to load status 1a30 : 28 > plp -1a31 : ad1902 lda abs1+2 +1a31 : ad1a02 lda abs1+2 1a34 : 08 php ;test stores do not alter flags 1a35 : 49c3 eor #$c3 1a37 : 28 plp 1a38 : 850e sta zpt+2 1a3a : 08 php ;flags after load/store sequence 1a3b : 49c3 eor #$c3 -1a3d : c515 cmp zp1+2 ;test result +1a3d : c517 cmp zp1+2 ;test result trap_ne 1a3f : d0fe > bne * ;failed not equal (non zero) @@ -6633,7 +6635,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1a42 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1a44 : cd1e02 cmp fLDx+2 ;test flags +1a44 : cd1f02 cmp fLDx+2 ;test flags trap_ne 1a47 : d0fe > bne * ;failed not equal (non zero) @@ -6644,14 +6646,14 @@ ffff = ram_top = -1 1a4b : 48 > pha ;use stack to load status 1a4c : 28 > plp -1a4d : ad1a02 lda abs1+3 +1a4d : ad1b02 lda abs1+3 1a50 : 08 php ;test stores do not alter flags 1a51 : 49c3 eor #$c3 1a53 : 28 plp 1a54 : 850f sta zpt+3 1a56 : 08 php ;flags after load/store sequence 1a57 : 49c3 eor #$c3 -1a59 : c516 cmp zp1+3 ;test result +1a59 : c518 cmp zp1+3 ;test result trap_ne 1a5b : d0fe > bne * ;failed not equal (non zero) @@ -6659,7 +6661,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1a5e : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1a60 : cd1f02 cmp fLDx+3 ;test flags +1a60 : cd2002 cmp fLDx+3 ;test flags trap_ne 1a63 : d0fe > bne * ;failed not equal (non zero) @@ -6672,7 +6674,7 @@ ffff = ram_top = -1 1a69 : a9c3 lda #$c3 1a6b : 08 php -1a6c : cd1702 cmp abs1 ;test result +1a6c : cd1802 cmp abs1 ;test result trap_ne 1a6f : d0fe > bne * ;failed not equal (non zero) @@ -6680,7 +6682,7 @@ ffff = ram_top = -1 eor_flag 0 1a72 : 4930 > eor #0|fao ;invert expected flags + always on bits -1a74 : cd1c02 cmp fLDx ;test flags +1a74 : cd1d02 cmp fLDx ;test flags trap_ne 1a77 : d0fe > bne * ;failed not equal (non zero) @@ -6693,7 +6695,7 @@ ffff = ram_top = -1 1a7d : a982 lda #$82 1a7f : 08 php -1a80 : cd1802 cmp abs1+1 ;test result +1a80 : cd1902 cmp abs1+1 ;test result trap_ne 1a83 : d0fe > bne * ;failed not equal (non zero) @@ -6701,7 +6703,7 @@ ffff = ram_top = -1 eor_flag 0 1a86 : 4930 > eor #0|fao ;invert expected flags + always on bits -1a88 : cd1d02 cmp fLDx+1 ;test flags +1a88 : cd1e02 cmp fLDx+1 ;test flags trap_ne 1a8b : d0fe > bne * ;failed not equal (non zero) @@ -6714,7 +6716,7 @@ ffff = ram_top = -1 1a91 : a941 lda #$41 1a93 : 08 php -1a94 : cd1902 cmp abs1+2 ;test result +1a94 : cd1a02 cmp abs1+2 ;test result trap_ne 1a97 : d0fe > bne * ;failed not equal (non zero) @@ -6722,7 +6724,7 @@ ffff = ram_top = -1 eor_flag 0 1a9a : 4930 > eor #0|fao ;invert expected flags + always on bits -1a9c : cd1e02 cmp fLDx+2 ;test flags +1a9c : cd1f02 cmp fLDx+2 ;test flags trap_ne 1a9f : d0fe > bne * ;failed not equal (non zero) @@ -6735,7 +6737,7 @@ ffff = ram_top = -1 1aa5 : a900 lda #0 1aa7 : 08 php -1aa8 : cd1a02 cmp abs1+3 ;test result +1aa8 : cd1b02 cmp abs1+3 ;test result trap_ne 1aab : d0fe > bne * ;failed not equal (non zero) @@ -6743,7 +6745,7 @@ ffff = ram_top = -1 eor_flag 0 1aae : 4930 > eor #0|fao ;invert expected flags + always on bits -1ab0 : cd1f02 cmp fLDx+3 ;test flags +1ab0 : cd2002 cmp fLDx+3 ;test flags trap_ne 1ab3 : d0fe > bne * ;failed not equal (non zero) @@ -6757,7 +6759,7 @@ ffff = ram_top = -1 1ab9 : a9c3 lda #$c3 1abb : 08 php -1abc : cd1702 cmp abs1 ;test result +1abc : cd1802 cmp abs1 ;test result trap_ne 1abf : d0fe > bne * ;failed not equal (non zero) @@ -6765,7 +6767,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1ac2 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1ac4 : cd1c02 cmp fLDx ;test flags +1ac4 : cd1d02 cmp fLDx ;test flags trap_ne 1ac7 : d0fe > bne * ;failed not equal (non zero) @@ -6778,7 +6780,7 @@ ffff = ram_top = -1 1acd : a982 lda #$82 1acf : 08 php -1ad0 : cd1802 cmp abs1+1 ;test result +1ad0 : cd1902 cmp abs1+1 ;test result trap_ne 1ad3 : d0fe > bne * ;failed not equal (non zero) @@ -6786,7 +6788,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1ad6 : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1ad8 : cd1d02 cmp fLDx+1 ;test flags +1ad8 : cd1e02 cmp fLDx+1 ;test flags trap_ne 1adb : d0fe > bne * ;failed not equal (non zero) @@ -6799,7 +6801,7 @@ ffff = ram_top = -1 1ae1 : a941 lda #$41 1ae3 : 08 php -1ae4 : cd1902 cmp abs1+2 ;test result +1ae4 : cd1a02 cmp abs1+2 ;test result trap_ne 1ae7 : d0fe > bne * ;failed not equal (non zero) @@ -6807,7 +6809,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1aea : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1aec : cd1e02 cmp fLDx+2 ;test flags +1aec : cd1f02 cmp fLDx+2 ;test flags trap_ne 1aef : d0fe > bne * ;failed not equal (non zero) @@ -6820,7 +6822,7 @@ ffff = ram_top = -1 1af5 : a900 lda #0 1af7 : 08 php -1af8 : cd1a02 cmp abs1+3 ;test result +1af8 : cd1b02 cmp abs1+3 ;test result trap_ne 1afb : d0fe > bne * ;failed not equal (non zero) @@ -6828,7 +6830,7 @@ ffff = ram_top = -1 eor_flag lo~fnz ;mask bits not altered 1afe : 497d > eor #lo~fnz |fao ;invert expected flags + always on bits -1b00 : cd1f02 cmp fLDx+3 ;test flags +1b00 : cd2002 cmp fLDx+3 ;test flags trap_ne 1b03 : d0fe > bne * ;failed not equal (non zero) @@ -6836,56 +6838,56 @@ ffff = ram_top = -1 1b05 : a200 ldx #0 1b07 : a50c lda zpt 1b09 : 49c3 eor #$c3 -1b0b : c513 cmp zp1 +1b0b : c515 cmp zp1 trap_ne ;store to zp data 1b0d : d0fe > bne * ;failed not equal (non zero) 1b0f : 860c stx zpt ;clear 1b11 : ad0302 lda abst 1b14 : 49c3 eor #$c3 -1b16 : cd1702 cmp abs1 +1b16 : cd1802 cmp abs1 trap_ne ;store to abs data 1b19 : d0fe > bne * ;failed not equal (non zero) 1b1b : 8e0302 stx abst ;clear 1b1e : a50d lda zpt+1 1b20 : 49c3 eor #$c3 -1b22 : c514 cmp zp1+1 +1b22 : c516 cmp zp1+1 trap_ne ;store to zp data 1b24 : d0fe > bne * ;failed not equal (non zero) 1b26 : 860d stx zpt+1 ;clear 1b28 : ad0402 lda abst+1 1b2b : 49c3 eor #$c3 -1b2d : cd1802 cmp abs1+1 +1b2d : cd1902 cmp abs1+1 trap_ne ;store to abs data 1b30 : d0fe > bne * ;failed not equal (non zero) 1b32 : 8e0402 stx abst+1 ;clear 1b35 : a50e lda zpt+2 1b37 : 49c3 eor #$c3 -1b39 : c515 cmp zp1+2 +1b39 : c517 cmp zp1+2 trap_ne ;store to zp data 1b3b : d0fe > bne * ;failed not equal (non zero) 1b3d : 860e stx zpt+2 ;clear 1b3f : ad0502 lda abst+2 1b42 : 49c3 eor #$c3 -1b44 : cd1902 cmp abs1+2 +1b44 : cd1a02 cmp abs1+2 trap_ne ;store to abs data 1b47 : d0fe > bne * ;failed not equal (non zero) 1b49 : 8e0502 stx abst+2 ;clear 1b4c : a50f lda zpt+3 1b4e : 49c3 eor #$c3 -1b50 : c516 cmp zp1+3 +1b50 : c518 cmp zp1+3 trap_ne ;store to zp data 1b52 : d0fe > bne * ;failed not equal (non zero) 1b54 : 860f stx zpt+3 ;clear 1b56 : ad0602 lda abst+3 1b59 : 49c3 eor #$c3 -1b5b : cd1a02 cmp abs1+3 +1b5b : cd1b02 cmp abs1+3 trap_ne ;store to abs data 1b5e : d0fe > bne * ;failed not equal (non zero) @@ -6912,7 +6914,7 @@ ffff = ram_top = -1 1b72 : a9ff > lda #$ff ;precharge accu 1b74 : 28 > plp -1b75 : 2416 bit zp1+3 ;00 - should set Z / clear NV +1b75 : 2418 bit zp1+3 ;00 - should set Z / clear NV tst_a $ff,fz 1b77 : 08 > php ;save flags 1b78 : c9ff > cmp #$ff ;test result @@ -6937,7 +6939,7 @@ ffff = ram_top = -1 1b86 : a901 > lda #1 ;precharge accu 1b88 : 28 > plp -1b89 : 2415 bit zp1+2 ;41 - should set V (M6) / clear NZ +1b89 : 2417 bit zp1+2 ;41 - should set V (M6) / clear NZ tst_a 1,fv 1b8b : 08 > php ;save flags 1b8c : c901 > cmp #1 ;test result @@ -6962,7 +6964,7 @@ ffff = ram_top = -1 1b9a : a901 > lda #1 ;precharge accu 1b9c : 28 > plp -1b9d : 2414 bit zp1+1 ;82 - should set N (M7) & Z / clear V +1b9d : 2416 bit zp1+1 ;82 - should set N (M7) & Z / clear V tst_a 1,fnz 1b9f : 08 > php ;save flags 1ba0 : c901 > cmp #1 ;test result @@ -6987,7 +6989,7 @@ ffff = ram_top = -1 1bae : a901 > lda #1 ;precharge accu 1bb0 : 28 > plp -1bb1 : 2413 bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z +1bb1 : 2415 bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z tst_a 1,fnv 1bb3 : 08 > php ;save flags 1bb4 : c901 > cmp #1 ;test result @@ -7013,7 +7015,7 @@ ffff = ram_top = -1 1bc2 : a9ff > lda #$ff ;precharge accu 1bc4 : 28 > plp -1bc5 : 2416 bit zp1+3 ;00 - should set Z / clear NV +1bc5 : 2418 bit zp1+3 ;00 - should set Z / clear NV tst_a $ff,~fnv 1bc7 : 08 > php ;save flags 1bc8 : c9ff > cmp #$ff ;test result @@ -7038,7 +7040,7 @@ ffff = ram_top = -1 1bd6 : a901 > lda #1 ;precharge accu 1bd8 : 28 > plp -1bd9 : 2415 bit zp1+2 ;41 - should set V (M6) / clear NZ +1bd9 : 2417 bit zp1+2 ;41 - should set V (M6) / clear NZ tst_a 1,~fnz 1bdb : 08 > php ;save flags 1bdc : c901 > cmp #1 ;test result @@ -7063,7 +7065,7 @@ ffff = ram_top = -1 1bea : a901 > lda #1 ;precharge accu 1bec : 28 > plp -1bed : 2414 bit zp1+1 ;82 - should set N (M7) & Z / clear V +1bed : 2416 bit zp1+1 ;82 - should set N (M7) & Z / clear V tst_a 1,~fv 1bef : 08 > php ;save flags 1bf0 : c901 > cmp #1 ;test result @@ -7088,7 +7090,7 @@ ffff = ram_top = -1 1bfe : a901 > lda #1 ;precharge accu 1c00 : 28 > plp -1c01 : 2413 bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z +1c01 : 2415 bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z tst_a 1,~fz 1c03 : 08 > php ;save flags 1c04 : c901 > cmp #1 ;test result @@ -7114,7 +7116,7 @@ ffff = ram_top = -1 1c12 : a9ff > lda #$ff ;precharge accu 1c14 : 28 > plp -1c15 : 2c1a02 bit abs1+3 ;00 - should set Z / clear NV +1c15 : 2c1b02 bit abs1+3 ;00 - should set Z / clear NV tst_a $ff,fz 1c18 : 08 > php ;save flags 1c19 : c9ff > cmp #$ff ;test result @@ -7139,7 +7141,7 @@ ffff = ram_top = -1 1c27 : a901 > lda #1 ;precharge accu 1c29 : 28 > plp -1c2a : 2c1902 bit abs1+2 ;41 - should set V (M6) / clear NZ +1c2a : 2c1a02 bit abs1+2 ;41 - should set V (M6) / clear NZ tst_a 1,fv 1c2d : 08 > php ;save flags 1c2e : c901 > cmp #1 ;test result @@ -7164,7 +7166,7 @@ ffff = ram_top = -1 1c3c : a901 > lda #1 ;precharge accu 1c3e : 28 > plp -1c3f : 2c1802 bit abs1+1 ;82 - should set N (M7) & Z / clear V +1c3f : 2c1902 bit abs1+1 ;82 - should set N (M7) & Z / clear V tst_a 1,fnz 1c42 : 08 > php ;save flags 1c43 : c901 > cmp #1 ;test result @@ -7189,7 +7191,7 @@ ffff = ram_top = -1 1c51 : a901 > lda #1 ;precharge accu 1c53 : 28 > plp -1c54 : 2c1702 bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z +1c54 : 2c1802 bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z tst_a 1,fnv 1c57 : 08 > php ;save flags 1c58 : c901 > cmp #1 ;test result @@ -7215,7 +7217,7 @@ ffff = ram_top = -1 1c66 : a9ff > lda #$ff ;precharge accu 1c68 : 28 > plp -1c69 : 2c1a02 bit abs1+3 ;00 - should set Z / clear NV +1c69 : 2c1b02 bit abs1+3 ;00 - should set Z / clear NV tst_a $ff,~fnv 1c6c : 08 > php ;save flags 1c6d : c9ff > cmp #$ff ;test result @@ -7240,7 +7242,7 @@ ffff = ram_top = -1 1c7b : a901 > lda #1 ;precharge accu 1c7d : 28 > plp -1c7e : 2c1902 bit abs1+2 ;41 - should set V (M6) / clear NZ +1c7e : 2c1a02 bit abs1+2 ;41 - should set V (M6) / clear NZ tst_a 1,~fnz 1c81 : 08 > php ;save flags 1c82 : c901 > cmp #1 ;test result @@ -7265,7 +7267,7 @@ ffff = ram_top = -1 1c90 : a901 > lda #1 ;precharge accu 1c92 : 28 > plp -1c93 : 2c1802 bit abs1+1 ;82 - should set N (M7) & Z / clear V +1c93 : 2c1902 bit abs1+1 ;82 - should set N (M7) & Z / clear V tst_a 1,~fv 1c96 : 08 > php ;save flags 1c97 : c901 > cmp #1 ;test result @@ -7290,7 +7292,7 @@ ffff = ram_top = -1 1ca5 : a901 > lda #1 ;precharge accu 1ca7 : 28 > plp -1ca8 : 2c1702 bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z +1ca8 : 2c1802 bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z tst_a 1,~fz 1cab : 08 > php ;save flags 1cac : c901 > cmp #1 ;test result @@ -7328,7 +7330,7 @@ ffff = ram_top = -1 1cc6 : a280 > ldx #$80 ;precharge index x 1cc8 : 28 > plp -1cc9 : e417 cpx zp7f +1cc9 : e419 cpx zp7f tst_stat fc 1ccb : 08 > php ;save status 1ccc : 68 > pla ;use stack to retrieve status @@ -7342,7 +7344,7 @@ ffff = ram_top = -1 1cd2 : 28 > plp ;restore status 1cd3 : ca dex -1cd4 : e417 cpx zp7f +1cd4 : e419 cpx zp7f tst_stat fzc 1cd6 : 08 > php ;save status 1cd7 : 68 > pla ;use stack to retrieve status @@ -7356,7 +7358,7 @@ ffff = ram_top = -1 1cdd : 28 > plp ;restore status 1cde : ca dex -1cdf : e417 cpx zp7f +1cdf : e419 cpx zp7f tst_x $7e,fn 1ce1 : 08 > php ;save flags 1ce2 : e07e > cpx #$7e ;test result @@ -7381,7 +7383,7 @@ ffff = ram_top = -1 1cf0 : a280 > ldx #$80 ;precharge index x 1cf2 : 28 > plp -1cf3 : e417 cpx zp7f +1cf3 : e419 cpx zp7f tst_stat ~fnz 1cf5 : 08 > php ;save status 1cf6 : 68 > pla ;use stack to retrieve status @@ -7395,7 +7397,7 @@ ffff = ram_top = -1 1cfc : 28 > plp ;restore status 1cfd : ca dex -1cfe : e417 cpx zp7f +1cfe : e419 cpx zp7f tst_stat ~fn 1d00 : 08 > php ;save status 1d01 : 68 > pla ;use stack to retrieve status @@ -7409,7 +7411,7 @@ ffff = ram_top = -1 1d07 : 28 > plp ;restore status 1d08 : ca dex -1d09 : e417 cpx zp7f +1d09 : e419 cpx zp7f tst_x $7e,~fzc 1d0b : 08 > php ;save flags 1d0c : e07e > cpx #$7e ;test result @@ -7435,7 +7437,7 @@ ffff = ram_top = -1 1d1a : a280 > ldx #$80 ;precharge index x 1d1c : 28 > plp -1d1d : ec1b02 cpx abs7f +1d1d : ec1c02 cpx abs7f tst_stat fc 1d20 : 08 > php ;save status 1d21 : 68 > pla ;use stack to retrieve status @@ -7449,7 +7451,7 @@ ffff = ram_top = -1 1d27 : 28 > plp ;restore status 1d28 : ca dex -1d29 : ec1b02 cpx abs7f +1d29 : ec1c02 cpx abs7f tst_stat fzc 1d2c : 08 > php ;save status 1d2d : 68 > pla ;use stack to retrieve status @@ -7463,7 +7465,7 @@ ffff = ram_top = -1 1d33 : 28 > plp ;restore status 1d34 : ca dex -1d35 : ec1b02 cpx abs7f +1d35 : ec1c02 cpx abs7f tst_x $7e,fn 1d38 : 08 > php ;save flags 1d39 : e07e > cpx #$7e ;test result @@ -7488,7 +7490,7 @@ ffff = ram_top = -1 1d47 : a280 > ldx #$80 ;precharge index x 1d49 : 28 > plp -1d4a : ec1b02 cpx abs7f +1d4a : ec1c02 cpx abs7f tst_stat ~fnz 1d4d : 08 > php ;save status 1d4e : 68 > pla ;use stack to retrieve status @@ -7502,7 +7504,7 @@ ffff = ram_top = -1 1d54 : 28 > plp ;restore status 1d55 : ca dex -1d56 : ec1b02 cpx abs7f +1d56 : ec1c02 cpx abs7f tst_stat ~fn 1d59 : 08 > php ;save status 1d5a : 68 > pla ;use stack to retrieve status @@ -7516,7 +7518,7 @@ ffff = ram_top = -1 1d60 : 28 > plp ;restore status 1d61 : ca dex -1d62 : ec1b02 cpx abs7f +1d62 : ec1c02 cpx abs7f tst_x $7e,~fzc 1d65 : 08 > php ;save flags 1d66 : e07e > cpx #$7e ;test result @@ -7661,7 +7663,7 @@ ffff = ram_top = -1 1dd4 : a080 > ldy #$80 ;precharge index y 1dd6 : 28 > plp -1dd7 : c417 cpy zp7f +1dd7 : c419 cpy zp7f tst_stat fc 1dd9 : 08 > php ;save status 1dda : 68 > pla ;use stack to retrieve status @@ -7675,7 +7677,7 @@ ffff = ram_top = -1 1de0 : 28 > plp ;restore status 1de1 : 88 dey -1de2 : c417 cpy zp7f +1de2 : c419 cpy zp7f tst_stat fzc 1de4 : 08 > php ;save status 1de5 : 68 > pla ;use stack to retrieve status @@ -7689,7 +7691,7 @@ ffff = ram_top = -1 1deb : 28 > plp ;restore status 1dec : 88 dey -1ded : c417 cpy zp7f +1ded : c419 cpy zp7f tst_y $7e,fn 1def : 08 > php ;save flags 1df0 : c07e > cpy #$7e ;test result @@ -7714,7 +7716,7 @@ ffff = ram_top = -1 1dfe : a080 > ldy #$80 ;precharge index y 1e00 : 28 > plp -1e01 : c417 cpy zp7f +1e01 : c419 cpy zp7f tst_stat ~fnz 1e03 : 08 > php ;save status 1e04 : 68 > pla ;use stack to retrieve status @@ -7728,7 +7730,7 @@ ffff = ram_top = -1 1e0a : 28 > plp ;restore status 1e0b : 88 dey -1e0c : c417 cpy zp7f +1e0c : c419 cpy zp7f tst_stat ~fn 1e0e : 08 > php ;save status 1e0f : 68 > pla ;use stack to retrieve status @@ -7742,7 +7744,7 @@ ffff = ram_top = -1 1e15 : 28 > plp ;restore status 1e16 : 88 dey -1e17 : c417 cpy zp7f +1e17 : c419 cpy zp7f tst_y $7e,~fzc 1e19 : 08 > php ;save flags 1e1a : c07e > cpy #$7e ;test result @@ -7768,7 +7770,7 @@ ffff = ram_top = -1 1e28 : a080 > ldy #$80 ;precharge index y 1e2a : 28 > plp -1e2b : cc1b02 cpy abs7f +1e2b : cc1c02 cpy abs7f tst_stat fc 1e2e : 08 > php ;save status 1e2f : 68 > pla ;use stack to retrieve status @@ -7782,7 +7784,7 @@ ffff = ram_top = -1 1e35 : 28 > plp ;restore status 1e36 : 88 dey -1e37 : cc1b02 cpy abs7f +1e37 : cc1c02 cpy abs7f tst_stat fzc 1e3a : 08 > php ;save status 1e3b : 68 > pla ;use stack to retrieve status @@ -7796,7 +7798,7 @@ ffff = ram_top = -1 1e41 : 28 > plp ;restore status 1e42 : 88 dey -1e43 : cc1b02 cpy abs7f +1e43 : cc1c02 cpy abs7f tst_y $7e,fn 1e46 : 08 > php ;save flags 1e47 : c07e > cpy #$7e ;test result @@ -7821,7 +7823,7 @@ ffff = ram_top = -1 1e55 : a080 > ldy #$80 ;precharge index y 1e57 : 28 > plp -1e58 : cc1b02 cpy abs7f +1e58 : cc1c02 cpy abs7f tst_stat ~fnz 1e5b : 08 > php ;save status 1e5c : 68 > pla ;use stack to retrieve status @@ -7835,7 +7837,7 @@ ffff = ram_top = -1 1e62 : 28 > plp ;restore status 1e63 : 88 dey -1e64 : cc1b02 cpy abs7f +1e64 : cc1c02 cpy abs7f tst_stat ~fn 1e67 : 08 > php ;save status 1e68 : 68 > pla ;use stack to retrieve status @@ -7849,7 +7851,7 @@ ffff = ram_top = -1 1e6e : 28 > plp ;restore status 1e6f : 88 dey -1e70 : cc1b02 cpy abs7f +1e70 : cc1c02 cpy abs7f tst_y $7e,~fzc 1e73 : 08 > php ;save flags 1e74 : c07e > cpy #$7e ;test result @@ -7994,7 +7996,7 @@ ffff = ram_top = -1 1ee2 : a980 > lda #$80 ;precharge accu 1ee4 : 28 > plp -1ee5 : c517 cmp zp7f +1ee5 : c519 cmp zp7f tst_a $80,fc 1ee7 : 08 > php ;save flags 1ee8 : c980 > cmp #$80 ;test result @@ -8019,7 +8021,7 @@ ffff = ram_top = -1 1ef6 : a97f > lda #$7f ;precharge accu 1ef8 : 28 > plp -1ef9 : c517 cmp zp7f +1ef9 : c519 cmp zp7f tst_a $7f,fzc 1efb : 08 > php ;save flags 1efc : c97f > cmp #$7f ;test result @@ -8044,7 +8046,7 @@ ffff = ram_top = -1 1f0a : a97e > lda #$7e ;precharge accu 1f0c : 28 > plp -1f0d : c517 cmp zp7f +1f0d : c519 cmp zp7f tst_a $7e,fn 1f0f : 08 > php ;save flags 1f10 : c97e > cmp #$7e ;test result @@ -8069,7 +8071,7 @@ ffff = ram_top = -1 1f1e : a980 > lda #$80 ;precharge accu 1f20 : 28 > plp -1f21 : c517 cmp zp7f +1f21 : c519 cmp zp7f tst_a $80,~fnz 1f23 : 08 > php ;save flags 1f24 : c980 > cmp #$80 ;test result @@ -8094,7 +8096,7 @@ ffff = ram_top = -1 1f32 : a97f > lda #$7f ;precharge accu 1f34 : 28 > plp -1f35 : c517 cmp zp7f +1f35 : c519 cmp zp7f tst_a $7f,~fn 1f37 : 08 > php ;save flags 1f38 : c97f > cmp #$7f ;test result @@ -8119,7 +8121,7 @@ ffff = ram_top = -1 1f46 : a97e > lda #$7e ;precharge accu 1f48 : 28 > plp -1f49 : c517 cmp zp7f +1f49 : c519 cmp zp7f tst_a $7e,~fzc 1f4b : 08 > php ;save flags 1f4c : c97e > cmp #$7e ;test result @@ -8145,7 +8147,7 @@ ffff = ram_top = -1 1f5a : a980 > lda #$80 ;precharge accu 1f5c : 28 > plp -1f5d : cd1b02 cmp abs7f +1f5d : cd1c02 cmp abs7f tst_a $80,fc 1f60 : 08 > php ;save flags 1f61 : c980 > cmp #$80 ;test result @@ -8170,7 +8172,7 @@ ffff = ram_top = -1 1f6f : a97f > lda #$7f ;precharge accu 1f71 : 28 > plp -1f72 : cd1b02 cmp abs7f +1f72 : cd1c02 cmp abs7f tst_a $7f,fzc 1f75 : 08 > php ;save flags 1f76 : c97f > cmp #$7f ;test result @@ -8195,7 +8197,7 @@ ffff = ram_top = -1 1f84 : a97e > lda #$7e ;precharge accu 1f86 : 28 > plp -1f87 : cd1b02 cmp abs7f +1f87 : cd1c02 cmp abs7f tst_a $7e,fn 1f8a : 08 > php ;save flags 1f8b : c97e > cmp #$7e ;test result @@ -8220,7 +8222,7 @@ ffff = ram_top = -1 1f99 : a980 > lda #$80 ;precharge accu 1f9b : 28 > plp -1f9c : cd1b02 cmp abs7f +1f9c : cd1c02 cmp abs7f tst_a $80,~fnz 1f9f : 08 > php ;save flags 1fa0 : c980 > cmp #$80 ;test result @@ -8245,7 +8247,7 @@ ffff = ram_top = -1 1fae : a97f > lda #$7f ;precharge accu 1fb0 : 28 > plp -1fb1 : cd1b02 cmp abs7f +1fb1 : cd1c02 cmp abs7f tst_a $7f,~fn 1fb4 : 08 > php ;save flags 1fb5 : c97f > cmp #$7f ;test result @@ -8270,7 +8272,7 @@ ffff = ram_top = -1 1fc3 : a97e > lda #$7e ;precharge accu 1fc5 : 28 > plp -1fc6 : cd1b02 cmp abs7f +1fc6 : cd1c02 cmp abs7f tst_a $7e,~fzc 1fc9 : 08 > php ;save flags 1fca : c97e > cmp #$7e ;test result @@ -8448,7 +8450,7 @@ ffff = ram_top = -1 2052 : a980 > lda #$80 ;precharge accu 2054 : 28 > plp -2055 : d513 cmp zp1,x +2055 : d515 cmp zp1,x tst_a $80,fc 2057 : 08 > php ;save flags 2058 : c980 > cmp #$80 ;test result @@ -8473,7 +8475,7 @@ ffff = ram_top = -1 2066 : a97f > lda #$7f ;precharge accu 2068 : 28 > plp -2069 : d513 cmp zp1,x +2069 : d515 cmp zp1,x tst_a $7f,fzc 206b : 08 > php ;save flags 206c : c97f > cmp #$7f ;test result @@ -8498,7 +8500,7 @@ ffff = ram_top = -1 207a : a97e > lda #$7e ;precharge accu 207c : 28 > plp -207d : d513 cmp zp1,x +207d : d515 cmp zp1,x tst_a $7e,fn 207f : 08 > php ;save flags 2080 : c97e > cmp #$7e ;test result @@ -8523,7 +8525,7 @@ ffff = ram_top = -1 208e : a980 > lda #$80 ;precharge accu 2090 : 28 > plp -2091 : d513 cmp zp1,x +2091 : d515 cmp zp1,x tst_a $80,~fnz 2093 : 08 > php ;save flags 2094 : c980 > cmp #$80 ;test result @@ -8548,7 +8550,7 @@ ffff = ram_top = -1 20a2 : a97f > lda #$7f ;precharge accu 20a4 : 28 > plp -20a5 : d513 cmp zp1,x +20a5 : d515 cmp zp1,x tst_a $7f,~fn 20a7 : 08 > php ;save flags 20a8 : c97f > cmp #$7f ;test result @@ -8573,7 +8575,7 @@ ffff = ram_top = -1 20b6 : a97e > lda #$7e ;precharge accu 20b8 : 28 > plp -20b9 : d513 cmp zp1,x +20b9 : d515 cmp zp1,x tst_a $7e,~fzc 20bb : 08 > php ;save flags 20bc : c97e > cmp #$7e ;test result @@ -8599,7 +8601,7 @@ ffff = ram_top = -1 20ca : a980 > lda #$80 ;precharge accu 20cc : 28 > plp -20cd : dd1702 cmp abs1,x +20cd : dd1802 cmp abs1,x tst_a $80,fc 20d0 : 08 > php ;save flags 20d1 : c980 > cmp #$80 ;test result @@ -8624,7 +8626,7 @@ ffff = ram_top = -1 20df : a97f > lda #$7f ;precharge accu 20e1 : 28 > plp -20e2 : dd1702 cmp abs1,x +20e2 : dd1802 cmp abs1,x tst_a $7f,fzc 20e5 : 08 > php ;save flags 20e6 : c97f > cmp #$7f ;test result @@ -8649,7 +8651,7 @@ ffff = ram_top = -1 20f4 : a97e > lda #$7e ;precharge accu 20f6 : 28 > plp -20f7 : dd1702 cmp abs1,x +20f7 : dd1802 cmp abs1,x tst_a $7e,fn 20fa : 08 > php ;save flags 20fb : c97e > cmp #$7e ;test result @@ -8674,7 +8676,7 @@ ffff = ram_top = -1 2109 : a980 > lda #$80 ;precharge accu 210b : 28 > plp -210c : dd1702 cmp abs1,x +210c : dd1802 cmp abs1,x tst_a $80,~fnz 210f : 08 > php ;save flags 2110 : c980 > cmp #$80 ;test result @@ -8699,7 +8701,7 @@ ffff = ram_top = -1 211e : a97f > lda #$7f ;precharge accu 2120 : 28 > plp -2121 : dd1702 cmp abs1,x +2121 : dd1802 cmp abs1,x tst_a $7f,~fn 2124 : 08 > php ;save flags 2125 : c97f > cmp #$7f ;test result @@ -8724,7 +8726,7 @@ ffff = ram_top = -1 2133 : a97e > lda #$7e ;precharge accu 2135 : 28 > plp -2136 : dd1702 cmp abs1,x +2136 : dd1802 cmp abs1,x tst_a $7e,~fzc 2139 : 08 > php ;save flags 213a : c97e > cmp #$7e ;test result @@ -8752,7 +8754,7 @@ ffff = ram_top = -1 214c : a980 > lda #$80 ;precharge accu 214e : 28 > plp -214f : d91702 cmp abs1,y +214f : d91802 cmp abs1,y tst_a $80,fc 2152 : 08 > php ;save flags 2153 : c980 > cmp #$80 ;test result @@ -8777,7 +8779,7 @@ ffff = ram_top = -1 2161 : a97f > lda #$7f ;precharge accu 2163 : 28 > plp -2164 : d91702 cmp abs1,y +2164 : d91802 cmp abs1,y tst_a $7f,fzc 2167 : 08 > php ;save flags 2168 : c97f > cmp #$7f ;test result @@ -8802,7 +8804,7 @@ ffff = ram_top = -1 2176 : a97e > lda #$7e ;precharge accu 2178 : 28 > plp -2179 : d91702 cmp abs1,y +2179 : d91802 cmp abs1,y tst_a $7e,fn 217c : 08 > php ;save flags 217d : c97e > cmp #$7e ;test result @@ -8827,7 +8829,7 @@ ffff = ram_top = -1 218b : a980 > lda #$80 ;precharge accu 218d : 28 > plp -218e : d91702 cmp abs1,y +218e : d91802 cmp abs1,y tst_a $80,~fnz 2191 : 08 > php ;save flags 2192 : c980 > cmp #$80 ;test result @@ -8852,7 +8854,7 @@ ffff = ram_top = -1 21a0 : a97f > lda #$7f ;precharge accu 21a2 : 28 > plp -21a3 : d91702 cmp abs1,y +21a3 : d91802 cmp abs1,y tst_a $7f,~fn 21a6 : 08 > php ;save flags 21a7 : c97f > cmp #$7f ;test result @@ -8877,7 +8879,7 @@ ffff = ram_top = -1 21b5 : a97e > lda #$7e ;precharge accu 21b7 : 28 > plp -21b8 : d91702 cmp abs1,y +21b8 : d91802 cmp abs1,y tst_a $7e,~fzc 21bb : 08 > php ;save flags 21bc : c97e > cmp #$7e ;test result @@ -8903,7 +8905,7 @@ ffff = ram_top = -1 21ca : a980 > lda #$80 ;precharge accu 21cc : 28 > plp -21cd : c124 cmp (ind1,x) +21cd : c126 cmp (ind1,x) tst_a $80,fc 21cf : 08 > php ;save flags 21d0 : c980 > cmp #$80 ;test result @@ -8928,7 +8930,7 @@ ffff = ram_top = -1 21de : a97f > lda #$7f ;precharge accu 21e0 : 28 > plp -21e1 : c124 cmp (ind1,x) +21e1 : c126 cmp (ind1,x) tst_a $7f,fzc 21e3 : 08 > php ;save flags 21e4 : c97f > cmp #$7f ;test result @@ -8953,7 +8955,7 @@ ffff = ram_top = -1 21f2 : a97e > lda #$7e ;precharge accu 21f4 : 28 > plp -21f5 : c124 cmp (ind1,x) +21f5 : c126 cmp (ind1,x) tst_a $7e,fn 21f7 : 08 > php ;save flags 21f8 : c97e > cmp #$7e ;test result @@ -8978,7 +8980,7 @@ ffff = ram_top = -1 2206 : a980 > lda #$80 ;precharge accu 2208 : 28 > plp -2209 : c124 cmp (ind1,x) +2209 : c126 cmp (ind1,x) tst_a $80,~fnz 220b : 08 > php ;save flags 220c : c980 > cmp #$80 ;test result @@ -9003,7 +9005,7 @@ ffff = ram_top = -1 221a : a97f > lda #$7f ;precharge accu 221c : 28 > plp -221d : c124 cmp (ind1,x) +221d : c126 cmp (ind1,x) tst_a $7f,~fn 221f : 08 > php ;save flags 2220 : c97f > cmp #$7f ;test result @@ -9028,7 +9030,7 @@ ffff = ram_top = -1 222e : a97e > lda #$7e ;precharge accu 2230 : 28 > plp -2231 : c124 cmp (ind1,x) +2231 : c126 cmp (ind1,x) tst_a $7e,~fzc 2233 : 08 > php ;save flags 2234 : c97e > cmp #$7e ;test result @@ -9054,7 +9056,7 @@ ffff = ram_top = -1 2242 : a980 > lda #$80 ;precharge accu 2244 : 28 > plp -2245 : d124 cmp (ind1),y +2245 : d126 cmp (ind1),y tst_a $80,fc 2247 : 08 > php ;save flags 2248 : c980 > cmp #$80 ;test result @@ -9079,7 +9081,7 @@ ffff = ram_top = -1 2256 : a97f > lda #$7f ;precharge accu 2258 : 28 > plp -2259 : d124 cmp (ind1),y +2259 : d126 cmp (ind1),y tst_a $7f,fzc 225b : 08 > php ;save flags 225c : c97f > cmp #$7f ;test result @@ -9104,7 +9106,7 @@ ffff = ram_top = -1 226a : a97e > lda #$7e ;precharge accu 226c : 28 > plp -226d : d124 cmp (ind1),y +226d : d126 cmp (ind1),y tst_a $7e,fn 226f : 08 > php ;save flags 2270 : c97e > cmp #$7e ;test result @@ -9129,7 +9131,7 @@ ffff = ram_top = -1 227e : a980 > lda #$80 ;precharge accu 2280 : 28 > plp -2281 : d124 cmp (ind1),y +2281 : d126 cmp (ind1),y tst_a $80,~fnz 2283 : 08 > php ;save flags 2284 : c980 > cmp #$80 ;test result @@ -9154,7 +9156,7 @@ ffff = ram_top = -1 2292 : a97f > lda #$7f ;precharge accu 2294 : 28 > plp -2295 : d124 cmp (ind1),y +2295 : d126 cmp (ind1),y tst_a $7f,~fn 2297 : 08 > php ;save flags 2298 : c97f > cmp #$7f ;test result @@ -9179,7 +9181,7 @@ ffff = ram_top = -1 22a6 : a97e > lda #$7e ;precharge accu 22a8 : 28 > plp -22a9 : d124 cmp (ind1),y +22a9 : d126 cmp (ind1),y tst_a $7e,~fzc 22ab : 08 > php ;save flags 22ac : c97e > cmp #$7e ;test result @@ -9210,20 +9212,20 @@ ffff = ram_top = -1 ; testing shifts - ASL LSR ROL ROR all addressing modes ; shifts - accumulator -22c3 : a203 ldx #3 +22c3 : a205 ldx #5 22c5 : tasl - set_ax zp1,0 + set_ax zps,0 > load_flag 0 22c5 : a900 > lda #0 ;allow test to change I-flag (no mask) > 22c7 : 48 > pha ;use stack to load status -22c8 : b513 > lda zp1,x ;precharge accu +22c8 : b513 > lda zps,x ;precharge accu 22ca : 28 > plp 22cb : 0a asl a tst_ax rASL,fASL,0 22cc : 08 > php ;save flags -22cd : dd2002 > cmp rASL,x ;test result +22cd : dd2102 > cmp rASL,x ;test result > trap_ne 22d0 : d0fe > bne * ;failed not equal (non zero) > @@ -9231,27 +9233,27 @@ ffff = ram_top = -1 > eor_flag 0 22d3 : 4930 > eor #0|fao ;invert expected flags + always on bits > -22d5 : dd3002 > cmp fASL,x ;test flags +22d5 : dd3902 > cmp fASL,x ;test flags > trap_ne ; 22d8 : d0fe > bne * ;failed not equal (non zero) > 22da : ca dex 22db : 10e8 bpl tasl -22dd : a203 ldx #3 +22dd : a205 ldx #5 22df : tasl1 - set_ax zp1,$ff + set_ax zps,$ff > load_flag $ff 22df : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 22e1 : 48 > pha ;use stack to load status -22e2 : b513 > lda zp1,x ;precharge accu +22e2 : b513 > lda zps,x ;precharge accu 22e4 : 28 > plp 22e5 : 0a asl a tst_ax rASL,fASL,$ff-fnzc 22e6 : 08 > php ;save flags -22e7 : dd2002 > cmp rASL,x ;test result +22e7 : dd2102 > cmp rASL,x ;test result > trap_ne 22ea : d0fe > bne * ;failed not equal (non zero) > @@ -9259,7 +9261,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 22ed : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -22ef : dd3002 > cmp fASL,x ;test flags +22ef : dd3902 > cmp fASL,x ;test flags > trap_ne ; 22f2 : d0fe > bne * ;failed not equal (non zero) > @@ -9267,20 +9269,20 @@ ffff = ram_top = -1 22f4 : ca dex 22f5 : 10e8 bpl tasl1 -22f7 : a203 ldx #3 +22f7 : a205 ldx #5 22f9 : tlsr - set_ax zp1,0 + set_ax zps,0 > load_flag 0 22f9 : a900 > lda #0 ;allow test to change I-flag (no mask) > 22fb : 48 > pha ;use stack to load status -22fc : b513 > lda zp1,x ;precharge accu +22fc : b513 > lda zps,x ;precharge accu 22fe : 28 > plp 22ff : 4a lsr a tst_ax rLSR,fLSR,0 2300 : 08 > php ;save flags -2301 : dd2802 > cmp rLSR,x ;test result +2301 : dd2d02 > cmp rLSR,x ;test result > trap_ne 2304 : d0fe > bne * ;failed not equal (non zero) > @@ -9288,27 +9290,27 @@ ffff = ram_top = -1 > eor_flag 0 2307 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2309 : dd3802 > cmp fLSR,x ;test flags +2309 : dd4502 > cmp fLSR,x ;test flags > trap_ne ; 230c : d0fe > bne * ;failed not equal (non zero) > 230e : ca dex 230f : 10e8 bpl tlsr -2311 : a203 ldx #3 +2311 : a205 ldx #5 2313 : tlsr1 - set_ax zp1,$ff + set_ax zps,$ff > load_flag $ff 2313 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2315 : 48 > pha ;use stack to load status -2316 : b513 > lda zp1,x ;precharge accu +2316 : b513 > lda zps,x ;precharge accu 2318 : 28 > plp 2319 : 4a lsr a tst_ax rLSR,fLSR,$ff-fnzc 231a : 08 > php ;save flags -231b : dd2802 > cmp rLSR,x ;test result +231b : dd2d02 > cmp rLSR,x ;test result > trap_ne 231e : d0fe > bne * ;failed not equal (non zero) > @@ -9316,7 +9318,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2321 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2323 : dd3802 > cmp fLSR,x ;test flags +2323 : dd4502 > cmp fLSR,x ;test flags > trap_ne ; 2326 : d0fe > bne * ;failed not equal (non zero) > @@ -9324,20 +9326,20 @@ ffff = ram_top = -1 2328 : ca dex 2329 : 10e8 bpl tlsr1 -232b : a203 ldx #3 +232b : a205 ldx #5 232d : trol - set_ax zp1,0 + set_ax zps,0 > load_flag 0 232d : a900 > lda #0 ;allow test to change I-flag (no mask) > 232f : 48 > pha ;use stack to load status -2330 : b513 > lda zp1,x ;precharge accu +2330 : b513 > lda zps,x ;precharge accu 2332 : 28 > plp 2333 : 2a rol a tst_ax rROL,fROL,0 2334 : 08 > php ;save flags -2335 : dd2002 > cmp rROL,x ;test result +2335 : dd2102 > cmp rROL,x ;test result > trap_ne 2338 : d0fe > bne * ;failed not equal (non zero) > @@ -9345,27 +9347,27 @@ ffff = ram_top = -1 > eor_flag 0 233b : 4930 > eor #0|fao ;invert expected flags + always on bits > -233d : dd3002 > cmp fROL,x ;test flags +233d : dd3902 > cmp fROL,x ;test flags > trap_ne ; 2340 : d0fe > bne * ;failed not equal (non zero) > 2342 : ca dex 2343 : 10e8 bpl trol -2345 : a203 ldx #3 +2345 : a205 ldx #5 2347 : trol1 - set_ax zp1,$ff-fc + set_ax zps,$ff-fc > load_flag $ff-fc 2347 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 2349 : 48 > pha ;use stack to load status -234a : b513 > lda zp1,x ;precharge accu +234a : b513 > lda zps,x ;precharge accu 234c : 28 > plp 234d : 2a rol a tst_ax rROL,fROL,$ff-fnzc 234e : 08 > php ;save flags -234f : dd2002 > cmp rROL,x ;test result +234f : dd2102 > cmp rROL,x ;test result > trap_ne 2352 : d0fe > bne * ;failed not equal (non zero) > @@ -9373,7 +9375,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2355 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2357 : dd3002 > cmp fROL,x ;test flags +2357 : dd3902 > cmp fROL,x ;test flags > trap_ne ; 235a : d0fe > bne * ;failed not equal (non zero) > @@ -9381,20 +9383,20 @@ ffff = ram_top = -1 235c : ca dex 235d : 10e8 bpl trol1 -235f : a203 ldx #3 +235f : a205 ldx #5 2361 : trolc - set_ax zp1,fc + set_ax zps,fc > load_flag fc 2361 : a901 > lda #fc ;allow test to change I-flag (no mask) > 2363 : 48 > pha ;use stack to load status -2364 : b513 > lda zp1,x ;precharge accu +2364 : b513 > lda zps,x ;precharge accu 2366 : 28 > plp 2367 : 2a rol a tst_ax rROLc,fROLc,0 2368 : 08 > php ;save flags -2369 : dd2402 > cmp rROLc,x ;test result +2369 : dd2702 > cmp rROLc,x ;test result > trap_ne 236c : d0fe > bne * ;failed not equal (non zero) > @@ -9402,27 +9404,27 @@ ffff = ram_top = -1 > eor_flag 0 236f : 4930 > eor #0|fao ;invert expected flags + always on bits > -2371 : dd3402 > cmp fROLc,x ;test flags +2371 : dd3f02 > cmp fROLc,x ;test flags > trap_ne ; 2374 : d0fe > bne * ;failed not equal (non zero) > 2376 : ca dex 2377 : 10e8 bpl trolc -2379 : a203 ldx #3 +2379 : a205 ldx #5 237b : trolc1 - set_ax zp1,$ff + set_ax zps,$ff > load_flag $ff 237b : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 237d : 48 > pha ;use stack to load status -237e : b513 > lda zp1,x ;precharge accu +237e : b513 > lda zps,x ;precharge accu 2380 : 28 > plp 2381 : 2a rol a tst_ax rROLc,fROLc,$ff-fnzc 2382 : 08 > php ;save flags -2383 : dd2402 > cmp rROLc,x ;test result +2383 : dd2702 > cmp rROLc,x ;test result > trap_ne 2386 : d0fe > bne * ;failed not equal (non zero) > @@ -9430,7 +9432,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2389 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -238b : dd3402 > cmp fROLc,x ;test flags +238b : dd3f02 > cmp fROLc,x ;test flags > trap_ne ; 238e : d0fe > bne * ;failed not equal (non zero) > @@ -9438,20 +9440,20 @@ ffff = ram_top = -1 2390 : ca dex 2391 : 10e8 bpl trolc1 -2393 : a203 ldx #3 +2393 : a205 ldx #5 2395 : tror - set_ax zp1,0 + set_ax zps,0 > load_flag 0 2395 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2397 : 48 > pha ;use stack to load status -2398 : b513 > lda zp1,x ;precharge accu +2398 : b513 > lda zps,x ;precharge accu 239a : 28 > plp 239b : 6a ror a tst_ax rROR,fROR,0 239c : 08 > php ;save flags -239d : dd2802 > cmp rROR,x ;test result +239d : dd2d02 > cmp rROR,x ;test result > trap_ne 23a0 : d0fe > bne * ;failed not equal (non zero) > @@ -9459,27 +9461,27 @@ ffff = ram_top = -1 > eor_flag 0 23a3 : 4930 > eor #0|fao ;invert expected flags + always on bits > -23a5 : dd3802 > cmp fROR,x ;test flags +23a5 : dd4502 > cmp fROR,x ;test flags > trap_ne ; 23a8 : d0fe > bne * ;failed not equal (non zero) > 23aa : ca dex 23ab : 10e8 bpl tror -23ad : a203 ldx #3 +23ad : a205 ldx #5 23af : tror1 - set_ax zp1,$ff-fc + set_ax zps,$ff-fc > load_flag $ff-fc 23af : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 23b1 : 48 > pha ;use stack to load status -23b2 : b513 > lda zp1,x ;precharge accu +23b2 : b513 > lda zps,x ;precharge accu 23b4 : 28 > plp 23b5 : 6a ror a tst_ax rROR,fROR,$ff-fnzc 23b6 : 08 > php ;save flags -23b7 : dd2802 > cmp rROR,x ;test result +23b7 : dd2d02 > cmp rROR,x ;test result > trap_ne 23ba : d0fe > bne * ;failed not equal (non zero) > @@ -9487,7 +9489,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 23bd : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -23bf : dd3802 > cmp fROR,x ;test flags +23bf : dd4502 > cmp fROR,x ;test flags > trap_ne ; 23c2 : d0fe > bne * ;failed not equal (non zero) > @@ -9495,20 +9497,20 @@ ffff = ram_top = -1 23c4 : ca dex 23c5 : 10e8 bpl tror1 -23c7 : a203 ldx #3 +23c7 : a205 ldx #5 23c9 : trorc - set_ax zp1,fc + set_ax zps,fc > load_flag fc 23c9 : a901 > lda #fc ;allow test to change I-flag (no mask) > 23cb : 48 > pha ;use stack to load status -23cc : b513 > lda zp1,x ;precharge accu +23cc : b513 > lda zps,x ;precharge accu 23ce : 28 > plp 23cf : 6a ror a tst_ax rRORc,fRORc,0 23d0 : 08 > php ;save flags -23d1 : dd2c02 > cmp rRORc,x ;test result +23d1 : dd3302 > cmp rRORc,x ;test result > trap_ne 23d4 : d0fe > bne * ;failed not equal (non zero) > @@ -9516,27 +9518,27 @@ ffff = ram_top = -1 > eor_flag 0 23d7 : 4930 > eor #0|fao ;invert expected flags + always on bits > -23d9 : dd3c02 > cmp fRORc,x ;test flags +23d9 : dd4b02 > cmp fRORc,x ;test flags > trap_ne ; 23dc : d0fe > bne * ;failed not equal (non zero) > 23de : ca dex 23df : 10e8 bpl trorc -23e1 : a203 ldx #3 +23e1 : a205 ldx #5 23e3 : trorc1 - set_ax zp1,$ff + set_ax zps,$ff > load_flag $ff 23e3 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 23e5 : 48 > pha ;use stack to load status -23e6 : b513 > lda zp1,x ;precharge accu +23e6 : b513 > lda zps,x ;precharge accu 23e8 : 28 > plp 23e9 : 6a ror a tst_ax rRORc,fRORc,$ff-fnzc 23ea : 08 > php ;save flags -23eb : dd2c02 > cmp rRORc,x ;test result +23eb : dd3302 > cmp rRORc,x ;test result > trap_ne 23ee : d0fe > bne * ;failed not equal (non zero) > @@ -9544,7 +9546,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 23f1 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -23f3 : dd3c02 > cmp fRORc,x ;test flags +23f3 : dd4b02 > cmp fRORc,x ;test flags > trap_ne ; 23f6 : d0fe > bne * ;failed not equal (non zero) > @@ -9564,14 +9566,14 @@ ffff = ram_top = -1 ; shifts - zeropage -2407 : a203 ldx #3 +2407 : a205 ldx #5 2409 : tasl2 - set_z zp1,0 + set_z zps,0 > load_flag 0 2409 : a900 > lda #0 ;allow test to change I-flag (no mask) > 240b : 48 > pha ;use stack to load status -240c : b513 > lda zp1,x ;load to zeropage +240c : b513 > lda zps,x ;load to zeropage 240e : 850c > sta zpt 2410 : 28 > plp @@ -9579,7 +9581,7 @@ ffff = ram_top = -1 tst_z rASL,fASL,0 2413 : 08 > php ;save flags 2414 : a50c > lda zpt -2416 : dd2002 > cmp rASL,x ;test result +2416 : dd2102 > cmp rASL,x ;test result > trap_ne 2419 : d0fe > bne * ;failed not equal (non zero) > @@ -9587,21 +9589,21 @@ ffff = ram_top = -1 > eor_flag 0 241c : 4930 > eor #0|fao ;invert expected flags + always on bits > -241e : dd3002 > cmp fASL,x ;test flags +241e : dd3902 > cmp fASL,x ;test flags > trap_ne 2421 : d0fe > bne * ;failed not equal (non zero) > 2423 : ca dex 2424 : 10e3 bpl tasl2 -2426 : a203 ldx #3 +2426 : a205 ldx #5 2428 : tasl3 - set_z zp1,$ff + set_z zps,$ff > load_flag $ff 2428 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 242a : 48 > pha ;use stack to load status -242b : b513 > lda zp1,x ;load to zeropage +242b : b513 > lda zps,x ;load to zeropage 242d : 850c > sta zpt 242f : 28 > plp @@ -9609,7 +9611,7 @@ ffff = ram_top = -1 tst_z rASL,fASL,$ff-fnzc 2432 : 08 > php ;save flags 2433 : a50c > lda zpt -2435 : dd2002 > cmp rASL,x ;test result +2435 : dd2102 > cmp rASL,x ;test result > trap_ne 2438 : d0fe > bne * ;failed not equal (non zero) > @@ -9617,7 +9619,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 243b : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -243d : dd3002 > cmp fASL,x ;test flags +243d : dd3902 > cmp fASL,x ;test flags > trap_ne 2440 : d0fe > bne * ;failed not equal (non zero) > @@ -9625,14 +9627,14 @@ ffff = ram_top = -1 2442 : ca dex 2443 : 10e3 bpl tasl3 -2445 : a203 ldx #3 +2445 : a205 ldx #5 2447 : tlsr2 - set_z zp1,0 + set_z zps,0 > load_flag 0 2447 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2449 : 48 > pha ;use stack to load status -244a : b513 > lda zp1,x ;load to zeropage +244a : b513 > lda zps,x ;load to zeropage 244c : 850c > sta zpt 244e : 28 > plp @@ -9640,7 +9642,7 @@ ffff = ram_top = -1 tst_z rLSR,fLSR,0 2451 : 08 > php ;save flags 2452 : a50c > lda zpt -2454 : dd2802 > cmp rLSR,x ;test result +2454 : dd2d02 > cmp rLSR,x ;test result > trap_ne 2457 : d0fe > bne * ;failed not equal (non zero) > @@ -9648,21 +9650,21 @@ ffff = ram_top = -1 > eor_flag 0 245a : 4930 > eor #0|fao ;invert expected flags + always on bits > -245c : dd3802 > cmp fLSR,x ;test flags +245c : dd4502 > cmp fLSR,x ;test flags > trap_ne 245f : d0fe > bne * ;failed not equal (non zero) > 2461 : ca dex 2462 : 10e3 bpl tlsr2 -2464 : a203 ldx #3 +2464 : a205 ldx #5 2466 : tlsr3 - set_z zp1,$ff + set_z zps,$ff > load_flag $ff 2466 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2468 : 48 > pha ;use stack to load status -2469 : b513 > lda zp1,x ;load to zeropage +2469 : b513 > lda zps,x ;load to zeropage 246b : 850c > sta zpt 246d : 28 > plp @@ -9670,7 +9672,7 @@ ffff = ram_top = -1 tst_z rLSR,fLSR,$ff-fnzc 2470 : 08 > php ;save flags 2471 : a50c > lda zpt -2473 : dd2802 > cmp rLSR,x ;test result +2473 : dd2d02 > cmp rLSR,x ;test result > trap_ne 2476 : d0fe > bne * ;failed not equal (non zero) > @@ -9678,7 +9680,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2479 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -247b : dd3802 > cmp fLSR,x ;test flags +247b : dd4502 > cmp fLSR,x ;test flags > trap_ne 247e : d0fe > bne * ;failed not equal (non zero) > @@ -9686,14 +9688,14 @@ ffff = ram_top = -1 2480 : ca dex 2481 : 10e3 bpl tlsr3 -2483 : a203 ldx #3 +2483 : a205 ldx #5 2485 : trol2 - set_z zp1,0 + set_z zps,0 > load_flag 0 2485 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2487 : 48 > pha ;use stack to load status -2488 : b513 > lda zp1,x ;load to zeropage +2488 : b513 > lda zps,x ;load to zeropage 248a : 850c > sta zpt 248c : 28 > plp @@ -9701,7 +9703,7 @@ ffff = ram_top = -1 tst_z rROL,fROL,0 248f : 08 > php ;save flags 2490 : a50c > lda zpt -2492 : dd2002 > cmp rROL,x ;test result +2492 : dd2102 > cmp rROL,x ;test result > trap_ne 2495 : d0fe > bne * ;failed not equal (non zero) > @@ -9709,21 +9711,21 @@ ffff = ram_top = -1 > eor_flag 0 2498 : 4930 > eor #0|fao ;invert expected flags + always on bits > -249a : dd3002 > cmp fROL,x ;test flags +249a : dd3902 > cmp fROL,x ;test flags > trap_ne 249d : d0fe > bne * ;failed not equal (non zero) > 249f : ca dex 24a0 : 10e3 bpl trol2 -24a2 : a203 ldx #3 +24a2 : a205 ldx #5 24a4 : trol3 - set_z zp1,$ff-fc + set_z zps,$ff-fc > load_flag $ff-fc 24a4 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 24a6 : 48 > pha ;use stack to load status -24a7 : b513 > lda zp1,x ;load to zeropage +24a7 : b513 > lda zps,x ;load to zeropage 24a9 : 850c > sta zpt 24ab : 28 > plp @@ -9731,7 +9733,7 @@ ffff = ram_top = -1 tst_z rROL,fROL,$ff-fnzc 24ae : 08 > php ;save flags 24af : a50c > lda zpt -24b1 : dd2002 > cmp rROL,x ;test result +24b1 : dd2102 > cmp rROL,x ;test result > trap_ne 24b4 : d0fe > bne * ;failed not equal (non zero) > @@ -9739,7 +9741,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 24b7 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -24b9 : dd3002 > cmp fROL,x ;test flags +24b9 : dd3902 > cmp fROL,x ;test flags > trap_ne 24bc : d0fe > bne * ;failed not equal (non zero) > @@ -9747,14 +9749,14 @@ ffff = ram_top = -1 24be : ca dex 24bf : 10e3 bpl trol3 -24c1 : a203 ldx #3 +24c1 : a205 ldx #5 24c3 : trolc2 - set_z zp1,fc + set_z zps,fc > load_flag fc 24c3 : a901 > lda #fc ;allow test to change I-flag (no mask) > 24c5 : 48 > pha ;use stack to load status -24c6 : b513 > lda zp1,x ;load to zeropage +24c6 : b513 > lda zps,x ;load to zeropage 24c8 : 850c > sta zpt 24ca : 28 > plp @@ -9762,7 +9764,7 @@ ffff = ram_top = -1 tst_z rROLc,fROLc,0 24cd : 08 > php ;save flags 24ce : a50c > lda zpt -24d0 : dd2402 > cmp rROLc,x ;test result +24d0 : dd2702 > cmp rROLc,x ;test result > trap_ne 24d3 : d0fe > bne * ;failed not equal (non zero) > @@ -9770,21 +9772,21 @@ ffff = ram_top = -1 > eor_flag 0 24d6 : 4930 > eor #0|fao ;invert expected flags + always on bits > -24d8 : dd3402 > cmp fROLc,x ;test flags +24d8 : dd3f02 > cmp fROLc,x ;test flags > trap_ne 24db : d0fe > bne * ;failed not equal (non zero) > 24dd : ca dex 24de : 10e3 bpl trolc2 -24e0 : a203 ldx #3 +24e0 : a205 ldx #5 24e2 : trolc3 - set_z zp1,$ff + set_z zps,$ff > load_flag $ff 24e2 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 24e4 : 48 > pha ;use stack to load status -24e5 : b513 > lda zp1,x ;load to zeropage +24e5 : b513 > lda zps,x ;load to zeropage 24e7 : 850c > sta zpt 24e9 : 28 > plp @@ -9792,7 +9794,7 @@ ffff = ram_top = -1 tst_z rROLc,fROLc,$ff-fnzc 24ec : 08 > php ;save flags 24ed : a50c > lda zpt -24ef : dd2402 > cmp rROLc,x ;test result +24ef : dd2702 > cmp rROLc,x ;test result > trap_ne 24f2 : d0fe > bne * ;failed not equal (non zero) > @@ -9800,7 +9802,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 24f5 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -24f7 : dd3402 > cmp fROLc,x ;test flags +24f7 : dd3f02 > cmp fROLc,x ;test flags > trap_ne 24fa : d0fe > bne * ;failed not equal (non zero) > @@ -9808,14 +9810,14 @@ ffff = ram_top = -1 24fc : ca dex 24fd : 10e3 bpl trolc3 -24ff : a203 ldx #3 +24ff : a205 ldx #5 2501 : tror2 - set_z zp1,0 + set_z zps,0 > load_flag 0 2501 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2503 : 48 > pha ;use stack to load status -2504 : b513 > lda zp1,x ;load to zeropage +2504 : b513 > lda zps,x ;load to zeropage 2506 : 850c > sta zpt 2508 : 28 > plp @@ -9823,7 +9825,7 @@ ffff = ram_top = -1 tst_z rROR,fROR,0 250b : 08 > php ;save flags 250c : a50c > lda zpt -250e : dd2802 > cmp rROR,x ;test result +250e : dd2d02 > cmp rROR,x ;test result > trap_ne 2511 : d0fe > bne * ;failed not equal (non zero) > @@ -9831,21 +9833,21 @@ ffff = ram_top = -1 > eor_flag 0 2514 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2516 : dd3802 > cmp fROR,x ;test flags +2516 : dd4502 > cmp fROR,x ;test flags > trap_ne 2519 : d0fe > bne * ;failed not equal (non zero) > 251b : ca dex 251c : 10e3 bpl tror2 -251e : a203 ldx #3 +251e : a205 ldx #5 2520 : tror3 - set_z zp1,$ff-fc + set_z zps,$ff-fc > load_flag $ff-fc 2520 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 2522 : 48 > pha ;use stack to load status -2523 : b513 > lda zp1,x ;load to zeropage +2523 : b513 > lda zps,x ;load to zeropage 2525 : 850c > sta zpt 2527 : 28 > plp @@ -9853,7 +9855,7 @@ ffff = ram_top = -1 tst_z rROR,fROR,$ff-fnzc 252a : 08 > php ;save flags 252b : a50c > lda zpt -252d : dd2802 > cmp rROR,x ;test result +252d : dd2d02 > cmp rROR,x ;test result > trap_ne 2530 : d0fe > bne * ;failed not equal (non zero) > @@ -9861,7 +9863,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2533 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2535 : dd3802 > cmp fROR,x ;test flags +2535 : dd4502 > cmp fROR,x ;test flags > trap_ne 2538 : d0fe > bne * ;failed not equal (non zero) > @@ -9869,14 +9871,14 @@ ffff = ram_top = -1 253a : ca dex 253b : 10e3 bpl tror3 -253d : a203 ldx #3 +253d : a205 ldx #5 253f : trorc2 - set_z zp1,fc + set_z zps,fc > load_flag fc 253f : a901 > lda #fc ;allow test to change I-flag (no mask) > 2541 : 48 > pha ;use stack to load status -2542 : b513 > lda zp1,x ;load to zeropage +2542 : b513 > lda zps,x ;load to zeropage 2544 : 850c > sta zpt 2546 : 28 > plp @@ -9884,7 +9886,7 @@ ffff = ram_top = -1 tst_z rRORc,fRORc,0 2549 : 08 > php ;save flags 254a : a50c > lda zpt -254c : dd2c02 > cmp rRORc,x ;test result +254c : dd3302 > cmp rRORc,x ;test result > trap_ne 254f : d0fe > bne * ;failed not equal (non zero) > @@ -9892,21 +9894,21 @@ ffff = ram_top = -1 > eor_flag 0 2552 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2554 : dd3c02 > cmp fRORc,x ;test flags +2554 : dd4b02 > cmp fRORc,x ;test flags > trap_ne 2557 : d0fe > bne * ;failed not equal (non zero) > 2559 : ca dex 255a : 10e3 bpl trorc2 -255c : a203 ldx #3 +255c : a205 ldx #5 255e : trorc3 - set_z zp1,$ff + set_z zps,$ff > load_flag $ff 255e : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2560 : 48 > pha ;use stack to load status -2561 : b513 > lda zp1,x ;load to zeropage +2561 : b513 > lda zps,x ;load to zeropage 2563 : 850c > sta zpt 2565 : 28 > plp @@ -9914,7 +9916,7 @@ ffff = ram_top = -1 tst_z rRORc,fRORc,$ff-fnzc 2568 : 08 > php ;save flags 2569 : a50c > lda zpt -256b : dd2c02 > cmp rRORc,x ;test result +256b : dd3302 > cmp rRORc,x ;test result > trap_ne 256e : d0fe > bne * ;failed not equal (non zero) > @@ -9922,7 +9924,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2571 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2573 : dd3c02 > cmp fRORc,x ;test flags +2573 : dd4b02 > cmp fRORc,x ;test flags > trap_ne 2576 : d0fe > bne * ;failed not equal (non zero) > @@ -9942,14 +9944,14 @@ ffff = ram_top = -1 ; shifts - absolute -2587 : a203 ldx #3 +2587 : a205 ldx #5 2589 : tasl4 - set_abs zp1,0 + set_abs zps,0 > load_flag 0 2589 : a900 > lda #0 ;allow test to change I-flag (no mask) > 258b : 48 > pha ;use stack to load status -258c : b513 > lda zp1,x ;load to memory +258c : b513 > lda zps,x ;load to memory 258e : 8d0302 > sta abst 2591 : 28 > plp @@ -9957,7 +9959,7 @@ ffff = ram_top = -1 tst_abs rASL,fASL,0 2595 : 08 > php ;save flags 2596 : ad0302 > lda abst -2599 : dd2002 > cmp rASL,x ;test result +2599 : dd2102 > cmp rASL,x ;test result > trap_ne 259c : d0fe > bne * ;failed not equal (non zero) > @@ -9965,21 +9967,21 @@ ffff = ram_top = -1 > eor_flag 0 259f : 4930 > eor #0|fao ;invert expected flags + always on bits > -25a1 : dd3002 > cmp fASL,x ;test flags +25a1 : dd3902 > cmp fASL,x ;test flags > trap_ne 25a4 : d0fe > bne * ;failed not equal (non zero) > 25a6 : ca dex 25a7 : 10e0 bpl tasl4 -25a9 : a203 ldx #3 +25a9 : a205 ldx #5 25ab : tasl5 - set_abs zp1,$ff + set_abs zps,$ff > load_flag $ff 25ab : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 25ad : 48 > pha ;use stack to load status -25ae : b513 > lda zp1,x ;load to memory +25ae : b513 > lda zps,x ;load to memory 25b0 : 8d0302 > sta abst 25b3 : 28 > plp @@ -9987,7 +9989,7 @@ ffff = ram_top = -1 tst_abs rASL,fASL,$ff-fnzc 25b7 : 08 > php ;save flags 25b8 : ad0302 > lda abst -25bb : dd2002 > cmp rASL,x ;test result +25bb : dd2102 > cmp rASL,x ;test result > trap_ne 25be : d0fe > bne * ;failed not equal (non zero) > @@ -9995,7 +9997,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 25c1 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -25c3 : dd3002 > cmp fASL,x ;test flags +25c3 : dd3902 > cmp fASL,x ;test flags > trap_ne 25c6 : d0fe > bne * ;failed not equal (non zero) > @@ -10003,14 +10005,14 @@ ffff = ram_top = -1 25c8 : ca dex 25c9 : 10e0 bpl tasl5 -25cb : a203 ldx #3 +25cb : a205 ldx #5 25cd : tlsr4 - set_abs zp1,0 + set_abs zps,0 > load_flag 0 25cd : a900 > lda #0 ;allow test to change I-flag (no mask) > 25cf : 48 > pha ;use stack to load status -25d0 : b513 > lda zp1,x ;load to memory +25d0 : b513 > lda zps,x ;load to memory 25d2 : 8d0302 > sta abst 25d5 : 28 > plp @@ -10018,7 +10020,7 @@ ffff = ram_top = -1 tst_abs rLSR,fLSR,0 25d9 : 08 > php ;save flags 25da : ad0302 > lda abst -25dd : dd2802 > cmp rLSR,x ;test result +25dd : dd2d02 > cmp rLSR,x ;test result > trap_ne 25e0 : d0fe > bne * ;failed not equal (non zero) > @@ -10026,21 +10028,21 @@ ffff = ram_top = -1 > eor_flag 0 25e3 : 4930 > eor #0|fao ;invert expected flags + always on bits > -25e5 : dd3802 > cmp fLSR,x ;test flags +25e5 : dd4502 > cmp fLSR,x ;test flags > trap_ne 25e8 : d0fe > bne * ;failed not equal (non zero) > 25ea : ca dex 25eb : 10e0 bpl tlsr4 -25ed : a203 ldx #3 +25ed : a205 ldx #5 25ef : tlsr5 - set_abs zp1,$ff + set_abs zps,$ff > load_flag $ff 25ef : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 25f1 : 48 > pha ;use stack to load status -25f2 : b513 > lda zp1,x ;load to memory +25f2 : b513 > lda zps,x ;load to memory 25f4 : 8d0302 > sta abst 25f7 : 28 > plp @@ -10048,7 +10050,7 @@ ffff = ram_top = -1 tst_abs rLSR,fLSR,$ff-fnzc 25fb : 08 > php ;save flags 25fc : ad0302 > lda abst -25ff : dd2802 > cmp rLSR,x ;test result +25ff : dd2d02 > cmp rLSR,x ;test result > trap_ne 2602 : d0fe > bne * ;failed not equal (non zero) > @@ -10056,7 +10058,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2605 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2607 : dd3802 > cmp fLSR,x ;test flags +2607 : dd4502 > cmp fLSR,x ;test flags > trap_ne 260a : d0fe > bne * ;failed not equal (non zero) > @@ -10064,14 +10066,14 @@ ffff = ram_top = -1 260c : ca dex 260d : 10e0 bpl tlsr5 -260f : a203 ldx #3 +260f : a205 ldx #5 2611 : trol4 - set_abs zp1,0 + set_abs zps,0 > load_flag 0 2611 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2613 : 48 > pha ;use stack to load status -2614 : b513 > lda zp1,x ;load to memory +2614 : b513 > lda zps,x ;load to memory 2616 : 8d0302 > sta abst 2619 : 28 > plp @@ -10079,7 +10081,7 @@ ffff = ram_top = -1 tst_abs rROL,fROL,0 261d : 08 > php ;save flags 261e : ad0302 > lda abst -2621 : dd2002 > cmp rROL,x ;test result +2621 : dd2102 > cmp rROL,x ;test result > trap_ne 2624 : d0fe > bne * ;failed not equal (non zero) > @@ -10087,21 +10089,21 @@ ffff = ram_top = -1 > eor_flag 0 2627 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2629 : dd3002 > cmp fROL,x ;test flags +2629 : dd3902 > cmp fROL,x ;test flags > trap_ne 262c : d0fe > bne * ;failed not equal (non zero) > 262e : ca dex 262f : 10e0 bpl trol4 -2631 : a203 ldx #3 +2631 : a205 ldx #5 2633 : trol5 - set_abs zp1,$ff-fc + set_abs zps,$ff-fc > load_flag $ff-fc 2633 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 2635 : 48 > pha ;use stack to load status -2636 : b513 > lda zp1,x ;load to memory +2636 : b513 > lda zps,x ;load to memory 2638 : 8d0302 > sta abst 263b : 28 > plp @@ -10109,7 +10111,7 @@ ffff = ram_top = -1 tst_abs rROL,fROL,$ff-fnzc 263f : 08 > php ;save flags 2640 : ad0302 > lda abst -2643 : dd2002 > cmp rROL,x ;test result +2643 : dd2102 > cmp rROL,x ;test result > trap_ne 2646 : d0fe > bne * ;failed not equal (non zero) > @@ -10117,7 +10119,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2649 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -264b : dd3002 > cmp fROL,x ;test flags +264b : dd3902 > cmp fROL,x ;test flags > trap_ne 264e : d0fe > bne * ;failed not equal (non zero) > @@ -10125,14 +10127,14 @@ ffff = ram_top = -1 2650 : ca dex 2651 : 10e0 bpl trol5 -2653 : a203 ldx #3 +2653 : a205 ldx #5 2655 : trolc4 - set_abs zp1,fc + set_abs zps,fc > load_flag fc 2655 : a901 > lda #fc ;allow test to change I-flag (no mask) > 2657 : 48 > pha ;use stack to load status -2658 : b513 > lda zp1,x ;load to memory +2658 : b513 > lda zps,x ;load to memory 265a : 8d0302 > sta abst 265d : 28 > plp @@ -10140,7 +10142,7 @@ ffff = ram_top = -1 tst_abs rROLc,fROLc,0 2661 : 08 > php ;save flags 2662 : ad0302 > lda abst -2665 : dd2402 > cmp rROLc,x ;test result +2665 : dd2702 > cmp rROLc,x ;test result > trap_ne 2668 : d0fe > bne * ;failed not equal (non zero) > @@ -10148,21 +10150,21 @@ ffff = ram_top = -1 > eor_flag 0 266b : 4930 > eor #0|fao ;invert expected flags + always on bits > -266d : dd3402 > cmp fROLc,x ;test flags +266d : dd3f02 > cmp fROLc,x ;test flags > trap_ne 2670 : d0fe > bne * ;failed not equal (non zero) > 2672 : ca dex 2673 : 10e0 bpl trolc4 -2675 : a203 ldx #3 +2675 : a205 ldx #5 2677 : trolc5 - set_abs zp1,$ff + set_abs zps,$ff > load_flag $ff 2677 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2679 : 48 > pha ;use stack to load status -267a : b513 > lda zp1,x ;load to memory +267a : b513 > lda zps,x ;load to memory 267c : 8d0302 > sta abst 267f : 28 > plp @@ -10170,7 +10172,7 @@ ffff = ram_top = -1 tst_abs rROLc,fROLc,$ff-fnzc 2683 : 08 > php ;save flags 2684 : ad0302 > lda abst -2687 : dd2402 > cmp rROLc,x ;test result +2687 : dd2702 > cmp rROLc,x ;test result > trap_ne 268a : d0fe > bne * ;failed not equal (non zero) > @@ -10178,7 +10180,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 268d : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -268f : dd3402 > cmp fROLc,x ;test flags +268f : dd3f02 > cmp fROLc,x ;test flags > trap_ne 2692 : d0fe > bne * ;failed not equal (non zero) > @@ -10186,14 +10188,14 @@ ffff = ram_top = -1 2694 : ca dex 2695 : 10e0 bpl trolc5 -2697 : a203 ldx #3 +2697 : a205 ldx #5 2699 : tror4 - set_abs zp1,0 + set_abs zps,0 > load_flag 0 2699 : a900 > lda #0 ;allow test to change I-flag (no mask) > 269b : 48 > pha ;use stack to load status -269c : b513 > lda zp1,x ;load to memory +269c : b513 > lda zps,x ;load to memory 269e : 8d0302 > sta abst 26a1 : 28 > plp @@ -10201,7 +10203,7 @@ ffff = ram_top = -1 tst_abs rROR,fROR,0 26a5 : 08 > php ;save flags 26a6 : ad0302 > lda abst -26a9 : dd2802 > cmp rROR,x ;test result +26a9 : dd2d02 > cmp rROR,x ;test result > trap_ne 26ac : d0fe > bne * ;failed not equal (non zero) > @@ -10209,21 +10211,21 @@ ffff = ram_top = -1 > eor_flag 0 26af : 4930 > eor #0|fao ;invert expected flags + always on bits > -26b1 : dd3802 > cmp fROR,x ;test flags +26b1 : dd4502 > cmp fROR,x ;test flags > trap_ne 26b4 : d0fe > bne * ;failed not equal (non zero) > 26b6 : ca dex 26b7 : 10e0 bpl tror4 -26b9 : a203 ldx #3 +26b9 : a205 ldx #5 26bb : tror5 - set_abs zp1,$ff-fc + set_abs zps,$ff-fc > load_flag $ff-fc 26bb : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 26bd : 48 > pha ;use stack to load status -26be : b513 > lda zp1,x ;load to memory +26be : b513 > lda zps,x ;load to memory 26c0 : 8d0302 > sta abst 26c3 : 28 > plp @@ -10231,7 +10233,7 @@ ffff = ram_top = -1 tst_abs rROR,fROR,$ff-fnzc 26c7 : 08 > php ;save flags 26c8 : ad0302 > lda abst -26cb : dd2802 > cmp rROR,x ;test result +26cb : dd2d02 > cmp rROR,x ;test result > trap_ne 26ce : d0fe > bne * ;failed not equal (non zero) > @@ -10239,7 +10241,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 26d1 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -26d3 : dd3802 > cmp fROR,x ;test flags +26d3 : dd4502 > cmp fROR,x ;test flags > trap_ne 26d6 : d0fe > bne * ;failed not equal (non zero) > @@ -10247,14 +10249,14 @@ ffff = ram_top = -1 26d8 : ca dex 26d9 : 10e0 bpl tror5 -26db : a203 ldx #3 +26db : a205 ldx #5 26dd : trorc4 - set_abs zp1,fc + set_abs zps,fc > load_flag fc 26dd : a901 > lda #fc ;allow test to change I-flag (no mask) > 26df : 48 > pha ;use stack to load status -26e0 : b513 > lda zp1,x ;load to memory +26e0 : b513 > lda zps,x ;load to memory 26e2 : 8d0302 > sta abst 26e5 : 28 > plp @@ -10262,7 +10264,7 @@ ffff = ram_top = -1 tst_abs rRORc,fRORc,0 26e9 : 08 > php ;save flags 26ea : ad0302 > lda abst -26ed : dd2c02 > cmp rRORc,x ;test result +26ed : dd3302 > cmp rRORc,x ;test result > trap_ne 26f0 : d0fe > bne * ;failed not equal (non zero) > @@ -10270,21 +10272,21 @@ ffff = ram_top = -1 > eor_flag 0 26f3 : 4930 > eor #0|fao ;invert expected flags + always on bits > -26f5 : dd3c02 > cmp fRORc,x ;test flags +26f5 : dd4b02 > cmp fRORc,x ;test flags > trap_ne 26f8 : d0fe > bne * ;failed not equal (non zero) > 26fa : ca dex 26fb : 10e0 bpl trorc4 -26fd : a203 ldx #3 +26fd : a205 ldx #5 26ff : trorc5 - set_abs zp1,$ff + set_abs zps,$ff > load_flag $ff 26ff : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2701 : 48 > pha ;use stack to load status -2702 : b513 > lda zp1,x ;load to memory +2702 : b513 > lda zps,x ;load to memory 2704 : 8d0302 > sta abst 2707 : 28 > plp @@ -10292,7 +10294,7 @@ ffff = ram_top = -1 tst_abs rRORc,fRORc,$ff-fnzc 270b : 08 > php ;save flags 270c : ad0302 > lda abst -270f : dd2c02 > cmp rRORc,x ;test result +270f : dd3302 > cmp rRORc,x ;test result > trap_ne 2712 : d0fe > bne * ;failed not equal (non zero) > @@ -10300,7 +10302,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2715 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2717 : dd3c02 > cmp fRORc,x ;test flags +2717 : dd4b02 > cmp fRORc,x ;test flags > trap_ne 271a : d0fe > bne * ;failed not equal (non zero) > @@ -10320,14 +10322,14 @@ ffff = ram_top = -1 ; shifts - zp indexed -272b : a203 ldx #3 +272b : a205 ldx #5 272d : tasl6 - set_zx zp1,0 + set_zx zps,0 > load_flag 0 272d : a900 > lda #0 ;allow test to change I-flag (no mask) > 272f : 48 > pha ;use stack to load status -2730 : b513 > lda zp1,x ;load to indexed zeropage +2730 : b513 > lda zps,x ;load to indexed zeropage 2732 : 950c > sta zpt,x 2734 : 28 > plp @@ -10335,7 +10337,7 @@ ffff = ram_top = -1 tst_zx rASL,fASL,0 2737 : 08 > php ;save flags 2738 : b50c > lda zpt,x -273a : dd2002 > cmp rASL,x ;test result +273a : dd2102 > cmp rASL,x ;test result > trap_ne 273d : d0fe > bne * ;failed not equal (non zero) > @@ -10343,21 +10345,21 @@ ffff = ram_top = -1 > eor_flag 0 2740 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2742 : dd3002 > cmp fASL,x ;test flags +2742 : dd3902 > cmp fASL,x ;test flags > trap_ne 2745 : d0fe > bne * ;failed not equal (non zero) > 2747 : ca dex 2748 : 10e3 bpl tasl6 -274a : a203 ldx #3 +274a : a205 ldx #5 274c : tasl7 - set_zx zp1,$ff + set_zx zps,$ff > load_flag $ff 274c : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 274e : 48 > pha ;use stack to load status -274f : b513 > lda zp1,x ;load to indexed zeropage +274f : b513 > lda zps,x ;load to indexed zeropage 2751 : 950c > sta zpt,x 2753 : 28 > plp @@ -10365,7 +10367,7 @@ ffff = ram_top = -1 tst_zx rASL,fASL,$ff-fnzc 2756 : 08 > php ;save flags 2757 : b50c > lda zpt,x -2759 : dd2002 > cmp rASL,x ;test result +2759 : dd2102 > cmp rASL,x ;test result > trap_ne 275c : d0fe > bne * ;failed not equal (non zero) > @@ -10373,7 +10375,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 275f : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2761 : dd3002 > cmp fASL,x ;test flags +2761 : dd3902 > cmp fASL,x ;test flags > trap_ne 2764 : d0fe > bne * ;failed not equal (non zero) > @@ -10381,14 +10383,14 @@ ffff = ram_top = -1 2766 : ca dex 2767 : 10e3 bpl tasl7 -2769 : a203 ldx #3 +2769 : a205 ldx #5 276b : tlsr6 - set_zx zp1,0 + set_zx zps,0 > load_flag 0 276b : a900 > lda #0 ;allow test to change I-flag (no mask) > 276d : 48 > pha ;use stack to load status -276e : b513 > lda zp1,x ;load to indexed zeropage +276e : b513 > lda zps,x ;load to indexed zeropage 2770 : 950c > sta zpt,x 2772 : 28 > plp @@ -10396,7 +10398,7 @@ ffff = ram_top = -1 tst_zx rLSR,fLSR,0 2775 : 08 > php ;save flags 2776 : b50c > lda zpt,x -2778 : dd2802 > cmp rLSR,x ;test result +2778 : dd2d02 > cmp rLSR,x ;test result > trap_ne 277b : d0fe > bne * ;failed not equal (non zero) > @@ -10404,21 +10406,21 @@ ffff = ram_top = -1 > eor_flag 0 277e : 4930 > eor #0|fao ;invert expected flags + always on bits > -2780 : dd3802 > cmp fLSR,x ;test flags +2780 : dd4502 > cmp fLSR,x ;test flags > trap_ne 2783 : d0fe > bne * ;failed not equal (non zero) > 2785 : ca dex 2786 : 10e3 bpl tlsr6 -2788 : a203 ldx #3 +2788 : a205 ldx #5 278a : tlsr7 - set_zx zp1,$ff + set_zx zps,$ff > load_flag $ff 278a : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 278c : 48 > pha ;use stack to load status -278d : b513 > lda zp1,x ;load to indexed zeropage +278d : b513 > lda zps,x ;load to indexed zeropage 278f : 950c > sta zpt,x 2791 : 28 > plp @@ -10426,7 +10428,7 @@ ffff = ram_top = -1 tst_zx rLSR,fLSR,$ff-fnzc 2794 : 08 > php ;save flags 2795 : b50c > lda zpt,x -2797 : dd2802 > cmp rLSR,x ;test result +2797 : dd2d02 > cmp rLSR,x ;test result > trap_ne 279a : d0fe > bne * ;failed not equal (non zero) > @@ -10434,7 +10436,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 279d : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -279f : dd3802 > cmp fLSR,x ;test flags +279f : dd4502 > cmp fLSR,x ;test flags > trap_ne 27a2 : d0fe > bne * ;failed not equal (non zero) > @@ -10442,14 +10444,14 @@ ffff = ram_top = -1 27a4 : ca dex 27a5 : 10e3 bpl tlsr7 -27a7 : a203 ldx #3 +27a7 : a205 ldx #5 27a9 : trol6 - set_zx zp1,0 + set_zx zps,0 > load_flag 0 27a9 : a900 > lda #0 ;allow test to change I-flag (no mask) > 27ab : 48 > pha ;use stack to load status -27ac : b513 > lda zp1,x ;load to indexed zeropage +27ac : b513 > lda zps,x ;load to indexed zeropage 27ae : 950c > sta zpt,x 27b0 : 28 > plp @@ -10457,7 +10459,7 @@ ffff = ram_top = -1 tst_zx rROL,fROL,0 27b3 : 08 > php ;save flags 27b4 : b50c > lda zpt,x -27b6 : dd2002 > cmp rROL,x ;test result +27b6 : dd2102 > cmp rROL,x ;test result > trap_ne 27b9 : d0fe > bne * ;failed not equal (non zero) > @@ -10465,21 +10467,21 @@ ffff = ram_top = -1 > eor_flag 0 27bc : 4930 > eor #0|fao ;invert expected flags + always on bits > -27be : dd3002 > cmp fROL,x ;test flags +27be : dd3902 > cmp fROL,x ;test flags > trap_ne 27c1 : d0fe > bne * ;failed not equal (non zero) > 27c3 : ca dex 27c4 : 10e3 bpl trol6 -27c6 : a203 ldx #3 +27c6 : a205 ldx #5 27c8 : trol7 - set_zx zp1,$ff-fc + set_zx zps,$ff-fc > load_flag $ff-fc 27c8 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 27ca : 48 > pha ;use stack to load status -27cb : b513 > lda zp1,x ;load to indexed zeropage +27cb : b513 > lda zps,x ;load to indexed zeropage 27cd : 950c > sta zpt,x 27cf : 28 > plp @@ -10487,7 +10489,7 @@ ffff = ram_top = -1 tst_zx rROL,fROL,$ff-fnzc 27d2 : 08 > php ;save flags 27d3 : b50c > lda zpt,x -27d5 : dd2002 > cmp rROL,x ;test result +27d5 : dd2102 > cmp rROL,x ;test result > trap_ne 27d8 : d0fe > bne * ;failed not equal (non zero) > @@ -10495,7 +10497,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 27db : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -27dd : dd3002 > cmp fROL,x ;test flags +27dd : dd3902 > cmp fROL,x ;test flags > trap_ne 27e0 : d0fe > bne * ;failed not equal (non zero) > @@ -10503,14 +10505,14 @@ ffff = ram_top = -1 27e2 : ca dex 27e3 : 10e3 bpl trol7 -27e5 : a203 ldx #3 +27e5 : a205 ldx #5 27e7 : trolc6 - set_zx zp1,fc + set_zx zps,fc > load_flag fc 27e7 : a901 > lda #fc ;allow test to change I-flag (no mask) > 27e9 : 48 > pha ;use stack to load status -27ea : b513 > lda zp1,x ;load to indexed zeropage +27ea : b513 > lda zps,x ;load to indexed zeropage 27ec : 950c > sta zpt,x 27ee : 28 > plp @@ -10518,7 +10520,7 @@ ffff = ram_top = -1 tst_zx rROLc,fROLc,0 27f1 : 08 > php ;save flags 27f2 : b50c > lda zpt,x -27f4 : dd2402 > cmp rROLc,x ;test result +27f4 : dd2702 > cmp rROLc,x ;test result > trap_ne 27f7 : d0fe > bne * ;failed not equal (non zero) > @@ -10526,21 +10528,21 @@ ffff = ram_top = -1 > eor_flag 0 27fa : 4930 > eor #0|fao ;invert expected flags + always on bits > -27fc : dd3402 > cmp fROLc,x ;test flags +27fc : dd3f02 > cmp fROLc,x ;test flags > trap_ne 27ff : d0fe > bne * ;failed not equal (non zero) > 2801 : ca dex 2802 : 10e3 bpl trolc6 -2804 : a203 ldx #3 +2804 : a205 ldx #5 2806 : trolc7 - set_zx zp1,$ff + set_zx zps,$ff > load_flag $ff 2806 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2808 : 48 > pha ;use stack to load status -2809 : b513 > lda zp1,x ;load to indexed zeropage +2809 : b513 > lda zps,x ;load to indexed zeropage 280b : 950c > sta zpt,x 280d : 28 > plp @@ -10548,7 +10550,7 @@ ffff = ram_top = -1 tst_zx rROLc,fROLc,$ff-fnzc 2810 : 08 > php ;save flags 2811 : b50c > lda zpt,x -2813 : dd2402 > cmp rROLc,x ;test result +2813 : dd2702 > cmp rROLc,x ;test result > trap_ne 2816 : d0fe > bne * ;failed not equal (non zero) > @@ -10556,7 +10558,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2819 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -281b : dd3402 > cmp fROLc,x ;test flags +281b : dd3f02 > cmp fROLc,x ;test flags > trap_ne 281e : d0fe > bne * ;failed not equal (non zero) > @@ -10564,14 +10566,14 @@ ffff = ram_top = -1 2820 : ca dex 2821 : 10e3 bpl trolc7 -2823 : a203 ldx #3 +2823 : a205 ldx #5 2825 : tror6 - set_zx zp1,0 + set_zx zps,0 > load_flag 0 2825 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2827 : 48 > pha ;use stack to load status -2828 : b513 > lda zp1,x ;load to indexed zeropage +2828 : b513 > lda zps,x ;load to indexed zeropage 282a : 950c > sta zpt,x 282c : 28 > plp @@ -10579,7 +10581,7 @@ ffff = ram_top = -1 tst_zx rROR,fROR,0 282f : 08 > php ;save flags 2830 : b50c > lda zpt,x -2832 : dd2802 > cmp rROR,x ;test result +2832 : dd2d02 > cmp rROR,x ;test result > trap_ne 2835 : d0fe > bne * ;failed not equal (non zero) > @@ -10587,21 +10589,21 @@ ffff = ram_top = -1 > eor_flag 0 2838 : 4930 > eor #0|fao ;invert expected flags + always on bits > -283a : dd3802 > cmp fROR,x ;test flags +283a : dd4502 > cmp fROR,x ;test flags > trap_ne 283d : d0fe > bne * ;failed not equal (non zero) > 283f : ca dex 2840 : 10e3 bpl tror6 -2842 : a203 ldx #3 +2842 : a205 ldx #5 2844 : tror7 - set_zx zp1,$ff-fc + set_zx zps,$ff-fc > load_flag $ff-fc 2844 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 2846 : 48 > pha ;use stack to load status -2847 : b513 > lda zp1,x ;load to indexed zeropage +2847 : b513 > lda zps,x ;load to indexed zeropage 2849 : 950c > sta zpt,x 284b : 28 > plp @@ -10609,7 +10611,7 @@ ffff = ram_top = -1 tst_zx rROR,fROR,$ff-fnzc 284e : 08 > php ;save flags 284f : b50c > lda zpt,x -2851 : dd2802 > cmp rROR,x ;test result +2851 : dd2d02 > cmp rROR,x ;test result > trap_ne 2854 : d0fe > bne * ;failed not equal (non zero) > @@ -10617,7 +10619,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2857 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2859 : dd3802 > cmp fROR,x ;test flags +2859 : dd4502 > cmp fROR,x ;test flags > trap_ne 285c : d0fe > bne * ;failed not equal (non zero) > @@ -10625,14 +10627,14 @@ ffff = ram_top = -1 285e : ca dex 285f : 10e3 bpl tror7 -2861 : a203 ldx #3 +2861 : a205 ldx #5 2863 : trorc6 - set_zx zp1,fc + set_zx zps,fc > load_flag fc 2863 : a901 > lda #fc ;allow test to change I-flag (no mask) > 2865 : 48 > pha ;use stack to load status -2866 : b513 > lda zp1,x ;load to indexed zeropage +2866 : b513 > lda zps,x ;load to indexed zeropage 2868 : 950c > sta zpt,x 286a : 28 > plp @@ -10640,7 +10642,7 @@ ffff = ram_top = -1 tst_zx rRORc,fRORc,0 286d : 08 > php ;save flags 286e : b50c > lda zpt,x -2870 : dd2c02 > cmp rRORc,x ;test result +2870 : dd3302 > cmp rRORc,x ;test result > trap_ne 2873 : d0fe > bne * ;failed not equal (non zero) > @@ -10648,21 +10650,21 @@ ffff = ram_top = -1 > eor_flag 0 2876 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2878 : dd3c02 > cmp fRORc,x ;test flags +2878 : dd4b02 > cmp fRORc,x ;test flags > trap_ne 287b : d0fe > bne * ;failed not equal (non zero) > 287d : ca dex 287e : 10e3 bpl trorc6 -2880 : a203 ldx #3 +2880 : a205 ldx #5 2882 : trorc7 - set_zx zp1,$ff + set_zx zps,$ff > load_flag $ff 2882 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2884 : 48 > pha ;use stack to load status -2885 : b513 > lda zp1,x ;load to indexed zeropage +2885 : b513 > lda zps,x ;load to indexed zeropage 2887 : 950c > sta zpt,x 2889 : 28 > plp @@ -10670,7 +10672,7 @@ ffff = ram_top = -1 tst_zx rRORc,fRORc,$ff-fnzc 288c : 08 > php ;save flags 288d : b50c > lda zpt,x -288f : dd2c02 > cmp rRORc,x ;test result +288f : dd3302 > cmp rRORc,x ;test result > trap_ne 2892 : d0fe > bne * ;failed not equal (non zero) > @@ -10678,7 +10680,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2895 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2897 : dd3c02 > cmp fRORc,x ;test flags +2897 : dd4b02 > cmp fRORc,x ;test flags > trap_ne 289a : d0fe > bne * ;failed not equal (non zero) > @@ -10698,14 +10700,14 @@ ffff = ram_top = -1 ; shifts - abs indexed -28ab : a203 ldx #3 +28ab : a205 ldx #5 28ad : tasl8 - set_absx zp1,0 + set_absx zps,0 > load_flag 0 28ad : a900 > lda #0 ;allow test to change I-flag (no mask) > 28af : 48 > pha ;use stack to load status -28b0 : b513 > lda zp1,x ;load to indexed memory +28b0 : b513 > lda zps,x ;load to indexed memory 28b2 : 9d0302 > sta abst,x 28b5 : 28 > plp @@ -10713,7 +10715,7 @@ ffff = ram_top = -1 tst_absx rASL,fASL,0 28b9 : 08 > php ;save flags 28ba : bd0302 > lda abst,x -28bd : dd2002 > cmp rASL,x ;test result +28bd : dd2102 > cmp rASL,x ;test result > trap_ne 28c0 : d0fe > bne * ;failed not equal (non zero) > @@ -10721,21 +10723,21 @@ ffff = ram_top = -1 > eor_flag 0 28c3 : 4930 > eor #0|fao ;invert expected flags + always on bits > -28c5 : dd3002 > cmp fASL,x ;test flags +28c5 : dd3902 > cmp fASL,x ;test flags > trap_ne 28c8 : d0fe > bne * ;failed not equal (non zero) > 28ca : ca dex 28cb : 10e0 bpl tasl8 -28cd : a203 ldx #3 +28cd : a205 ldx #5 28cf : tasl9 - set_absx zp1,$ff + set_absx zps,$ff > load_flag $ff 28cf : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 28d1 : 48 > pha ;use stack to load status -28d2 : b513 > lda zp1,x ;load to indexed memory +28d2 : b513 > lda zps,x ;load to indexed memory 28d4 : 9d0302 > sta abst,x 28d7 : 28 > plp @@ -10743,7 +10745,7 @@ ffff = ram_top = -1 tst_absx rASL,fASL,$ff-fnzc 28db : 08 > php ;save flags 28dc : bd0302 > lda abst,x -28df : dd2002 > cmp rASL,x ;test result +28df : dd2102 > cmp rASL,x ;test result > trap_ne 28e2 : d0fe > bne * ;failed not equal (non zero) > @@ -10751,7 +10753,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 28e5 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -28e7 : dd3002 > cmp fASL,x ;test flags +28e7 : dd3902 > cmp fASL,x ;test flags > trap_ne 28ea : d0fe > bne * ;failed not equal (non zero) > @@ -10759,14 +10761,14 @@ ffff = ram_top = -1 28ec : ca dex 28ed : 10e0 bpl tasl9 -28ef : a203 ldx #3 +28ef : a205 ldx #5 28f1 : tlsr8 - set_absx zp1,0 + set_absx zps,0 > load_flag 0 28f1 : a900 > lda #0 ;allow test to change I-flag (no mask) > 28f3 : 48 > pha ;use stack to load status -28f4 : b513 > lda zp1,x ;load to indexed memory +28f4 : b513 > lda zps,x ;load to indexed memory 28f6 : 9d0302 > sta abst,x 28f9 : 28 > plp @@ -10774,7 +10776,7 @@ ffff = ram_top = -1 tst_absx rLSR,fLSR,0 28fd : 08 > php ;save flags 28fe : bd0302 > lda abst,x -2901 : dd2802 > cmp rLSR,x ;test result +2901 : dd2d02 > cmp rLSR,x ;test result > trap_ne 2904 : d0fe > bne * ;failed not equal (non zero) > @@ -10782,21 +10784,21 @@ ffff = ram_top = -1 > eor_flag 0 2907 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2909 : dd3802 > cmp fLSR,x ;test flags +2909 : dd4502 > cmp fLSR,x ;test flags > trap_ne 290c : d0fe > bne * ;failed not equal (non zero) > 290e : ca dex 290f : 10e0 bpl tlsr8 -2911 : a203 ldx #3 +2911 : a205 ldx #5 2913 : tlsr9 - set_absx zp1,$ff + set_absx zps,$ff > load_flag $ff 2913 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2915 : 48 > pha ;use stack to load status -2916 : b513 > lda zp1,x ;load to indexed memory +2916 : b513 > lda zps,x ;load to indexed memory 2918 : 9d0302 > sta abst,x 291b : 28 > plp @@ -10804,7 +10806,7 @@ ffff = ram_top = -1 tst_absx rLSR,fLSR,$ff-fnzc 291f : 08 > php ;save flags 2920 : bd0302 > lda abst,x -2923 : dd2802 > cmp rLSR,x ;test result +2923 : dd2d02 > cmp rLSR,x ;test result > trap_ne 2926 : d0fe > bne * ;failed not equal (non zero) > @@ -10812,7 +10814,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2929 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -292b : dd3802 > cmp fLSR,x ;test flags +292b : dd4502 > cmp fLSR,x ;test flags > trap_ne 292e : d0fe > bne * ;failed not equal (non zero) > @@ -10820,14 +10822,14 @@ ffff = ram_top = -1 2930 : ca dex 2931 : 10e0 bpl tlsr9 -2933 : a203 ldx #3 +2933 : a205 ldx #5 2935 : trol8 - set_absx zp1,0 + set_absx zps,0 > load_flag 0 2935 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2937 : 48 > pha ;use stack to load status -2938 : b513 > lda zp1,x ;load to indexed memory +2938 : b513 > lda zps,x ;load to indexed memory 293a : 9d0302 > sta abst,x 293d : 28 > plp @@ -10835,7 +10837,7 @@ ffff = ram_top = -1 tst_absx rROL,fROL,0 2941 : 08 > php ;save flags 2942 : bd0302 > lda abst,x -2945 : dd2002 > cmp rROL,x ;test result +2945 : dd2102 > cmp rROL,x ;test result > trap_ne 2948 : d0fe > bne * ;failed not equal (non zero) > @@ -10843,21 +10845,21 @@ ffff = ram_top = -1 > eor_flag 0 294b : 4930 > eor #0|fao ;invert expected flags + always on bits > -294d : dd3002 > cmp fROL,x ;test flags +294d : dd3902 > cmp fROL,x ;test flags > trap_ne 2950 : d0fe > bne * ;failed not equal (non zero) > 2952 : ca dex 2953 : 10e0 bpl trol8 -2955 : a203 ldx #3 +2955 : a205 ldx #5 2957 : trol9 - set_absx zp1,$ff-fc + set_absx zps,$ff-fc > load_flag $ff-fc 2957 : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 2959 : 48 > pha ;use stack to load status -295a : b513 > lda zp1,x ;load to indexed memory +295a : b513 > lda zps,x ;load to indexed memory 295c : 9d0302 > sta abst,x 295f : 28 > plp @@ -10865,7 +10867,7 @@ ffff = ram_top = -1 tst_absx rROL,fROL,$ff-fnzc 2963 : 08 > php ;save flags 2964 : bd0302 > lda abst,x -2967 : dd2002 > cmp rROL,x ;test result +2967 : dd2102 > cmp rROL,x ;test result > trap_ne 296a : d0fe > bne * ;failed not equal (non zero) > @@ -10873,7 +10875,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 296d : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -296f : dd3002 > cmp fROL,x ;test flags +296f : dd3902 > cmp fROL,x ;test flags > trap_ne 2972 : d0fe > bne * ;failed not equal (non zero) > @@ -10881,14 +10883,14 @@ ffff = ram_top = -1 2974 : ca dex 2975 : 10e0 bpl trol9 -2977 : a203 ldx #3 +2977 : a205 ldx #5 2979 : trolc8 - set_absx zp1,fc + set_absx zps,fc > load_flag fc 2979 : a901 > lda #fc ;allow test to change I-flag (no mask) > 297b : 48 > pha ;use stack to load status -297c : b513 > lda zp1,x ;load to indexed memory +297c : b513 > lda zps,x ;load to indexed memory 297e : 9d0302 > sta abst,x 2981 : 28 > plp @@ -10896,7 +10898,7 @@ ffff = ram_top = -1 tst_absx rROLc,fROLc,0 2985 : 08 > php ;save flags 2986 : bd0302 > lda abst,x -2989 : dd2402 > cmp rROLc,x ;test result +2989 : dd2702 > cmp rROLc,x ;test result > trap_ne 298c : d0fe > bne * ;failed not equal (non zero) > @@ -10904,21 +10906,21 @@ ffff = ram_top = -1 > eor_flag 0 298f : 4930 > eor #0|fao ;invert expected flags + always on bits > -2991 : dd3402 > cmp fROLc,x ;test flags +2991 : dd3f02 > cmp fROLc,x ;test flags > trap_ne 2994 : d0fe > bne * ;failed not equal (non zero) > 2996 : ca dex 2997 : 10e0 bpl trolc8 -2999 : a203 ldx #3 +2999 : a205 ldx #5 299b : trolc9 - set_absx zp1,$ff + set_absx zps,$ff > load_flag $ff 299b : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 299d : 48 > pha ;use stack to load status -299e : b513 > lda zp1,x ;load to indexed memory +299e : b513 > lda zps,x ;load to indexed memory 29a0 : 9d0302 > sta abst,x 29a3 : 28 > plp @@ -10926,7 +10928,7 @@ ffff = ram_top = -1 tst_absx rROLc,fROLc,$ff-fnzc 29a7 : 08 > php ;save flags 29a8 : bd0302 > lda abst,x -29ab : dd2402 > cmp rROLc,x ;test result +29ab : dd2702 > cmp rROLc,x ;test result > trap_ne 29ae : d0fe > bne * ;failed not equal (non zero) > @@ -10934,7 +10936,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 29b1 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -29b3 : dd3402 > cmp fROLc,x ;test flags +29b3 : dd3f02 > cmp fROLc,x ;test flags > trap_ne 29b6 : d0fe > bne * ;failed not equal (non zero) > @@ -10942,14 +10944,14 @@ ffff = ram_top = -1 29b8 : ca dex 29b9 : 10e0 bpl trolc9 -29bb : a203 ldx #3 +29bb : a205 ldx #5 29bd : tror8 - set_absx zp1,0 + set_absx zps,0 > load_flag 0 29bd : a900 > lda #0 ;allow test to change I-flag (no mask) > 29bf : 48 > pha ;use stack to load status -29c0 : b513 > lda zp1,x ;load to indexed memory +29c0 : b513 > lda zps,x ;load to indexed memory 29c2 : 9d0302 > sta abst,x 29c5 : 28 > plp @@ -10957,7 +10959,7 @@ ffff = ram_top = -1 tst_absx rROR,fROR,0 29c9 : 08 > php ;save flags 29ca : bd0302 > lda abst,x -29cd : dd2802 > cmp rROR,x ;test result +29cd : dd2d02 > cmp rROR,x ;test result > trap_ne 29d0 : d0fe > bne * ;failed not equal (non zero) > @@ -10965,21 +10967,21 @@ ffff = ram_top = -1 > eor_flag 0 29d3 : 4930 > eor #0|fao ;invert expected flags + always on bits > -29d5 : dd3802 > cmp fROR,x ;test flags +29d5 : dd4502 > cmp fROR,x ;test flags > trap_ne 29d8 : d0fe > bne * ;failed not equal (non zero) > 29da : ca dex 29db : 10e0 bpl tror8 -29dd : a203 ldx #3 +29dd : a205 ldx #5 29df : tror9 - set_absx zp1,$ff-fc + set_absx zps,$ff-fc > load_flag $ff-fc 29df : a9fe > lda #$ff-fc ;allow test to change I-flag (no mask) > 29e1 : 48 > pha ;use stack to load status -29e2 : b513 > lda zp1,x ;load to indexed memory +29e2 : b513 > lda zps,x ;load to indexed memory 29e4 : 9d0302 > sta abst,x 29e7 : 28 > plp @@ -10987,7 +10989,7 @@ ffff = ram_top = -1 tst_absx rROR,fROR,$ff-fnzc 29eb : 08 > php ;save flags 29ec : bd0302 > lda abst,x -29ef : dd2802 > cmp rROR,x ;test result +29ef : dd2d02 > cmp rROR,x ;test result > trap_ne 29f2 : d0fe > bne * ;failed not equal (non zero) > @@ -10995,7 +10997,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 29f5 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -29f7 : dd3802 > cmp fROR,x ;test flags +29f7 : dd4502 > cmp fROR,x ;test flags > trap_ne 29fa : d0fe > bne * ;failed not equal (non zero) > @@ -11003,14 +11005,14 @@ ffff = ram_top = -1 29fc : ca dex 29fd : 10e0 bpl tror9 -29ff : a203 ldx #3 +29ff : a205 ldx #5 2a01 : trorc8 - set_absx zp1,fc + set_absx zps,fc > load_flag fc 2a01 : a901 > lda #fc ;allow test to change I-flag (no mask) > 2a03 : 48 > pha ;use stack to load status -2a04 : b513 > lda zp1,x ;load to indexed memory +2a04 : b513 > lda zps,x ;load to indexed memory 2a06 : 9d0302 > sta abst,x 2a09 : 28 > plp @@ -11018,7 +11020,7 @@ ffff = ram_top = -1 tst_absx rRORc,fRORc,0 2a0d : 08 > php ;save flags 2a0e : bd0302 > lda abst,x -2a11 : dd2c02 > cmp rRORc,x ;test result +2a11 : dd3302 > cmp rRORc,x ;test result > trap_ne 2a14 : d0fe > bne * ;failed not equal (non zero) > @@ -11026,21 +11028,21 @@ ffff = ram_top = -1 > eor_flag 0 2a17 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2a19 : dd3c02 > cmp fRORc,x ;test flags +2a19 : dd4b02 > cmp fRORc,x ;test flags > trap_ne 2a1c : d0fe > bne * ;failed not equal (non zero) > 2a1e : ca dex 2a1f : 10e0 bpl trorc8 -2a21 : a203 ldx #3 +2a21 : a205 ldx #5 2a23 : trorc9 - set_absx zp1,$ff + set_absx zps,$ff > load_flag $ff 2a23 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2a25 : 48 > pha ;use stack to load status -2a26 : b513 > lda zp1,x ;load to indexed memory +2a26 : b513 > lda zps,x ;load to indexed memory 2a28 : 9d0302 > sta abst,x 2a2b : 28 > plp @@ -11048,7 +11050,7 @@ ffff = ram_top = -1 tst_absx rRORc,fRORc,$ff-fnzc 2a2f : 08 > php ;save flags 2a30 : bd0302 > lda abst,x -2a33 : dd2c02 > cmp rRORc,x ;test result +2a33 : dd3302 > cmp rRORc,x ;test result > trap_ne 2a36 : d0fe > bne * ;failed not equal (non zero) > @@ -11056,7 +11058,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnzc 2a39 : 497c > eor #$ff-fnzc|fao ;invert expected flags + always on bits > -2a3b : dd3c02 > cmp fRORc,x ;test flags +2a3b : dd4b02 > cmp fRORc,x ;test flags > trap_ne 2a3e : d0fe > bne * ;failed not equal (non zero) > @@ -11092,7 +11094,7 @@ ffff = ram_top = -1 tst_z rINC,fINC,0 2a5b : 08 > php ;save flags 2a5c : a50c > lda zpt -2a5e : dd4002 > cmp rINC,x ;test result +2a5e : dd5102 > cmp rINC,x ;test result > trap_ne 2a61 : d0fe > bne * ;failed not equal (non zero) > @@ -11100,7 +11102,7 @@ ffff = ram_top = -1 > eor_flag 0 2a64 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2a66 : dd4502 > cmp fINC,x ;test flags +2a66 : dd5602 > cmp fINC,x ;test flags > trap_ne 2a69 : d0fe > bne * ;failed not equal (non zero) > @@ -11126,7 +11128,7 @@ ffff = ram_top = -1 tst_z rINC,fINC,0 2a81 : 08 > php ;save flags 2a82 : a50c > lda zpt -2a84 : dd4002 > cmp rINC,x ;test result +2a84 : dd5102 > cmp rINC,x ;test result > trap_ne 2a87 : d0fe > bne * ;failed not equal (non zero) > @@ -11134,7 +11136,7 @@ ffff = ram_top = -1 > eor_flag 0 2a8a : 4930 > eor #0|fao ;invert expected flags + always on bits > -2a8c : dd4502 > cmp fINC,x ;test flags +2a8c : dd5602 > cmp fINC,x ;test flags > trap_ne 2a8f : d0fe > bne * ;failed not equal (non zero) > @@ -11162,7 +11164,7 @@ ffff = ram_top = -1 tst_z rINC,fINC,$ff-fnz 2aaa : 08 > php ;save flags 2aab : a50c > lda zpt -2aad : dd4002 > cmp rINC,x ;test result +2aad : dd5102 > cmp rINC,x ;test result > trap_ne 2ab0 : d0fe > bne * ;failed not equal (non zero) > @@ -11170,7 +11172,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2ab3 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2ab5 : dd4502 > cmp fINC,x ;test flags +2ab5 : dd5602 > cmp fINC,x ;test flags > trap_ne 2ab8 : d0fe > bne * ;failed not equal (non zero) > @@ -11196,7 +11198,7 @@ ffff = ram_top = -1 tst_z rINC,fINC,$ff-fnz 2ad0 : 08 > php ;save flags 2ad1 : a50c > lda zpt -2ad3 : dd4002 > cmp rINC,x ;test result +2ad3 : dd5102 > cmp rINC,x ;test result > trap_ne 2ad6 : d0fe > bne * ;failed not equal (non zero) > @@ -11204,7 +11206,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2ad9 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2adb : dd4502 > cmp fINC,x ;test flags +2adb : dd5602 > cmp fINC,x ;test flags > trap_ne 2ade : d0fe > bne * ;failed not equal (non zero) > @@ -11245,7 +11247,7 @@ ffff = ram_top = -1 tst_abs rINC,fINC,0 2b07 : 08 > php ;save flags 2b08 : ad0302 > lda abst -2b0b : dd4002 > cmp rINC,x ;test result +2b0b : dd5102 > cmp rINC,x ;test result > trap_ne 2b0e : d0fe > bne * ;failed not equal (non zero) > @@ -11253,7 +11255,7 @@ ffff = ram_top = -1 > eor_flag 0 2b11 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2b13 : dd4502 > cmp fINC,x ;test flags +2b13 : dd5602 > cmp fINC,x ;test flags > trap_ne 2b16 : d0fe > bne * ;failed not equal (non zero) > @@ -11279,7 +11281,7 @@ ffff = ram_top = -1 tst_abs rINC,fINC,0 2b31 : 08 > php ;save flags 2b32 : ad0302 > lda abst -2b35 : dd4002 > cmp rINC,x ;test result +2b35 : dd5102 > cmp rINC,x ;test result > trap_ne 2b38 : d0fe > bne * ;failed not equal (non zero) > @@ -11287,7 +11289,7 @@ ffff = ram_top = -1 > eor_flag 0 2b3b : 4930 > eor #0|fao ;invert expected flags + always on bits > -2b3d : dd4502 > cmp fINC,x ;test flags +2b3d : dd5602 > cmp fINC,x ;test flags > trap_ne 2b40 : d0fe > bne * ;failed not equal (non zero) > @@ -11315,7 +11317,7 @@ ffff = ram_top = -1 tst_abs rINC,fINC,$ff-fnz 2b5e : 08 > php ;save flags 2b5f : ad0302 > lda abst -2b62 : dd4002 > cmp rINC,x ;test result +2b62 : dd5102 > cmp rINC,x ;test result > trap_ne 2b65 : d0fe > bne * ;failed not equal (non zero) > @@ -11323,7 +11325,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2b68 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2b6a : dd4502 > cmp fINC,x ;test flags +2b6a : dd5602 > cmp fINC,x ;test flags > trap_ne 2b6d : d0fe > bne * ;failed not equal (non zero) > @@ -11349,7 +11351,7 @@ ffff = ram_top = -1 tst_abs rINC,fINC,$ff-fnz 2b88 : 08 > php ;save flags 2b89 : ad0302 > lda abst -2b8c : dd4002 > cmp rINC,x ;test result +2b8c : dd5102 > cmp rINC,x ;test result > trap_ne 2b8f : d0fe > bne * ;failed not equal (non zero) > @@ -11357,7 +11359,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2b92 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2b94 : dd4502 > cmp fINC,x ;test flags +2b94 : dd5602 > cmp fINC,x ;test flags > trap_ne 2b97 : d0fe > bne * ;failed not equal (non zero) > @@ -11397,7 +11399,7 @@ ffff = ram_top = -1 tst_zx rINC,fINC,0 2bbf : 08 > php ;save flags 2bc0 : b50c > lda zpt,x -2bc2 : dd4002 > cmp rINC,x ;test result +2bc2 : dd5102 > cmp rINC,x ;test result > trap_ne 2bc5 : d0fe > bne * ;failed not equal (non zero) > @@ -11405,7 +11407,7 @@ ffff = ram_top = -1 > eor_flag 0 2bc8 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2bca : dd4502 > cmp fINC,x ;test flags +2bca : dd5602 > cmp fINC,x ;test flags > trap_ne 2bcd : d0fe > bne * ;failed not equal (non zero) > @@ -11431,7 +11433,7 @@ ffff = ram_top = -1 tst_zx rINC,fINC,0 2be7 : 08 > php ;save flags 2be8 : b50c > lda zpt,x -2bea : dd4002 > cmp rINC,x ;test result +2bea : dd5102 > cmp rINC,x ;test result > trap_ne 2bed : d0fe > bne * ;failed not equal (non zero) > @@ -11439,7 +11441,7 @@ ffff = ram_top = -1 > eor_flag 0 2bf0 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2bf2 : dd4502 > cmp fINC,x ;test flags +2bf2 : dd5602 > cmp fINC,x ;test flags > trap_ne 2bf5 : d0fe > bne * ;failed not equal (non zero) > @@ -11466,7 +11468,7 @@ ffff = ram_top = -1 tst_zx rINC,fINC,$ff-fnz 2c10 : 08 > php ;save flags 2c11 : b50c > lda zpt,x -2c13 : dd4002 > cmp rINC,x ;test result +2c13 : dd5102 > cmp rINC,x ;test result > trap_ne 2c16 : d0fe > bne * ;failed not equal (non zero) > @@ -11474,7 +11476,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2c19 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2c1b : dd4502 > cmp fINC,x ;test flags +2c1b : dd5602 > cmp fINC,x ;test flags > trap_ne 2c1e : d0fe > bne * ;failed not equal (non zero) > @@ -11500,7 +11502,7 @@ ffff = ram_top = -1 tst_zx rINC,fINC,$ff-fnz 2c38 : 08 > php ;save flags 2c39 : b50c > lda zpt,x -2c3b : dd4002 > cmp rINC,x ;test result +2c3b : dd5102 > cmp rINC,x ;test result > trap_ne 2c3e : d0fe > bne * ;failed not equal (non zero) > @@ -11508,7 +11510,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2c41 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2c43 : dd4502 > cmp fINC,x ;test flags +2c43 : dd5602 > cmp fINC,x ;test flags > trap_ne 2c46 : d0fe > bne * ;failed not equal (non zero) > @@ -11548,7 +11550,7 @@ ffff = ram_top = -1 tst_absx rINC,fINC,0 2c6f : 08 > php ;save flags 2c70 : bd0302 > lda abst,x -2c73 : dd4002 > cmp rINC,x ;test result +2c73 : dd5102 > cmp rINC,x ;test result > trap_ne 2c76 : d0fe > bne * ;failed not equal (non zero) > @@ -11556,7 +11558,7 @@ ffff = ram_top = -1 > eor_flag 0 2c79 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2c7b : dd4502 > cmp fINC,x ;test flags +2c7b : dd5602 > cmp fINC,x ;test flags > trap_ne 2c7e : d0fe > bne * ;failed not equal (non zero) > @@ -11582,7 +11584,7 @@ ffff = ram_top = -1 tst_absx rINC,fINC,0 2c9b : 08 > php ;save flags 2c9c : bd0302 > lda abst,x -2c9f : dd4002 > cmp rINC,x ;test result +2c9f : dd5102 > cmp rINC,x ;test result > trap_ne 2ca2 : d0fe > bne * ;failed not equal (non zero) > @@ -11590,7 +11592,7 @@ ffff = ram_top = -1 > eor_flag 0 2ca5 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2ca7 : dd4502 > cmp fINC,x ;test flags +2ca7 : dd5602 > cmp fINC,x ;test flags > trap_ne 2caa : d0fe > bne * ;failed not equal (non zero) > @@ -11617,7 +11619,7 @@ ffff = ram_top = -1 tst_absx rINC,fINC,$ff-fnz 2cc8 : 08 > php ;save flags 2cc9 : bd0302 > lda abst,x -2ccc : dd4002 > cmp rINC,x ;test result +2ccc : dd5102 > cmp rINC,x ;test result > trap_ne 2ccf : d0fe > bne * ;failed not equal (non zero) > @@ -11625,7 +11627,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2cd2 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2cd4 : dd4502 > cmp fINC,x ;test flags +2cd4 : dd5602 > cmp fINC,x ;test flags > trap_ne 2cd7 : d0fe > bne * ;failed not equal (non zero) > @@ -11651,7 +11653,7 @@ ffff = ram_top = -1 tst_absx rINC,fINC,$ff-fnz 2cf4 : 08 > php ;save flags 2cf5 : bd0302 > lda abst,x -2cf8 : dd4002 > cmp rINC,x ;test result +2cf8 : dd5102 > cmp rINC,x ;test result > trap_ne 2cfb : d0fe > bne * ;failed not equal (non zero) > @@ -11659,7 +11661,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2cfe : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2d00 : dd4502 > cmp fINC,x ;test flags +2d00 : dd5602 > cmp fINC,x ;test flags > trap_ne 2d03 : d0fe > bne * ;failed not equal (non zero) > @@ -11687,20 +11689,20 @@ ffff = ram_top = -1 ; testing logical instructions - AND EOR ORA all addressing modes ; AND 2d1f : a203 ldx #3 ;immediate -2d21 : b51c tand lda zpAN,x -2d23 : 8d0902 sta ex_andi+1 ;set AND # operand +2d21 : b51e tand lda zpAN,x +2d23 : 8d0a02 sta ex_andi+1 ;set AND # operand set_ax absANa,0 > load_flag 0 2d26 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2d28 : 48 > pha ;use stack to load status -2d29 : bd5a02 > lda absANa,x ;precharge accu +2d29 : bd6b02 > lda absANa,x ;precharge accu 2d2c : 28 > plp -2d2d : 200802 jsr ex_andi ;execute AND # in RAM +2d2d : 200902 jsr ex_andi ;execute AND # in RAM tst_ax absrlo,absflo,0 2d30 : 08 > php ;save flags -2d31 : dd6202 > cmp absrlo,x ;test result +2d31 : dd7302 > cmp absrlo,x ;test result > trap_ne 2d34 : d0fe > bne * ;failed not equal (non zero) > @@ -11708,7 +11710,7 @@ ffff = ram_top = -1 > eor_flag 0 2d37 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2d39 : dd6602 > cmp absflo,x ;test flags +2d39 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2d3c : d0fe > bne * ;failed not equal (non zero) > @@ -11716,20 +11718,20 @@ ffff = ram_top = -1 2d3e : ca dex 2d3f : 10e0 bpl tand 2d41 : a203 ldx #3 -2d43 : b51c tand1 lda zpAN,x -2d45 : 8d0902 sta ex_andi+1 ;set AND # operand +2d43 : b51e tand1 lda zpAN,x +2d45 : 8d0a02 sta ex_andi+1 ;set AND # operand set_ax absANa,$ff > load_flag $ff 2d48 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2d4a : 48 > pha ;use stack to load status -2d4b : bd5a02 > lda absANa,x ;precharge accu +2d4b : bd6b02 > lda absANa,x ;precharge accu 2d4e : 28 > plp -2d4f : 200802 jsr ex_andi ;execute AND # in RAM +2d4f : 200902 jsr ex_andi ;execute AND # in RAM tst_ax absrlo,absflo,$ff-fnz 2d52 : 08 > php ;save flags -2d53 : dd6202 > cmp absrlo,x ;test result +2d53 : dd7302 > cmp absrlo,x ;test result > trap_ne 2d56 : d0fe > bne * ;failed not equal (non zero) > @@ -11737,7 +11739,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2d59 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2d5b : dd6602 > cmp absflo,x ;test flags +2d5b : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2d5e : d0fe > bne * ;failed not equal (non zero) > @@ -11746,20 +11748,20 @@ ffff = ram_top = -1 2d61 : 10e0 bpl tand1 2d63 : a203 ldx #3 ;zp -2d65 : b51c tand2 lda zpAN,x +2d65 : b51e tand2 lda zpAN,x 2d67 : 850c sta zpt set_ax absANa,0 > load_flag 0 2d69 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2d6b : 48 > pha ;use stack to load status -2d6c : bd5a02 > lda absANa,x ;precharge accu +2d6c : bd6b02 > lda absANa,x ;precharge accu 2d6f : 28 > plp 2d70 : 250c and zpt tst_ax absrlo,absflo,0 2d72 : 08 > php ;save flags -2d73 : dd6202 > cmp absrlo,x ;test result +2d73 : dd7302 > cmp absrlo,x ;test result > trap_ne 2d76 : d0fe > bne * ;failed not equal (non zero) > @@ -11767,7 +11769,7 @@ ffff = ram_top = -1 > eor_flag 0 2d79 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2d7b : dd6602 > cmp absflo,x ;test flags +2d7b : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2d7e : d0fe > bne * ;failed not equal (non zero) > @@ -11775,20 +11777,20 @@ ffff = ram_top = -1 2d80 : ca dex 2d81 : 10e2 bpl tand2 2d83 : a203 ldx #3 -2d85 : b51c tand3 lda zpAN,x +2d85 : b51e tand3 lda zpAN,x 2d87 : 850c sta zpt set_ax absANa,$ff > load_flag $ff 2d89 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2d8b : 48 > pha ;use stack to load status -2d8c : bd5a02 > lda absANa,x ;precharge accu +2d8c : bd6b02 > lda absANa,x ;precharge accu 2d8f : 28 > plp 2d90 : 250c and zpt tst_ax absrlo,absflo,$ff-fnz 2d92 : 08 > php ;save flags -2d93 : dd6202 > cmp absrlo,x ;test result +2d93 : dd7302 > cmp absrlo,x ;test result > trap_ne 2d96 : d0fe > bne * ;failed not equal (non zero) > @@ -11796,7 +11798,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2d99 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2d9b : dd6602 > cmp absflo,x ;test flags +2d9b : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2d9e : d0fe > bne * ;failed not equal (non zero) > @@ -11805,20 +11807,20 @@ ffff = ram_top = -1 2da1 : 10e2 bpl tand3 2da3 : a203 ldx #3 ;abs -2da5 : b51c tand4 lda zpAN,x +2da5 : b51e tand4 lda zpAN,x 2da7 : 8d0302 sta abst set_ax absANa,0 > load_flag 0 2daa : a900 > lda #0 ;allow test to change I-flag (no mask) > 2dac : 48 > pha ;use stack to load status -2dad : bd5a02 > lda absANa,x ;precharge accu +2dad : bd6b02 > lda absANa,x ;precharge accu 2db0 : 28 > plp 2db1 : 2d0302 and abst tst_ax absrlo,absflo,0 2db4 : 08 > php ;save flags -2db5 : dd6202 > cmp absrlo,x ;test result +2db5 : dd7302 > cmp absrlo,x ;test result > trap_ne 2db8 : d0fe > bne * ;failed not equal (non zero) > @@ -11826,7 +11828,7 @@ ffff = ram_top = -1 > eor_flag 0 2dbb : 4930 > eor #0|fao ;invert expected flags + always on bits > -2dbd : dd6602 > cmp absflo,x ;test flags +2dbd : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2dc0 : d0fe > bne * ;failed not equal (non zero) > @@ -11834,20 +11836,20 @@ ffff = ram_top = -1 2dc2 : ca dex 2dc3 : 10e0 bpl tand4 2dc5 : a203 ldx #3 -2dc7 : b51c tand5 lda zpAN,x +2dc7 : b51e tand5 lda zpAN,x 2dc9 : 8d0302 sta abst set_ax absANa,$ff > load_flag $ff 2dcc : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2dce : 48 > pha ;use stack to load status -2dcf : bd5a02 > lda absANa,x ;precharge accu +2dcf : bd6b02 > lda absANa,x ;precharge accu 2dd2 : 28 > plp 2dd3 : 2d0302 and abst tst_ax absrlo,absflo,$ff-fnz 2dd6 : 08 > php ;save flags -2dd7 : dd6202 > cmp absrlo,x ;test result +2dd7 : dd7302 > cmp absrlo,x ;test result > trap_ne 2dda : d0fe > bne * ;failed not equal (non zero) > @@ -11855,7 +11857,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2ddd : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2ddf : dd6602 > cmp absflo,x ;test flags +2ddf : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2de2 : d0fe > bne * ;failed not equal (non zero) > @@ -11870,13 +11872,13 @@ ffff = ram_top = -1 2de9 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2deb : 48 > pha ;use stack to load status -2dec : bd5a02 > lda absANa,x ;precharge accu +2dec : bd6b02 > lda absANa,x ;precharge accu 2def : 28 > plp -2df0 : 351c and zpAN,x +2df0 : 351e and zpAN,x tst_ax absrlo,absflo,0 2df2 : 08 > php ;save flags -2df3 : dd6202 > cmp absrlo,x ;test result +2df3 : dd7302 > cmp absrlo,x ;test result > trap_ne 2df6 : d0fe > bne * ;failed not equal (non zero) > @@ -11884,7 +11886,7 @@ ffff = ram_top = -1 > eor_flag 0 2df9 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2dfb : dd6602 > cmp absflo,x ;test flags +2dfb : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2dfe : d0fe > bne * ;failed not equal (non zero) > @@ -11898,13 +11900,13 @@ ffff = ram_top = -1 2e05 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2e07 : 48 > pha ;use stack to load status -2e08 : bd5a02 > lda absANa,x ;precharge accu +2e08 : bd6b02 > lda absANa,x ;precharge accu 2e0b : 28 > plp -2e0c : 351c and zpAN,x +2e0c : 351e and zpAN,x tst_ax absrlo,absflo,$ff-fnz 2e0e : 08 > php ;save flags -2e0f : dd6202 > cmp absrlo,x ;test result +2e0f : dd7302 > cmp absrlo,x ;test result > trap_ne 2e12 : d0fe > bne * ;failed not equal (non zero) > @@ -11912,7 +11914,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2e15 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2e17 : dd6602 > cmp absflo,x ;test flags +2e17 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2e1a : d0fe > bne * ;failed not equal (non zero) > @@ -11927,13 +11929,13 @@ ffff = ram_top = -1 2e21 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2e23 : 48 > pha ;use stack to load status -2e24 : bd5a02 > lda absANa,x ;precharge accu +2e24 : bd6b02 > lda absANa,x ;precharge accu 2e27 : 28 > plp -2e28 : 3d4e02 and absAN,x +2e28 : 3d5f02 and absAN,x tst_ax absrlo,absflo,0 2e2b : 08 > php ;save flags -2e2c : dd6202 > cmp absrlo,x ;test result +2e2c : dd7302 > cmp absrlo,x ;test result > trap_ne 2e2f : d0fe > bne * ;failed not equal (non zero) > @@ -11941,7 +11943,7 @@ ffff = ram_top = -1 > eor_flag 0 2e32 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2e34 : dd6602 > cmp absflo,x ;test flags +2e34 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2e37 : d0fe > bne * ;failed not equal (non zero) > @@ -11955,13 +11957,13 @@ ffff = ram_top = -1 2e3e : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2e40 : 48 > pha ;use stack to load status -2e41 : bd5a02 > lda absANa,x ;precharge accu +2e41 : bd6b02 > lda absANa,x ;precharge accu 2e44 : 28 > plp -2e45 : 3d4e02 and absAN,x +2e45 : 3d5f02 and absAN,x tst_ax absrlo,absflo,$ff-fnz 2e48 : 08 > php ;save flags -2e49 : dd6202 > cmp absrlo,x ;test result +2e49 : dd7302 > cmp absrlo,x ;test result > trap_ne 2e4c : d0fe > bne * ;failed not equal (non zero) > @@ -11969,7 +11971,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2e4f : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2e51 : dd6602 > cmp absflo,x ;test flags +2e51 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2e54 : d0fe > bne * ;failed not equal (non zero) > @@ -11984,13 +11986,13 @@ ffff = ram_top = -1 2e5b : a900 > lda #0 ;allow test to change I-flag (no mask) > 2e5d : 48 > pha ;use stack to load status -2e5e : b95a02 > lda absANa,y ;precharge accu +2e5e : b96b02 > lda absANa,y ;precharge accu 2e61 : 28 > plp -2e62 : 394e02 and absAN,y +2e62 : 395f02 and absAN,y tst_ay absrlo,absflo,0 2e65 : 08 > php ;save flags -2e66 : d96202 > cmp absrlo,y ;test result +2e66 : d97302 > cmp absrlo,y ;test result > trap_ne ; 2e69 : d0fe > bne * ;failed not equal (non zero) > @@ -11998,7 +12000,7 @@ ffff = ram_top = -1 > eor_flag 0 2e6c : 4930 > eor #0|fao ;invert expected flags + always on bits > -2e6e : d96602 > cmp absflo,y ;test flags +2e6e : d97702 > cmp absflo,y ;test flags > trap_ne 2e71 : d0fe > bne * ;failed not equal (non zero) > @@ -12012,13 +12014,13 @@ ffff = ram_top = -1 2e78 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2e7a : 48 > pha ;use stack to load status -2e7b : b95a02 > lda absANa,y ;precharge accu +2e7b : b96b02 > lda absANa,y ;precharge accu 2e7e : 28 > plp -2e7f : 394e02 and absAN,y +2e7f : 395f02 and absAN,y tst_ay absrlo,absflo,$ff-fnz 2e82 : 08 > php ;save flags -2e83 : d96202 > cmp absrlo,y ;test result +2e83 : d97302 > cmp absrlo,y ;test result > trap_ne ; 2e86 : d0fe > bne * ;failed not equal (non zero) > @@ -12026,7 +12028,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2e89 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2e8b : d96602 > cmp absflo,y ;test flags +2e8b : d97702 > cmp absflo,y ;test flags > trap_ne 2e8e : d0fe > bne * ;failed not equal (non zero) > @@ -12042,13 +12044,13 @@ ffff = ram_top = -1 2e97 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2e99 : 48 > pha ;use stack to load status -2e9a : b95a02 > lda absANa,y ;precharge accu +2e9a : b96b02 > lda absANa,y ;precharge accu 2e9d : 28 > plp -2e9e : 213a and (indAN,x) +2e9e : 213c and (indAN,x) tst_ay absrlo,absflo,0 2ea0 : 08 > php ;save flags -2ea1 : d96202 > cmp absrlo,y ;test result +2ea1 : d97302 > cmp absrlo,y ;test result > trap_ne ; 2ea4 : d0fe > bne * ;failed not equal (non zero) > @@ -12056,7 +12058,7 @@ ffff = ram_top = -1 > eor_flag 0 2ea7 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2ea9 : d96602 > cmp absflo,y ;test flags +2ea9 : d97702 > cmp absflo,y ;test flags > trap_ne 2eac : d0fe > bne * ;failed not equal (non zero) > @@ -12073,13 +12075,13 @@ ffff = ram_top = -1 2eb7 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2eb9 : 48 > pha ;use stack to load status -2eba : b95a02 > lda absANa,y ;precharge accu +2eba : b96b02 > lda absANa,y ;precharge accu 2ebd : 28 > plp -2ebe : 213a and (indAN,x) +2ebe : 213c and (indAN,x) tst_ay absrlo,absflo,$ff-fnz 2ec0 : 08 > php ;save flags -2ec1 : d96202 > cmp absrlo,y ;test result +2ec1 : d97302 > cmp absrlo,y ;test result > trap_ne ; 2ec4 : d0fe > bne * ;failed not equal (non zero) > @@ -12087,7 +12089,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2ec7 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2ec9 : d96602 > cmp absflo,y ;test flags +2ec9 : d97702 > cmp absflo,y ;test flags > trap_ne 2ecc : d0fe > bne * ;failed not equal (non zero) > @@ -12104,13 +12106,13 @@ ffff = ram_top = -1 2ed5 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2ed7 : 48 > pha ;use stack to load status -2ed8 : b95a02 > lda absANa,y ;precharge accu +2ed8 : b96b02 > lda absANa,y ;precharge accu 2edb : 28 > plp -2edc : 313a and (indAN),y +2edc : 313c and (indAN),y tst_ay absrlo,absflo,0 2ede : 08 > php ;save flags -2edf : d96202 > cmp absrlo,y ;test result +2edf : d97302 > cmp absrlo,y ;test result > trap_ne ; 2ee2 : d0fe > bne * ;failed not equal (non zero) > @@ -12118,7 +12120,7 @@ ffff = ram_top = -1 > eor_flag 0 2ee5 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2ee7 : d96602 > cmp absflo,y ;test flags +2ee7 : d97702 > cmp absflo,y ;test flags > trap_ne 2eea : d0fe > bne * ;failed not equal (non zero) > @@ -12132,13 +12134,13 @@ ffff = ram_top = -1 2ef1 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2ef3 : 48 > pha ;use stack to load status -2ef4 : b95a02 > lda absANa,y ;precharge accu +2ef4 : b96b02 > lda absANa,y ;precharge accu 2ef7 : 28 > plp -2ef8 : 313a and (indAN),y +2ef8 : 313c and (indAN),y tst_ay absrlo,absflo,$ff-fnz 2efa : 08 > php ;save flags -2efb : d96202 > cmp absrlo,y ;test result +2efb : d97302 > cmp absrlo,y ;test result > trap_ne ; 2efe : d0fe > bne * ;failed not equal (non zero) > @@ -12146,7 +12148,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2f01 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2f03 : d96602 > cmp absflo,y ;test flags +2f03 : d97702 > cmp absflo,y ;test flags > trap_ne 2f06 : d0fe > bne * ;failed not equal (non zero) > @@ -12167,20 +12169,20 @@ ffff = ram_top = -1 ; EOR 2f17 : a203 ldx #3 ;immediate - self modifying code -2f19 : b520 teor lda zpEO,x -2f1b : 8d0c02 sta ex_eori+1 ;set EOR # operand +2f19 : b522 teor lda zpEO,x +2f1b : 8d0d02 sta ex_eori+1 ;set EOR # operand set_ax absEOa,0 > load_flag 0 2f1e : a900 > lda #0 ;allow test to change I-flag (no mask) > 2f20 : 48 > pha ;use stack to load status -2f21 : bd5e02 > lda absEOa,x ;precharge accu +2f21 : bd6f02 > lda absEOa,x ;precharge accu 2f24 : 28 > plp -2f25 : 200b02 jsr ex_eori ;execute EOR # in RAM +2f25 : 200c02 jsr ex_eori ;execute EOR # in RAM tst_ax absrlo,absflo,0 2f28 : 08 > php ;save flags -2f29 : dd6202 > cmp absrlo,x ;test result +2f29 : dd7302 > cmp absrlo,x ;test result > trap_ne 2f2c : d0fe > bne * ;failed not equal (non zero) > @@ -12188,7 +12190,7 @@ ffff = ram_top = -1 > eor_flag 0 2f2f : 4930 > eor #0|fao ;invert expected flags + always on bits > -2f31 : dd6602 > cmp absflo,x ;test flags +2f31 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2f34 : d0fe > bne * ;failed not equal (non zero) > @@ -12196,20 +12198,20 @@ ffff = ram_top = -1 2f36 : ca dex 2f37 : 10e0 bpl teor 2f39 : a203 ldx #3 -2f3b : b520 teor1 lda zpEO,x -2f3d : 8d0c02 sta ex_eori+1 ;set EOR # operand +2f3b : b522 teor1 lda zpEO,x +2f3d : 8d0d02 sta ex_eori+1 ;set EOR # operand set_ax absEOa,$ff > load_flag $ff 2f40 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2f42 : 48 > pha ;use stack to load status -2f43 : bd5e02 > lda absEOa,x ;precharge accu +2f43 : bd6f02 > lda absEOa,x ;precharge accu 2f46 : 28 > plp -2f47 : 200b02 jsr ex_eori ;execute EOR # in RAM +2f47 : 200c02 jsr ex_eori ;execute EOR # in RAM tst_ax absrlo,absflo,$ff-fnz 2f4a : 08 > php ;save flags -2f4b : dd6202 > cmp absrlo,x ;test result +2f4b : dd7302 > cmp absrlo,x ;test result > trap_ne 2f4e : d0fe > bne * ;failed not equal (non zero) > @@ -12217,7 +12219,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2f51 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2f53 : dd6602 > cmp absflo,x ;test flags +2f53 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2f56 : d0fe > bne * ;failed not equal (non zero) > @@ -12226,20 +12228,20 @@ ffff = ram_top = -1 2f59 : 10e0 bpl teor1 2f5b : a203 ldx #3 ;zp -2f5d : b520 teor2 lda zpEO,x +2f5d : b522 teor2 lda zpEO,x 2f5f : 850c sta zpt set_ax absEOa,0 > load_flag 0 2f61 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2f63 : 48 > pha ;use stack to load status -2f64 : bd5e02 > lda absEOa,x ;precharge accu +2f64 : bd6f02 > lda absEOa,x ;precharge accu 2f67 : 28 > plp 2f68 : 450c eor zpt tst_ax absrlo,absflo,0 2f6a : 08 > php ;save flags -2f6b : dd6202 > cmp absrlo,x ;test result +2f6b : dd7302 > cmp absrlo,x ;test result > trap_ne 2f6e : d0fe > bne * ;failed not equal (non zero) > @@ -12247,7 +12249,7 @@ ffff = ram_top = -1 > eor_flag 0 2f71 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2f73 : dd6602 > cmp absflo,x ;test flags +2f73 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2f76 : d0fe > bne * ;failed not equal (non zero) > @@ -12255,20 +12257,20 @@ ffff = ram_top = -1 2f78 : ca dex 2f79 : 10e2 bpl teor2 2f7b : a203 ldx #3 -2f7d : b520 teor3 lda zpEO,x +2f7d : b522 teor3 lda zpEO,x 2f7f : 850c sta zpt set_ax absEOa,$ff > load_flag $ff 2f81 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2f83 : 48 > pha ;use stack to load status -2f84 : bd5e02 > lda absEOa,x ;precharge accu +2f84 : bd6f02 > lda absEOa,x ;precharge accu 2f87 : 28 > plp 2f88 : 450c eor zpt tst_ax absrlo,absflo,$ff-fnz 2f8a : 08 > php ;save flags -2f8b : dd6202 > cmp absrlo,x ;test result +2f8b : dd7302 > cmp absrlo,x ;test result > trap_ne 2f8e : d0fe > bne * ;failed not equal (non zero) > @@ -12276,7 +12278,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2f91 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2f93 : dd6602 > cmp absflo,x ;test flags +2f93 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2f96 : d0fe > bne * ;failed not equal (non zero) > @@ -12285,20 +12287,20 @@ ffff = ram_top = -1 2f99 : 10e2 bpl teor3 2f9b : a203 ldx #3 ;abs -2f9d : b520 teor4 lda zpEO,x +2f9d : b522 teor4 lda zpEO,x 2f9f : 8d0302 sta abst set_ax absEOa,0 > load_flag 0 2fa2 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2fa4 : 48 > pha ;use stack to load status -2fa5 : bd5e02 > lda absEOa,x ;precharge accu +2fa5 : bd6f02 > lda absEOa,x ;precharge accu 2fa8 : 28 > plp 2fa9 : 4d0302 eor abst tst_ax absrlo,absflo,0 2fac : 08 > php ;save flags -2fad : dd6202 > cmp absrlo,x ;test result +2fad : dd7302 > cmp absrlo,x ;test result > trap_ne 2fb0 : d0fe > bne * ;failed not equal (non zero) > @@ -12306,7 +12308,7 @@ ffff = ram_top = -1 > eor_flag 0 2fb3 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2fb5 : dd6602 > cmp absflo,x ;test flags +2fb5 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2fb8 : d0fe > bne * ;failed not equal (non zero) > @@ -12314,20 +12316,20 @@ ffff = ram_top = -1 2fba : ca dex 2fbb : 10e0 bpl teor4 2fbd : a203 ldx #3 -2fbf : b520 teor5 lda zpEO,x +2fbf : b522 teor5 lda zpEO,x 2fc1 : 8d0302 sta abst set_ax absEOa,$ff > load_flag $ff 2fc4 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2fc6 : 48 > pha ;use stack to load status -2fc7 : bd5e02 > lda absEOa,x ;precharge accu +2fc7 : bd6f02 > lda absEOa,x ;precharge accu 2fca : 28 > plp 2fcb : 4d0302 eor abst tst_ax absrlo,absflo,$ff-fnz 2fce : 08 > php ;save flags -2fcf : dd6202 > cmp absrlo,x ;test result +2fcf : dd7302 > cmp absrlo,x ;test result > trap_ne 2fd2 : d0fe > bne * ;failed not equal (non zero) > @@ -12335,7 +12337,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 2fd5 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -2fd7 : dd6602 > cmp absflo,x ;test flags +2fd7 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2fda : d0fe > bne * ;failed not equal (non zero) > @@ -12350,13 +12352,13 @@ ffff = ram_top = -1 2fe1 : a900 > lda #0 ;allow test to change I-flag (no mask) > 2fe3 : 48 > pha ;use stack to load status -2fe4 : bd5e02 > lda absEOa,x ;precharge accu +2fe4 : bd6f02 > lda absEOa,x ;precharge accu 2fe7 : 28 > plp -2fe8 : 5520 eor zpEO,x +2fe8 : 5522 eor zpEO,x tst_ax absrlo,absflo,0 2fea : 08 > php ;save flags -2feb : dd6202 > cmp absrlo,x ;test result +2feb : dd7302 > cmp absrlo,x ;test result > trap_ne 2fee : d0fe > bne * ;failed not equal (non zero) > @@ -12364,7 +12366,7 @@ ffff = ram_top = -1 > eor_flag 0 2ff1 : 4930 > eor #0|fao ;invert expected flags + always on bits > -2ff3 : dd6602 > cmp absflo,x ;test flags +2ff3 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 2ff6 : d0fe > bne * ;failed not equal (non zero) > @@ -12378,13 +12380,13 @@ ffff = ram_top = -1 2ffd : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 2fff : 48 > pha ;use stack to load status -3000 : bd5e02 > lda absEOa,x ;precharge accu +3000 : bd6f02 > lda absEOa,x ;precharge accu 3003 : 28 > plp -3004 : 5520 eor zpEO,x +3004 : 5522 eor zpEO,x tst_ax absrlo,absflo,$ff-fnz 3006 : 08 > php ;save flags -3007 : dd6202 > cmp absrlo,x ;test result +3007 : dd7302 > cmp absrlo,x ;test result > trap_ne 300a : d0fe > bne * ;failed not equal (non zero) > @@ -12392,7 +12394,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 300d : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -300f : dd6602 > cmp absflo,x ;test flags +300f : dd7702 > cmp absflo,x ;test flags > trap_ne ; 3012 : d0fe > bne * ;failed not equal (non zero) > @@ -12407,13 +12409,13 @@ ffff = ram_top = -1 3019 : a900 > lda #0 ;allow test to change I-flag (no mask) > 301b : 48 > pha ;use stack to load status -301c : bd5e02 > lda absEOa,x ;precharge accu +301c : bd6f02 > lda absEOa,x ;precharge accu 301f : 28 > plp -3020 : 5d5202 eor absEO,x +3020 : 5d6302 eor absEO,x tst_ax absrlo,absflo,0 3023 : 08 > php ;save flags -3024 : dd6202 > cmp absrlo,x ;test result +3024 : dd7302 > cmp absrlo,x ;test result > trap_ne 3027 : d0fe > bne * ;failed not equal (non zero) > @@ -12421,7 +12423,7 @@ ffff = ram_top = -1 > eor_flag 0 302a : 4930 > eor #0|fao ;invert expected flags + always on bits > -302c : dd6602 > cmp absflo,x ;test flags +302c : dd7702 > cmp absflo,x ;test flags > trap_ne ; 302f : d0fe > bne * ;failed not equal (non zero) > @@ -12435,13 +12437,13 @@ ffff = ram_top = -1 3036 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 3038 : 48 > pha ;use stack to load status -3039 : bd5e02 > lda absEOa,x ;precharge accu +3039 : bd6f02 > lda absEOa,x ;precharge accu 303c : 28 > plp -303d : 5d5202 eor absEO,x +303d : 5d6302 eor absEO,x tst_ax absrlo,absflo,$ff-fnz 3040 : 08 > php ;save flags -3041 : dd6202 > cmp absrlo,x ;test result +3041 : dd7302 > cmp absrlo,x ;test result > trap_ne 3044 : d0fe > bne * ;failed not equal (non zero) > @@ -12449,7 +12451,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 3047 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -3049 : dd6602 > cmp absflo,x ;test flags +3049 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 304c : d0fe > bne * ;failed not equal (non zero) > @@ -12464,13 +12466,13 @@ ffff = ram_top = -1 3053 : a900 > lda #0 ;allow test to change I-flag (no mask) > 3055 : 48 > pha ;use stack to load status -3056 : b95e02 > lda absEOa,y ;precharge accu +3056 : b96f02 > lda absEOa,y ;precharge accu 3059 : 28 > plp -305a : 595202 eor absEO,y +305a : 596302 eor absEO,y tst_ay absrlo,absflo,0 305d : 08 > php ;save flags -305e : d96202 > cmp absrlo,y ;test result +305e : d97302 > cmp absrlo,y ;test result > trap_ne ; 3061 : d0fe > bne * ;failed not equal (non zero) > @@ -12478,7 +12480,7 @@ ffff = ram_top = -1 > eor_flag 0 3064 : 4930 > eor #0|fao ;invert expected flags + always on bits > -3066 : d96602 > cmp absflo,y ;test flags +3066 : d97702 > cmp absflo,y ;test flags > trap_ne 3069 : d0fe > bne * ;failed not equal (non zero) > @@ -12492,13 +12494,13 @@ ffff = ram_top = -1 3070 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 3072 : 48 > pha ;use stack to load status -3073 : b95e02 > lda absEOa,y ;precharge accu +3073 : b96f02 > lda absEOa,y ;precharge accu 3076 : 28 > plp -3077 : 595202 eor absEO,y +3077 : 596302 eor absEO,y tst_ay absrlo,absflo,$ff-fnz 307a : 08 > php ;save flags -307b : d96202 > cmp absrlo,y ;test result +307b : d97302 > cmp absrlo,y ;test result > trap_ne ; 307e : d0fe > bne * ;failed not equal (non zero) > @@ -12506,7 +12508,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 3081 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -3083 : d96602 > cmp absflo,y ;test flags +3083 : d97702 > cmp absflo,y ;test flags > trap_ne 3086 : d0fe > bne * ;failed not equal (non zero) > @@ -12522,13 +12524,13 @@ ffff = ram_top = -1 308f : a900 > lda #0 ;allow test to change I-flag (no mask) > 3091 : 48 > pha ;use stack to load status -3092 : b95e02 > lda absEOa,y ;precharge accu +3092 : b96f02 > lda absEOa,y ;precharge accu 3095 : 28 > plp -3096 : 4142 eor (indEO,x) +3096 : 4144 eor (indEO,x) tst_ay absrlo,absflo,0 3098 : 08 > php ;save flags -3099 : d96202 > cmp absrlo,y ;test result +3099 : d97302 > cmp absrlo,y ;test result > trap_ne ; 309c : d0fe > bne * ;failed not equal (non zero) > @@ -12536,7 +12538,7 @@ ffff = ram_top = -1 > eor_flag 0 309f : 4930 > eor #0|fao ;invert expected flags + always on bits > -30a1 : d96602 > cmp absflo,y ;test flags +30a1 : d97702 > cmp absflo,y ;test flags > trap_ne 30a4 : d0fe > bne * ;failed not equal (non zero) > @@ -12553,13 +12555,13 @@ ffff = ram_top = -1 30af : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 30b1 : 48 > pha ;use stack to load status -30b2 : b95e02 > lda absEOa,y ;precharge accu +30b2 : b96f02 > lda absEOa,y ;precharge accu 30b5 : 28 > plp -30b6 : 4142 eor (indEO,x) +30b6 : 4144 eor (indEO,x) tst_ay absrlo,absflo,$ff-fnz 30b8 : 08 > php ;save flags -30b9 : d96202 > cmp absrlo,y ;test result +30b9 : d97302 > cmp absrlo,y ;test result > trap_ne ; 30bc : d0fe > bne * ;failed not equal (non zero) > @@ -12567,7 +12569,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 30bf : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -30c1 : d96602 > cmp absflo,y ;test flags +30c1 : d97702 > cmp absflo,y ;test flags > trap_ne 30c4 : d0fe > bne * ;failed not equal (non zero) > @@ -12584,13 +12586,13 @@ ffff = ram_top = -1 30cd : a900 > lda #0 ;allow test to change I-flag (no mask) > 30cf : 48 > pha ;use stack to load status -30d0 : b95e02 > lda absEOa,y ;precharge accu +30d0 : b96f02 > lda absEOa,y ;precharge accu 30d3 : 28 > plp -30d4 : 5142 eor (indEO),y +30d4 : 5144 eor (indEO),y tst_ay absrlo,absflo,0 30d6 : 08 > php ;save flags -30d7 : d96202 > cmp absrlo,y ;test result +30d7 : d97302 > cmp absrlo,y ;test result > trap_ne ; 30da : d0fe > bne * ;failed not equal (non zero) > @@ -12598,7 +12600,7 @@ ffff = ram_top = -1 > eor_flag 0 30dd : 4930 > eor #0|fao ;invert expected flags + always on bits > -30df : d96602 > cmp absflo,y ;test flags +30df : d97702 > cmp absflo,y ;test flags > trap_ne 30e2 : d0fe > bne * ;failed not equal (non zero) > @@ -12612,13 +12614,13 @@ ffff = ram_top = -1 30e9 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 30eb : 48 > pha ;use stack to load status -30ec : b95e02 > lda absEOa,y ;precharge accu +30ec : b96f02 > lda absEOa,y ;precharge accu 30ef : 28 > plp -30f0 : 5142 eor (indEO),y +30f0 : 5144 eor (indEO),y tst_ay absrlo,absflo,$ff-fnz 30f2 : 08 > php ;save flags -30f3 : d96202 > cmp absrlo,y ;test result +30f3 : d97302 > cmp absrlo,y ;test result > trap_ne ; 30f6 : d0fe > bne * ;failed not equal (non zero) > @@ -12626,7 +12628,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 30f9 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -30fb : d96602 > cmp absflo,y ;test flags +30fb : d97702 > cmp absflo,y ;test flags > trap_ne 30fe : d0fe > bne * ;failed not equal (non zero) > @@ -12647,20 +12649,20 @@ ffff = ram_top = -1 ; OR 310f : a203 ldx #3 ;immediate - self modifying code -3111 : b518 tora lda zpOR,x -3113 : 8d0f02 sta ex_orai+1 ;set ORA # operand +3111 : b51a tora lda zpOR,x +3113 : 8d1002 sta ex_orai+1 ;set ORA # operand set_ax absORa,0 > load_flag 0 3116 : a900 > lda #0 ;allow test to change I-flag (no mask) > 3118 : 48 > pha ;use stack to load status -3119 : bd5602 > lda absORa,x ;precharge accu +3119 : bd6702 > lda absORa,x ;precharge accu 311c : 28 > plp -311d : 200e02 jsr ex_orai ;execute ORA # in RAM +311d : 200f02 jsr ex_orai ;execute ORA # in RAM tst_ax absrlo,absflo,0 3120 : 08 > php ;save flags -3121 : dd6202 > cmp absrlo,x ;test result +3121 : dd7302 > cmp absrlo,x ;test result > trap_ne 3124 : d0fe > bne * ;failed not equal (non zero) > @@ -12668,7 +12670,7 @@ ffff = ram_top = -1 > eor_flag 0 3127 : 4930 > eor #0|fao ;invert expected flags + always on bits > -3129 : dd6602 > cmp absflo,x ;test flags +3129 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 312c : d0fe > bne * ;failed not equal (non zero) > @@ -12676,20 +12678,20 @@ ffff = ram_top = -1 312e : ca dex 312f : 10e0 bpl tora 3131 : a203 ldx #3 -3133 : b518 tora1 lda zpOR,x -3135 : 8d0f02 sta ex_orai+1 ;set ORA # operand +3133 : b51a tora1 lda zpOR,x +3135 : 8d1002 sta ex_orai+1 ;set ORA # operand set_ax absORa,$ff > load_flag $ff 3138 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 313a : 48 > pha ;use stack to load status -313b : bd5602 > lda absORa,x ;precharge accu +313b : bd6702 > lda absORa,x ;precharge accu 313e : 28 > plp -313f : 200e02 jsr ex_orai ;execute ORA # in RAM +313f : 200f02 jsr ex_orai ;execute ORA # in RAM tst_ax absrlo,absflo,$ff-fnz 3142 : 08 > php ;save flags -3143 : dd6202 > cmp absrlo,x ;test result +3143 : dd7302 > cmp absrlo,x ;test result > trap_ne 3146 : d0fe > bne * ;failed not equal (non zero) > @@ -12697,7 +12699,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 3149 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -314b : dd6602 > cmp absflo,x ;test flags +314b : dd7702 > cmp absflo,x ;test flags > trap_ne ; 314e : d0fe > bne * ;failed not equal (non zero) > @@ -12706,20 +12708,20 @@ ffff = ram_top = -1 3151 : 10e0 bpl tora1 3153 : a203 ldx #3 ;zp -3155 : b518 tora2 lda zpOR,x +3155 : b51a tora2 lda zpOR,x 3157 : 850c sta zpt set_ax absORa,0 > load_flag 0 3159 : a900 > lda #0 ;allow test to change I-flag (no mask) > 315b : 48 > pha ;use stack to load status -315c : bd5602 > lda absORa,x ;precharge accu +315c : bd6702 > lda absORa,x ;precharge accu 315f : 28 > plp 3160 : 050c ora zpt tst_ax absrlo,absflo,0 3162 : 08 > php ;save flags -3163 : dd6202 > cmp absrlo,x ;test result +3163 : dd7302 > cmp absrlo,x ;test result > trap_ne 3166 : d0fe > bne * ;failed not equal (non zero) > @@ -12727,7 +12729,7 @@ ffff = ram_top = -1 > eor_flag 0 3169 : 4930 > eor #0|fao ;invert expected flags + always on bits > -316b : dd6602 > cmp absflo,x ;test flags +316b : dd7702 > cmp absflo,x ;test flags > trap_ne ; 316e : d0fe > bne * ;failed not equal (non zero) > @@ -12735,20 +12737,20 @@ ffff = ram_top = -1 3170 : ca dex 3171 : 10e2 bpl tora2 3173 : a203 ldx #3 -3175 : b518 tora3 lda zpOR,x +3175 : b51a tora3 lda zpOR,x 3177 : 850c sta zpt set_ax absORa,$ff > load_flag $ff 3179 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 317b : 48 > pha ;use stack to load status -317c : bd5602 > lda absORa,x ;precharge accu +317c : bd6702 > lda absORa,x ;precharge accu 317f : 28 > plp 3180 : 050c ora zpt tst_ax absrlo,absflo,$ff-fnz 3182 : 08 > php ;save flags -3183 : dd6202 > cmp absrlo,x ;test result +3183 : dd7302 > cmp absrlo,x ;test result > trap_ne 3186 : d0fe > bne * ;failed not equal (non zero) > @@ -12756,7 +12758,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 3189 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -318b : dd6602 > cmp absflo,x ;test flags +318b : dd7702 > cmp absflo,x ;test flags > trap_ne ; 318e : d0fe > bne * ;failed not equal (non zero) > @@ -12765,20 +12767,20 @@ ffff = ram_top = -1 3191 : 10e2 bpl tora3 3193 : a203 ldx #3 ;abs -3195 : b518 tora4 lda zpOR,x +3195 : b51a tora4 lda zpOR,x 3197 : 8d0302 sta abst set_ax absORa,0 > load_flag 0 319a : a900 > lda #0 ;allow test to change I-flag (no mask) > 319c : 48 > pha ;use stack to load status -319d : bd5602 > lda absORa,x ;precharge accu +319d : bd6702 > lda absORa,x ;precharge accu 31a0 : 28 > plp 31a1 : 0d0302 ora abst tst_ax absrlo,absflo,0 31a4 : 08 > php ;save flags -31a5 : dd6202 > cmp absrlo,x ;test result +31a5 : dd7302 > cmp absrlo,x ;test result > trap_ne 31a8 : d0fe > bne * ;failed not equal (non zero) > @@ -12786,7 +12788,7 @@ ffff = ram_top = -1 > eor_flag 0 31ab : 4930 > eor #0|fao ;invert expected flags + always on bits > -31ad : dd6602 > cmp absflo,x ;test flags +31ad : dd7702 > cmp absflo,x ;test flags > trap_ne ; 31b0 : d0fe > bne * ;failed not equal (non zero) > @@ -12794,20 +12796,20 @@ ffff = ram_top = -1 31b2 : ca dex 31b3 : 10e0 bpl tora4 31b5 : a203 ldx #3 -31b7 : b518 tora5 lda zpOR,x +31b7 : b51a tora5 lda zpOR,x 31b9 : 8d0302 sta abst set_ax absORa,$ff > load_flag $ff 31bc : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 31be : 48 > pha ;use stack to load status -31bf : bd5602 > lda absORa,x ;precharge accu +31bf : bd6702 > lda absORa,x ;precharge accu 31c2 : 28 > plp 31c3 : 0d0302 ora abst tst_ax absrlo,absflo,$ff-fnz 31c6 : 08 > php ;save flags -31c7 : dd6202 > cmp absrlo,x ;test result +31c7 : dd7302 > cmp absrlo,x ;test result > trap_ne 31ca : d0fe > bne * ;failed not equal (non zero) > @@ -12815,7 +12817,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 31cd : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -31cf : dd6602 > cmp absflo,x ;test flags +31cf : dd7702 > cmp absflo,x ;test flags > trap_ne ; 31d2 : d0fe > bne * ;failed not equal (non zero) > @@ -12830,13 +12832,13 @@ ffff = ram_top = -1 31d9 : a900 > lda #0 ;allow test to change I-flag (no mask) > 31db : 48 > pha ;use stack to load status -31dc : bd5602 > lda absORa,x ;precharge accu +31dc : bd6702 > lda absORa,x ;precharge accu 31df : 28 > plp -31e0 : 1518 ora zpOR,x +31e0 : 151a ora zpOR,x tst_ax absrlo,absflo,0 31e2 : 08 > php ;save flags -31e3 : dd6202 > cmp absrlo,x ;test result +31e3 : dd7302 > cmp absrlo,x ;test result > trap_ne 31e6 : d0fe > bne * ;failed not equal (non zero) > @@ -12844,7 +12846,7 @@ ffff = ram_top = -1 > eor_flag 0 31e9 : 4930 > eor #0|fao ;invert expected flags + always on bits > -31eb : dd6602 > cmp absflo,x ;test flags +31eb : dd7702 > cmp absflo,x ;test flags > trap_ne ; 31ee : d0fe > bne * ;failed not equal (non zero) > @@ -12858,13 +12860,13 @@ ffff = ram_top = -1 31f5 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 31f7 : 48 > pha ;use stack to load status -31f8 : bd5602 > lda absORa,x ;precharge accu +31f8 : bd6702 > lda absORa,x ;precharge accu 31fb : 28 > plp -31fc : 1518 ora zpOR,x +31fc : 151a ora zpOR,x tst_ax absrlo,absflo,$ff-fnz 31fe : 08 > php ;save flags -31ff : dd6202 > cmp absrlo,x ;test result +31ff : dd7302 > cmp absrlo,x ;test result > trap_ne 3202 : d0fe > bne * ;failed not equal (non zero) > @@ -12872,7 +12874,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 3205 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -3207 : dd6602 > cmp absflo,x ;test flags +3207 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 320a : d0fe > bne * ;failed not equal (non zero) > @@ -12887,13 +12889,13 @@ ffff = ram_top = -1 3211 : a900 > lda #0 ;allow test to change I-flag (no mask) > 3213 : 48 > pha ;use stack to load status -3214 : bd5602 > lda absORa,x ;precharge accu +3214 : bd6702 > lda absORa,x ;precharge accu 3217 : 28 > plp -3218 : 1d4a02 ora absOR,x +3218 : 1d5b02 ora absOR,x tst_ax absrlo,absflo,0 321b : 08 > php ;save flags -321c : dd6202 > cmp absrlo,x ;test result +321c : dd7302 > cmp absrlo,x ;test result > trap_ne 321f : d0fe > bne * ;failed not equal (non zero) > @@ -12901,7 +12903,7 @@ ffff = ram_top = -1 > eor_flag 0 3222 : 4930 > eor #0|fao ;invert expected flags + always on bits > -3224 : dd6602 > cmp absflo,x ;test flags +3224 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 3227 : d0fe > bne * ;failed not equal (non zero) > @@ -12915,13 +12917,13 @@ ffff = ram_top = -1 322e : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 3230 : 48 > pha ;use stack to load status -3231 : bd5602 > lda absORa,x ;precharge accu +3231 : bd6702 > lda absORa,x ;precharge accu 3234 : 28 > plp -3235 : 1d4a02 ora absOR,x +3235 : 1d5b02 ora absOR,x tst_ax absrlo,absflo,$ff-fnz 3238 : 08 > php ;save flags -3239 : dd6202 > cmp absrlo,x ;test result +3239 : dd7302 > cmp absrlo,x ;test result > trap_ne 323c : d0fe > bne * ;failed not equal (non zero) > @@ -12929,7 +12931,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 323f : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -3241 : dd6602 > cmp absflo,x ;test flags +3241 : dd7702 > cmp absflo,x ;test flags > trap_ne ; 3244 : d0fe > bne * ;failed not equal (non zero) > @@ -12944,13 +12946,13 @@ ffff = ram_top = -1 324b : a900 > lda #0 ;allow test to change I-flag (no mask) > 324d : 48 > pha ;use stack to load status -324e : b95602 > lda absORa,y ;precharge accu +324e : b96702 > lda absORa,y ;precharge accu 3251 : 28 > plp -3252 : 194a02 ora absOR,y +3252 : 195b02 ora absOR,y tst_ay absrlo,absflo,0 3255 : 08 > php ;save flags -3256 : d96202 > cmp absrlo,y ;test result +3256 : d97302 > cmp absrlo,y ;test result > trap_ne ; 3259 : d0fe > bne * ;failed not equal (non zero) > @@ -12958,7 +12960,7 @@ ffff = ram_top = -1 > eor_flag 0 325c : 4930 > eor #0|fao ;invert expected flags + always on bits > -325e : d96602 > cmp absflo,y ;test flags +325e : d97702 > cmp absflo,y ;test flags > trap_ne 3261 : d0fe > bne * ;failed not equal (non zero) > @@ -12972,13 +12974,13 @@ ffff = ram_top = -1 3268 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 326a : 48 > pha ;use stack to load status -326b : b95602 > lda absORa,y ;precharge accu +326b : b96702 > lda absORa,y ;precharge accu 326e : 28 > plp -326f : 194a02 ora absOR,y +326f : 195b02 ora absOR,y tst_ay absrlo,absflo,$ff-fnz 3272 : 08 > php ;save flags -3273 : d96202 > cmp absrlo,y ;test result +3273 : d97302 > cmp absrlo,y ;test result > trap_ne ; 3276 : d0fe > bne * ;failed not equal (non zero) > @@ -12986,7 +12988,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 3279 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -327b : d96602 > cmp absflo,y ;test flags +327b : d97702 > cmp absflo,y ;test flags > trap_ne 327e : d0fe > bne * ;failed not equal (non zero) > @@ -13002,13 +13004,13 @@ ffff = ram_top = -1 3287 : a900 > lda #0 ;allow test to change I-flag (no mask) > 3289 : 48 > pha ;use stack to load status -328a : b95602 > lda absORa,y ;precharge accu +328a : b96702 > lda absORa,y ;precharge accu 328d : 28 > plp -328e : 014a ora (indOR,x) +328e : 014c ora (indOR,x) tst_ay absrlo,absflo,0 3290 : 08 > php ;save flags -3291 : d96202 > cmp absrlo,y ;test result +3291 : d97302 > cmp absrlo,y ;test result > trap_ne ; 3294 : d0fe > bne * ;failed not equal (non zero) > @@ -13016,7 +13018,7 @@ ffff = ram_top = -1 > eor_flag 0 3297 : 4930 > eor #0|fao ;invert expected flags + always on bits > -3299 : d96602 > cmp absflo,y ;test flags +3299 : d97702 > cmp absflo,y ;test flags > trap_ne 329c : d0fe > bne * ;failed not equal (non zero) > @@ -13033,13 +13035,13 @@ ffff = ram_top = -1 32a7 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 32a9 : 48 > pha ;use stack to load status -32aa : b95602 > lda absORa,y ;precharge accu +32aa : b96702 > lda absORa,y ;precharge accu 32ad : 28 > plp -32ae : 014a ora (indOR,x) +32ae : 014c ora (indOR,x) tst_ay absrlo,absflo,$ff-fnz 32b0 : 08 > php ;save flags -32b1 : d96202 > cmp absrlo,y ;test result +32b1 : d97302 > cmp absrlo,y ;test result > trap_ne ; 32b4 : d0fe > bne * ;failed not equal (non zero) > @@ -13047,7 +13049,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 32b7 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -32b9 : d96602 > cmp absflo,y ;test flags +32b9 : d97702 > cmp absflo,y ;test flags > trap_ne 32bc : d0fe > bne * ;failed not equal (non zero) > @@ -13064,13 +13066,13 @@ ffff = ram_top = -1 32c5 : a900 > lda #0 ;allow test to change I-flag (no mask) > 32c7 : 48 > pha ;use stack to load status -32c8 : b95602 > lda absORa,y ;precharge accu +32c8 : b96702 > lda absORa,y ;precharge accu 32cb : 28 > plp -32cc : 114a ora (indOR),y +32cc : 114c ora (indOR),y tst_ay absrlo,absflo,0 32ce : 08 > php ;save flags -32cf : d96202 > cmp absrlo,y ;test result +32cf : d97302 > cmp absrlo,y ;test result > trap_ne ; 32d2 : d0fe > bne * ;failed not equal (non zero) > @@ -13078,7 +13080,7 @@ ffff = ram_top = -1 > eor_flag 0 32d5 : 4930 > eor #0|fao ;invert expected flags + always on bits > -32d7 : d96602 > cmp absflo,y ;test flags +32d7 : d97702 > cmp absflo,y ;test flags > trap_ne 32da : d0fe > bne * ;failed not equal (non zero) > @@ -13092,13 +13094,13 @@ ffff = ram_top = -1 32e1 : a9ff > lda #$ff ;allow test to change I-flag (no mask) > 32e3 : 48 > pha ;use stack to load status -32e4 : b95602 > lda absORa,y ;precharge accu +32e4 : b96702 > lda absORa,y ;precharge accu 32e7 : 28 > plp -32e8 : 114a ora (indOR),y +32e8 : 114c ora (indOR),y tst_ay absrlo,absflo,$ff-fnz 32ea : 08 > php ;save flags -32eb : d96202 > cmp absrlo,y ;test result +32eb : d97302 > cmp absrlo,y ;test result > trap_ne ; 32ee : d0fe > bne * ;failed not equal (non zero) > @@ -13106,7 +13108,7 @@ ffff = ram_top = -1 > eor_flag $ff-fnz 32f1 : 497d > eor #$ff-fnz|fao ;invert expected flags + always on bits > -32f3 : d96602 > cmp absflo,y ;test flags +32f3 : d97702 > cmp absflo,y ;test flags > trap_ne 32f6 : d0fe > bne * ;failed not equal (non zero) > @@ -13452,9 +13454,9 @@ ffff = ram_top = -1 ; decimal ADC / SBC # 34b9 : 08 php ;save carry for subtract 34ba : a50e lda ad2 -34bc : 8d1202 sta ex_adci+1 ;set ADC # operand +34bc : 8d1302 sta ex_adci+1 ;set ADC # operand 34bf : a50d lda ad1 -34c1 : 201102 jsr ex_adci ;execute ADC # in RAM +34c1 : 201202 jsr ex_adci ;execute ADC # in RAM 34c4 : 08 php 34c5 : c50f cmp adrl ;check result trap_ne ;bad result @@ -13469,9 +13471,9 @@ ffff = ram_top = -1 34d0 : 28 plp 34d1 : 08 php ;save carry for next add 34d2 : a512 lda sb2 -34d4 : 8d1502 sta ex_sbci+1 ;set SBC # operand +34d4 : 8d1602 sta ex_sbci+1 ;set SBC # operand 34d7 : a50d lda ad1 -34d9 : 201402 jsr ex_sbci ;execute SBC # in RAM +34d9 : 201502 jsr ex_sbci ;execute SBC # in RAM 34dc : 08 php 34dd : c50f cmp adrl ;check result trap_ne ;bad result @@ -13580,7 +13582,7 @@ ffff = ram_top = -1 ; decimal ADC / SBC (zp,x) 3559 : 08 php ;save carry for subtract 355a : a50d lda ad1 -355c : 6144 adc (lo adi2-ad2,x) ;perform add +355c : 6146 adc (lo adi2-ad2,x) ;perform add 355e : 08 php 355f : c50f cmp adrl ;check result trap_ne ;bad result @@ -13595,7 +13597,7 @@ ffff = ram_top = -1 356a : 28 plp 356b : 08 php ;save carry for next add 356c : a50d lda ad1 -356e : e146 sbc (lo sbi2-ad2,x) ;perform subtract +356e : e148 sbc (lo sbi2-ad2,x) ;perform subtract 3570 : 08 php 3571 : c50f cmp adrl ;check result trap_ne ;bad result @@ -13611,7 +13613,7 @@ ffff = ram_top = -1 ; decimal ADC / SBC (abs),y 357d : 08 php ;save carry for subtract 357e : a50d lda ad1 -3580 : 7156 adc (adiy2),y ;perform add +3580 : 7158 adc (adiy2),y ;perform add 3582 : 08 php 3583 : c50f cmp adrl ;check result trap_ne ;bad result @@ -13626,7 +13628,7 @@ ffff = ram_top = -1 358e : 28 plp 358f : 08 php ;save carry for next add 3590 : a50d lda ad1 -3592 : f158 sbc (sbiy2),y ;perform subtract +3592 : f15a sbc (sbiy2),y ;perform subtract 3594 : 08 php 3595 : c50f cmp adrl ;check result trap_ne ;bad result @@ -13724,9 +13726,9 @@ ffff = ram_top = -1 ; binary ADC / SBC # 3604 : 08 php ;save carry for subtract 3605 : a50e lda ad2 -3607 : 8d1202 sta ex_adci+1 ;set ADC # operand +3607 : 8d1302 sta ex_adci+1 ;set ADC # operand 360a : a50d lda ad1 -360c : 201102 jsr ex_adci ;execute ADC # in RAM +360c : 201202 jsr ex_adci ;execute ADC # in RAM 360f : 08 php 3610 : c50f cmp adrl ;check result trap_ne ;bad result @@ -13741,9 +13743,9 @@ ffff = ram_top = -1 361b : 28 plp 361c : 08 php ;save carry for next add 361d : a512 lda sb2 -361f : 8d1502 sta ex_sbci+1 ;set SBC # operand +361f : 8d1602 sta ex_sbci+1 ;set SBC # operand 3622 : a50d lda ad1 -3624 : 201402 jsr ex_sbci ;execute SBC # in RAM +3624 : 201502 jsr ex_sbci ;execute SBC # in RAM 3627 : 08 php 3628 : c50f cmp adrl ;check result trap_ne ;bad result @@ -13852,7 +13854,7 @@ ffff = ram_top = -1 ; binary ADC / SBC (zp,x) 36a4 : 08 php ;save carry for subtract 36a5 : a50d lda ad1 -36a7 : 6144 adc (lo adi2-ad2,x) ;perform add +36a7 : 6146 adc (lo adi2-ad2,x) ;perform add 36a9 : 08 php 36aa : c50f cmp adrl ;check result trap_ne ;bad result @@ -13867,7 +13869,7 @@ ffff = ram_top = -1 36b5 : 28 plp 36b6 : 08 php ;save carry for next add 36b7 : a50d lda ad1 -36b9 : e146 sbc (lo sbi2-ad2,x) ;perform subtract +36b9 : e148 sbc (lo sbi2-ad2,x) ;perform subtract 36bb : 08 php 36bc : c50f cmp adrl ;check result trap_ne ;bad result @@ -13883,7 +13885,7 @@ ffff = ram_top = -1 ; binary ADC / SBC (abs),y 36c8 : 08 php ;save carry for subtract 36c9 : a50d lda ad1 -36cb : 7156 adc (adiy2),y ;perform add +36cb : 7158 adc (adiy2),y ;perform add 36cd : 08 php 36ce : c50f cmp adrl ;check result trap_ne ;bad result @@ -13898,7 +13900,7 @@ ffff = ram_top = -1 36d9 : 28 plp 36da : 08 php ;save carry for next add 36db : a50d lda ad1 -36dd : f158 sbc (sbiy2),y ;perform subtract +36dd : f15a sbc (sbiy2),y ;perform subtract 36df : 08 php 36e0 : c50f cmp adrl ;check result trap_ne ;bad result @@ -14249,6 +14251,7 @@ ffff = ram_top = -1 ;copy of data to initialize BSS segment if load_data_direct != 1 zp_init + zps_ db $80,1 ;additional shift pattern to test zero result & flag zp1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR zp7f_ db $7f ;test pattern for compare ;logical zeropage operands @@ -14300,34 +14303,35 @@ ffff = ram_top = -1 rts ex_sbc_ sbc #0 ;execute immediate opcodes rts + ;zps db $80,1 ;additional shift patterns test zero result & flag abs1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR abs7f_ db $7f ;test pattern for compare ;loads - fLDx_ db fn,fn,0,fz ;expected flags for load + fLDx_ db fn,fn,0,fz ;expected flags for load ;shifts - rASL_ ;expected result ASL & ROL -carry - rROL_ db $86,$04,$82,0 ; " - rROLc_ db $87,$05,$83,1 ;expected result ROL +carry - rLSR_ ;expected result LSR & ROR -carry - rROR_ db $61,$41,$20,0 ; " - rRORc_ db $e1,$c1,$a0,$80 ;expected result ROR +carry - fASL_ ;expected flags for shifts - fROL_ db fnc,fc,fn,fz ;no carry in - fROLc_ db fnc,fc,fn,0 ;carry in + rASL_ ;expected result ASL & ROL -carry + rROL_ db 0,2,$86,$04,$82,0 + rROLc_ db 1,3,$87,$05,$83,1 ;expected result ROL +carry + rLSR_ ;expected result LSR & ROR -carry + rROR_ db $40,0,$61,$41,$20,0 + rRORc_ db $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry + fASL_ ;expected flags for shifts + fROL_ db fzc,0,fnc,fc,fn,fz ;no carry in + fROLc_ db fc,0,fnc,fc,fn,0 ;carry in fLSR_ - fROR_ db fc,0,fc,fz ;no carry in - fRORc_ db fnc,fn,fnc,fn ;carry in + fROR_ db 0,fzc,fc,0,fc,fz ;no carry in + fRORc_ db fn,fnc,fnc,fn,fnc,fn ;carry in ;increments (decrements) - rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC - fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC + rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC + fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC ;logical memory operand - absOR_ db 0,$1f,$71,$80 ;test pattern for OR - absAN_ db $0f,$ff,$7f,$80 ;test pattern for AND - absEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR + absOR_ db 0,$1f,$71,$80 ;test pattern for OR + absAN_ db $0f,$ff,$7f,$80 ;test pattern for AND + absEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR ;logical accu operand - absORa_ db 0,$f1,$1f,0 ;test pattern for OR - absANa_ db $f0,$ff,$ff,$ff ;test pattern for AND - absEOa_ db $ff,$f0,$f0,$0f ;test pattern for EOR + absORa_ db 0,$f1,$1f,0 ;test pattern for OR + absANa_ db $f0,$ff,$ff,$ff ;test pattern for AND + absEOa_ db $ff,$f0,$f0,$0f ;test pattern for EOR ;logical results absrlo_ db 0,$ff,$7f,$80 absflo_ db fz,fn,0,fn @@ -14354,7 +14358,7 @@ fffe : ab37 dw irq_trap fffa = end start No errors in pass 2. -Wrote binary from address $0000 through $ffff. -Total size 65536 bytes. +Wrote binary from address $000a through $ffff. +Total size 65526 bytes. Program start address is at $0400 (1024). \ No newline at end of file diff --git a/src/test/kotlin/6502_functional_tests/bin_files/6502_interrupt_test.bin b/src/test/kotlin/6502_functional_tests/bin_files/6502_interrupt_test.bin new file mode 100644 index 0000000000000000000000000000000000000000..52a3f6bdbc4316190318bfe1fc7b2cd644908a77 GIT binary patch literal 65526 zcmeIxzfMz87y$6w+r}b)eFe8RaddGbnwTO*gOiWIBe0+o#HBodQ$qsDjbV^M6B5M4 z$q~#>+P50PI`EH*-3Y2SJG1bq?3m1 zou&56u^Df}m^yvdNxv+2(r>F->P07A%Q81YiRthCQc>Vzd%q}fe*Kk2flr~p-mL}3 zCQsaNQYyL&ZABqyQdf^dS0j(x{z;W;$tep_)xshj%%j&U3QG2i0EhXRp_MSPj=8#Ba`R&95~!7eYY2 za+a<&^53Pejl-k3RKM3rvxW0kIUasgd-L7xC{C7Yi_P_6jp?nKP-8X=Esv>jKU;{; z@=}+BQrUO9H`CoN#mQ=IF$*Xa0ci-x7UFn!I$5qQ-uT>25FkK+009C72oNAZfB*pk z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7 z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5;& Ne+WFPu2(mzzX6;68z2Ax literal 0 HcmV?d00001 diff --git a/src/test/kotlin/6502_functional_tests/bin_files/6502_interrupt_test.lst b/src/test/kotlin/6502_functional_tests/bin_files/6502_interrupt_test.lst new file mode 100644 index 0000000..4f12385 --- /dev/null +++ b/src/test/kotlin/6502_functional_tests/bin_files/6502_interrupt_test.lst @@ -0,0 +1,1375 @@ +AS65 Assembler for R6502 [1.42]. Copyright 1994-2007, Frank A. Kingswood Page 1 +---------------------------------------------------- 6502_interrupt_test.a65 ----------------------------------------------------- + +1025 lines read, no errors in pass 1. + ; + ; 6 5 0 2 I N T E R R U P T T E S T + ; + ; Copyright (C) 2013 Klaus Dormann + ; + ; This program is free software: you can redistribute it and/or modify + ; it under the terms of the GNU General Public License as published by + ; the Free Software Foundation, either version 3 of the License, or + ; (at your option) any later version. + ; + ; This program is distributed in the hope that it will be useful, + ; but WITHOUT ANY WARRANTY; without even the implied warranty of + ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + ; GNU General Public License for more details. + ; + ; You should have received a copy of the GNU General Public License + ; along with this program. If not, see . + + + ; This program is designed to test IRQ and NMI of a 6502 emulator. It requires + ; an internal or external feedback register to the IRQ & NMI inputs + ; + ; version 15-aug-2014 + ; contact info at http://2m5.de or email K@2m5.de + ; + ; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/ + ; command line switches: -l -m -s2 -w -h0 + ; | | | | no page headers in listing + ; | | | wide listing (133 char/col) + ; | | write intel hex file instead of binary + ; | expand macros in listing + ; generate pass2 listing + ; + ; No IO - should be run from a monitor with access to registers. + ; To run load intel hex image with a load command, than alter PC to 400 hex and + ; enter a go command. + ; Loop on program counter determines error or successful completion of test. + ; Check listing for relevant traps (jump/branch *). + ; + ; Debugging hints: + ; Most of the code is written sequentially. if you hit a trap, check the + ; immediately preceeding code for the instruction to be tested. Results are + ; tested first, flags are checked second by pushing them onto the stack and + ; pulling them to the accumulator after the result was checked. The "real" + ; flags are no longer valid for the tested instruction at this time! + ; If the tested instruction was indexed, the relevant index (X or Y) must + ; also be checked. Opposed to the flags, X and Y registers are still valid. + ; + ; versions: + ; 19-jul-2013 1st version distributed for testing + ; 16-aug-2013 added error report to standard output option + ; 15-aug-2014 added filter to feedback (bit 7 will cause diag stop in emu) + + + ; C O N F I G U R A T I O N + ; + ;ROM_vectors MUST be writable & the I_flag MUST be alterable + + ;load_data_direct (0=move from code segment, 1=load directly) + ;loading directly is preferred but may not be supported by your platform + ;0 produces only consecutive object code, 1 is not suitable for a binary image +0001 = load_data_direct = 1 + + ;NMI & IRQ are tested with a feedback register + ;emulators diag register - set i_drive = 0 for a latch (74HC573) +bffc = I_port = $bffc ;feedback port address +0000 = I_ddr = 0 ;feedback DDR address, 0 = no DDR +0001 = I_drive = 1 ;0 = totem pole, 1 = open collector +0000 = IRQ_bit = 0 ;bit number of feedback to IRQ +0001 = NMI_bit = 1 ;bit number of feedback to NMI, -1 if not available +007f = I_filter = $7f ;filtering bit 7 = diag stop + + ;typical IO chip port B - set i_drive = 0 to avoid pullup resistors + ;I_port = $bfb2 ;feedback port address + ;I_ddr = $bfb3 ;feedback DDR address, 0 = no DDR + ;I_drive = 1 ;0 = totem pole, 1 = open collector + ;IRQ_bit = 0 ;bit number of feedback to IRQ + ;NMI_bit = 1 ;bit number of feedback to NMI, -1 if not available + ;I_filter = $ff ;no bits filtered + + ;decimal mode flag during IRQ, NMI & BRK +0000 = D_clear = 0 ;0 = not cleared (NMOS), 1 = cleared (CMOS) + + ;configure memory - try to stay away from memory used by the system + ;zero_page memory start address, 6 consecutive Bytes required +000a = zero_page = $a + + ;data_segment memory start address, 4 consecutive Bytes required +0200 = data_segment = $200 + + ;code_segment memory start address +0400 = code_segment = $400 + + ;report errors through I/O channel (0=use standard self trap loops, 1=include + ;report.i65 as I/O channel) +0000 = report = 0 + + noopt ;do not take shortcuts + + ;macros for error & success traps to allow user modification + ;example: + ;trap macro + ; jsr my_error_handler + ; endm + ;trap_eq macro + ; bne skip\? + ; trap ;failed equal (zero) + ;skip\? + ; endm + ; + ; my_error_handler should pop the calling address from the stack and report it. + ; putting larger portions of code (more than 3 bytes) inside the trap macro + ; may lead to branch range problems for some tests. + if report = 0 + trap macro + jmp * ;failed anyway + endm + trap_eq macro + beq * ;failed equal (zero) + endm + trap_ne macro + bne * ;failed not equal (non zero) + endm + ; please observe that during the test the stack gets invalidated + ; therefore a RTS inside the success macro is not possible + success macro + jmp * ;test passed, no errors + endm + endif + if report = 1 + trap macro + jsr report_error + endm + trap_eq macro + bne skip\? + trap ;failed equal (zero) + skip\? + endm + trap_ne macro + beq skip\? + trap ;failed not equal (non zero) + skip\? + endm + ; please observe that during the test the stack gets invalidated + ; therefore a RTS inside the success macro is not possible + success macro + jsr report_success + endm + endif + + +0001 = carry equ %00000001 ;flag bits in status +0002 = zero equ %00000010 +0004 = intdis equ %00000100 +0008 = decmode equ %00001000 +0010 = break equ %00010000 +0020 = reserv equ %00100000 +0040 = overfl equ %01000000 +0080 = minus equ %10000000 + +0001 = fc equ carry +0002 = fz equ zero +0003 = fzc equ carry+zero +0040 = fv equ overfl +0042 = fvz equ overfl+zero +0080 = fn equ minus +0081 = fnc equ minus+carry +0082 = fnz equ minus+zero +0083 = fnzc equ minus+zero+carry +00c0 = fnv equ minus+overfl + +0030 = fao equ break+reserv ;bits always on after PHP, BRK +0034 = fai equ fao+intdis ;+ forced interrupt disable +00ff = m8 equ $ff ;8 bit mask +00fb = m8i equ $ff&~intdis ;8 bit mask - interrupt disable + + ;macros to set status + push_stat macro ;setting flags in the processor status register + lda #\1 + pha ;use stack to load status + endm + + set_stat macro ;setting flags in the processor status register + lda #\1 + pha ;use stack to load status + plp + endm + + if load_data_direct = 1 + data + else + bss ;uninitialized segment, copy of data at end of code! + endif +000a = org zero_page + ;BRK, IRQ, NMI test interrupt save +000a : zpt +000a : 00 irq_a ds 1 ;a register +000b : 00 irq_x ds 1 ;x register +000c : 00 irq_f ds 1 ;flags +000d : 00 nmi_a ds 1 ;a register +000e : 00 nmi_x ds 1 ;x register +000f : 00 nmi_f ds 1 ;flags +0010 : zp_bss + + ;fixed stack locations +01fe = lst_f equ $1fe ;last flags before interrupt +01ff = lst_a equ $1ff ;last accumulator before interrupt + +0200 = org data_segment + ;concurrent NMI, IRQ & BRK test result +0200 : 00 nmi_count ds 1 ;lowest number handled first, $ff = never +0201 : 00 irq_count ds 1 ;separation-1 = instructions between interrupts +0202 : 00 brk_count ds 1 + ;expected interrupt mask +0203 : 00 I_src ds 1 ;bit: 0=BRK, 1=IRQ, 2=NMI +0204 : data_bss + + code +0400 = org code_segment +0400 : d8 start cld +0401 : a900 lda #0 ;clear expected interrupts for 2nd run +0403 : 8d0302 sta I_src +0406 : a2ff ldx #$ff +0408 : 9a txs + + ;initialize I/O for report channel + if report = 1 + jsr report_init + endif + + ; load system vectors + if load_data_direct != 1 + ldx #5 + ld_vect lda vec_init,x + sta vec_bss,x + dex + bpl ld_vect + endif + + ; IRQ & NMI test - requires a feedback register + if I_drive > 1 + ERROR ;invalid interrupt drive! + endif + if NMI_bit < 0 + if I_drive = 0 ;totem pole (push/pull, 0 -> I_port to force interrupt) + I_set macro ibit ;ibit = interrupt bit + lda I_port ;turn on interrupt by bit + and #I_filter-(1<<\1) + plp ;set flags + pha ;save to verify + php + sta I_port ;interrupt next instruction plus outbound delay + endm + I_clr macro ibit ;ibit = interrupt bit + lda I_port ;turn off interrupt by bit + and #I_filter + ora #(1< I_DDR or I_port to force interrupt + if I_ddr != 0 ;with DDR + I_set macro ibit ;ibit = interrupt bit + lda I_ddr ;turn on interrupt by bit + and #I_filter + ora #(1<<\1) + plp ;set flags + pha ;save to verify + php + sta I_ddr ;interrupt next instruction plus outbound delay + endm + I_clr macro ibit ;ibit = interrupt bit + lda I_ddr ;turn off interrupt by bit + and #I_filter-(1< I_port to force interrupt) + I_set macro ibit ;ibit = interrupt bit + lda I_port ;turn on interrupt by bit + if ibit > 7 ;set both NMI & IRQ + and #I_filter-(1< I_DDR or I_port to force interrupt + if I_ddr != 0 ;with DDR + I_set macro ibit ;ibit = interrupt bit + lda I_ddr ;turn on interrupt by bit + and #I_filter + if ibit > 7 ;set both NMI & IRQ + ora #(1< 7 ;set both NMI & IRQ + ora #(1< lda I_port ;turn off interrupt by bit +040c : 297e > and #I_filter-(1< sta I_port + + I_clr NMI_bit +0411 : adfcbf > lda I_port ;turn off interrupt by bit +0414 : 297d > and #I_filter-(1< sta I_port + + endif + endif + endif + + ; IRQ integrity test + ; test for clear flags seen in IRQ vector +0419 : a902 lda #2 ;set expected interrupt source IRQ +041b : 8d0302 sta I_src + push_stat 0 +041e : a900 > lda #0 +0420 : 48 > pha ;use stack to load status + + I_set IRQ_bit +0421 : adfcbf > lda I_port ;turn on interrupt by bit +0424 : 297f > and #I_filter + > if IRQ_bit > 7 ;set both NMI & IRQ + > ora #(1< else +0426 : 0901 > ora #(1< endif +0428 : 28 > plp ;set flags +0429 : 48 > pha ;save to verify +042a : 08 > php +042b : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +042e : ea nop ;allow 6 cycles for interrupt to trip +042f : ea nop +0430 : ea nop +0431 : ad0302 lda I_src + trap_ne ;IRQ timeout +0434 : d0fe > bne * ;failed not equal (non zero) + +0436 : ba tsx +0437 : e0fd cpx #$ff-2 ;original accu & flags remain on stack + trap_ne ;returned SP +0439 : d0fe > bne * ;failed not equal (non zero) + +043b : a50c lda irq_f ;flags seen in IRQ vector + if D_clear = 1 + and #decmode + trap_ne ;D-flag not cleared + lda irq_f + eor lst_f ;turn off unchanged bits + and #m8-fai-decmode ;mask untested other flags + trap_ne ;other flags (N,V,Z,C) changed + else +043d : 4dfe01 eor lst_f ;turn off unchanged bits +0440 : 29cb and #m8-fai ;mask untested other flags + trap_ne ;other flags (N,V,Z,C,D) changed +0442 : d0fe > bne * ;failed not equal (non zero) + + endif +0444 : a2ff ldx #$ff ;reset stack pointer +0446 : 9a txs + ; test all other registers +0447 : a249 ldx #'I' +0449 : a052 ldy #'R' +044b : a902 lda #2 ;set expected interrupt source IRQ +044d : 8d0302 sta I_src + push_stat 0 +0450 : a900 > lda #0 +0452 : 48 > pha ;use stack to load status + + I_set IRQ_bit +0453 : adfcbf > lda I_port ;turn on interrupt by bit +0456 : 297f > and #I_filter + > if IRQ_bit > 7 ;set both NMI & IRQ + > ora #(1< else +0458 : 0901 > ora #(1< endif +045a : 28 > plp ;set flags +045b : 48 > pha ;save to verify +045c : 08 > php +045d : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +0460 : 88 dey ;Y count will fail, if instructions are skipped +0461 : 88 dey +0462 : 88 dey +0463 : 88 dey +0464 : 08 php ;check processor status later +0465 : e04a cpx #('I'+1) ;returned registers OK? + trap_ne ;returned X +0467 : d0fe > bne * ;failed not equal (non zero) + +0469 : c04b cpy #('R'-7) + trap_ne ;returned Y +046b : d0fe > bne * ;failed not equal (non zero) + +046d : c951 cmp #'Q' + trap_ne ;returned A +046f : d0fe > bne * ;failed not equal (non zero) + +0471 : ba tsx +0472 : e0fc cpx #$ff-3 + trap_ne ;returned SP +0474 : d0fe > bne * ;failed not equal (non zero) + +0476 : 68 pla ;flags +0477 : 4dfe01 eor lst_f +047a : 297d and #$ff-fnz ;ignore flags changed by dey + trap_ne ;returned flags +047c : d0fe > bne * ;failed not equal (non zero) + +047e : a50a lda irq_a ;accu seen in IRQ vector +0480 : cdff01 cmp lst_a + trap_ne ;IRQ A received +0483 : d0fe > bne * ;failed not equal (non zero) + +0485 : a2ff ldx #$ff ;reset stack pointer +0487 : 9a txs + ; repeat with reversed registers +0488 : a2b6 ldx #$ff-'I' +048a : a0ad ldy #$ff-'R' +048c : a902 lda #2 ;set expected interrupt source IRQ +048e : 8d0302 sta I_src + push_stat $ff-intdis +0491 : a9fb > lda #$ff-intdis +0493 : 48 > pha ;use stack to load status + + I_set IRQ_bit +0494 : adfcbf > lda I_port ;turn on interrupt by bit +0497 : 297f > and #I_filter + > if IRQ_bit > 7 ;set both NMI & IRQ + > ora #(1< else +0499 : 0901 > ora #(1< endif +049b : 28 > plp ;set flags +049c : 48 > pha ;save to verify +049d : 08 > php +049e : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +04a1 : 88 dey ;Y count will fail, if instructions are skipped +04a2 : 88 dey +04a3 : 88 dey +04a4 : 88 dey +04a5 : 08 php ;check processor status later +04a6 : e0b7 cpx #($ff-'I'+1) ;returned registers OK? + trap_ne ;returned X +04a8 : d0fe > bne * ;failed not equal (non zero) + +04aa : c0a6 cpy #($ff-'R'-7) + trap_ne ;returned Y +04ac : d0fe > bne * ;failed not equal (non zero) + +04ae : c951 cmp #'Q' + trap_ne ;returned A +04b0 : d0fe > bne * ;failed not equal (non zero) + +04b2 : ba tsx +04b3 : e0fc cpx #$ff-3 + trap_ne ;returned SP +04b5 : d0fe > bne * ;failed not equal (non zero) + +04b7 : 68 pla ;flags +04b8 : 4dfe01 eor lst_f +04bb : 297d and #$ff-fnz ;ignore flags changed by dey + trap_ne ;returned flags +04bd : d0fe > bne * ;failed not equal (non zero) + +04bf : a50a lda irq_a ;accu seen in IRQ vector +04c1 : cdff01 cmp lst_a + trap_ne ;IRQ A received +04c4 : d0fe > bne * ;failed not equal (non zero) + +04c6 : a2ff ldx #$ff ;reset stack pointer +04c8 : 9a txs + ; retest for set flags seen in IRQ vector +04c9 : a902 lda #2 ;set expected interrupt source IRQ +04cb : 8d0302 sta I_src + push_stat $ff-intdis +04ce : a9fb > lda #$ff-intdis +04d0 : 48 > pha ;use stack to load status + + I_set IRQ_bit +04d1 : adfcbf > lda I_port ;turn on interrupt by bit +04d4 : 297f > and #I_filter + > if IRQ_bit > 7 ;set both NMI & IRQ + > ora #(1< else +04d6 : 0901 > ora #(1< endif +04d8 : 28 > plp ;set flags +04d9 : 48 > pha ;save to verify +04da : 08 > php +04db : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +04de : ea nop ;allow 6 cycles for interrupt to trip +04df : ea nop +04e0 : ea nop +04e1 : ad0302 lda I_src + trap_ne ;IRQ timeout +04e4 : d0fe > bne * ;failed not equal (non zero) + +04e6 : ba tsx +04e7 : e0fd cpx #$ff-2 ;original accu & flags remain on stack + trap_ne ;returned SP +04e9 : d0fe > bne * ;failed not equal (non zero) + +04eb : a50c lda irq_f ;flags seen in IRQ vector + if D_clear = 1 + and #decmode + trap_ne ;D-flag not cleared + lda irq_f + eor lst_f ;turn off unchanged bits + and #m8-fai-decmode ;mask untested other flags + trap_ne ;other flags (N,V,Z,C) changed + else +04ed : 4dfe01 eor lst_f ;turn off unchanged bits +04f0 : 29cb and #m8-fai ;mask untested other flags + trap_ne ;other flags (N,V,Z,C,D) changed +04f2 : d0fe > bne * ;failed not equal (non zero) + + endif +04f4 : a2ff ldx #$ff ;reset stack pointer +04f6 : 9a txs + + ; BRK integrity test + ; test for clear flags seen in IRQ vector +04f7 : a901 lda #1 ;set expected interrupt source BRK +04f9 : 8d0302 sta I_src + set_stat 0 +04fc : a900 > lda #0 +04fe : 48 > pha ;use stack to load status +04ff : 28 > plp + +0500 : 48 pha ;save entry registers +0501 : 08 php +0502 : 00 brk +0503 : ea nop ;should not be executed +0504 : ea nop ;allow 6 cycles for interrupt to trip +0505 : ea nop +0506 : ea nop +0507 : ad0302 lda I_src + trap_ne ;IRQ timeout +050a : d0fe > bne * ;failed not equal (non zero) + +050c : ba tsx +050d : e0fd cpx #$ff-2 ;original accu & flags remain on stack + trap_ne ;returned SP +050f : d0fe > bne * ;failed not equal (non zero) + +0511 : a50c lda irq_f ;flags seen in IRQ vector + if D_clear = 1 + and #decmode + trap_ne ;D-flag not cleared + lda irq_f + eor lst_f ;turn off unchanged bits + and #m8-fai-decmode ;mask untested other flags + trap_ne ;other flags (N,V,Z,C) changed + else +0513 : 4dfe01 eor lst_f ;turn off unchanged bits +0516 : 29cb and #m8-fai ;mask untested other flags + trap_ne ;other flags (N,V,Z,C,D) changed +0518 : d0fe > bne * ;failed not equal (non zero) + + endif +051a : a2ff ldx #$ff ;reset stack pointer +051c : 9a txs + ; test all other registers +051d : a242 ldx #'B' +051f : a052 ldy #'R' +0521 : a901 lda #1 ;set expected interrupt source BRK +0523 : 8d0302 sta I_src + set_stat 0 +0526 : a900 > lda #0 +0528 : 48 > pha ;use stack to load status +0529 : 28 > plp + +052a : 48 pha ;save entry +052b : 08 php +052c : 00 brk +052d : 88 dey ;should not be executed +052e : 88 dey ;Y count will fail, if return address is wrong +052f : 88 dey +0530 : 88 dey +0531 : 88 dey +0532 : 08 php ;check processor status later +0533 : e043 cpx #('B'+1) ;returned registers OK? + trap_ne ;returned X +0535 : d0fe > bne * ;failed not equal (non zero) + +0537 : c04b cpy #('R'-7) + trap_ne ;returned Y +0539 : d0fe > bne * ;failed not equal (non zero) + +053b : c94b cmp #'K' + trap_ne ;returned A +053d : d0fe > bne * ;failed not equal (non zero) + +053f : ba tsx +0540 : e0fc cpx #$ff-3 + trap_ne ;returned SP +0542 : d0fe > bne * ;failed not equal (non zero) + +0544 : 68 pla ;flags +0545 : 4dfe01 eor lst_f +0548 : 297d and #$ff-fnz ;ignore flags changed by dey + trap_ne ;returned flags +054a : d0fe > bne * ;failed not equal (non zero) + +054c : a50a lda irq_a ;accu seen in IRQ vector +054e : cdff01 cmp lst_a + trap_ne ;IRQ A received +0551 : d0fe > bne * ;failed not equal (non zero) + +0553 : a2ff ldx #$ff ;reset stack pointer +0555 : 9a txs + ; repeat with reversed registers +0556 : a2bd ldx #$ff-'B' +0558 : a0ad ldy #$ff-'R' +055a : a901 lda #1 ;set expected interrupt source BRK +055c : 8d0302 sta I_src + set_stat $ff +055f : a9ff > lda #$ff +0561 : 48 > pha ;use stack to load status +0562 : 28 > plp + +0563 : 48 pha ;save entry registers +0564 : 08 php +0565 : 00 brk +0566 : 88 dey ;should not be executed +0567 : 88 dey ;Y count will fail, if return address is wrong +0568 : 88 dey +0569 : 88 dey +056a : 88 dey +056b : 08 php ;check processor status later +056c : e0be cpx #($ff-'B'+1) ;returned registers OK? + trap_ne ;returned X +056e : d0fe > bne * ;failed not equal (non zero) + +0570 : c0a6 cpy #($ff-'R'-7) + trap_ne ;returned Y +0572 : d0fe > bne * ;failed not equal (non zero) + +0574 : c94b cmp #'K' + trap_ne ;returned A +0576 : d0fe > bne * ;failed not equal (non zero) + +0578 : ba tsx +0579 : e0fc cpx #$ff-3 + trap_ne ;returned SP +057b : d0fe > bne * ;failed not equal (non zero) + +057d : 68 pla ;flags +057e : 4dfe01 eor lst_f +0581 : 297d and #$ff-fnz ;ignore flags changed by dey + trap_ne ;returned flags +0583 : d0fe > bne * ;failed not equal (non zero) + +0585 : a50a lda irq_a ;accu seen in IRQ vector +0587 : cdff01 cmp lst_a + trap_ne ;IRQ A received +058a : d0fe > bne * ;failed not equal (non zero) + +058c : a2ff ldx #$ff ;reset stack pointer +058e : 9a txs + ; retest for set flags seen in IRQ vector +058f : a901 lda #1 ;set expected interrupt source BRK +0591 : 8d0302 sta I_src + set_stat $ff +0594 : a9ff > lda #$ff +0596 : 48 > pha ;use stack to load status +0597 : 28 > plp + +0598 : 48 pha ;save entry registers +0599 : 08 php +059a : 00 brk +059b : ea nop ;should not be executed +059c : ea nop ;allow 6 cycles for interrupt to trip +059d : ea nop +059e : ea nop +059f : ad0302 lda I_src + trap_ne ;IRQ timeout +05a2 : d0fe > bne * ;failed not equal (non zero) + +05a4 : ba tsx +05a5 : e0fd cpx #$ff-2 ;original accu & flags remain on stack + trap_ne ;returned SP +05a7 : d0fe > bne * ;failed not equal (non zero) + +05a9 : a50c lda irq_f ;flags seen in IRQ vector + if D_clear = 1 + and #decmode + trap_ne ;D-flag not cleared + lda irq_f + eor lst_f ;turn off unchanged bits + and #m8-fai-decmode ;mask untested other flags + trap_ne ;other flags (N,V,Z,C) changed + else +05ab : 4dfe01 eor lst_f ;turn off unchanged bits +05ae : 29cb and #m8-fai ;mask untested other flags + trap_ne ;other flags (N,V,Z,C,D) changed +05b0 : d0fe > bne * ;failed not equal (non zero) + + endif +05b2 : a2ff ldx #$ff ;reset stack pointer +05b4 : 9a txs + + if NMI_bit < 0 + ; test IRQ with interrupts disabled + ldx #0 + lda #0 + sta I_src + push_stat intdis + I_set IRQ_bit ;IRQ pending + inx + inx + inx + ldx #0 + lda #2 ;now re-enable IRQ + sta I_src + cli + inx + inx + inx + lda I_src ;test IRQ done? + trap_ne + ldx #$ff ;purge stack + txs + + ldx #0 ;now overlap IRQ & BRK + lda #3 + sta I_src + lda #$ff ;measure timing + sta nmi_count + sta irq_count + sta brk_count + push_stat 0 + I_set IRQ_bit ;trigger IRQ + else + ; NMI integrity test + ; test for clear flags seen in NMI vector +05b5 : a904 lda #4 ;set expected interrupt source NMI +05b7 : 8d0302 sta I_src + push_stat 0 +05ba : a900 > lda #0 +05bc : 48 > pha ;use stack to load status + + I_set NMI_bit +05bd : adfcbf > lda I_port ;turn on interrupt by bit +05c0 : 297f > and #I_filter + > if NMI_bit > 7 ;set both NMI & IRQ + > ora #(1< else +05c2 : 0902 > ora #(1< endif +05c4 : 28 > plp ;set flags +05c5 : 48 > pha ;save to verify +05c6 : 08 > php +05c7 : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +05ca : ea nop ;allow 6 cycles for interrupt to trip +05cb : ea nop +05cc : ea nop +05cd : ad0302 lda I_src + trap_ne ;NMI timeout +05d0 : d0fe > bne * ;failed not equal (non zero) + +05d2 : ba tsx +05d3 : e0fd cpx #$ff-2 ;original accu & flags remain on stack + trap_ne ;returned SP +05d5 : d0fe > bne * ;failed not equal (non zero) + +05d7 : a50f lda nmi_f ;flags seen in NMI vector + if D_clear = 1 + and #decmode + trap_ne ;D-flag not cleared + lda nmi_f + eor lst_f ;turn off unchanged bits + and #m8-fai-decmode ;mask untested other flags + trap_ne ;other flags (N,V,Z,C) changed + else +05d9 : 4dfe01 eor lst_f ;turn off unchanged bits +05dc : 29cb and #m8-fai ;mask untested other flags + trap_ne ;other flags (N,V,Z,C,D) changed +05de : d0fe > bne * ;failed not equal (non zero) + + endif +05e0 : a2ff ldx #$ff ;reset stack pointer +05e2 : 9a txs + ; test all other registers +05e3 : a24e ldx #'N' +05e5 : a04d ldy #'M' +05e7 : a904 lda #4 ;set expected interrupt source NMI +05e9 : 8d0302 sta I_src + push_stat 0 +05ec : a900 > lda #0 +05ee : 48 > pha ;use stack to load status + + I_set NMI_bit +05ef : adfcbf > lda I_port ;turn on interrupt by bit +05f2 : 297f > and #I_filter + > if NMI_bit > 7 ;set both NMI & IRQ + > ora #(1< else +05f4 : 0902 > ora #(1< endif +05f6 : 28 > plp ;set flags +05f7 : 48 > pha ;save to verify +05f8 : 08 > php +05f9 : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +05fc : 88 dey ;Y count will fail, if instructions are skipped +05fd : 88 dey +05fe : 88 dey +05ff : 88 dey +0600 : 08 php ;check processor status later +0601 : e04f cpx #('N'+1) ;returned registers OK? + trap_ne ;returned X +0603 : d0fe > bne * ;failed not equal (non zero) + +0605 : c046 cpy #('M'-7) + trap_ne ;returned Y +0607 : d0fe > bne * ;failed not equal (non zero) + +0609 : c949 cmp #'I' + trap_ne ;returned A +060b : d0fe > bne * ;failed not equal (non zero) + +060d : ba tsx +060e : e0fc cpx #$ff-3 + trap_ne ;returned SP +0610 : d0fe > bne * ;failed not equal (non zero) + +0612 : 68 pla ;flags +0613 : 4dfe01 eor lst_f +0616 : 297d and #$ff-fnz ;ignore flags changed by dey + trap_ne ;returned flags +0618 : d0fe > bne * ;failed not equal (non zero) + +061a : a50d lda nmi_a ;accu seen in NMI vector +061c : cdff01 cmp lst_a + trap_ne ;NMI A received +061f : d0fe > bne * ;failed not equal (non zero) + +0621 : a2ff ldx #$ff ;reset stack pointer +0623 : 9a txs + ; repeat with reversed registers +0624 : a2b1 ldx #$ff-'N' +0626 : a0b2 ldy #$ff-'M' +0628 : a904 lda #4 ;set expected interrupt source NMI +062a : 8d0302 sta I_src + push_stat $ff-intdis +062d : a9fb > lda #$ff-intdis +062f : 48 > pha ;use stack to load status + + I_set NMI_bit +0630 : adfcbf > lda I_port ;turn on interrupt by bit +0633 : 297f > and #I_filter + > if NMI_bit > 7 ;set both NMI & IRQ + > ora #(1< else +0635 : 0902 > ora #(1< endif +0637 : 28 > plp ;set flags +0638 : 48 > pha ;save to verify +0639 : 08 > php +063a : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +063d : 88 dey ;Y count will fail, if instructions are skipped +063e : 88 dey +063f : 88 dey +0640 : 88 dey +0641 : 08 php ;check processor status later +0642 : e0b2 cpx #($ff-'N'+1) ;returned registers OK? + trap_ne ;returned X +0644 : d0fe > bne * ;failed not equal (non zero) + +0646 : c0ab cpy #($ff-'M'-7) + trap_ne ;returned Y +0648 : d0fe > bne * ;failed not equal (non zero) + +064a : c949 cmp #'I' + trap_ne ;returned A +064c : d0fe > bne * ;failed not equal (non zero) + +064e : ba tsx +064f : e0fc cpx #$ff-3 + trap_ne ;returned SP +0651 : d0fe > bne * ;failed not equal (non zero) + +0653 : 68 pla ;flags +0654 : 4dfe01 eor lst_f +0657 : 297d and #$ff-fnz ;ignore flags changed by dey + trap_ne ;returned flags +0659 : d0fe > bne * ;failed not equal (non zero) + +065b : a50d lda nmi_a ;accu seen in NMI vector +065d : cdff01 cmp lst_a + trap_ne ;NMI A received +0660 : d0fe > bne * ;failed not equal (non zero) + +0662 : a2ff ldx #$ff ;reset stack pointer +0664 : 9a txs + ; retest for set flags seen in NMI vector +0665 : a904 lda #4 ;set expected interrupt source NMI +0667 : 8d0302 sta I_src + push_stat $ff-intdis +066a : a9fb > lda #$ff-intdis +066c : 48 > pha ;use stack to load status + + I_set NMI_bit +066d : adfcbf > lda I_port ;turn on interrupt by bit +0670 : 297f > and #I_filter + > if NMI_bit > 7 ;set both NMI & IRQ + > ora #(1< else +0672 : 0902 > ora #(1< endif +0674 : 28 > plp ;set flags +0675 : 48 > pha ;save to verify +0676 : 08 > php +0677 : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +067a : ea nop ;allow 6 cycles for interrupt to trip +067b : ea nop +067c : ea nop +067d : ad0302 lda I_src + trap_ne ;NMI timeout +0680 : d0fe > bne * ;failed not equal (non zero) + +0682 : ba tsx +0683 : e0fd cpx #$ff-2 ;original accu & flags remain on stack + trap_ne ;returned SP +0685 : d0fe > bne * ;failed not equal (non zero) + +0687 : a50f lda nmi_f ;flags seen in NMI vector + if D_clear = 1 + and #decmode + trap_ne ;D-flag not cleared + lda nmi_f + eor lst_f ;turn off unchanged bits + and #m8-fai-decmode ;mask untested other flags + trap_ne ;other flags (N,V,Z,C) changed + else +0689 : 4dfe01 eor lst_f ;turn off unchanged bits +068c : 29cb and #m8-fai ;mask untested other flags + trap_ne ;other flags (N,V,Z,C,D) changed +068e : d0fe > bne * ;failed not equal (non zero) + + endif +0690 : a2ff ldx #$ff ;reset stack pointer +0692 : 9a txs + + ; test IRQ & NMI with interrupts disabled +0693 : a200 ldx #0 +0695 : a904 lda #4 ;set expected interrupt NMI only +0697 : 8d0302 sta I_src + push_stat intdis +069a : a904 > lda #intdis +069c : 48 > pha ;use stack to load status + + I_set 8 ;both interrupts pending +069d : adfcbf > lda I_port ;turn on interrupt by bit +06a0 : 297f > and #I_filter + > if 8 > 7 ;set both NMI & IRQ +06a2 : 0903 > ora #(1< else + > ora #(1<<8 ) + > endif +06a4 : 28 > plp ;set flags +06a5 : 48 > pha ;save to verify +06a6 : 08 > php +06a7 : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + +06aa : e8 inx +06ab : e8 inx +06ac : e8 inx +06ad : ad0302 lda I_src ;test NMI done? + trap_ne +06b0 : d0fe > bne * ;failed not equal (non zero) + +06b2 : a200 ldx #0 +06b4 : a902 lda #2 ;now re-enable IRQ +06b6 : 8d0302 sta I_src +06b9 : 58 cli +06ba : e8 inx +06bb : e8 inx +06bc : e8 inx +06bd : ad0302 lda I_src ;test IRQ done? + trap_ne +06c0 : d0fe > bne * ;failed not equal (non zero) + +06c2 : a2ff ldx #$ff ;purge stack +06c4 : 9a txs + + ;test overlapping NMI, IRQ & BRK +06c5 : a200 ldx #0 +06c7 : a907 lda #7 +06c9 : 8d0302 sta I_src +06cc : a9ff lda #$ff ;measure timing +06ce : 8d0002 sta nmi_count +06d1 : 8d0102 sta irq_count +06d4 : 8d0202 sta brk_count + push_stat 0 +06d7 : a900 > lda #0 +06d9 : 48 > pha ;use stack to load status + + I_set 8 ;trigger NMI + IRQ +06da : adfcbf > lda I_port ;turn on interrupt by bit +06dd : 297f > and #I_filter + > if 8 > 7 ;set both NMI & IRQ +06df : 0903 > ora #(1< else + > ora #(1<<8 ) + > endif +06e1 : 28 > plp ;set flags +06e2 : 48 > pha ;save to verify +06e3 : 08 > php +06e4 : 8dfcbf > sta I_port ;interrupt next instruction plus outbound delay + + endif +06e7 : 00 brk +06e8 : e8 inx +06e9 : e8 inx +06ea : e8 inx +06eb : e8 inx +06ec : e8 inx +06ed : e8 inx +06ee : e8 inx +06ef : e8 inx +06f0 : ad0302 lda I_src ;test all done? + ;may fail due to a bug on a real NMOS 6502 - NMI could mask BRK + trap_ne ;lost an interrupt +06f3 : d0fe > bne * ;failed not equal (non zero) + + + ; S U C C E S S ************************************************ + ; ------------- + success ;if you get here everything went well +06f5 : 4cf506 > jmp * ;test passed, no errors + + ; ------------- + ; S U C C E S S ************************************************ + ; check data_segment +0 to +2 for sequence of concurrent interrupts + ; e.g. 0x200 = NMI, 0x201 = IRQ, 0x202 = BRK, lower values = earlier +06f8 : 4c0004 jmp start ;run again + + ; manual tests for the WAI opcode of the 65c02 + + wai macro + db $cb ;WAI opcode + endm + + ; requires single step operation, report = 0 + ; set PC to the 1st instruction of the test + ; step to the WAI opcode, then manually tie the IRQ input low + ; continue to step until you see the PC advance, then remove IRQ + ; allow the routine to complete. + + ; WAI with interrupts disabled +06fb : a2ff ldx #$ff +06fd : 9a txs +06fe : a003 ldy #3 +0700 : a900 lda #0 ;IRQ not expected +0702 : 8d0302 sta I_src + set_stat intdis +0705 : a904 > lda #intdis +0707 : 48 > pha ;use stack to load status +0708 : 28 > plp + + wai +0709 : cb > db $cb ;WAI opcode + +070a : 88 dey +070b : 88 dey +070c : 88 dey + trap_ne ;skipped opcodes! +070d : d0fe > bne * ;failed not equal (non zero) + + + success +070f : 4c0f07 > jmp * ;test passed, no errors + + + ; WAI with interrupts enabled +0712 : a2ff ldx #$ff +0714 : 9a txs +0715 : a007 ldy #7 +0717 : a902 lda #2 ;IRQ expected +0719 : 8d0302 sta I_src + set_stat 0 +071c : a900 > lda #0 +071e : 48 > pha ;use stack to load status +071f : 28 > plp + + wai +0720 : cb > db $cb ;WAI opcode + +0721 : 88 dey +0722 : 88 dey +0723 : 88 dey +0724 : ad0302 lda I_src + trap_ne ;IRQ vector not called +0727 : d0fe > bne * ;failed not equal (non zero) + +0729 : 88 dey + trap_ne ;skipped opcodes! +072a : d0fe > bne * ;failed not equal (non zero) + + + success +072c : 4c2c07 > jmp * ;test passed, no errors + + + ; manual test for the STP opcode of the 65c02 + + stp macro + db $db ;STP opcode + endm + + ; set PC to the 1st instruction of the test, then run +072f : ea nop +0730 : ea nop + stp ;expected end of operation +0731 : db > db $db ;STP opcode + +0732 : ea nop +0733 : ea nop + trap ;overran STP +0734 : 4c3407 > jmp * ;failed anyway + + + ;end of manual tests + + ;--------------------------------------------------------------------------- + ;trap in case of unexpected IRQ, NMI, BRK, RESET - IRQ, NMI, BRK test target +0737 : 88 dey +0738 : 88 dey +0739 : nmi_trap + if NMI_bit < 0 + dey + dey + dey + trap ;unexpected NMI + else +0739 : 08 php ;either SP or Y count will fail, if we do not hit +073a : 88 dey +073b : 88 dey +073c : 88 dey +073d : 850d sta nmi_a ;save regsters during NMI +073f : 860e stx nmi_x +0741 : 68 pla +0742 : 48 pha +0743 : 850f sta nmi_f +0745 : ad0302 lda I_src ;NMI expected? +0748 : 2904 and #4 + trap_eq ;unexpexted NMI - check stack for conditions +074a : f0fe > beq * ;failed equal (zero) + +074c : 68 pla ;test I-flag was set +074d : 48 pha +074e : 2904 and #intdis + trap_eq ;I-flag not set +0750 : f0fe > beq * ;failed equal (zero) + +0752 : 68 pla ;return with other flags reversed +0753 : 49c3 eor #m8-fai-decmode +0755 : 48 pha +0756 : ba tsx +0757 : bd0201 lda $102,x ;test break on stack +075a : 2910 and #break + trap_ne ;unexpected B-flag! - this may fail on a real 6502 +075c : d0fe > bne * ;failed not equal (non zero) + + ;due to a hardware bug on concurrent BRK & NMI +075e : ad0302 lda I_src ;mark expected NMI has occured +0761 : 29fb and #$ff-4 +0763 : 8d0302 sta I_src + I_clr NMI_bit +0766 : adfcbf > lda I_port ;turn off interrupt by bit +0769 : 297d > and #I_filter-(1< sta I_port + +076e : a60e ldx nmi_x +0770 : e8 inx +0771 : 8e0002 stx nmi_count +0774 : a949 lda #'I' ;mark (NM)I +0776 : 28 plp ;should be reversed by rti +0777 : 40 rti + endif + +0778 : res_trap + trap ;unexpected RESET +0778 : 4c7807 > jmp * ;failed anyway + + +077b : 88 dey +077c : 88 dey +077d : irq_trap ;BRK & IRQ test +077d : 08 php ;either SP or Y count will fail, if we do not hit +077e : 88 dey +077f : 88 dey +0780 : 88 dey +0781 : 850a sta irq_a ;save registers during IRQ/BRK +0783 : 860b stx irq_x +0785 : 68 pla +0786 : 48 pha +0787 : 850c sta irq_f +0789 : ad0302 lda I_src ;IRQ expected? +078c : 2903 and #3 + trap_eq ;unexpexted IRQ/BRK - check stack for conditions +078e : f0fe > beq * ;failed equal (zero) + +0790 : 68 pla ;test I-flag was set +0791 : 48 pha +0792 : 2904 and #intdis + trap_eq ;I-flag not set +0794 : f0fe > beq * ;failed equal (zero) + +0796 : 68 pla ;return with other flags reversed +0797 : 49c3 eor #m8-fai-decmode +0799 : 48 pha +079a : ba tsx +079b : bd0201 lda $102,x ;test break on stack +079e : 2910 and #break +07a0 : d021 bne brk_trap + +07a2 : ad0302 lda I_src ;IRQ expected? +07a5 : 2902 and #2 + trap_eq ;unexpexted IRQ - check stack for conditions +07a7 : f0fe > beq * ;failed equal (zero) + +07a9 : ad0302 lda I_src ;mark expected IRQ has occured +07ac : 29fd and #$ff-2 +07ae : 8d0302 sta I_src + I_clr IRQ_bit +07b1 : adfcbf > lda I_port ;turn off interrupt by bit +07b4 : 297e > and #I_filter-(1< sta I_port + +07b9 : a60b ldx irq_x +07bb : e8 inx +07bc : 8e0102 stx irq_count +07bf : a951 lda #'Q' ;mark (IR)Q +07c1 : 28 plp ;should be reversed by rti +07c2 : 40 rti + +07c3 : brk_trap +07c3 : ad0302 lda I_src ;break expected? +07c6 : 2901 and #1 + trap_eq ;unexpected BRK - check stack for conditions +07c8 : f0fe > beq * ;failed equal (zero) + +07ca : ad0302 lda I_src ;mark expected BRK has occured +07cd : 29fe and #$ff-1 +07cf : 8d0302 sta I_src +07d2 : a60b ldx irq_x +07d4 : e8 inx +07d5 : 8e0202 stx brk_count +07d8 : a50a lda irq_a +07da : a94b lda #'K' ;mark (BR)K +07dc : 28 plp ;should be reversed by rti +07dd : 40 rti + + if report = 1 + rep_int = 1 + include "report.i65" + endif + + + ;system vectors + if (load_data_direct = 1) +fffa = org $fffa +fffa : 3907 dw nmi_trap +fffc : 7807 dw res_trap +fffe : 7d07 dw irq_trap + else + vec_init + vec_bss equ $fffa + dw nmi_trap + dw res_trap + dw irq_trap + endif + +fffa = end start + + +No errors in pass 2. +Wrote binary from address $000a through $ffff. +Total size 65526 bytes. +Program start address is at $0400 (1024). + \ No newline at end of file diff --git a/src/test/kotlin/6502_functional_tests/bin_files/65C02_decimal_test.bin b/src/test/kotlin/6502_functional_tests/bin_files/65C02_decimal_test.bin new file mode 100644 index 0000000000000000000000000000000000000000..4393baa81c20c52ac7e415b74290098dcb94b2c8 GIT binary patch literal 242 zcmYj}F$%&k7)Jl3O>Ar1IEqu&-k=w7^A62Y&;xh_e{k#(q>w>edIUif>eNkfa7vX?5APr<&g1a!6Ff}U@4r!E;pIANMhvX<;~GiedF=p zFw!^FC-Mk$DC{N@V-`F`LEGdG9c?*srR^iHxMou?B1(UP19X+#(I0CI9rV;2@uyF} literal 0 HcmV?d00001 diff --git a/src/test/kotlin/6502_functional_tests/bin_files/65C02_decimal_test.lst b/src/test/kotlin/6502_functional_tests/bin_files/65C02_decimal_test.lst new file mode 100644 index 0000000..2a2c08d --- /dev/null +++ b/src/test/kotlin/6502_functional_tests/bin_files/65C02_decimal_test.lst @@ -0,0 +1,9 @@ +AS65 Assembler for R6502 [1.42]. Page 1 +--------------------------- 65C02_decimal_test.a65 --------------------------- + +356 lines read, no errors in pass 1. +No errors in pass 2. +Wrote binary from address $0200 through $02f1. +Total size 242 bytes. +Program start address is at $0200 (512). + \ No newline at end of file diff --git a/src/test/kotlin/6502_functional_tests/readme.txt b/src/test/kotlin/6502_functional_tests/readme.txt index a3e30cf..12aacac 100644 --- a/src/test/kotlin/6502_functional_tests/readme.txt +++ b/src/test/kotlin/6502_functional_tests/readme.txt @@ -10,14 +10,18 @@ The 6502_interrupt_test.a65 is a simple test to check the interrupt system of both processors. A feedback register is required to inject IRQ and NMI requests. +The 6502_decimal_test.a65 is Bruce Clark's code to accurately test decimal mode +of the various 6502 cores (6502, 65c02 & 65816 in 8-bit mode) with added +configuration options (invalid bcd or not, which flags to ignore). + Detailed information about how to configure, assemble and run the tests is included in each source file. -The tests have primarily been written to test my own ATMega16 6502 emulator -project. You can find it here: http://2m5.de/6502_Emu/index.htm +The assembler used is no longer available on the author's website. as65_142.zip +is now included in this repository. -A discussion about the tests can be found here: -http://forum.6502.org/viewtopic.php?f=2&t=2241 +And no, I will not switch to another assembler. However, GitHub user amb5l has +a CA65 compatible version in his repository. Good luck debugging your emulator, simulator, fpga core, discrete logic implementation or whatever you have! diff --git a/src/test/kotlin/Test6502CpuBasics.kt b/src/test/kotlin/Test6502CpuBasics.kt index d6481bc..d705cef 100644 --- a/src/test/kotlin/Test6502CpuBasics.kt +++ b/src/test/kotlin/Test6502CpuBasics.kt @@ -111,13 +111,14 @@ class Test6502CpuBasics { @Test fun testBCD6502() { + // this test only works on 6502, not on the 65c02 val cpu = Cpu6502() val bus = Bus() bus.add(cpu) val ram = Ram(0, 0xffff) ram[Cpu6502.RESET_vector] = 0x00 ram[Cpu6502.RESET_vector +1] = 0x10 - val bytes = javaClass.getResource("bcdtest6502.bin").readBytes() // only works on 6502, not on the 65c02 + val bytes = javaClass.getResource("bcdtest6502.bin").readBytes() ram.load(bytes, 0x1000) bus.add(ram) bus.reset() diff --git a/src/test/kotlin/Test6502Functional.kt b/src/test/kotlin/Test6502Functional.kt deleted file mode 100644 index 1f08bfd..0000000 --- a/src/test/kotlin/Test6502Functional.kt +++ /dev/null @@ -1,77 +0,0 @@ -import razorvine.ksim65.Bus -import razorvine.ksim65.components.Ram -import razorvine.ksim65.Cpu6502 -import razorvine.ksim65.Cpu65C02 -import java.lang.Exception -import kotlin.test.* - - -class Test6502Functional { - - private class SuccessfulTestResult: Exception() - - @Test - fun testFunctional6502() { - val cpu = Cpu6502() - val bus = Bus() - val ram = Ram(0, 0xffff) - ram.load("src/test/kotlin/6502_functional_tests/bin_files/6502_functional_test.bin", 0) - bus.add(cpu) - bus.add(ram) - cpu.reset() - cpu.regPC = 0x0400 - cpu.addBreakpoint(0x3469) { _, _ -> - // reaching this address means successful test result - if(cpu.currentOpcode==0x4c) - throw SuccessfulTestResult() - Cpu6502.BreakpointResultAction(null, null) - } - - try { - while (cpu.totalCycles < 100000000) { - cpu.clock() - } - } catch (sx: SuccessfulTestResult) { - println("test successful ${cpu.totalCycles}") - return - } - - println(cpu.snapshot()) - val d = cpu.disassemble(ram, cpu.regPC-20, cpu.regPC+20) - println(d.first.joinToString ("\n")) - fail("test failed") - } - - @Test - fun testFunctional65C02() { - val cpu = Cpu65C02() - val bus = Bus() - val ram = Ram(0, 0xffff) - ram.load("src/test/kotlin/6502_functional_tests/bin_files/65C02_extended_opcodes_test.bin", 0) - bus.add(cpu) - bus.add(ram) - cpu.reset() - cpu.regPC = 0x0400 - cpu.addBreakpoint(0x24f1) { _, _ -> - // reaching this address means successful test result - if(cpu.currentOpcode==0x4c) - throw SuccessfulTestResult() - Cpu6502.BreakpointResultAction(null, null) - } - - try { - while (cpu.totalCycles < 100000000) { - cpu.clock() - } - } catch (sx: SuccessfulTestResult) { - println("test successful") - return - } - - println(cpu.snapshot()) - val d = cpu.disassemble(ram, cpu.regPC-20, cpu.regPC+20) - println(d.first.joinToString ("\n")) - fail("test failed") - } - -} diff --git a/src/test/kotlin/Test6502Klaus2m5Functional.kt b/src/test/kotlin/Test6502Klaus2m5Functional.kt new file mode 100644 index 0000000..5409339 --- /dev/null +++ b/src/test/kotlin/Test6502Klaus2m5Functional.kt @@ -0,0 +1,192 @@ +import razorvine.ksim65.Bus +import razorvine.ksim65.components.Ram +import razorvine.ksim65.Cpu6502 +import razorvine.ksim65.Cpu65C02 +import razorvine.ksim65.hexW +import java.lang.Exception +import kotlin.math.max +import kotlin.math.min +import kotlin.test.* + + +/** + * This runs the 'functional 6502/65c02' tests from Klaus2m5 + * (Klaus Dormann, sourced from here https://github.com/Klaus2m5/6502_65C02_functional_tests) + */ +class Test6502Klaus2m5Functional { + + private class SuccessfulTestResult: Exception() + + @Test + fun testFunctional6502() { + val cpu = Cpu6502() + val bus = Bus() + val ram = Ram(0, 0xffff) + ram.load("src/test/kotlin/6502_functional_tests/bin_files/6502_functional_test.bin", 0) + bus.add(cpu) + bus.add(ram) + cpu.reset() + cpu.regPC = 0x0400 + cpu.addBreakpoint(0x3469) { _, _ -> + // reaching this address means successful test result + if(cpu.currentOpcode==0x4c) + throw SuccessfulTestResult() + Cpu6502.BreakpointResultAction(null, null) + } + + try { + while (cpu.totalCycles < 100000000) { + cpu.clock() + } + } catch (sx: SuccessfulTestResult) { + println("test successful ${cpu.totalCycles}") + return + } catch(nx: NotImplementedError) { + println("encountered a not yet implemented feature: ${nx.message}") + } + + println(cpu.snapshot()) + val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20)) + println(d.first.joinToString ("\n")) + fail("test failed") + } + + @Test + fun testFunctional65C02() { + val cpu = Cpu65C02() + val bus = Bus() + val ram = Ram(0, 0xffff) + ram.load("src/test/kotlin/6502_functional_tests/bin_files/65C02_extended_opcodes_test.bin", 0) + bus.add(cpu) + bus.add(ram) + cpu.reset() + cpu.regPC = 0x0400 + cpu.addBreakpoint(0x24f1) { _, _ -> + // reaching this address means successful test result + if(cpu.currentOpcode==0x4c) + throw SuccessfulTestResult() + Cpu6502.BreakpointResultAction(null, null) + } + + try { + while (cpu.totalCycles < 100000000) { + cpu.clock() + } + } catch (sx: SuccessfulTestResult) { + println("test successful") + return + } catch(nx: NotImplementedError) { + println("encountered a not yet implemented feature: ${nx.message}") + } + + println(cpu.snapshot()) + val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20)) + println(d.first.joinToString ("\n")) + fail("test failed") + } + + @Test + //@Ignore("todo: fix the interrupt tests") // TODO the test code is not correct + fun testInterrupts6502() { + val cpu = Cpu6502() + val bus = Bus() + val ram = Ram(0, 0xffff) + ram.load("src/test/kotlin/6502_functional_tests/bin_files/6502_interrupt_test.bin", 0) + bus.add(cpu) + bus.add(ram) + cpu.reset() + cpu.regPC = 0x0400 +// cpu.addBreakpoint(0x3469) { _, _ -> +// // reaching this address means successful test result +// if(cpu.currentOpcode==0x4c) +// throw SuccessfulTestResult() +// Cpu6502.BreakpointResultAction(null, null) +// } + + try { + while (cpu.totalCycles < 100000000) { + cpu.clock() + } + } catch (sx: SuccessfulTestResult) { + println("test successful ${cpu.totalCycles}") + return + } catch(nx: NotImplementedError) { + println("encountered a not yet implemented feature: ${nx.message}") + } + + println(cpu.snapshot()) + val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20)) + println(d.first.joinToString ("\n")) + fail("test failed") + } + + @Test + fun testDecimal6502() { + val cpu = Cpu6502() + val bus = Bus() + val ram = Ram(0, 0xffff) + ram.load("src/test/kotlin/6502_functional_tests/bin_files/6502_decimal_test.bin", 0x0200) + bus.add(cpu) + bus.add(ram) + cpu.reset() + cpu.regPC = 0x0200 + cpu.breakpointForBRK = { cpu, address -> + if(address in 513..2047) { + val error=bus.read(0x000b) // the 'ERROR' variable is stored here + if(error==0.toShort()) + throw SuccessfulTestResult() + } + Cpu6502.BreakpointResultAction(null, null) + } + try { + while (cpu.totalCycles < 100000000) { + cpu.clock() + } + } catch (sx: SuccessfulTestResult) { + println("test successful ${cpu.totalCycles}") + return + } catch(nx: NotImplementedError) { + println("encountered a not yet implemented feature: ${nx.message}") + } + + println(cpu.snapshot()) + val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20)) + println(d.first.joinToString ("\n")) + fail("test failed") + } + + @Test + fun testDecimal65C02() { + val cpu = Cpu65C02() + val bus = Bus() + val ram = Ram(0, 0xffff) + ram.load("src/test/kotlin/6502_functional_tests/bin_files/65C02_decimal_test.bin", 0x0200) + bus.add(cpu) + bus.add(ram) + cpu.reset() + cpu.regPC = 0x0200 + cpu.breakpointForBRK = { cpu, address -> + if(address in 513..2047) { + val error=bus.read(0x000b) // the 'ERROR' variable is stored here + if(error==0.toShort()) + throw SuccessfulTestResult() + } + Cpu6502.BreakpointResultAction(null, null) + } + try { + while (cpu.totalCycles < 100000000) { + cpu.clock() + } + } catch (sx: SuccessfulTestResult) { + println("test successful ${cpu.totalCycles}") + return + } catch(nx: NotImplementedError) { + println("encountered a not yet implemented feature: ${nx.message}") + } + + println(cpu.snapshot()) + val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20)) + println(d.first.joinToString ("\n")) + fail("test failed") + } +}