mirror of
https://github.com/irmen/ksim65.git
synced 2024-11-15 09:05:52 +00:00
introduced separate Disassembler class
This commit is contained in:
Irmen de Jong
parent
d5f533c300
commit
c619ddabf1
@ -198,24 +198,6 @@ class C64Machine(title: String) : IVirtualMachine {
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return listing.toTypedArray()
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}
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private fun determineRomPath(): Path {
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val candidates = listOf("./roms", "~/roms/c64", "~/roms", "~/.vice/C64")
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candidates.forEach {
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val path = Paths.get(expandUser(it))
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if (path.toFile().isDirectory) return path
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}
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throw FileNotFoundException("no roms directory found, tried: $candidates")
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}
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private fun expandUser(path: String): String {
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return when {
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path.startsWith("~/") -> System.getProperty("user.home")+path.substring(1)
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path.startsWith("~"+File.separatorChar) -> System.getProperty("user.home")+path.substring(1)
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path.startsWith("~") -> throw UnsupportedOperationException("home dir expansion not implemented for other users")
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else -> path
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}
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}
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override fun loadFileInRam(file: File, loadAddress: Address?) {
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if (file.extension == "prg" && (loadAddress == null || loadAddress == 0x0801)) ram.loadPrg(file.inputStream(), null)
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else ram.load(file.readBytes(), loadAddress!!)
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@ -268,6 +250,26 @@ class C64Machine(title: String) : IVirtualMachine {
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}
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}
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fun determineRomPath(): Path {
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val candidates = listOf("./roms", "~/roms/c64", "~/roms", "~/.vice/C64")
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candidates.forEach {
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val path = Paths.get(expandUser(it))
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if (path.toFile().isDirectory) return path
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}
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throw FileNotFoundException("no roms directory found, tried: $candidates")
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}
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fun expandUser(path: String): String {
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return when {
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path.startsWith("~/") -> System.getProperty("user.home")+path.substring(1)
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path.startsWith("~"+File.separatorChar) -> System.getProperty("user.home")+path.substring(1)
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path.startsWith("~") -> throw UnsupportedOperationException("home dir expansion not implemented for other users")
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else -> path
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}
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}
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fun main() {
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val machine = C64Machine("virtual Commodore-64 - using KSim65 v${Version.version}")
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machine.start()
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@ -44,6 +44,7 @@ class DebugWindow(private val vm: IVirtualMachine) : JFrame("Debugger - ksim65 v
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it.disabledTextColor = Color.DARK_GRAY
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it.font = Font(Font.MONOSPACED, Font.PLAIN, 12)
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}
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private val disassembler = Disassembler(vm.cpu)
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init {
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contentPane.layout = GridBagLayout()
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@ -217,7 +218,8 @@ class DebugWindow(private val vm: IVirtualMachine) : JFrame("Debugger - ksim65 v
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regSPtf.text = hexB(state.SP)
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val memory = listOf(bus[state.PC], bus[state.PC+1], bus[state.PC+2]).toTypedArray()
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val disassem = cpu.disassembleOneInstruction(memory, 0, state.PC).first.substringAfter(' ').trim()
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val disassem = disassembler.disassembleOneInstruction(memory, 0, state.PC).first.substringAfter(' ').trim()
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disassemTf.text = disassem
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if (zeropageTf.isVisible || stackpageTf.isVisible) {
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@ -29,7 +29,14 @@ open class Cpu6502 : BusComponent() {
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class StatusRegister(var C: Boolean = false, var Z: Boolean = false, var I: Boolean = false, var D: Boolean = false,
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var B: Boolean = false, var V: Boolean = false, var N: Boolean = false) {
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fun asInt(): Int {
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return (0b00100000 or (if (N) 0b10000000 else 0) or (if (V) 0b01000000 else 0) or (if (B) 0b00010000 else 0) or (if (D) 0b00001000 else 0) or (if (I) 0b00000100 else 0) or (if (Z) 0b00000010 else 0) or (if (C) 0b00000001 else 0))
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return (0b00100000
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or (if (N) 0b10000000 else 0)
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or (if (V) 0b01000000 else 0)
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or (if (B) 0b00010000 else 0)
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or (if (D) 0b00001000 else 0)
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or (if (I) 0b00000100 else 0)
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or (if (Z) 0b00000010 else 0)
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or (if (C) 0b00000001 else 0))
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}
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fun fromInt(byte: Int) {
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@ -128,106 +135,6 @@ open class Cpu6502 : BusComponent() {
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fun removeBreakpoint(address: Address) = breakpoints.remove(address)
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fun disassemble(memory: Array<UByte>, range: IntRange, baseAddress: Address): Pair<List<String>, Address> {
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var offset = range.first
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val result = mutableListOf<String>()
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while (offset <= range.last) {
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val dis = disassembleOneInstruction(memory, offset, baseAddress)
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result.add(dis.first)
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offset += dis.second
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}
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return Pair(result, offset+baseAddress)
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}
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fun disassembleOneInstruction(memory: Array<UByte>, offset: Int, baseAddress: Address): Pair<String, Int> {
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val spacing1 = " "
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val spacing2 = " "
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val spacing3 = " "
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val byte = memory[offset]
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val line = "\$${hexW(offset+baseAddress)} ${hexB(byte)} "
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val opcode = instructions[byte.toInt()]
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return when (opcode.mode) {
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AddrMode.Acc -> {
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Pair(line+"$spacing1 ${opcode.mnemonic} a", 1)
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}
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AddrMode.Imp -> {
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Pair(line+"$spacing1 ${opcode.mnemonic}", 1)
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}
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AddrMode.Imm -> {
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val value = memory[offset+1]
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Pair(line+"${hexB(value)} $spacing2 ${opcode.mnemonic} #\$${hexB(value)}", 2)
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}
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AddrMode.Zp -> {
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)}", 2)
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}
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AddrMode.Zpr -> {
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// addressing mode used by the 65C02, put here for convenience rather than the subclass
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val zpAddr = memory[offset+1]
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val rel = memory[offset+2]
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val target = (if (rel <= 0x7f) offset+3+rel+baseAddress else offset+3-(256-rel)+baseAddress) and 0xffff
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Pair(line+"${hexB(zpAddr)} ${hexB(rel)} $spacing3 ${opcode.mnemonic} \$${hexB(zpAddr)}, \$${hexW(target, true)}", 3)
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}
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AddrMode.Izp -> {
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// addressing mode used by the 65C02, put here for convenience rather than the subclass
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$(${hexB(zpAddr)})", 2)
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}
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AddrMode.IaX -> {
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// addressing mode used by the 65C02, put here for convenience rather than the subclass
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val lo = memory[offset+1]
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val hi = memory[offset+2]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$(${hexW(absAddr)},x)", 3)
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}
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AddrMode.ZpX -> {
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)},x", 2)
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}
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AddrMode.ZpY -> {
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)},y", 2)
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}
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AddrMode.Rel -> {
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val rel = memory[offset+1]
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val target = (if (rel <= 0x7f) offset+2+rel+baseAddress else offset+2-(256-rel)+baseAddress) and 0xffff
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Pair(line+"${hexB(rel)} $spacing2 ${opcode.mnemonic} \$${hexW(target, true)}", 2)
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}
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AddrMode.Abs -> {
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val lo = memory[offset+1]
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val hi = memory[offset+2]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)}", 3)
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}
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AddrMode.AbsX -> {
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val lo = memory[offset+1]
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val hi = memory[offset+2]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)},x", 3)
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}
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AddrMode.AbsY -> {
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val lo = memory[offset+1]
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val hi = memory[offset+2]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)},y", 3)
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}
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AddrMode.Ind -> {
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val lo = memory[offset+1]
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val hi = memory[offset+2]
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val indirectAddr = lo.toInt() or (hi.toInt() shl 8)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} (\$${hexW(indirectAddr)})", 3)
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}
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AddrMode.IzX -> {
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} (\$${hexB(zpAddr)},x)", 2)
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}
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AddrMode.IzY -> {
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} (\$${hexB(zpAddr)}),y", 2)
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}
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}
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}
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/**
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* Reset the cpu
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*/
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110
src/main/kotlin/razorvine/ksim65/Disassembler.kt
Normal file
110
src/main/kotlin/razorvine/ksim65/Disassembler.kt
Normal file
@ -0,0 +1,110 @@
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package razorvine.ksim65
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import razorvine.ksim65.components.Address
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import razorvine.ksim65.components.UByte
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class Disassembler(cpu: Cpu6502) {
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private val instructions = cpu.instructions
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fun disassemble(memory: Array<UByte>, range: IntRange, baseAddress: Address): Pair<List<String>, Address> {
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var offset = range.first
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val result = mutableListOf<String>()
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while (offset <= range.last) {
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val dis = disassembleOneInstruction(memory, offset, baseAddress)
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result.add(dis.first)
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offset += dis.second
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}
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return Pair(result, offset+baseAddress)
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}
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fun disassembleOneInstruction(memory: Array<UByte>, offset: Int, baseAddress: Address): Pair<String, Int> {
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val spacing1 = " "
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val spacing2 = " "
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val spacing3 = " "
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val byte = memory[offset]
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val line = "\$${hexW(offset+baseAddress)} ${hexB(byte)} "
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val opcode = instructions[byte.toInt()]
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return when (opcode.mode) {
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Cpu6502.AddrMode.Acc -> {
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Pair(line+"$spacing1 ${opcode.mnemonic} a", 1)
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}
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Cpu6502.AddrMode.Imp -> {
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Pair(line+"$spacing1 ${opcode.mnemonic}", 1)
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}
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Cpu6502.AddrMode.Imm -> {
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val value = memory[offset+1]
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Pair(line+"${hexB(value)} $spacing2 ${opcode.mnemonic} #\$${hexB(value)}", 2)
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}
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Cpu6502.AddrMode.Zp -> {
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)}", 2)
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}
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Cpu6502.AddrMode.Zpr -> {
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// addressing mode used by the 65C02, put here for convenience rather than the subclass
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val zpAddr = memory[offset+1]
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val rel = memory[offset+2]
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val target = (if (rel <= 0x7f) offset+3+rel+baseAddress else offset+3-(256-rel)+baseAddress) and 0xffff
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Pair(line+"${hexB(zpAddr)} ${hexB(rel)} $spacing3 ${opcode.mnemonic} \$${hexB(zpAddr)}, \$${hexW(target, true)}", 3)
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}
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Cpu6502.AddrMode.Izp -> {
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// addressing mode used by the 65C02, put here for convenience rather than the subclass
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$(${hexB(zpAddr)})", 2)
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}
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Cpu6502.AddrMode.IaX -> {
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// addressing mode used by the 65C02, put here for convenience rather than the subclass
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val lo = memory[offset+1]
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val hi = memory[offset+2]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$(${hexW(absAddr)},x)", 3)
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}
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Cpu6502.AddrMode.ZpX -> {
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)},x", 2)
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}
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Cpu6502.AddrMode.ZpY -> {
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)},y", 2)
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}
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Cpu6502.AddrMode.Rel -> {
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val rel = memory[offset+1]
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val target = (if (rel <= 0x7f) offset+2+rel+baseAddress else offset+2-(256-rel)+baseAddress) and 0xffff
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Pair(line+"${hexB(rel)} $spacing2 ${opcode.mnemonic} \$${hexW(target, true)}", 2)
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}
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Cpu6502.AddrMode.Abs -> {
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val lo = memory[offset+1]
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val hi = memory[offset+2]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)}", 3)
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}
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Cpu6502.AddrMode.AbsX -> {
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val lo = memory[offset+1]
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val hi = memory[offset+2]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)},x", 3)
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}
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Cpu6502.AddrMode.AbsY -> {
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val lo = memory[offset+1]
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val hi = memory[offset+2]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)},y", 3)
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}
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Cpu6502.AddrMode.Ind -> {
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val lo = memory[offset+1]
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val hi = memory[offset+2]
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val indirectAddr = lo.toInt() or (hi.toInt() shl 8)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} (\$${hexW(indirectAddr)})", 3)
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}
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Cpu6502.AddrMode.IzX -> {
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} (\$${hexB(zpAddr)},x)", 2)
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}
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Cpu6502.AddrMode.IzY -> {
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} (\$${hexB(zpAddr)}),y", 2)
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}
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}
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}
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}
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@ -12,6 +12,8 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
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instr.toMap()
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}
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private val disassembler = Disassembler(cpu)
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fun command(command: String): IVirtualMachine.MonitorCmdResult {
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if (command.isEmpty()) return IVirtualMachine.MonitorCmdResult("", "", false)
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@ -97,7 +99,7 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
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val start = parseNumber(addresses[0])
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val end = if (addresses.size > 1) parseNumber(addresses[1]) else start
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val memory = (start .. max(0xffff, end+3)).map {bus[it]}.toTypedArray()
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val disassem = cpu.disassemble(memory, 0 .. end-start, start)
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val disassem = disassembler.disassemble(memory, 0 .. end-start, start)
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IVirtualMachine.MonitorCmdResult(disassem.first.joinToString("\n") { "d$it" }, "d$${hexW(disassem.second)}", false)
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}
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else -> {
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@ -238,7 +240,7 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
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}
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val memory = listOf(bus[address], bus[address+1], bus[address+2]).toTypedArray()
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val disassem = cpu.disassembleOneInstruction(memory, 0, address)
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val disassem = disassembler.disassembleOneInstruction(memory, 0, address)
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return IVirtualMachine.MonitorCmdResult(disassem.first, "a$${hexW(disassem.second + address)} ", false)
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}
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@ -19,13 +19,16 @@ abstract class FunctionalTestsBase {
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cpu.addBreakpoint(0xffd2) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) }
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cpu.addBreakpoint(0xffe4) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) }
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cpu.addBreakpoint(0xe16f) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) }
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cpu.addBreakpoint(0x8000) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) }
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cpu.addBreakpoint(0xa474) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) }
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bus.add(cpu)
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bus.add(ram)
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bus.reset()
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}
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protected fun runTest(testprogram: String) {
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ram.fill(0)
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// setup the irq/brk routine TODO is this the right code?
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// setup the irq/brk routine and other stubbing
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// http://www.softwolves.com/arkiv/cbm-hackers/7/7114.html
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for(b in listOf(0x48, 0x8A, 0x48, 0x98, 0x48, 0xBA, 0xBD, 0x04,
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0x01, 0x29, 0x10, 0xF0, 0x03, 0x6C, 0x16, 0x03,
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0x6C, 0x14, 0x03).withIndex()) {
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@ -41,9 +44,8 @@ abstract class FunctionalTestsBase {
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ram[Cpu6502.RESET_vector + 1] = 0x08
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ram[0x01fe] = 0xff
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ram[0x01ff] = 0x7f
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ram[0x8000] = 2
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ram[0xa474] = 2
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bus.reset()
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cpu.regP.fromInt(4)
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cpu.regPC = 0x0801
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try {
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while (cpu.totalCycles < 40000000L) {
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bus.clock()
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@ -234,6 +234,7 @@ class Test6502CpuBasics {
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val cpu = NesCpu()
|
||||
val ram = Ram(0, 0xffff)
|
||||
val disassembler = Disassembler(cpu)
|
||||
|
||||
val bytes = javaClass.getResource("nestest.nes").readBytes().drop(0x10).take(0x4000).toByteArray()
|
||||
ram.load(bytes, 0x8000)
|
||||
@ -247,16 +248,16 @@ class Test6502CpuBasics {
|
||||
|
||||
val neslog = javaClass.getResource("nestest.log").readText().lineSequence()
|
||||
for(logline in neslog) {
|
||||
val s = cpu.snapshot()
|
||||
val s = cpu.snapshot() // TODO use cpu.tracing instead
|
||||
val nesAddressHex = logline.substring(0, 4).toInt(16)
|
||||
assertEquals(nesAddressHex, s.PC)
|
||||
|
||||
println("NES: $logline")
|
||||
val disassem = cpu.disassembleOneInstruction(ram.data, s.PC, 0).first.substring(1)
|
||||
val disassem = disassembler.disassembleOneInstruction(ram.data, s.PC, 0).first.substring(1)
|
||||
val spaces = " ".substring(disassem.length-1)
|
||||
println("EMU: $disassem $spaces A:${hexB(s.A)} X:${hexB(s.X)} Y:${hexB(s.Y)} P:${hexB(s.P.asInt())} SP:${hexB(s.SP)} PPU: 0, 0 CYC:${s.cycles}")
|
||||
|
||||
// TODO snapshotting as per https://forums.nesdev.com/viewtopic.php?t=19117 (i.e. BEFORE instruction gets executed):
|
||||
// TODO use cpu.tracing, as per https://forums.nesdev.com/viewtopic.php?t=19117 (i.e. BEFORE instruction gets executed):
|
||||
// "before fetching the first operation code byte, make an internal record of the program counter and other registers;
|
||||
// after reading the final operand byte, log all the values you stored back in step (1) plus the full instruction and its disassembly."
|
||||
|
||||
|
||||
@ -1,13 +1,99 @@
|
||||
import org.junit.jupiter.api.Disabled
|
||||
import org.junit.jupiter.api.parallel.Execution
|
||||
import org.junit.jupiter.api.parallel.ExecutionMode
|
||||
import razorvine.c64emu.*
|
||||
import razorvine.ksim65.Bus
|
||||
import razorvine.ksim65.Cpu6502
|
||||
import razorvine.ksim65.components.Ram
|
||||
import razorvine.ksim65.components.Rom
|
||||
import kotlin.test.*
|
||||
|
||||
// TODO: run these tests by using the C64 machine emulation components
|
||||
|
||||
@Execution(ExecutionMode.CONCURRENT)
|
||||
@Disabled("test code is not using C64 specific components yet")
|
||||
class Test6502TestSuiteC64Specific: FunctionalTestsBase() {
|
||||
// @Disabled("test code is not using C64 specific components yet")
|
||||
class Test6502TestSuiteC64Specific {
|
||||
|
||||
val cpu: Cpu6502 = Cpu6502()
|
||||
val ioPort = CpuIoPort(cpu)
|
||||
val ram = Ram(0, 0xffff)
|
||||
val bus: Bus
|
||||
val kernalStubs = C64KernalStubs(ram)
|
||||
|
||||
init {
|
||||
val romsPath = determineRomPath()
|
||||
val chargenRom = Rom(0xd000, 0xdfff).also {
|
||||
val chargenData = romsPath.resolve("chargen").toFile().readBytes()
|
||||
it.load(chargenData)
|
||||
}
|
||||
val basicRom = Rom(0xa000, 0xbfff).also {
|
||||
val basicData = romsPath.resolve("basic").toFile().readBytes()
|
||||
it.load(basicData)
|
||||
}
|
||||
val kernalRom = Rom(0xe000, 0xffff).also {
|
||||
val kernalData = romsPath.resolve("kernal").toFile().readBytes()
|
||||
it.load(kernalData)
|
||||
}
|
||||
|
||||
cpu.tracing = null
|
||||
cpu.addBreakpoint(0xffd2) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) }
|
||||
cpu.addBreakpoint(0xffe4) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) }
|
||||
cpu.addBreakpoint(0xe16f) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) }
|
||||
cpu.addBreakpoint(0x8000) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) }
|
||||
cpu.addBreakpoint(0xa474) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) }
|
||||
|
||||
bus = Bus6510(ioPort, chargenRom, basicRom, kernalRom)
|
||||
bus += VicII(0xd000, 0xd3ff, cpu)
|
||||
bus += Cia(1, 0xdc00, 0xdcff, cpu)
|
||||
bus += Cia(2, 0xdd00, 0xddff, cpu)
|
||||
bus += ioPort
|
||||
bus += cpu
|
||||
bus += ram // note: the ROMs are mapped depending on the cpu's io port
|
||||
bus.reset()
|
||||
}
|
||||
|
||||
private fun runTest(testprogram: String) {
|
||||
// setup the irq/brk routine and other stubbing
|
||||
// http://www.softwolves.com/arkiv/cbm-hackers/7/7114.html
|
||||
bus[0] = 47
|
||||
bus[1] = 55
|
||||
for(b in listOf(0x48, 0x8A, 0x48, 0x98, 0x48, 0xBA, 0xBD, 0x04,
|
||||
0x01, 0x29, 0x10, 0xF0, 0x03, 0x6C, 0x16, 0x03,
|
||||
0x6C, 0x14, 0x03).withIndex()) {
|
||||
ram[0xff48+b.index] = b.value.toShort()
|
||||
}
|
||||
ram.loadPrg("src/test/kotlin/6502testsuite/$testprogram", null)
|
||||
ram[0x02] = 0
|
||||
ram[0xa002] = 0
|
||||
ram[0xa003] = 0x80
|
||||
ram[Cpu6502.IRQ_vector] = 0x48
|
||||
ram[Cpu6502.IRQ_vector + 1] = 0xff
|
||||
ram[Cpu6502.RESET_vector] = 0x01
|
||||
ram[Cpu6502.RESET_vector + 1] = 0x08
|
||||
ram[0x01fe] = 0xff
|
||||
ram[0x01ff] = 0x7f
|
||||
cpu.regPC = 0x0801
|
||||
cpu.regP.fromInt(4)
|
||||
try {
|
||||
while (cpu.totalCycles < 40000000L) {
|
||||
bus.clock()
|
||||
}
|
||||
fail("test hangs: " + cpu.snapshot())
|
||||
} catch (e: Cpu6502.InstructionError) {
|
||||
println(">>> INSTRUCTION ERROR: ${e.message}")
|
||||
} catch (le: KernalLoadNextPart) {
|
||||
return // test ok
|
||||
} catch (ie: KernalInputRequired) {
|
||||
fail("test failed")
|
||||
}
|
||||
fail("test failed")
|
||||
}
|
||||
|
||||
@Test
|
||||
fun testRegularShouldSucceed() {
|
||||
// as long as this one doesn't succeed, there's something wrong with the test setup
|
||||
runTest("adca")
|
||||
}
|
||||
|
||||
@Test
|
||||
fun testCia1pb6() {
|
||||
@ -71,6 +157,7 @@ class Test6502TestSuiteC64Specific: FunctionalTestsBase() {
|
||||
|
||||
@Test
|
||||
fun testCnto2() {
|
||||
// todo fix: When the timer input is switched from o2 to CNT or from CNT back to o2, there must be a two clock delay until the switch is recognized.
|
||||
runTest("cnto2")
|
||||
}
|
||||
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
import razorvine.ksim65.Cpu6502
|
||||
import razorvine.ksim65.Cpu65C02
|
||||
import razorvine.ksim65.Disassembler
|
||||
import razorvine.ksim65.components.Ram
|
||||
import kotlin.test.*
|
||||
|
||||
@ -9,10 +10,11 @@ class TestDisassembler {
|
||||
@Test
|
||||
fun testDisassembleAll6502Opcodes() {
|
||||
val cpu = Cpu6502()
|
||||
val disassembler = Disassembler(cpu)
|
||||
val memory = Ram(0, 0xffff)
|
||||
val binfile = javaClass.classLoader.getResourceAsStream("disassem_instr_test.prg")?.readBytes()!!
|
||||
memory.load(binfile, 0x1000-2)
|
||||
val result = cpu.disassemble(memory.data, 0x1000..0x1221, 0)
|
||||
val result = disassembler.disassemble(memory.data, 0x1000..0x1221, 0)
|
||||
assertEquals(256, result.first.size)
|
||||
assertEquals(0x1222, result.second)
|
||||
assertEquals("\$1000 69 01 adc #\$01", result.first[0])
|
||||
@ -29,10 +31,11 @@ class TestDisassembler {
|
||||
@Test
|
||||
fun testDisassembleRockwell65C02() {
|
||||
val cpu = Cpu65C02()
|
||||
val disassembler = Disassembler(cpu)
|
||||
val memory = Ram(0, 0x0fff)
|
||||
val source = javaClass.classLoader.getResource("disassem_r65c02.bin").readBytes()
|
||||
memory.load(source, 0x0200)
|
||||
val disassem = cpu.disassemble(memory.data, 0x0200..0x0250, 0)
|
||||
val disassem = disassembler.disassemble(memory.data, 0x0200..0x0250, 0)
|
||||
assertEquals(0x251, disassem.second)
|
||||
val result = disassem.first.joinToString("\n")
|
||||
assertEquals("""${'$'}0200 07 12 rmb0 ${'$'}12
|
||||
@ -75,10 +78,11 @@ ${'$'}0250 00 brk""", result)
|
||||
@Test
|
||||
fun testDisassembleWDC65C02() {
|
||||
val cpu = Cpu65C02()
|
||||
val disassembler = Disassembler(cpu)
|
||||
val memory = Ram(0, 0x0fff)
|
||||
val source = javaClass.classLoader.getResource("disassem_wdc65c02.bin").readBytes()
|
||||
memory.load(source, 0x200)
|
||||
val disassem = cpu.disassemble(memory.data, 0x0200..0x0215, 0)
|
||||
val disassem = disassembler.disassemble(memory.data, 0x0200..0x0215, 0)
|
||||
assertEquals(0x216, disassem.second)
|
||||
val result = disassem.first.joinToString("\n")
|
||||
assertEquals("""${'$'}0200 cb wai
|
||||
|
||||
Loading…
Reference in New Issue
Block a user