mirror of
https://github.com/irmen/ksim65.git
synced 2024-09-27 07:54:29 +00:00
fixed monitor disassemble and assemble commands
This commit is contained in:
parent
6db5e792d6
commit
cc1fb9716b
@ -215,9 +215,9 @@ class DebugWindow(private val vm: IVirtualMachine) : JFrame("Debugger - ksim65 v
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regPtf.text = "NV-BDIZC\n"+state.P.asInt().toString(2).padStart(8, '0')
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regPtf.text = "NV-BDIZC\n"+state.P.asInt().toString(2).padStart(8, '0')
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regPCtf.text = hexW(state.PC)
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regPCtf.text = hexW(state.PC)
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regSPtf.text = hexB(state.SP)
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regSPtf.text = hexB(state.SP)
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val memory = bus.memoryComponentFor(state.PC)
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val disassem = cpu.disassembleOneInstruction(memory.data, state.PC, memory.startAddress).first.substringAfter(' ').trim()
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val memory = listOf(bus[state.PC], bus[state.PC+1], bus[state.PC+2]).toTypedArray()
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println("${hexW(state.PC)} $disassem") // XXX
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val disassem = cpu.disassembleOneInstruction(memory, 0, state.PC).first.substringAfter(' ').trim()
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disassemTf.text = disassem
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disassemTf.text = disassem
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if (zeropageTf.isVisible || stackpageTf.isVisible) {
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if (zeropageTf.isVisible || stackpageTf.isVisible) {
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@ -64,7 +64,4 @@ open class Bus {
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it[address-it.startAddress] = data
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it[address-it.startAddress] = data
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}
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}
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}
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}
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fun memoryComponentFor(address: Address) =
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memComponents.first { it is MemoryComponent && address >= it.startAddress && address <= it.endAddress } as MemoryComponent
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}
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}
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@ -2,7 +2,6 @@ package razorvine.ksim65
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import razorvine.ksim65.components.Address
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import razorvine.ksim65.components.Address
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import razorvine.ksim65.components.BusComponent
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import razorvine.ksim65.components.BusComponent
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import razorvine.ksim65.components.MemoryComponent
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import razorvine.ksim65.components.UByte
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import razorvine.ksim65.components.UByte
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@ -129,26 +128,23 @@ open class Cpu6502 : BusComponent() {
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fun removeBreakpoint(address: Address) = breakpoints.remove(address)
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fun removeBreakpoint(address: Address) = breakpoints.remove(address)
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fun disassemble(memory: MemoryComponent, from: Address, to: Address) = disassemble(memory.data, memory.startAddress, from, to)
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fun disassemble(memory: Array<UByte>, range: IntRange, baseAddress: Address): Pair<List<String>, Address> {
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var offset = range.first
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fun disassemble(memory: Array<UByte>, baseAddress: Address, from: Address, to: Address): Pair<List<String>, Address> {
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var location = from
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val result = mutableListOf<String>()
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val result = mutableListOf<String>()
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while (location <= to) {
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while (offset <= range.last) {
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val dis = disassembleOneInstruction(memory, location, baseAddress)
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val dis = disassembleOneInstruction(memory, offset, baseAddress)
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result.add(dis.first)
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result.add(dis.first)
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location += dis.second
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offset += dis.second
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}
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}
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return Pair(result, location)
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return Pair(result, offset+baseAddress)
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}
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}
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fun disassembleOneInstruction(memory: Array<UByte>, address: Address, baseAddress: Address): Pair<String, Int> {
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fun disassembleOneInstruction(memory: Array<UByte>, offset: Int, baseAddress: Address): Pair<String, Int> {
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val spacing1 = " "
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val spacing1 = " "
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val spacing2 = " "
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val spacing2 = " "
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val spacing3 = " "
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val spacing3 = " "
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val location = address-baseAddress
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val byte = memory[offset]
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val byte = memory[location]
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val line = "\$${hexW(offset+baseAddress)} ${hexB(byte)} "
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val line = "\$${hexW(location+baseAddress)} ${hexB(byte)} "
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val opcode = instructions[byte.toInt()]
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val opcode = instructions[byte.toInt()]
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return when (opcode.mode) {
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return when (opcode.mode) {
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AddrMode.Acc -> {
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AddrMode.Acc -> {
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@ -158,75 +154,75 @@ open class Cpu6502 : BusComponent() {
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Pair(line+"$spacing1 ${opcode.mnemonic}", 1)
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Pair(line+"$spacing1 ${opcode.mnemonic}", 1)
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}
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}
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AddrMode.Imm -> {
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AddrMode.Imm -> {
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val value = memory[location+1]
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val value = memory[offset+1]
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Pair(line+"${hexB(value)} $spacing2 ${opcode.mnemonic} #\$${hexB(value)}", 2)
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Pair(line+"${hexB(value)} $spacing2 ${opcode.mnemonic} #\$${hexB(value)}", 2)
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}
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}
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AddrMode.Zp -> {
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AddrMode.Zp -> {
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val zpAddr = memory[location+1]
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)}", 2)
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)}", 2)
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}
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}
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AddrMode.Zpr -> {
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AddrMode.Zpr -> {
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// addressing mode used by the 65C02, put here for convenience rather than the subclass
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// addressing mode used by the 65C02, put here for convenience rather than the subclass
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val zpAddr = memory[location+1]
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val zpAddr = memory[offset+1]
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val rel = memory[location+2]
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val rel = memory[offset+2]
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val target = (if (rel <= 0x7f) location+3+rel+baseAddress else location+3-(256-rel)+baseAddress) and 0xffff
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val target = (if (rel <= 0x7f) offset+3+rel+baseAddress else offset+3-(256-rel)+baseAddress) and 0xffff
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Pair(line+"${hexB(zpAddr)} ${hexB(rel)} $spacing3 ${opcode.mnemonic} \$${hexB(zpAddr)}, \$${hexW(target, true)}", 3)
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Pair(line+"${hexB(zpAddr)} ${hexB(rel)} $spacing3 ${opcode.mnemonic} \$${hexB(zpAddr)}, \$${hexW(target, true)}", 3)
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}
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}
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AddrMode.Izp -> {
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AddrMode.Izp -> {
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// addressing mode used by the 65C02, put here for convenience rather than the subclass
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// addressing mode used by the 65C02, put here for convenience rather than the subclass
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val zpAddr = memory[location+1]
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$(${hexB(zpAddr)})", 2)
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$(${hexB(zpAddr)})", 2)
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}
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}
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AddrMode.IaX -> {
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AddrMode.IaX -> {
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// addressing mode used by the 65C02, put here for convenience rather than the subclass
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// addressing mode used by the 65C02, put here for convenience rather than the subclass
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val lo = memory[location+1]
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val lo = memory[offset+1]
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val hi = memory[location+2]
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val hi = memory[offset+2]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$(${hexW(absAddr)},x)", 3)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$(${hexW(absAddr)},x)", 3)
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}
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}
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AddrMode.ZpX -> {
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AddrMode.ZpX -> {
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val zpAddr = memory[location+1]
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)},x", 2)
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)},x", 2)
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}
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}
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AddrMode.ZpY -> {
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AddrMode.ZpY -> {
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val zpAddr = memory[location+1]
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)},y", 2)
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)},y", 2)
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}
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}
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AddrMode.Rel -> {
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AddrMode.Rel -> {
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val rel = memory[location+1]
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val rel = memory[offset+1]
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val target = (if (rel <= 0x7f) location+2+rel+baseAddress else location+2-(256-rel)+baseAddress) and 0xffff
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val target = (if (rel <= 0x7f) offset+2+rel+baseAddress else offset+2-(256-rel)+baseAddress) and 0xffff
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Pair(line+"${hexB(rel)} $spacing2 ${opcode.mnemonic} \$${hexW(target, true)}", 2)
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Pair(line+"${hexB(rel)} $spacing2 ${opcode.mnemonic} \$${hexW(target, true)}", 2)
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}
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}
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AddrMode.Abs -> {
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AddrMode.Abs -> {
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val lo = memory[location+1]
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val lo = memory[offset+1]
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val hi = memory[location+2]
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val hi = memory[offset+2]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)}", 3)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)}", 3)
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}
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}
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AddrMode.AbsX -> {
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AddrMode.AbsX -> {
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val lo = memory[location+1]
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val lo = memory[offset+1]
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val hi = memory[location+2]
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val hi = memory[offset+2]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)},x", 3)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)},x", 3)
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}
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}
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AddrMode.AbsY -> {
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AddrMode.AbsY -> {
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val lo = memory[location+1]
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val lo = memory[offset+1]
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val hi = memory[location+2]
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val hi = memory[offset+2]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)},y", 3)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)},y", 3)
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}
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}
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AddrMode.Ind -> {
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AddrMode.Ind -> {
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val lo = memory[location+1]
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val lo = memory[offset+1]
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val hi = memory[location+2]
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val hi = memory[offset+2]
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val indirectAddr = lo.toInt() or (hi.toInt() shl 8)
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val indirectAddr = lo.toInt() or (hi.toInt() shl 8)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} (\$${hexW(indirectAddr)})", 3)
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Pair(line+"${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} (\$${hexW(indirectAddr)})", 3)
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}
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}
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AddrMode.IzX -> {
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AddrMode.IzX -> {
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val zpAddr = memory[location+1]
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} (\$${hexB(zpAddr)},x)", 2)
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} (\$${hexB(zpAddr)},x)", 2)
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}
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}
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AddrMode.IzY -> {
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AddrMode.IzY -> {
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val zpAddr = memory[location+1]
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val zpAddr = memory[offset+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} (\$${hexB(zpAddr)}),y", 2)
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} (\$${hexB(zpAddr)}),y", 2)
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}
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}
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}
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}
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@ -1,5 +1,7 @@
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package razorvine.ksim65
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package razorvine.ksim65
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import kotlin.math.max
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class Monitor(val bus: Bus, val cpu: Cpu6502) {
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class Monitor(val bus: Bus, val cpu: Cpu6502) {
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private val instructions by lazy {
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private val instructions by lazy {
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@ -94,7 +96,8 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
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val addresses = command.substring(1).trim().split(' ')
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val addresses = command.substring(1).trim().split(' ')
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val start = parseNumber(addresses[0])
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val start = parseNumber(addresses[0])
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val end = if (addresses.size > 1) parseNumber(addresses[1]) else start
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val end = if (addresses.size > 1) parseNumber(addresses[1]) else start
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val disassem = cpu.disassemble(bus.memoryComponentFor(start), start, end)
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val memory = (start .. max(0xffff, end+3)).map {bus[it]}.toTypedArray()
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val disassem = cpu.disassemble(memory, 0 .. end-start, start)
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IVirtualMachine.MonitorCmdResult(disassem.first.joinToString("\n") { "d$it" }, "d$${hexW(disassem.second)}", false)
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IVirtualMachine.MonitorCmdResult(disassem.first.joinToString("\n") { "d$it" }, "d$${hexW(disassem.second)}", false)
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}
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}
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else -> {
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else -> {
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@ -213,18 +216,16 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
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} else {
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} else {
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// absolute or absZp
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// absolute or absZp
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val absAddress = try {
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val absAddress = try {
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parseRelativeToPC(arg, address)
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if(arg.startsWith('*')) parseRelativeToPC(arg, address) else parseNumber(arg)
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} catch (x: NumberFormatException) {
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} catch (x: NumberFormatException) {
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return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
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return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
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}
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}
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if (absAddress <= 255) {
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val zpInstruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Zp)]
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val absInstr = instructions[Pair(mnemonic, Cpu6502.AddrMode.Zp)] ?: return IVirtualMachine.MonitorCmdResult(
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if (absAddress <= 255 && zpInstruction!=null) {
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"?invalid instruction", command, false)
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bus.write(address, zpInstruction.toShort())
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bus.write(address, absInstr.toShort())
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bus.write(address+1, absAddress.toShort())
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bus.write(address+1, absAddress.toShort())
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} else {
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} else {
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val absInstr =
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val absInstr = instructions[Pair(mnemonic, Cpu6502.AddrMode.Abs)] ?: return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
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instructions[Pair(mnemonic, Cpu6502.AddrMode.Abs)] ?: return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
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bus.write(address, absInstr.toShort())
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bus.write(address, absInstr.toShort())
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bus.write(address+1, (absAddress and 255).toShort())
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bus.write(address+1, (absAddress and 255).toShort())
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bus.write(address+2, (absAddress ushr 8).toShort())
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bus.write(address+2, (absAddress ushr 8).toShort())
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@ -236,13 +237,14 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
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else -> return IVirtualMachine.MonitorCmdResult("?syntax error", command, false)
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else -> return IVirtualMachine.MonitorCmdResult("?syntax error", command, false)
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}
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}
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val disassem = cpu.disassemble(bus.memoryComponentFor(address), address, address)
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val memory = listOf(bus[address], bus[address+1], bus[address+2]).toTypedArray()
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return IVirtualMachine.MonitorCmdResult(disassem.first.single(), "a$${hexW(disassem.second)} ", false)
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val disassem = cpu.disassembleOneInstruction(memory, 0, address)
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return IVirtualMachine.MonitorCmdResult(disassem.first, "a$${hexW(disassem.second + address)} ", false)
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}
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}
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private fun parseRelativeToPC(relative: String, currentAddress: Int): Int {
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private fun parseRelativeToPC(relative: String, currentAddress: Int): Int {
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val rest = relative.substring(1).trimStart()
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val rest = relative.substring(1).trim()
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if(rest.any()) {
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if(rest.isNotEmpty()) {
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return when(rest[0]) {
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return when(rest[0]) {
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'-' -> currentAddress-parseNumber(rest.substring(1))
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'-' -> currentAddress-parseNumber(rest.substring(1))
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'+' -> currentAddress+parseNumber(rest.substring(1))
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'+' -> currentAddress+parseNumber(rest.substring(1))
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@ -3,13 +3,10 @@ import razorvine.ksim65.components.Ram
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import razorvine.ksim65.Cpu6502
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import razorvine.ksim65.Cpu6502
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import razorvine.ksim65.Cpu65C02
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import razorvine.ksim65.Cpu65C02
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import razorvine.ksim65.components.Address
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import razorvine.ksim65.components.Address
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import razorvine.ksim65.components.BusComponent
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import razorvine.ksim65.components.MemMappedComponent
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import razorvine.ksim65.components.MemMappedComponent
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import razorvine.ksim65.components.UByte
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import razorvine.ksim65.components.UByte
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import razorvine.ksim65.hexW
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import razorvine.ksim65.hexW
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import java.lang.Exception
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import java.lang.Exception
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import kotlin.math.max
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import kotlin.math.min
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import kotlin.test.*
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import kotlin.test.*
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@ -44,8 +41,6 @@ class Test6502Klaus2m5Functional {
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val testnum = bus[0x200].toInt()
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val testnum = bus[0x200].toInt()
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if(cpu.regPC!=0x3469 || testnum!=0xf0) {
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if(cpu.regPC!=0x3469 || testnum!=0xf0) {
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println(cpu.snapshot())
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println(cpu.snapshot())
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val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20))
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println(d.first.joinToString("\n"))
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fail("test failed")
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fail("test failed")
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}
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}
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}
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}
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@ -74,8 +69,6 @@ class Test6502Klaus2m5Functional {
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println(testnum)
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println(testnum)
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if(cpu.regPC!=0x24f1 || testnum!=0xf0) {
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if(cpu.regPC!=0x24f1 || testnum!=0xf0) {
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println(cpu.snapshot())
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println(cpu.snapshot())
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val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20))
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println(d.first.joinToString("\n"))
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fail("test failed")
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fail("test failed")
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}
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}
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}
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}
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@ -138,8 +131,6 @@ class Test6502Klaus2m5Functional {
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if(cpu.regPC!=0x06f5) {
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if(cpu.regPC!=0x06f5) {
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println("Last IRQ triggered at ${hexW(irqtrigger.lastIRQpc)} last NMI at ${hexW(irqtrigger.lastNMIpc)}")
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println("Last IRQ triggered at ${hexW(irqtrigger.lastIRQpc)} last NMI at ${hexW(irqtrigger.lastNMIpc)}")
|
||||||
println(cpu.snapshot())
|
println(cpu.snapshot())
|
||||||
val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20))
|
|
||||||
println(d.first.joinToString("\n"))
|
|
||||||
fail("test failed")
|
fail("test failed")
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -174,8 +165,6 @@ class Test6502Klaus2m5Functional {
|
|||||||
}
|
}
|
||||||
|
|
||||||
println(cpu.snapshot())
|
println(cpu.snapshot())
|
||||||
val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20))
|
|
||||||
println(d.first.joinToString ("\n"))
|
|
||||||
fail("test failed")
|
fail("test failed")
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -209,8 +198,6 @@ class Test6502Klaus2m5Functional {
|
|||||||
}
|
}
|
||||||
|
|
||||||
println(cpu.snapshot())
|
println(cpu.snapshot())
|
||||||
val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20))
|
|
||||||
println(d.first.joinToString ("\n"))
|
|
||||||
fail("test failed")
|
fail("test failed")
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -12,7 +12,7 @@ class TestDisassembler {
|
|||||||
val memory = Ram(0, 0xffff)
|
val memory = Ram(0, 0xffff)
|
||||||
val binfile = javaClass.classLoader.getResourceAsStream("disassem_instr_test.prg")?.readBytes()!!
|
val binfile = javaClass.classLoader.getResourceAsStream("disassem_instr_test.prg")?.readBytes()!!
|
||||||
memory.load(binfile, 0x1000-2)
|
memory.load(binfile, 0x1000-2)
|
||||||
val result = cpu.disassemble(memory, 0x1000, 0x1221)
|
val result = cpu.disassemble(memory.data, 0x1000..0x1221, 0)
|
||||||
assertEquals(256, result.first.size)
|
assertEquals(256, result.first.size)
|
||||||
assertEquals(0x1222, result.second)
|
assertEquals(0x1222, result.second)
|
||||||
assertEquals("\$1000 69 01 adc #\$01", result.first[0])
|
assertEquals("\$1000 69 01 adc #\$01", result.first[0])
|
||||||
@ -32,7 +32,7 @@ class TestDisassembler {
|
|||||||
val memory = Ram(0, 0x0fff)
|
val memory = Ram(0, 0x0fff)
|
||||||
val source = javaClass.classLoader.getResource("disassem_r65c02.bin").readBytes()
|
val source = javaClass.classLoader.getResource("disassem_r65c02.bin").readBytes()
|
||||||
memory.load(source, 0x0200)
|
memory.load(source, 0x0200)
|
||||||
val disassem = cpu.disassemble(memory, 0x0200, 0x0250)
|
val disassem = cpu.disassemble(memory.data, 0x0200..0x0250, 0)
|
||||||
assertEquals(0x251, disassem.second)
|
assertEquals(0x251, disassem.second)
|
||||||
val result = disassem.first.joinToString("\n")
|
val result = disassem.first.joinToString("\n")
|
||||||
assertEquals("""${'$'}0200 07 12 rmb0 ${'$'}12
|
assertEquals("""${'$'}0200 07 12 rmb0 ${'$'}12
|
||||||
@ -78,7 +78,7 @@ ${'$'}0250 00 brk""", result)
|
|||||||
val memory = Ram(0, 0x0fff)
|
val memory = Ram(0, 0x0fff)
|
||||||
val source = javaClass.classLoader.getResource("disassem_wdc65c02.bin").readBytes()
|
val source = javaClass.classLoader.getResource("disassem_wdc65c02.bin").readBytes()
|
||||||
memory.load(source, 0x200)
|
memory.load(source, 0x200)
|
||||||
val disassem = cpu.disassemble(memory, 0x0200, 0x0215)
|
val disassem = cpu.disassemble(memory.data, 0x0200..0x0215, 0)
|
||||||
assertEquals(0x216, disassem.second)
|
assertEquals(0x216, disassem.second)
|
||||||
val result = disassem.first.joinToString("\n")
|
val result = disassem.first.joinToString("\n")
|
||||||
assertEquals("""${'$'}0200 cb wai
|
assertEquals("""${'$'}0200 cb wai
|
||||||
|
Loading…
Reference in New Issue
Block a user