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fix cpu irq/nmi handling

This commit is contained in:
Irmen de Jong 2020-02-16 05:46:55 +01:00
parent 30b164bb6d
commit d940b9d136
3 changed files with 13 additions and 23 deletions

View File

@ -257,9 +257,7 @@ open class Cpu6502 : BusComponent() {
*/
override fun clock() {
if (instrCycles == 0) {
if (pendingIRQ || pendingNMI) {
// NMI or IRQ interrupt.
regPC++
if(pendingNMI || (pendingIRQ && !regP.I)) {
handleInterrupt()
return
}
@ -330,7 +328,7 @@ open class Cpu6502 : BusComponent() {
}
fun irq() {
if (!regP.I && !pendingNMI) pendingIRQ = true
pendingIRQ = true
}
protected fun getFetched() =
@ -1087,17 +1085,20 @@ open class Cpu6502 : BusComponent() {
protected open fun handleInterrupt() {
// handle NMI or IRQ -- very similar to the BRK opcode above
pushStackAddr(regPC-1)
pushStackAddr(regPC)
regPC++
regP.B = false
pushStack(regP)
regP.I = true // interrupts are now disabled
// NMOS 6502 doesn't clear the D flag (CMOS 65C02 version does...)
regPC = readWord(if (pendingNMI) NMI_vector else IRQ_vector)
if(pendingNMI)
if(pendingNMI) {
regPC = readWord(NMI_vector)
pendingNMI = false
else
} else {
regPC = readWord(IRQ_vector)
pendingIRQ = false
}
}
protected fun iBvc() {

View File

@ -636,18 +636,8 @@ class Cpu65C02 : Cpu6502() {
}
override fun handleInterrupt() {
// handle NMI or IRQ -- very similar to the BRK opcode above
pushStackAddr(regPC-1)
regP.B = false
pushStack(regP)
regP.I = true // interrupts are now disabled
super.handleInterrupt()
regP.D = false // this is different from NMOS 6502
regPC = readWord(if (pendingNMI) NMI_vector else IRQ_vector)
if(pendingNMI)
pendingNMI = false
else
pendingIRQ = false
}
override fun iBit() {

View File

@ -82,7 +82,6 @@ class Test6502Klaus2m5Functional {
@Test
fun testInterrupts6502() {
// TODO fix this test code
val cpu = Cpu6502()
class Trigger(startAddress: Address, endAddress: Address) : MemMappedComponent(startAddress, endAddress) {
var value: UByte = 0
@ -95,17 +94,17 @@ class Test6502Klaus2m5Functional {
value = data
when(value.toInt()) {
1 -> {
println("IRQ at pc ${hexW(cpu.regPC)}")
// println("IRQ at pc ${hexW(cpu.regPC)}")
lastIRQpc = cpu.regPC
cpu.irq()
}
2 -> {
println("NMI at pc ${hexW(cpu.regPC)}")
// println("NMI at pc ${hexW(cpu.regPC)}")
lastNMIpc = cpu.regPC
cpu.nmi()
}
3 -> {
println("IRQ+NMI at pc ${hexW(cpu.regPC)}")
// println("IRQ+NMI at pc ${hexW(cpu.regPC)}")
lastIRQpc = cpu.regPC
lastNMIpc = cpu.regPC
cpu.nmi()