From ec9b80433f00c152b1dab01b27f697684ce05064 Mon Sep 17 00:00:00 2001 From: Irmen de Jong Date: Fri, 21 Feb 2020 01:57:00 +0100 Subject: [PATCH] doc --- README.md | 12 ++++++------ src/main/kotlin/razorvine/c64emu/Cia.kt | 2 +- src/main/kotlin/razorvine/ksim65/Cpu6502.kt | 4 ++-- src/main/kotlin/razorvine/ksim65/Cpu65C02.kt | 4 ++-- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/README.md b/README.md index 70b69d0..9302a2e 100644 --- a/README.md +++ b/README.md @@ -16,15 +16,15 @@ This is a Kotlin/JVM library that simulates the 8-bit 6502 and 65C02 microproces Properties of this simulator: -- Written in Kotlin. It is low-level code, but hopefully still readable :-) -- Designed to simulate various hardware components (bus, cpu, memory, i/o controllers) -- IRQ and NMI simulation -- Aims to simulate correct instruction cycle timing, but is not 100% cycle exact for simplicity -- Aims to implements all 6502 and 65c02 instructions, including the 'illegal' 6502 instructions (not yet done) +- written in Kotlin. It is low-level code, but hopefully still readable :-) +- simulates various hardware components (bus, cpu, memory, i/o controllers) +- IRQ and NMI +- instruction cycle times are simulated (however the *internal* cpu behavior is not cycle-exact for simplicity reasons) +- has all 6502 and 65c02 instructions, including many of the 'illegal' 6502 instructions (goal is 100% eventually) - correct BCD mode for adc/sbc instructions on both cpu types - passes several extensive unit test suites that verify instruction and cpu flags behavior - simple debugging machine monitor, which basic disassembler and assembler functions -- provide a few virtual example machines, one of which is a Commodore-64 +- provide a few virtual example machines, one of which is a fairly capable Commodore-64 ## Documentation diff --git a/src/main/kotlin/razorvine/c64emu/Cia.kt b/src/main/kotlin/razorvine/c64emu/Cia.kt index ca8f8fc..a948315 100644 --- a/src/main/kotlin/razorvine/c64emu/Cia.kt +++ b/src/main/kotlin/razorvine/c64emu/Cia.kt @@ -86,7 +86,7 @@ class Cia(val number: Int, startAddress: Address, endAddress: Address, val cpu: totalCycles++ if (totalCycles%20000 == 0) { - // TOD resolution is 0.1 second, no need to update it in every cycle + // TOD resolution is 0.1 second, no need to update it in every bus cycle tod.update() } diff --git a/src/main/kotlin/razorvine/ksim65/Cpu6502.kt b/src/main/kotlin/razorvine/ksim65/Cpu6502.kt index d64ca50..edeab49 100644 --- a/src/main/kotlin/razorvine/ksim65/Cpu6502.kt +++ b/src/main/kotlin/razorvine/ksim65/Cpu6502.kt @@ -160,7 +160,7 @@ open class Cpu6502 : BusComponent() { /** * Process once clock cycle in the cpu. - * Use this if goal is cycle-perfect emulation. + * Use this if you need cycle-perfect instruction timing simulation. */ override fun clock() { if (instrCycles == 0) { @@ -222,7 +222,7 @@ open class Cpu6502 : BusComponent() { /** * Execute one single complete instruction. - * Use this when the goal is emulation performance and not a cycle perfect system. + * Use this when you don't care about clock cycle instruction timing simulation. */ open fun step() { totalCycles += instrCycles diff --git a/src/main/kotlin/razorvine/ksim65/Cpu65C02.kt b/src/main/kotlin/razorvine/ksim65/Cpu65C02.kt index 83ecace..e3abbaf 100644 --- a/src/main/kotlin/razorvine/ksim65/Cpu65C02.kt +++ b/src/main/kotlin/razorvine/ksim65/Cpu65C02.kt @@ -17,7 +17,7 @@ class Cpu65C02 : Cpu6502() { /** * Process once clock cycle in the cpu - * Use this if goal is cycle-perfect emulation. + * Use this if you need cycle-perfect instruction timing simulation. */ override fun clock() { when (waiting) { @@ -40,7 +40,7 @@ class Cpu65C02 : Cpu6502() { /** * Execute one single complete instruction. - * Use this when the goal is emulation performance and not a cycle perfect system. + * Use this when you don't care about clock cycle instruction timing simulation. */ override fun step() { totalCycles += instrCycles