mirror of
https://github.com/irmen/ksim65.git
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57 lines
1.8 KiB
Kotlin
57 lines
1.8 KiB
Kotlin
package razorvine.c64emu
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import razorvine.ksim65.components.MemMappedComponent
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import razorvine.ksim65.components.UByte
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/**
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* The 6510's IO port located at $00/$01
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* Controlling the memory layout, and cassette port (not processed at all).
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* TODO: there are a few functional tests that still fail. Is this not implemented correctly yet?
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*/
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class CpuIoPort : MemMappedComponent(0x0000, 0x0001) {
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private var dataDirections: Int = 0
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private var ioPort: Int = 0
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var loram: Boolean = false // Bit 0: LORAM signal. Selects ROM or RAM at 40960 ($A000). 1=BASIC, 0=RAM
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private set
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var hiram: Boolean = false // Bit 1: HIRAM signal. Selects ROM or RAM at 57344 ($E000). 1=Kernal, 0=RAM
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private set
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var charen: Boolean = false // Bit 2: CHAREN signal. Selects character ROM or I/O devices. 1=I/O, 0=ROM
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private set
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override fun clock() { }
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override fun reset() {
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dataDirections = 0xef
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ioPort = 0x37
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determineRoms()
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}
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override operator fun get(offset: Int): UByte {
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return if(offset==0) {
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dataDirections.toShort()
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} else {
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if(dataDirections and 0b00100000 == 0)
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(ioPort and 0b11011111).toShort() // bit 5 is low when input
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else
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ioPort.toShort()
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}
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}
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override operator fun set(offset: Int, data: UByte) {
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if(offset==0) {
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dataDirections = data.toInt()
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determineRoms()
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} else {
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ioPort = (ioPort and dataDirections.inv()) or (data.toInt() and dataDirections)
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determineRoms()
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}
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}
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private fun determineRoms() {
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loram = ioPort and 0b00000001 != 0
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hiram = ioPort and 0b00000010 != 0
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charen = ioPort and 0b00000100 != 0
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}
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}
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