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https://github.com/g012/l65.git
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Added 16 bits implied instructions (ei, di, etc...).
This commit is contained in:
mooz
parent
564746133a
commit
6efbd07034
26
l7801.lua
26
l7801.lua
@ -38,9 +38,9 @@ local Keywords_data = {
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'dc',
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}
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local Keywords_7801 = {
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'block', 'calb', 'calf', 'calt', 'daa', 'dcr', 'exa', 'exx',
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'halt', 'jb', 'jr', 'lxi', 'mvi', 'nop', 'ret', 'reti',
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'rets', 'sio', 'softi', 'stm', 'table',
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'block', 'calb', 'calf', 'calt', 'ei', 'daa', 'di', 'dcr',
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'exa', 'exx', 'halt', 'jb', 'jr', 'lxi', 'mvi', 'nop',
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'ret', 'reti', 'rets', 'sio', 'softi', 'stm', 'table',
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}
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local Registers_7801 = {
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a=8,b=8,c=8,d=8,e=8,h=8,l=8,v=8,
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@ -64,7 +64,7 @@ opcode_arg_encapsulate(true)
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local opcode_encapsulate = {} -- additionnal opcode, to have basic encapsulation (function(a) return a end)
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local opcode_alias = {} -- alternate user names for opcodes
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local opcode_implied = lookupify{
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'block', 'calb', 'daa', 'exa', 'exx', 'halt', 'jb', 'nop', 'ret', 'reti', 'rets', 'sio', 'softi', 'stm', 'table'
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'block', 'calb', 'ei', 'daa', 'di', 'exa', 'exx', 'halt', 'jb', 'nop', 'ret', 'reti', 'rets', 'sio', 'softi', 'stm', 'table'
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}
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local opcode_immediate = lookupify{
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'calf', 'calt'
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@ -75,13 +75,20 @@ local opcode_relative = lookupify{
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local opcode_reg = lookupify{
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'dcr', 'inr'
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}
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local opcode_regb = lookupify{
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'mvi'
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}
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local opcode_regw = lookupify{
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'lxi'
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}
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local opcode_reg_list = {
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a = lookupify{'dcr','inr'},
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b = lookupify{'dcr','inr'},
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c = lookupify{'dcr','inr'},
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a = lookupify{'dcr','inr', 'mvi'},
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b = lookupify{'dcr','inr', 'mvi'},
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c = lookupify{'dcr','inr', 'mvi'},
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d = lookupify{'mvi'},
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e = lookupify{'mvi'},
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h = lookupify{'mvi'},
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l = lookupify{'mvi'},
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bc = lookupify{'lxi'},
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de = lookupify{'lxi'},
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hl = lookupify{'lxi'},
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@ -93,6 +100,7 @@ local addressing_map = {
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imm = opcode_immediate,
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rel = opcode_relative,
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reg = opcode_reg,
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regb = opcode_regb,
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regw = opcode_regw,
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}
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@ -1401,7 +1409,7 @@ local function ParseLua(src, src_name)
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end
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stat = emit_call{name=op, args={expr, mod_expr}, inverse_encapsulate=inverse_encapsulate, paren_open_white=paren_open_whites} break
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end
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if opcode_reg[op] or opcode_regw[op] then
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if opcode_reg[op] or opcode_regb[op] or opcode_regw[op] then
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tok:Save()
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local register_name = tok:Get(tokenList).Data
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local call_args = {name=op..register_name}
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@ -1411,7 +1419,7 @@ local function ParseLua(src, src_name)
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if not opcode_reg_list[register_name] and opcode_reg_list[register_name][op] then tok:Restore()
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return false, GenerateError("Opcode " .. op .. " doesn't support this addressing mode")
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end
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if opcode_regw[op] then
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if opcode_regw[op] or opcode_regb[op] then
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if not tok:ConsumeSymbol(',', tokenList) then tok:Restore()
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return false, GenerateError("Opcode " .. op .. " doesn't support this addressing mode")
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end
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40
samples/scv_hello.l65
Normal file
40
samples/scv_hello.l65
Normal file
@ -0,0 +1,40 @@
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require 'scv'
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location(0x8000, 0x8FFF)
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section{"rom", org=0x8000}
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dc.b 'H'
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@main
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di
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lxi sp,0xFFD2
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ei
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calt 0x8C
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lxi hl,vdc_data
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lxi de,0x3400
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mvi c,0x03
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block
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lxi hl,message
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lxi de,0x3043
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lxi bc,0x01ff
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@loop_0
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block
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dcr b
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jr loop_0
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-- beep
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lxi hl,0x3600
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calf 0xfb0
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@loop_1
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nop
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jr loop_1
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section{"vdc_data", org=0x8030}
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dc.b 0xC0,0x00,0x00,0xF2
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section{"message", org=0x8040}
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dc.b "hello world"
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dc.b 0x00
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writebin(filename .. '.bin')
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65
uPD7801.lua
65
uPD7801.lua
@ -141,7 +141,7 @@ for k,v in pairs(oprr) do
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end
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end
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local oprxx ={
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local opregb ={
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mvib=M.op(0x6a,7),
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mvic=M.op(0x6b,7),
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mvid=M.op(0x6c,7),
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@ -149,9 +149,9 @@ local oprxx ={
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mvih=M.op(0x6e,7),
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mvil=M.op(0x6f,7),
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mviv=M.op(0x68,7)
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} M.oprxx = oprxx
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for k,v in pairs(oprxx) do
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M[k .. 'xx'] = function(late, early)
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} M.opregb = opregb
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for k,v in pairs(opregb) do
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M[k] = function(late, early)
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local l65dbg = { info=debug.getinfo(2, 'Sl'), trace=debug.traceback(nil, 1) }
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local size = function() late,early = M.size_op(late,early) return 2 end
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local bin = function() local l65dbg=l65dbg return { v.opc, M.op_eval_byte(late,early) } end
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@ -209,37 +209,6 @@ for k,v in pairs(opvind) do
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end
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end
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--[[
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local opviwaxx ={
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aniw=M.op(0x05,16),
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oriw=M.op(0x15,16),
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gtiw=M.op(0x25,13),
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ltiw=M.op(0x35,13),
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oniw=M.op(0x45,13),
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offiw=M.op(0x55,13),
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neiw=M.op(0x65,13),
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mviw=M.op(0x71,13),
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eqiw=M.op(0x75,13)
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} M.opvwaxx = opvwaxx
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for k,v in pairs(opvwaxx) do
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M[k .. 'vindxx'] = function(late0, early0, late1, early1)
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local l65dbg = { info=debug.getinfo(2, 'Sl'), trace=debug.traceback(nil, 1) }
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local size = function()
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late0,early0 = M.size_op(late,early)
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late1,early1 = M.size_op(late,early)
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return 3
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end
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local bin = function()
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local l65dbg=l65dbg
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local offset = M.op_eval_byte(late0,early0)
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local x = M.op_eval_byte(late1,early1)
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return { v.opc, offset, x }
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end
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table.insert(M.section_current.instructions, { size=size, cycles=v.cycles, bin=bin })
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end
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end
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]]--
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local opw = {
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call=M.op(0x44,16),
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jmp=M.op(0x54,10),
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@ -319,12 +288,38 @@ M.jr = function(label)
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table.insert(M.section_current.instructions, op)
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end
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local op48imm = {
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ei=M.op(0x20,8),
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di=M.op(0x24,8),
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clc=M.op(0x2a,8),
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stc=M.op(0x2b,8),
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pen=M.op(0x2c,11),
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per=M.op(0x3c,11),
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pex=M.op(0x2d,11),
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rld=M.op(0x38,17),
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rrd=M.op(0x39,17),
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} M.op48imm = op48imm
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for k,v in pairs(op48imm) do
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M[k] = function()
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table.insert(M.section_current.instructions, { size=2, cycles=v.cycles, bin={ 0x48, v.opc } })
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end
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end
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return M
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--[[ [todo]
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8 bits instructions:
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JRE+ 0x4e xx 17
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JRE- 0x4f xx 17
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ani
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ori
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gti
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lti
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oni
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offi
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nei
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mvi
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eqi
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16 bits instructions:
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0x48xx
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