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Added LDAX+, LDAX-, STAX+ and STAX- (renamed ldaxi, ldaxd, staxi, staxd).
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26
l7801.lua
26
l7801.lua
@ -38,11 +38,16 @@ local Keywords_data = {
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'dc',
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}
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local Keywords_7801 = {
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'aci','adi','adinc','ani','bit0','bit1','bit2','bit3','bit4','bit5','bit6','bit7',
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'block','calb','calf','call','calt','clc','ei','eqi','eqiw','daa','di','dcr','dcrw','dcx',
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'ex','exx','gti','halt','inr','inrw','inx','jb','jmp','jr','jre','ldaw','ldax','lti','lxi','mov','mvi','mviw','mvix','nei','nop',
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'offi','oni','ori','pen','per','pex','ret','reti','rets','rld','rrd','sio','softi','staw','stax','stc','stm',
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'sbi','sui','suinb','table','xri',
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'aci','adi','adinc','ani','bit0','bit1','bit2','bit3',
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'bit4','bit5','bit6','bit7','block','calb','calf','call',
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'calt','clc','ei','eqi','eqiw','daa','di','dcr',
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'dcrw','dcx','ex','exx','gti','halt','inr','inrw',
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'inx','jb','jmp','jr','jre','ldaw','ldax','ldaxd',
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'ldaxi','lti','lxi','mov','mvi','mviw','mvix','nei',
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'nop','offi','oni','ori','pen','per','pex','ret',
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'reti','rets','rld','rrd','sio','softi','staw','stax',
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'staxd','staxi','stc','stm','sbi','sui','suinb','table',
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'xri',
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}
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local Registers_7801 = {
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@ -94,8 +99,8 @@ local opcode_regb = lookupify{
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'aci','adi','adinc','ani','eqi','gti','lti','mvi','nei','offi','oni','ori','sbi','sui','suinb','xri',
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}
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local opcode_reg_ind = lookupify{
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'ldax',
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'stax',
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'ldax','ldaxd','ldaxi',
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'stax','staxd','staxi',
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}
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local opcode_reg_ind_ex = lookupify{
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'mvix'
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@ -113,8 +118,8 @@ local opcode_reg_list = {
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l = lookupify{'mvi'},
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v = lookupify{'mvi'},
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bc = lookupify{'ldax','lxi','mvix','stax'},
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de = lookupify{'ldax','lxi','mvix','stax'},
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hl = lookupify{'dcx','inx','ldax','lxi','mvix','stax'},
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de = lookupify{'ldax','ldaxd','ldaxi','lxi','mvix','stax','staxd','staxi'},
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hl = lookupify{'dcx','inx','ldax','ldaxd','ldaxi','lxi','mvix','stax','staxd','staxi'},
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sp = lookupify{'dcx','inx','lxi'},
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}
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@ -1490,14 +1495,13 @@ local function ParseLua(src, src_name)
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if not (opcode_reg_list[register_name] and opcode_reg_list[register_name][op]) then
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return false, GenerateError("Opcode " .. op .. " doesn't support this addressing mode")
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end
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for _,v in ipairs(tokenList[#tokenList].LeadingWhite) do table.insert(paren_open_whites, v) end
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if not tok:ConsumeSymbol(')', tokenList) then
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return false, GenerateError("Unexpected character")
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end
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if opcode_reg_ind[op] then
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for _,v in ipairs(tokenList[#tokenList-1].LeadingWhite) do table.insert(paren_close_whites, v) end
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for _,v in ipairs(tokenList[#tokenList].LeadingWhite) do table.insert(paren_close_whites, v) end
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stat = emit_call{name=op .. register_name, paren_open_white=paren_open_whites} break
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stat = emit_call{name=op .. register_name, paren_open_white=paren_open_whites, paren_close_white=paren_close_whites} break
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end
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if not tok:ConsumeSymbol(',', tokenList) then
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return false, GenerateError("Unexpected character")
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@ -124,5 +124,13 @@ section{"rom", org=0x8000}
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stax (hl)
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mviw (v,0x9a),0x3f
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eqiw (v,0xc5),0x1b
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ldaxd (de)
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ldaxi (de)
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ldaxd (hl)
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ldaxi (hl)
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staxd (de)
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staxi (de)
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staxd (hl)
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staxi (hl)
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writebin(filename .. '.bin')
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20
uPD7801.lua
20
uPD7801.lua
@ -77,11 +77,19 @@ local opr16={
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inxde=M.op(0x22,7),
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inxhl=M.op(0x32,7),
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ldaxbc=M.op(0x29,7),
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ldaxdde=M.op(0x2e,7),
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ldaxde=M.op(0x2a,7),
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ldaxhl=M.op(0x2b,7),
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ldaxide=M.op(0x2c,7),
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ldaxdhl=M.op(0x2f,7),
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ldaxihl=M.op(0x2d,7),
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staxbc=M.op(0x39,7),
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staxde=M.op(0x3a,7),
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staxdde=M.op(0x3e,7),
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staxdhl=M.op(0x3f,7),
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staxhl=M.op(0x3b,7),
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staxide=M.op(0x3c,7),
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staxihl=M.op(0x3d,7),
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} M.opr16 = opr16
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for k,v in pairs(opr16) do
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M[k] = function()
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@ -320,18 +328,6 @@ end
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return M
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--[[ [todo]
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8 bits instructions:
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-- d
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ldaxm=M.op(0x2e,7),
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ldaxp=M.op(0x2c,7),
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staxm=M.op(0x3e,7),
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staxp=M.op(0x3c,7)
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-- h
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ldaxm=M.op(0x2f,7),
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ldaxp=M.op(0x2d,7),
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staxm=M.op(0x3f,7),
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staxp=M.op(0x3d,7)
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16 bits instructions:
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0x48xx
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