6502/l65
1
0
Fork 0
mirror of https://github.com/g012/l65.git synced 2024-12-22 16:30:45 +00:00
Code Issues Projects Releases Wiki Activity

Added LDAX+, LDAX-, STAX+ and STAX- (renamed ldaxi, ldaxd, staxi, staxd).

Browse Source
This commit is contained in:
mooz 2018-11-11 15:54:56 +01:00
parent fe3cdabf4f
commit 77b69902c2
3 changed files with 32 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
l7801.lua
View File

@ -38,11 +38,16 @@ local Keywords_data = {
'dc',
}
local Keywords_7801 = {
'aci','adi','adinc','ani','bit0','bit1','bit2','bit3','bit4','bit5','bit6','bit7',
'block','calb','calf','call','calt','clc','ei','eqi','eqiw','daa','di','dcr','dcrw','dcx',
'ex','exx','gti','halt','inr','inrw','inx','jb','jmp','jr','jre','ldaw','ldax','lti','lxi','mov','mvi','mviw','mvix','nei','nop',
'offi','oni','ori','pen','per','pex','ret','reti','rets','rld','rrd','sio','softi','staw','stax','stc','stm',
'sbi','sui','suinb','table','xri',
'aci','adi','adinc','ani','bit0','bit1','bit2','bit3',
'bit4','bit5','bit6','bit7','block','calb','calf','call',
'calt','clc','ei','eqi','eqiw','daa','di','dcr',
'dcrw','dcx','ex','exx','gti','halt','inr','inrw',
'inx','jb','jmp','jr','jre','ldaw','ldax','ldaxd',
'ldaxi','lti','lxi','mov','mvi','mviw','mvix','nei',
'nop','offi','oni','ori','pen','per','pex','ret',
'reti','rets','rld','rrd','sio','softi','staw','stax',
'staxd','staxi','stc','stm','sbi','sui','suinb','table',
'xri',
}
local Registers_7801 = {
@ -94,8 +99,8 @@ local opcode_regb = lookupify{
'aci','adi','adinc','ani','eqi','gti','lti','mvi','nei','offi','oni','ori','sbi','sui','suinb','xri',
}
local opcode_reg_ind = lookupify{
'ldax',
'stax',
'ldax','ldaxd','ldaxi',
'stax','staxd','staxi',
}
local opcode_reg_ind_ex = lookupify{
'mvix'
@ -113,8 +118,8 @@ local opcode_reg_list = {
l = lookupify{'mvi'},
v = lookupify{'mvi'},
bc = lookupify{'ldax','lxi','mvix','stax'},
de = lookupify{'ldax','lxi','mvix','stax'},
hl = lookupify{'dcx','inx','ldax','lxi','mvix','stax'},
de = lookupify{'ldax','ldaxd','ldaxi','lxi','mvix','stax','staxd','staxi'},
hl = lookupify{'dcx','inx','ldax','ldaxd','ldaxi','lxi','mvix','stax','staxd','staxi'},
sp = lookupify{'dcx','inx','lxi'},
}
@ -1490,14 +1495,13 @@ local function ParseLua(src, src_name)
if not (opcode_reg_list[register_name] and opcode_reg_list[register_name][op]) then
return false, GenerateError("Opcode " .. op .. " doesn't support this addressing mode")
end
for _,v in ipairs(tokenList[#tokenList].LeadingWhite) do table.insert(paren_open_whites, v) end
if not tok:ConsumeSymbol(')', tokenList) then
return false, GenerateError("Unexpected character")
end
if opcode_reg_ind[op] then
for _,v in ipairs(tokenList[#tokenList-1].LeadingWhite) do table.insert(paren_close_whites, v) end
for _,v in ipairs(tokenList[#tokenList].LeadingWhite) do table.insert(paren_close_whites, v) end
stat = emit_call{name=op .. register_name, paren_open_white=paren_open_whites} break
stat = emit_call{name=op .. register_name, paren_open_white=paren_open_whites, paren_close_white=paren_close_whites} break
end
if not tok:ConsumeSymbol(',', tokenList) then
return false, GenerateError("Unexpected character")

8
samples/scv_test.l65
View File

@ -124,5 +124,13 @@ section{"rom", org=0x8000}
stax (hl)
mviw (v,0x9a),0x3f
eqiw (v,0xc5),0x1b
ldaxd (de)
ldaxi (de)
ldaxd (hl)
ldaxi (hl)
staxd (de)
staxi (de)
staxd (hl)
staxi (hl)
writebin(filename .. '.bin')

20
uPD7801.lua
View File

@ -77,11 +77,19 @@ local opr16={
inxde=M.op(0x22,7),
inxhl=M.op(0x32,7),
ldaxbc=M.op(0x29,7),
ldaxdde=M.op(0x2e,7),
ldaxde=M.op(0x2a,7),
ldaxhl=M.op(0x2b,7),
ldaxide=M.op(0x2c,7),
ldaxdhl=M.op(0x2f,7),
ldaxihl=M.op(0x2d,7),
staxbc=M.op(0x39,7),
staxde=M.op(0x3a,7),
staxdde=M.op(0x3e,7),
staxdhl=M.op(0x3f,7),
staxhl=M.op(0x3b,7),
staxide=M.op(0x3c,7),
staxihl=M.op(0x3d,7),
} M.opr16 = opr16
for k,v in pairs(opr16) do
M[k] = function()
@ -320,18 +328,6 @@ end
return M
--[[ [todo]
8 bits instructions:
-- d
ldaxm=M.op(0x2e,7),
ldaxp=M.op(0x2c,7),
staxm=M.op(0x3e,7),
staxp=M.op(0x3c,7)
-- h
ldaxm=M.op(0x2f,7),
ldaxp=M.op(0x2d,7),
staxm=M.op(0x3f,7),
staxp=M.op(0x3d,7)
16 bits instructions:
0x48xx