Code Generation Notes for MSA
=============================

Intrinsics are lowered to SelectionDAG nodes where possible in order to enable
optimisation, reduce the size of the ISel matcher, and reduce repetition in
the implementation. In a small number of cases, this can cause different
(semantically equivalent) instructions to be used in place of the requested
instruction, even when no optimisation has taken place.

Instructions
============

This section describes any quirks of instruction selection for MSA. For
example, two instructions might be equally valid for some given IR and one is
chosen in preference to the other.

vshf.w:
        It is not possible to emit vshf.w when the shuffle description is
        constant since shf.w covers exactly the same cases. shf.w is used
        instead. It is also impossible for the shuffle description to be
        unknown at compile-time due to the definition of shufflevector in
        LLVM IR.

ilvl.d, pckev.d:
        It is not possible to emit ilvl.d, or pckev.d since ilvev.d covers the
        same shuffle. ilvev.d will be emitted instead.

ilvr.d, ilvod.d, pckod.d:
        It is not possible to emit ilvr.d, or pckod.d since ilvod.d covers the
        same shuffle. ilvod.d will be emitted instead.

splati.w:
        It is not possible to emit splati.w since shf.w covers the same cases.
        shf.w will be emitted instead.

copy_s.w
        On MIPS32, the copy_u.d intrinsic will emit this instruction instead of
        copy_u.w. This is semantically equivalent since the general-purpose
        register file is 32-bits wide.
