6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 04:33:05 +00:00
Code Issues Projects Releases Wiki Activity
210edf5559
llvm-6502/test/MC/AArch64/neon-rounding-halving-add.s

40 lines
1.9 KiB
ArmAsm
Raw Normal View History

AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 09:20:35 +00:00
// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
//------------------------------------------------------------------------------
// Vector Integer Rouding Halving Add (Signed)
//------------------------------------------------------------------------------
srhadd v0.8b, v1.8b, v2.8b
srhadd v0.16b, v1.16b, v2.16b
srhadd v0.4h, v1.4h, v2.4h
srhadd v0.8h, v1.8h, v2.8h
srhadd v0.2s, v1.2s, v2.2s
srhadd v0.4s, v1.4s, v2.4s
// CHECK: srhadd v0.8b, v1.8b, v2.8b // encoding: [0x20,0x14,0x22,0x0e]
// CHECK: srhadd v0.16b, v1.16b, v2.16b // encoding: [0x20,0x14,0x22,0x4e]
// CHECK: srhadd v0.4h, v1.4h, v2.4h // encoding: [0x20,0x14,0x62,0x0e]
// CHECK: srhadd v0.8h, v1.8h, v2.8h // encoding: [0x20,0x14,0x62,0x4e]
// CHECK: srhadd v0.2s, v1.2s, v2.2s // encoding: [0x20,0x14,0xa2,0x0e]
// CHECK: srhadd v0.4s, v1.4s, v2.4s // encoding: [0x20,0x14,0xa2,0x4e]
//------------------------------------------------------------------------------
// Vector Integer Rouding Halving Add (Unsigned)
//------------------------------------------------------------------------------
urhadd v0.8b, v1.8b, v2.8b
urhadd v0.16b, v1.16b, v2.16b
urhadd v0.4h, v1.4h, v2.4h
urhadd v0.8h, v1.8h, v2.8h
urhadd v0.2s, v1.2s, v2.2s
urhadd v0.4s, v1.4s, v2.4s
// CHECK: urhadd v0.8b, v1.8b, v2.8b // encoding: [0x20,0x14,0x22,0x2e]
// CHECK: urhadd v0.16b, v1.16b, v2.16b // encoding: [0x20,0x14,0x22,0x6e]
// CHECK: urhadd v0.4h, v1.4h, v2.4h // encoding: [0x20,0x14,0x62,0x2e]
// CHECK: urhadd v0.8h, v1.8h, v2.8h // encoding: [0x20,0x14,0x62,0x6e]
// CHECK: urhadd v0.2s, v1.2s, v2.2s // encoding: [0x20,0x14,0xa2,0x2e]
// CHECK: urhadd v0.4s, v1.4s, v2.4s // encoding: [0x20,0x14,0xa2,0x6e]
Reference in New Issue Copy Permalink