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llvm-6502/test/MC/Disassembler/Hexagon/st.txt

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[Hexagon] Renaming old multiclass for removal. Adding post-increment store classes and instruction defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224949 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 19:42:14 +00:00
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224952 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:44:51 +00:00
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# CHECK: memd(r17+#168) = r21:20
[Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224951 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:00:43 +00:00
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# CHECK: memd(r17++#40) = r21:20
[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224952 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:44:51 +00:00
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# CHECK: memd(r17++m1) = r21:20
0xab 0xde 0xd1 0x40
# CHECK: if (p3) memd(r17+#168) = r31:30
0xab 0xde 0xd1 0x44
# CHECK: if (!p3) memd(r17+#168) = r31:30
0x03 0x40 0x45 0x85 0xab 0xde 0xd1 0x42
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) memd(r17+#168) = r31:30
0x03 0x40 0x45 0x85 0xab 0xde 0xd1 0x46
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) memd(r17+#168) = r31:30
[Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224951 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:00:43 +00:00
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# CHECK: if (p3) memd(r17++#40) = r21:20
0x2f 0xf4 0xd1 0xab
# CHECK: if (!p3) memd(r17++#40) = r21:20
0x03 0x40 0x45 0x85 0xab 0xf4 0xd1 0xab
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) memd(r17++#40) = r21:20
0x03 0x40 0x45 0x85 0xaf 0xf4 0xd1 0xab
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) memd(r17++#40) = r21:20
[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224952 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:44:51 +00:00
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# CHECK: memb(r17+#21) = r21
[Hexagon] Renaming old multiclass for removal. Adding post-increment store classes and instruction defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224949 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 19:42:14 +00:00
0x28 0xd5 0x11 0xab
# CHECK: memb(r17++#5) = r21
[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224952 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:44:51 +00:00
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# CHECK: memb(r17++m1) = r21
0xab 0xdf 0x11 0x40
# CHECK: if (p3) memb(r17+#21) = r31
0xab 0xdf 0x11 0x44
# CHECK: if (!p3) memb(r17+#21) = r31
0x03 0x40 0x45 0x85 0xab 0xdf 0x11 0x42
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) memb(r17+#21) = r31
0x03 0x40 0x45 0x85 0xab 0xdf 0x11 0x46
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) memb(r17+#21) = r31
[Hexagon] Renaming old multiclass for removal. Adding post-increment store classes and instruction defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224949 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 19:42:14 +00:00
0x2b 0xf5 0x11 0xab
# CHECK: if (p3) memb(r17++#5) = r21
0x2f 0xf5 0x11 0xab
# CHECK: if (!p3) memb(r17++#5) = r21
0x03 0x40 0x45 0x85 0xab 0xf5 0x11 0xab
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) memb(r17++#5) = r21
0x03 0x40 0x45 0x85 0xaf 0xf5 0x11 0xab
# CHECK: p3 = r5
[Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224951 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:00:43 +00:00
# CHECK-NEXT: if (!p3.new) memb(r17++#5) = r21
[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224952 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:44:51 +00:00
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# CHECK: memh(r17+#42) = r31
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# CHECK: memh(r17+#42) = r31.h
[Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224951 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:00:43 +00:00
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# CHECK: memh(r17++#10) = r21
[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224952 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:44:51 +00:00
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# CHECK: memh(r17++#10) = r21.h
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# CHECK: memh(r17++m1) = r21
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# CHECK: memh(r17++m1) = r21.h
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# CHECK: if (p3) memh(r17+#62) = r21
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# CHECK: if (p3) memh(r17+#62) = r21.h
0xfb 0xd5 0x51 0x44
# CHECK: if (!p3) memh(r17+#62) = r21
0xfb 0xd5 0x71 0x44
# CHECK: if (!p3) memh(r17+#62) = r21.h
0x03 0x40 0x45 0x85 0xfb 0xd5 0x51 0x42
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) memh(r17+#62) = r21
0x03 0x40 0x45 0x85 0xfb 0xd5 0x71 0x42
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) memh(r17+#62) = r21.h
0x03 0x40 0x45 0x85 0xfb 0xd5 0x51 0x46
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) memh(r17+#62) = r21
0x03 0x40 0x45 0x85 0xfb 0xd5 0x71 0x46
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) memh(r17+#62) = r21.h
[Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224951 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:00:43 +00:00
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# CHECK: if (p3) memh(r17++#10) = r21
0x2f 0xf5 0x51 0xab
# CHECK: if (!p3) memh(r17++#10) = r21
0x03 0x40 0x45 0x85 0xab 0xf5 0x51 0xab
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) memh(r17++#10) = r21
0x03 0x40 0x45 0x85 0xaf 0xf5 0x51 0xab
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) memh(r17++#10) = r21
[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224952 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:44:51 +00:00
0x2b 0xf5 0x71 0xab
# CHECK: if (p3) memh(r17++#10) = r21.h
0x2f 0xf5 0x71 0xab
# CHECK: if (!p3) memh(r17++#10) = r21.h
0x03 0x40 0x45 0x85 0xab 0xf5 0x71 0xab
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) memh(r17++#10) = r21.h
0x03 0x40 0x45 0x85 0xaf 0xf5 0x71 0xab
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) memh(r17++#10) = r21.h
[Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224951 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:00:43 +00:00
[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224952 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:44:51 +00:00
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# CHECK: memw(r17+#84) = r31
[Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224951 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:00:43 +00:00
0x28 0xd5 0x91 0xab
# CHECK: memw(r17++#20) = r21
[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224952 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:44:51 +00:00
0x00 0xf5 0x91 0xad
# CHECK: memw(r17++m1) = r21
0xab 0xdf 0x91 0x40
# CHECK: if (p3) memw(r17+#84) = r31
0xab 0xdf 0x91 0x44
# CHECK: if (!p3) memw(r17+#84) = r31
0x03 0x40 0x45 0x85 0xab 0xdf 0x91 0x42
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) memw(r17+#84) = r31
0x03 0x40 0x45 0x85 0xab 0xdf 0x91 0x46
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) memw(r17+#84) = r31
[Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224951 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-29 20:00:43 +00:00
0x2b 0xf5 0x91 0xab
# CHECK: if (p3) memw(r17++#20) = r21
0x2f 0xf5 0x91 0xab
# CHECK: if (!p3) memw(r17++#20) = r21
0x03 0x40 0x45 0x85 0xaf 0xf5 0x91 0xab
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) memw(r17++#20) = r21
0x03 0x40 0x45 0x85 0xab 0xf5 0x91 0xab
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) memw(r17++#20) = r21
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