llvm-6502/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt

# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s

#------------------------------------------------------------------------------
# Load-store exclusive
#------------------------------------------------------------------------------

#ldxp x14, x14, [sp]
0xee 0x3b 0x7f 0xc8
#CHECK: warning: potentially undefined instruction encoding
#CHECK-NEXT: 0xee 0x3b 0x7f 0xc8

#ldaxp w19, w19, [x1]
0x33 0xcc 0x7f 0x88
#CHECK: warning: potentially undefined instruction encoding
#CHECK-NEXT: 0x33 0xcc 0x7f 0x88

#------------------------------------------------------------------------------
# Load-store register (immediate post-indexed)
#------------------------------------------------------------------------------

0x63 0x44 0x40 0xf8
#CHECK: warning: potentially undefined instruction encoding
#CHECK-NEXT: 0x63 0x44 0x40 0xf8

0x42 0x14 0xc0 0x38
#CHECK: warning: potentially undefined instruction encoding
#CHECK-NEXT: 0x42 0x14 0xc0 0x38

#------------------------------------------------------------------------------
# Load-store register (immediate pre-indexed)
#------------------------------------------------------------------------------

0x63 0x4c 0x40 0xf8
#CHECK: warning: potentially undefined instruction encoding
#CHECK-NEXT: 0x63 0x4c 0x40 0xf8

0x42 0x1c 0xc0 0x38
#CHECK: warning: potentially undefined instruction encoding
#CHECK-NEXT: 0x42 0x1c 0xc0 0x38

#------------------------------------------------------------------------------
# Load-store register pair (offset)
#------------------------------------------------------------------------------

# Unpredictable if Rt == Rt2 on a load.

0xe3 0x0f 0x40 0xa9
# CHECK:  warning: potentially undefined instruction encoding
# CHECK-NEXT: 0xe3 0x0f 0x40 0xa9
# CHECK-NEXT: ^

0xe2 0x8b 0x41 0x69
# CHECK: warning: potentially undefined instruction encoding
# CHECK-NEXT: 0xe2 0x8b 0x41 0x69
# CHECK-NEXT: ^

0x82 0x88 0x40 0x2d
# CHECK: warning: potentially undefined instruction encoding
# CHECK-NEXT: 0x82 0x88 0x40 0x2d
# CHECK-NEXT: ^

#------------------------------------------------------------------------------
# Load-store register pair (post-indexed)
#------------------------------------------------------------------------------

# Unpredictable if Rt == Rt2 on a load.

0xe3 0x0f 0xc0 0xa8
# CHECK:  warning: potentially undefined instruction encoding
# CHECK-NEXT: 0xe3 0x0f 0xc0 0xa8
# CHECK-NEXT: ^

0xe2 0x8b 0xc1 0x68
# CHECK: warning: potentially undefined instruction encoding
# CHECK-NEXT: 0xe2 0x8b 0xc1 0x68
# CHECK-NEXT: ^

0x82 0x88 0xc0 0x2c
# CHECK: warning: potentially undefined instruction encoding
# CHECK-NEXT: 0x82 0x88 0xc0 0x2c
# CHECK-NEXT: ^

# Also unpredictable if writeback clashes with either transfer register

0x63 0x94 0xc0 0xa8
# CHECK: warning: potentially undefined instruction encoding
# CHECK-NEXT: 0x63 0x94 0xc0 0xa8

0x69 0x2d 0x81 0xa8
# CHECK: warning: potentially undefined instruction encoding
# CHECK-NEXT: 0x69 0x2d 0x81 0xa8

0x29 0xad 0xc0 0x28
# CHECK: warning: potentially undefined instruction encoding
# CHECK-NEXT: 0x29 0xad 0xc0 0x28
[AArch64] Make the use of FP instructions optional, but enabled by default. This adds a new subtarget feature called FPARMv8 (implied by NEON), and predicates the support of the FP instructions and registers on this feature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8 2013-10-31 09:32:11 +00:00			`# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 \| FileCheck %s`
Add AArch64 as an experimental target. This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8 2013-01-31 12:12:40 +00:00
			`#------------------------------------------------------------------------------`
			`# Load-store exclusive`
			`#------------------------------------------------------------------------------`

			`#ldxp x14, x14, [sp]`
			`0xee 0x3b 0x7f 0xc8`
			`#CHECK: warning: potentially undefined instruction encoding`
			`#CHECK-NEXT: 0xee 0x3b 0x7f 0xc8`

			`#ldaxp w19, w19, [x1]`
			`0x33 0xcc 0x7f 0x88`
			`#CHECK: warning: potentially undefined instruction encoding`
			`#CHECK-NEXT: 0x33 0xcc 0x7f 0x88`

			`#------------------------------------------------------------------------------`
			`# Load-store register (immediate post-indexed)`
			`#------------------------------------------------------------------------------`

			`0x63 0x44 0x40 0xf8`
			`#CHECK: warning: potentially undefined instruction encoding`
			`#CHECK-NEXT: 0x63 0x44 0x40 0xf8`

			`0x42 0x14 0xc0 0x38`
			`#CHECK: warning: potentially undefined instruction encoding`
			`#CHECK-NEXT: 0x42 0x14 0xc0 0x38`

			`#------------------------------------------------------------------------------`
			`# Load-store register (immediate pre-indexed)`
			`#------------------------------------------------------------------------------`

			`0x63 0x4c 0x40 0xf8`
			`#CHECK: warning: potentially undefined instruction encoding`
			`#CHECK-NEXT: 0x63 0x4c 0x40 0xf8`

			`0x42 0x1c 0xc0 0x38`
			`#CHECK: warning: potentially undefined instruction encoding`
			`#CHECK-NEXT: 0x42 0x1c 0xc0 0x38`

			`#------------------------------------------------------------------------------`
			`# Load-store register pair (offset)`
			`#------------------------------------------------------------------------------`

			`# Unpredictable if Rt == Rt2 on a load.`

			`0xe3 0x0f 0x40 0xa9`
			`# CHECK: warning: potentially undefined instruction encoding`
			`# CHECK-NEXT: 0xe3 0x0f 0x40 0xa9`
			`# CHECK-NEXT: ^`

			`0xe2 0x8b 0x41 0x69`
			`# CHECK: warning: potentially undefined instruction encoding`
			`# CHECK-NEXT: 0xe2 0x8b 0x41 0x69`
			`# CHECK-NEXT: ^`

			`0x82 0x88 0x40 0x2d`
			`# CHECK: warning: potentially undefined instruction encoding`
			`# CHECK-NEXT: 0x82 0x88 0x40 0x2d`
			`# CHECK-NEXT: ^`

			`#------------------------------------------------------------------------------`
			`# Load-store register pair (post-indexed)`
			`#------------------------------------------------------------------------------`

			`# Unpredictable if Rt == Rt2 on a load.`

			`0xe3 0x0f 0xc0 0xa8`
			`# CHECK: warning: potentially undefined instruction encoding`
			`# CHECK-NEXT: 0xe3 0x0f 0xc0 0xa8`
			`# CHECK-NEXT: ^`

			`0xe2 0x8b 0xc1 0x68`
			`# CHECK: warning: potentially undefined instruction encoding`
			`# CHECK-NEXT: 0xe2 0x8b 0xc1 0x68`
			`# CHECK-NEXT: ^`

			`0x82 0x88 0xc0 0x2c`
			`# CHECK: warning: potentially undefined instruction encoding`
			`# CHECK-NEXT: 0x82 0x88 0xc0 0x2c`
			`# CHECK-NEXT: ^`

			`# Also unpredictable if writeback clashes with either transfer register`

			`0x63 0x94 0xc0 0xa8`
			`# CHECK: warning: potentially undefined instruction encoding`
			`# CHECK-NEXT: 0x63 0x94 0xc0 0xa8`

			`0x69 0x2d 0x81 0xa8`
			`# CHECK: warning: potentially undefined instruction encoding`
			`# CHECK-NEXT: 0x69 0x2d 0x81 0xa8`

			`0x29 0xad 0xc0 0x28`
			`# CHECK: warning: potentially undefined instruction encoding`
			`# CHECK-NEXT: 0x29 0xad 0xc0 0x28`