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llvm-6502/test/MC/Disassembler/ARM/d16.txt

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[ARM] Honor FeatureD16 in the assembler and disassembler Some ARM FPUs only have 16 double-precision registers, rather than the normal 32. LLVM represents this with the D16 target feature. This is currently used by CodeGen to avoid using high registers when they are not available, but the assembler and disassembler do not. I fix this in the assmebler and disassembler rather than the InstrInfo.td files, as the latter would require a large number of changes everywhere one of the floating-point instructions is referenced in the backend. This solution is similar to the one used for co-processor numbers and MSR masks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221341 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 12:06:39 +00:00
# RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -disassemble -mattr=+vfp4,-d16 |& FileCheck %s --check-prefix=D32
# RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -disassemble -mattr=+vfp4,-d16 |& FileCheck %s --check-prefix=D32
# D32: vadd.f64 d1, d2, d16
# D16: warning: invalid instruction encoding
[0x32,0xee,0x20,0x1b]
# D32: vadd.f64 d1, d17, d6
# D16: warning: invalid instruction encoding
[0x31,0xee,0x86,0x1b]
# D32: vadd.f64 d19, d7, d6
# D16: warning: invalid instruction encoding
[0x77,0xee,0x06,0x3b]
# D32: vcvt.f64.f32 d22, s4
# D16: warning: invalid instruction encoding
[0xf7,0xee,0xc2,0x6a]
# D32: vcvt.f32.f64 s26, d30
# D16: warning: invalid instruction encoding
[0xb7,0xee,0xee,0xdb]
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