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https://github.com/c64scene-ar/llvm-6502.git
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142 lines
4.6 KiB
C++
142 lines
4.6 KiB
C++
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//===-- OptimizePHIs.cpp - Optimize machine instruction PHIs --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass optimizes machine instruction PHIs to take advantage of
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// opportunities created during DAG legalization.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "phi-opt"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Function.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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STATISTIC(NumPHICycles, "Number of PHI cycles replaced");
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namespace {
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class OptimizePHIs : public MachineFunctionPass {
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MachineRegisterInfo *MRI;
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const TargetInstrInfo *TII;
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public:
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static char ID; // Pass identification
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OptimizePHIs() : MachineFunctionPass(&ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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bool IsSingleValuePHICycle(const MachineInstr *MI, unsigned &SingleValReg,
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SmallSet<unsigned, 16> &RegsInCycle);
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bool ReplacePHICycles(MachineBasicBlock &MBB);
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};
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}
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char OptimizePHIs::ID = 0;
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static RegisterPass<OptimizePHIs>
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X("opt-phis", "Optimize machine instruction PHIs");
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FunctionPass *llvm::createOptimizePHIsPass() { return new OptimizePHIs(); }
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bool OptimizePHIs::runOnMachineFunction(MachineFunction &Fn) {
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MRI = &Fn.getRegInfo();
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TII = Fn.getTarget().getInstrInfo();
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// Find PHI cycles that can be replaced by a single value. InstCombine
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// does this, but DAG legalization may introduce new opportunities, e.g.,
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// when i64 values are split up for 32-bit targets.
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bool Changed = false;
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for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
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Changed |= ReplacePHICycles(*I);
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return Changed;
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}
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/// IsSingleValuePHICycle - Check if MI is a PHI where all the source operands
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/// are copies of SingleValReg, possibly via copies through other PHIs. If
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/// SingleValReg is zero on entry, it is set to the register with the single
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/// non-copy value. RegsInCycle is a set used to keep track of the PHIs that
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/// have been scanned.
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bool OptimizePHIs::IsSingleValuePHICycle(const MachineInstr *MI,
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unsigned &SingleValReg,
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SmallSet<unsigned, 16> &RegsInCycle) {
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assert(MI->isPHI() && "IsSingleValuePHICycle expects a PHI instruction");
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unsigned DstReg = MI->getOperand(0).getReg();
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// See if we already saw this register.
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if (!RegsInCycle.insert(DstReg))
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return true;
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// Don't scan crazily complex things.
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if (RegsInCycle.size() == 16)
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return false;
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// Scan the PHI operands.
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for (unsigned i = 1; i != MI->getNumOperands(); i += 2) {
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unsigned SrcReg = MI->getOperand(i).getReg();
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if (SrcReg == DstReg)
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continue;
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const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
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// Skip over register-to-register moves.
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unsigned MvSrcReg, MvDstReg, SrcSubIdx, DstSubIdx;
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if (SrcMI &&
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TII->isMoveInstr(*SrcMI, MvSrcReg, MvDstReg, SrcSubIdx, DstSubIdx) &&
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SrcSubIdx == 0 && DstSubIdx == 0 &&
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TargetRegisterInfo::isVirtualRegister(MvSrcReg))
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SrcMI = MRI->getVRegDef(MvSrcReg);
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if (!SrcMI)
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return false;
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if (SrcMI->isPHI()) {
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if (!IsSingleValuePHICycle(SrcMI, SingleValReg, RegsInCycle))
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return false;
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} else {
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// Fail if there is more than one non-phi/non-move register.
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if (SingleValReg != 0)
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return false;
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SingleValReg = SrcReg;
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}
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}
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return true;
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}
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/// ReplacePHICycles - Find PHI cycles that can be replaced by a single
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/// value and remove them.
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bool OptimizePHIs::ReplacePHICycles(MachineBasicBlock &MBB) {
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bool Changed = false;
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for (MachineBasicBlock::iterator
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MII = MBB.begin(), E = MBB.end(); MII != E; ) {
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MachineInstr *MI = &*MII++;
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if (!MI->isPHI())
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break;
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unsigned SingleValReg = 0;
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SmallSet<unsigned, 16> RegsInCycle;
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if (IsSingleValuePHICycle(MI, SingleValReg, RegsInCycle) &&
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SingleValReg != 0) {
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MRI->replaceRegWith(MI->getOperand(0).getReg(), SingleValReg);
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MI->eraseFromParent();
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++NumPHICycles;
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Changed = true;
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}
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}
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return Changed;
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}
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